M393T5750BS3-CD5/CC - Samsung Electronics

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

DDR2 Registered SDRAM MODULE

240pin Registered Module based on 512Mb B-die

72-bit ECC

* Samsung Electronics reserves the right to change products or specification without notice.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

DDR2 Registered DIMM Ordering Information

Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products.

Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.

Part Number Density Organization Component Composition Number of Rank Height

M393T6553BG(Z)3-CD5/CC 512MB 64Mx72 64Mx8(K4T51083QB)*9EA 1 30mm

M393T6553BG(Z)0-CD5/CC 512MB 64Mx72 64Mx8(K4T51083QB)*9EA 1 30mm

M393T2953BG(Z)3-CD5/CC 1GB 128Mx72 64Mx8(K4T51083QB)*18EA 2 30mm

M393T2953BG(Z)0-CD5/CC 1GB 128Mx72 64Mx8(K4T51083QB)*18EA 2 30mm

M393T2950BG(Z)3-CD5/CC 1GB 128Mx72 128Mx4(K4T51043QB)*18EA 1 30mm

M393T2950BG(Z)0-CD5/CC 1GB 128Mx72 128Mx4(K4T51043QB)*18EA 1 30mm

M393T5750BS(Y)3-CD5/CC 2GB 256Mx72 128Mx4(K4T51043QB)*36EA 2 30mm

M393T5750BS(Y)0-CD5/CC 2GB 256Mx72 128Mx4(K4T51043QB)*36EA 2 30mm

Features

• Performance range

• JEDEC standard 1.8V ± 0.1V Power Supply

• VDDQ = 1.8V ± 0.1V

• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin

• 4 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8

• All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

D5(DDR2-533) CC(DDR2-400) Unit

Speed@CL3 400 400 Mbps

Speed@CL4 533 400 Mbps

Speed@CL5 --Mbps

CL-tRCD-tRP 4-4-4 3-3-3 CK

Address Configuration

Organization Row Address Column Address Bank Address Auto Precharge

128Mx4(512Mb) based Module A0-A13 A0-A9,A11 BA0-BA1 A10

64Mx8(512Mb) based Module A0-A13 A0-A9 BA0-BA1 A10

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Pin Configurations (Front side/Back side)

NC = No Connect, RFU = Reserved for Future Use

1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.

2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)

3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.

4. CKE1,S1 Pin is used for double side Registered DIMM.

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5/DQS14

2VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS5 212 NC/DQS14

3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS

4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46

5VSS 125 DM0/DQS9 35 VSS 155 DM3/DQS12 KEY 95 DQ42 215 DQ47

6DQS

0 126 NC/DQS936 DQS3 156 NC/DQS12 65 VSS 185 CK0 96 DQ43 216 VSS

7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK097 VSS 217 DQ52

8VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53

9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC/Par_In 188 A0 99 DQ49 219 VSS

10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 RFU

11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 RFU

12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC(TEST) 222 VSS

13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6/DQS15

14 VSS 134 DM1/DQS10 44 VSS 164 DM8/DQS17 73 WE 193 S0 104 DQS6 224 NC/DQS15

15 DQS1 135 NC/DQS10 45 DQS8 165 NC/DQS17 74 CAS 194 VDDQ 105 DQS6 225 VSS

16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54

17 VSS 137 RFU 47 VSS 167 CB6 76 S14196 A13 107 DQ50 227 DQ55

18 RESET 138 RFU 48 CB2 168 CB7 77 ODT1 197 VDD 108 DQ51 228 VSS

19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60

20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61

21 DQ10 141 DQ15 51 VDDQ 171 CKE1480 DQ32 200 DQ37 111 DQ57 231 VSS

22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7/DQS16

23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4/DQS13 113 DQS7 233 NC/DQS16

24 DQ16 144 DQ21 54 NC 174 NC 83 DQS4 203 NC/DQS13 114 DQS7 234 VSS

25 DQ17 145 VSS 55 NC/Err_Out 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62

26 VSS 146 DM2/DQS11 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63

27 DQS2 147 NC/DQS11 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS

28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD

29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0

30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1

90 DQ41 210 VSS

Pin Description

*The VDD and VDDQ pins are tied to the single power-plane on PCB.

Pin Name Description Pin Name Description

CK0 Clock Inputs, positive line ODT0~ODT1 On die termination

CK0 Clock inputs, negative line DQ0~DQ63 Data Input/Output

CKE0, CKE1 Clock Enables CB0~CB7 Data check bits Input/Output

RAS Row Address Strobe DQS0~DQS8 Data strobes

CAS Column Address Strobe DQS0~DQS8 Data strobes, negative line

WE Write Enable DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)

S0, S1 Chip Selects DQS9~DQS17 Data strobes (Read), negative line

A0~A9, A11~A13 Address Inputs RFU Reserved for Future Use

A10/AP Address Input/Autoprecharge NC No Connect

BA0, BA1 DDR2 SDRAM Bank Address TEST Memory bus test tool

(Not Connect and Not Useable on DIMMs)

SCL Serial Presence Detect (SPD) Clock Input VDD Core Power

SDA SPD Data Input/Output VDDQ I/O Power

SA0~SA2 SPD address VSS Ground

Par_In Parity bit for the Address and Control bus VREF Input/Output Reference

Err_Out Parity error found in the Address and Control bus VDDSPD SPD Power

RESET Register and PLL control pin

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Input/Output Functional Description

Symbol Type Function

CK0 Input Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.

CK0Input Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.

CKE0~CKE1 Input Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low

initiates the Power Down mode, or the Self Refresh mode.

S0~S1Input

Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-

abled, new commands are ignored but previous operations continue.

These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are

high.

ODT0~ODT1 Input I/O bus impedance control signals.

RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the

SDRAM.

VREF Supply Reference voltage for SSTL_18 inputs

VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity

BA0~BA1 Input Selects which SDRAM bank of four is activated.

A0~A9,A10/AP

A11~A13 Input

During a Bank Activate command cycle, Address defines the row address.

During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is

used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is

selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge

command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks

will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-

charge.

DQ0~63,

CB0~CB7 In/Out Data and Check Bit Input/Output pins

DM0~DM8 Input Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once

the write command is registered into the SDRAM.

VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic

DQS0~DQS17 In/Out Positive line of the differential data strobe for input and output data.

DQS0~DQS17 In/Out Negative line of the differential data strobe for input and output data.

SA0~SA2 Input These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.

SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA

bus line to VDDSPD to act as a pullup.

SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time

to VDDSPD to act as a pullup.

VDDSPD Supply Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to

3.6 Volt operation).

RESET Input

The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs

will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-

nized with the input clock )

Par_In Input Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)

Err_Out Input Parity error found in the Address and Control bus

TEST In/Out Used by memory bus analysis tools (unused on memory DIMMs)

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Functional Block Diagram: 512MB, 64Mx72 Module(populated as 1 rank of x8 DDR2 SDRAMs)

RS0

DQS0

DM0/DQS9

NC/DQS9

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS1

DM1/DQS10

NC/DQS10

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DM2/DQS11

NC/DQS11

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS3

DM3/DQS12

NC/DQS12

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

DM8/DQS17

NC/DQS17

DM/

RDQS

NU/

RDQS

CS DQS DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DM4/DQS13

NC/DQS13

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS5

DM5/DQS14

NC/DQS14

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS6

DM6/DQS15

NC/DQS15

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS7

DM7/DQS16

NC/DQS16

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS D0 - D8

VDD/VDDQ D0 - D8

D0 - D8VREF

VDDSPD Serial PD

Notes :

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. Unless otherwise noted, resister values are 22 Ohms

1:1

RST

S0*

BA0-BA1

A0-A13

RAS

CAS

CKE0

ODT0

RESET

PCK7

RSO-> CS : DDR2 SDRAMs D0-D8

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8

RRAS -> RAS : DDR2 SDRAMs D0-D8

RCAS -> CAS : DDR2 SDRAMs D0-D8

RWE -> WE : DDR2 SDRAMs D0-D8

RCKE0 -> CKE : DDR2 SDRAMs D0-D8

RODT0 -> ODT0 : DDR2 SDRAMs D0-D8

CK0

RESET

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8

PCK7 -> CK : Register

* S0 connects to DCS and VDD connects to CSR on the register.

M393T6553BG(Z)3 / M393T6553BG(Z)0

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

RS0

DQS0

DM0/DQS9

NC/DQS9

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS1

DM1/DQS10

NC/DQS10

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DM2/DQS11

NC/DQS11

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS3

DM3/DQS12

NC/DQS12

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

DM8/DQS17

NC/DQS17

DM/

RDQS

NU/

RDQS

CS DQS DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS4

DM4/DQS13

NC/DQS13

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS5

DM5/DQS14

NC/DQS14

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS6

DM6/DQS15

NC/DQS15

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS7

DM7/DQS16

NC/DQS16

DM/

RDQS

NU/

RDQS

CS DQS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D10

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D11

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D12

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D17

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D13

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D14

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D15

DM/

RDQS

NU/

RDQS

CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D16

RS1

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS D0 - D17

VDD/VDDQ D0 - D17

D0 - D17VREF

VDDSPD Serial PD

Notes :

1. DQ-to-I/O wiring may be changed per nibble.

2. Unless otherwise noted, resister values are 22 Ohms

3. RS0 and RS1 alternate between the back and front sides of the DIMM

1:2

RST

S1*

BA0-BA1

A0-A13

RAS

CAS

CKE0

CKE1

RESET**

PCK7**

RS1-> CS : DDR2 SDRAMs D9-D17

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17

RRAS -> RAS : DDR2 SDRAMs D0-D17

RCAS -> CAS : DDR2 SDRAMs D0-D17

RWE -> WE : DDR2 SDRAMs D0-D17

RCKE0 -> CKE : DDR2 SDRAMs D0-D8

RCKE1 -> CKE : DDR2 SDRAMs D9-D17

CK0

RESET

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17

PCK7 -> CK : Register

* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.

ODT0

ODT1

RODT0 -> ODT0 : DDR2 SDRAMs D0-D8

RODT1 -> ODT1 : DDR2 SDRAMs D9-D17

S0*RSO-> CS : DDR2 SDRAMs D0-D8

** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.

Functional Block Diagram: 1GB, 128Mx72 Module(populated as 2 rank of x8 DDR2 SDRAMs)

M393T2953BG(Z)3 / M393T2953BG(Z)0

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

VSS

RS0DQS0

DQS0

DM CS DQS DQS

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

DM0/DQS9

NC/DQS9

DM CS DQS DQS

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

DQS1

DM CS DQS DQS

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

DM1/DQS10

NC/DQS10

DM CS DQS DQS

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

D10

DQS2

DM CS DQS DQS

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

DM2/DQS11

NC/DQS11

DM CS DQS DQS

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

D11

DQS3

DM CS DQS DQS

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

DM3/DQS12

NC/DQS12

DM CS DQS DQS

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

D12

DQS5

DM CS DQS DQS

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

DM5/DQS14

NC/DQS14

DM CS DQS DQS

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

D14

DQS4

DM CS DQS DQS

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DM4/DQS13

NC/DQS13

DM CS DQS DQS

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

D13

DQS6

DM CS DQS DQS

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

DM6/DQS15

NC/DQS15

DM CS DQS DQS

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

D15

DQS8

DM CS DQS DQS

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

DM8/DQS17

NC/DQS17

DM CS DQS DQS

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

D17

DQS7

DM CS DQS DQS

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

DM7DQS16

NC/DQS16

DM CS DQS DQS

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

D16

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS D0 - D17

VDD/VDDQ D0 - D17

D0 - D17VREF

VDDSPD Serial PD

Notes :

1. DQ-to-I/O wiring may be changed per nibble.

2. Unless otherwise noted, resister values are 22 Ohms

1:2

RST

S0*

BA0-BA1

A0-A13

RAS

CAS

CKE0

ODT0

RESET**

PCK7**

RSO-> CS : DDR2 SDRAMs D0-D17

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17

RRAS -> RAS : DDR2 SDRAMs D0-D17

RCAS -> CAS : DDR2 SDRAMs D0-D17

RWE -> WE : DDR2 SDRAMs D0-D17

RCKE0 -> CKE : DDR2 SDRAMs D0-D17

RODT0 -> ODT0 : DDR2 SDRAMs D0-D17

CK0

RESET

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8

PCK7 -> CK : Register

* S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD

** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.

Functional Block Diagram: 1GB, 128Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs)

M393T2950BG(Z)3 / M393T2950BG(Z)0

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Functional Block Diagram: 2GB, 256Mx72 Module(populated as 2 rank of x4 DDR2 SDRAMs)

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

VSS D0 - D35

VDD/VDDQ D0 - D35

D0 - D35VREF

VDDSPD Serial PD

CK0

RESET

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35

PCK7 -> CK : Register

* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.

** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.

1:2

RST

S1*

BA0-BA1

A0-A13

RAS

CAS

CKE0

CKE1

RESET**

PCK7**

RS1-> CS : DDR2 SDRAMs D18-D35

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35

RRAS -> RAS : DDR2 SDRAMs D0-D35

RCAS -> CAS : DDR2 SDRAMs D0-D35

RWE -> WE : DDR2 SDRAMs D0-D35

RCKE0 -> CKE : DDR2 SDRAMs D0-D17

RCKE1 -> CKE : DDR2 SDRAMs D18-D35

ODT0

ODT1

RODT0 -> ODT0 : DDR2 SDRAMs D0-D17

RODT1 -> ODT1 : DDR2 SDRAMs D18-D35

S0*RSO-> CS : DDR2 SDRAMs D0-D17

VSS

RS0DQS0

DQS0

DM CS DQS DQS

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

DM0/DQS9

NC/DQS9

DM CS DQS DQS

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

DQS1

DM CS DQS DQS

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

DM1/DQS10

NC/DQS10

DM CS DQS DQS

DQ12

DQ13

DQ14

DQ15

I/O 0

I/O 1

I/O 2

I/O 3

D10

DQS2

DM CS DQS DQS

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

DM2/DQS11

NC/DQS11

DM CS DQS DQS

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

D11

DQS3

DM CS DQS DQS

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

DM3/DQS12

NC/DQS12

DM CS DQS DQS

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

D12

DQS5

DM CS DQS DQS

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

DM5/DQS14

NC/DQS14

DM CS DQS DQS

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

D14

DQS4

DM CS DQS DQS

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DM4/DQS13

NC/DQS13

DM CS DQS DQS

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

D13

DQS6

DM CS DQS DQS

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

DM6/DQS15

NC/DQS15

DM CS DQS DQS

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

D15

DQS8

DM CS DQS DQS

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

DM8/DQS17

NC/DQS17

DM CS DQS DQS

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

D17

DQS7

DM CS DQS DQS

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

DM7DQS16

NC/DQS16

DM CS DQS DQS

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

D16

DM/ CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D18

DM/ CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D19

DM/ CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D20

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D21

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D23

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D22

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D24

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D26

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D25

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D27

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D28

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D29

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D30

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D32

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D31

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D33

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D35

DM CS DQS DQS

I/O 0

I/O 1

I/O 2

I/O 3

D34

RS1

M393T5750BS(Y)3 / M393T5750BS(Y)0

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Absolute Maximum DC Ratings

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal

to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5

x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).

3. VTT of transmitting device must track VREF of receiving device.

4. AC parameters are measured with VDD, VDDQ and VDDL tied together.

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1

VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1

VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1

VIN, VOUT Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1

TSTG Storage Temperature -55 to +100 °C 1, 2

Symbol Parameter Rating Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.7 1.8 1.9 V

VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4

VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4

VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1,2

VTT Termination Voltage VREF-0.04 VREF VREF+0.04 V 3

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Operating Temperature Condition

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2

standard.

2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.

3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self

refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Input AC Logic Level

AC Input Test Conditions

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)

max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative

transitions.

Symbol Parameter Rating Units Notes

TOPER Operating Temperature 0 to 95 °C 1, 2, 3

Symbol Parameter Min. Max. Units Notes

VIH(DC) DC input logic high VREF + 0.125 VDDQ + 0.3 V

VIL(DC) DC input logic low - 0.3 VREF - 0.125 V

Symbol Parameter Min. Max. Units Notes

VIH(AC) AC input logic high VREF + 0.250 - V

VIL(AC) AC input logic low - VREF - 0.250 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

VDDQ

VIH(AC) min

VIH(DC) min

VREF

VIL(DC) max

VIL(AC) max

VSS

< AC Input Test Signal Waveform >

VSWING(MAX)

delta TRdelta TF

VREF - VIL(AC) max

delta TF

Falling Slew = Rising Slew = VIH(AC) min - VREF

delta TR

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol Proposed Conditions Units Notes

IDD0

Operating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Ad-

dress bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD1

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern

is same as IDD4W

IDD2P

Precharge power-down current;

All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

IDD2Q

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

IDD2N

Precharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD3P

Active power-down current;

All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0mA mA

Slow PDN Exit MRS(12) = 1mA mA

IDD3N

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD4W

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus in-

puts are SWITCHING

IDD4R

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-

max(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

IDD5B

Burst auto refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD6

Self refresh current;

CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal mA

Low Power mA

IDD7

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =

tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid com-

mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following

page for detailed timing conditions

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)

M393T6553BG(Z)3 / M393T6553BG(Z)0 : 512MB(64Mx8 *9) Module

* IDD6 = DRAM current + standby current of PLL and Register.

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol D5

(DDR2-533@CL=4)

(DDR2-400@CL=3) Unit Notes

IDD0 1,420 1,265 mA

IDD1 1,540 1,330 mA

IDD2P 562 522 mA

IDD2Q 715 665 mA

IDD2N 730 670 mA

IDD3P-F 750 720 mA

IDD3P-S 375 365 mA

IDD3N 1,180 1,065 mA

IDD4W 2,340 1,725 mA

IDD4R 2,020 1,655 mA

IDD5B 2,275 2,125 mA

IDD6* Normal 50 50 mA

IDD7 3,155 3,020 mA

M393T2953BG(Z)3 / M393T2953BG(Z)0 : 1GB(64Mx8 *18) Module

* IDD6 = DRAM current + standby current of PLL and Register.

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol D5

(DDR2-533@CL=4)

(DDR2-400@CL=3) Unit Notes

IDD0 1,790 1,665 mA

IDD1 1,920 1,770 mA

IDD2P 784 724 mA

IDD2Q 1,110 1,040 mA

IDD2N 1,090 1,060 mA

IDD3P-F 1,190 1,130 mA

IDD3P-S 600 570 mA

IDD3N 1,480 1,415 mA

IDD4W 2,740 2,135 mA

IDD4R 2,420 2,055 mA

IDD5B 2,665 2,485 mA

IDD6* Normal 99 99 mA

IDD7 3,785 3,785 mA

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)

M393T2950BG(Z)3 / M393T2950BG(Z)0 : 1GB(128Mx4 *18) Module

* IDD6 = DRAM current + standby current of PLL and Register.

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol D5

(DDR2-533@CL=4)

(DDR2-400@CL=3) Unit Notes

IDD0 2,420 2,250 mA

IDD1 2,640 2,400 mA

IDD2P 784 724 mA

IDD2Q 1,110 1,040 mA

IDD2N 1,090 1,060 mA

IDD3P-F 1,190 1,130 mA

IDD3P-S 600 570 mA

IDD3N 1,840 1,730 mA

IDD4W 3,820 2,900 mA

IDD4R 3,590 3,000 mA

IDD5B 4,150 3,880 mA

IDD6* Normal 99 99 mA

IDD7 5,900 5,570 mA

M393T5750BS(Y)3 / M393T5750BS(Y)0 : 2GB(128Mx4 *36) Module

* IDD6 = DRAM current + standby current of PLL and Register.

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol D5

(DDR2-533@CL=4)

(DDR2-400@CL=3) Unit Notes

IDD0 3,250 3,010 mA

IDD1 3,520 3,220 mA

IDD2P 1,238 1,138 mA

IDD2Q 1,880 1,770 mA

IDD2N 1,850 1,810 mA

IDD3P-F 2,050 1,950 mA

IDD3P-S 1,030 980 mA

IDD3N 2,620 2,500 mA

IDD4W 4,710 3,690 mA

IDD4R 4,330 3,700 mA

IDD5B 4,990 4,660 mA

IDD6* Normal 198 198 mA

IDD7 7,140 6,600 mA

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)

* DM is internally loaded to match DQ and DQS identically.

Parameter

Symbol

Min Max Min Max Min Max Min Max

Units

Part-Number M393T6553BG(Z)3

M393T6553BG(Z)0

M393T2953BG(Z)3

M393T2953BG(Z)0

M393T2950BG(Z)3

M393T2950BG(Z)0

M393T5750BS(Y)3

M393T5750BS(Y)0

Input capacitance, CK and CK CCK -11 -11 -11 -11

Input capacitance, CKE and CS CI1 -12 -12 -12 -12

Input capacitance, Addr,RAS,CAS,WE CI2 -12 -12 -12 -12

Input/output capacitance, DQ, DM, DQS,

DQS CIO -10 -10 -10 -10

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM

(0 °C < TCASE < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)

Refresh Parameters by Device Density

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units

Refresh to active/Refresh command time tRFC 75 105 127.5 195 tbd ns

Average periodic refresh interval tREFI

0 °C ≤ TCASE ≤ 85°C7.8 7.8 7.8 7.8 7.8 µs

85 °C < TCASE ≤ 95°C3.9 3.9 3.9 3.9 3.9 µs

Speed DDR2-533(D5) DDR2-400(CC)

UnitsBin (CL - tRCD - tRP) 4 - 4 - 4 3 - 3 - 3

Parameter min max min max

tCK, CL=3 5 8 5 8 ns

tCK, CL=4 3.75 8 5 8 ns

tCK, CL=5 - - - - ns

tRCD 15 15 ns

tRP 15 15 ns

tRC 55 55 ns

tRAS 40 70000 40 70000 ns

Parameter Symbol DDR2-533 DDR2-400 Units Notes

min max min max

DQ output access time from CK/CK tAC -500 +500 -600 +600 ps

DQS output access time from CK/CK tDQSCK -450 +450 -500 +500 ps

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK

CK half period tHP min(tCL, tCH) xmin(tCL, tCH) xps

Clock cycle time, CL=x tCK 3750 8000 5000 8000 ps

DQ and DM input hold time tDH 225 x275 xps

DQ and DM input setup time tDS 100 x150 xps

Control & Address input pulse width for each input tIPW 0.6 x0.6 xtCK

DQ and DM input pulse width for each input tDIPW 0.35 x0.35 xtCK

Data-out high-impedance time from CK/CK tHZ x tAC max x tAC max ps

DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2* tACmin tAC max 2* tACmin tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ x 300 x 350 ps

DQ hold skew factor tQHS x 400 x 450 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS xtHP - tQHS xps

Write command to first DQS latching transition tDQSS WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK

DQS input high pulse width tDQSH 0.35 x0.35 xtCK

DQS input low pulse width tDQSL 0.35 x0.35 xtCK

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Parameter Symbol DDR2-533 DDR2-400 Units Notes

min max min max

DQS falling edge to CK setup time tDSS 0.2 x0.2 xtCK

DQS falling edge hold time from CK tDSH 0.2 x0.2 xtCK

Mode register set command cycle time tMRD 2 x 2 x tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 x0.35 xtCK

Address and control input hold time tIH 375 x475 xps

Address and control input setup time tIS 250 x350 xps

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Active to active command period for 1KB page size products tRRD 7.5 x7.5 xns

Active to active command period for 2KB page size products tRRD 10 x10 xns

Four Activate Window for 1KB page size products tFAW 37.5 37.5 ns

Four Activate Window for 2KB page size products tFAW 50 50 ns

CAS to CAS command delay tCCD 2 2tCK

Write recovery time tWR 15 x15 xns

Auto precharge write recovery + precharge time tDAL tWR+tRP xtWR+tRP xtCK

Internal write to read command delay tWTR 7.5 x10 xns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 200 tCK

Exit precharge power down to any non-read command tXP 2 x 2 x tCK

Exit active power down to read command tXARD 2 x 2 x tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 33

tCK

ODT turn-on delay tAOND 2 2 2 2 tCK

ODT turn-on tAON tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+tAC(m

ax)+1 tAC(min)+2 2tCK+tAC

(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+

tAC(max)+1 tAC(min)+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK +tIH tIS+tCK +tIH ns

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Physical Dimensions: 64Mbx8 based 64Mx72 Module(1 Rank)

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB

PLL

1.27 ± 0.10

2.70

1.0 max

M393T6553BG(Z)3 / M393T6553BG(Z)0

Units : Millimeters

63.00 55.00

30.00

133.35

2.50 1.00

0.20

2.50±0.20

Detail B

5.00

Detail A

4.00

1.50±0.10

0.80±0.05

4.00

3.80

3.00

4.00

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Physical Dimensions: 64Mbx8/128Mbx4 based 128Mx72 Module(2/1 Ranks)

The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB / K4T51043QB

PLL

1.27 ± 0.10

4.00

1.0 max

1.7 max

M393T2953BG(Z)3 / M393T2953BG(Z)0

2.50 1.00

0.20

2.50±0.20

Detail B

5.00

Detail A

4.00

1.50±0.10

0.80±0.05

4.00

3.80

3.00

4.00

Units : Millimeters

133.35

30.00

63.00 55.00

M393T2950BG(Z)3 / M393T2950BG(Z)0

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Physical Dimensions: 128Mbx4 based 256Mx72 Module(2 Ranks)

The used device is 128M x4 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51043QB

M393T5750BS(Y)3 / M393T5750BS(Y)0

PLL

1.27 ± 0.10

4.00

1.0 max

1.7 max

2.50 1.00

0.20

2.50±0.20

Detail B

5.00

Detail A

4.00

1.50±0.10

0.80±0.05

4.00

3.80

3.00

4.00

Units : Millimeters

133.35

30.00

63.00 55.00

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

CK0

PLL

OUT1

OUTN

Reg.A

Reg.B

Feedback In

Feedback Out

0ns (nominal)

120 ohms

Note:

1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).

2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.

DDR2 SDRAM

240 Pin DDR2 Registered DIMM Clock Topology

Rev. 1.3 Aug. 2005

512MB, 1GB, 2GB Registered DIMMs DDR2 SDRAM

Revision History

Revision 1.0 (Jan. 2004)

- Initial Release

Revision 1.1 (Jun. 2004)

- Added lead-free part number in the ordering information

- Changed IDD2P

Revision 1.2 (Sep. 2004)

- Changed IDD6

Revision 1.3 (Aug. 2004)

- Added Dummy Pad PCB Product part number in the ordering information