MC14001UBDR2G - ON Semiconductor - Datasheet.Directory

September, 2009 − Rev. 7

1Publication Order Number:

MC14001UB/D

MC14001UB, MC14011UB

UB-Suffix Series

CMOS Gates

The UB Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired. The UB set of

CMOS gates are inverting non−buffered functions.

Features

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Linear and Oscillator Applications

•Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature Range

•Double Diode Protection on All Inputs

•Pin−for−Pin Replacements for Corresponding CD4000 Series UB

Suffix Devices

•These are Pb−Free Devices

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

PDIP−14

P SUFFIX

CASE 646

MC140xxUBCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

140xxUG

AWLYWW

http://onsemi.com

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Package

MC14001UB, MC14011UB

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LOGIC DIAGRAMS

MC14001UB

Quad 2−Input

NOR Gate

MC14011UB

Quad 2−Input

NAND Gate

VDD = PIN 14

VSS = PIN 7

FOR ALL DEVICES

11 13

PIN ASSIGNMENTS

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

MC14001UB

Quad 2−Input NOR Gate

MC14011UB

Quad 2−Input NAND Gate

MC14001UB, MC14011UB

http://onsemi.com

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 2)

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

ÎÎÎÎ

VOL

ÎÎÎ

5.0

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎÎ

ÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Vin = 0 or VDD “1” Level

ÎÎÎÎ

VOH

ÎÎÎ

5.0

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

ÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

ÎÎÎ

−

ÎÎÎ

1.0

2.0

2.5

ÎÎÎÎ

−

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.0

2.0

2.5

ÎÎÎ

−

ÎÎÎ

1.0

2.0

2.5

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

(VO = 0.5 Vdc) “1” Level

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0

ÎÎÎ

4.0

8.0

12.5

ÎÎÎ

−

ÎÎÎÎ

4.0

8.0

12.5

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

−

ÎÎÎ

4.0

8.0

12.5

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

ÎÎÎ

– 1.0

– 0.25

– 0.62

– 1.8

ÎÎÎ

−

ÎÎÎÎ

– 0.75

– 0.2

– 0.4

– 1.5

ÎÎÎÎ

– 1.7

– 0.36

– 0.9

– 3.5

ÎÎÎ

−

ÎÎÎ

– 0.55

– 0.14

– 0.15

– 1.0

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.1

3.4

ÎÎÎÎ

0.88

2.25

8.8

ÎÎÎ

−

ÎÎÎ

0.36

0.7

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

ÎÎÎ

−

ÎÎÎ

0.25

0.5

1.0

ÎÎÎÎ

−

ÎÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎ

7.5

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3, 4)

(Dynamic plus Quiescent,

Per Gate CL = 50 pF)

ÎÎÎÎ

ÎÎÎ

5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 mA/kHz) f + IDD/N

IT = (0.6 mA/kHz) f + IDD/N

IT = (0.8 mA/kHz) f + IDD/N

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mH (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates

per package.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time

tTLH = (3.0 ns/pF) CL + 30 ns

tTLH = (1.5 ns/pF) CL + 15 ns

tTLH = (1.1 ns/pF) CL + 10 ns

ÎÎÎÎÎ

tTLH

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

180

ÎÎÎÎ

360

180

130

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time

tTHL = (1.5 ns/pF) CL + 25 ns

tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎ

tTHL

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

100

ÎÎÎÎ

200

100

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

tPLH, tPHL = (1.7 ns/pF) CL + 30 ns

tPLH, tPHL = (0.66 ns/pF) CL + 22 ns

tPLH, tPHL = (0.50 ns/pF) CL + 15 ns

ÎÎÎÎÎ

tPLH, tPHL

ÎÎÎÎ

5.0

ÎÎÎÎ

−

ÎÎÎÎ

180

100

ÎÎÎ

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14001UB, MC14011UB

http://onsemi.com

ORDERING INFORMATION

Device Package Shipping†

MC14001UBCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14001UBDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14001UBDR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

MC14011UBCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14011UBDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14011UBDR2G SOIC−14

(Pb−Free) 2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Figure 1. Switching Time Test Circuit and Waveforms

VDD

VSS

OUTPUT

INPUT

PULSE

GENERATOR

20 ns 20 ns

INPUT

OUTPUT

INVERTING

tPHL tPLH

90%

50%

10%

90%

50%

10%

tTHL tTLH

VDD

0 V

VOH

VOL

*All unused inputs of AND, NAND gates must be

connected to VDD.

All unused inputs of OR, NOR gates must be

connected to VSS.

MC14001UB, MC14011UB

http://onsemi.com

MC14001UB CIRCUIT SCHEMATIC

14 103

VDD

VSS

4711

MC14011UB CIRCUIT SCHEMATIC

(1/4 of Device Shown)

2, 5, 9, 12

1, 6, 8, 13

7 VSS

14 VDD

3, 4, 10, 11

Figure 2. Typical Voltage and

Current Transfer Characteristics

Figure 3. Typical Voltage Transfer

Characteristics versus Temperature

Figure 4. Typical Output Source Characteristics Figure 5. Typical Output Sink Characteristics

Vout , OUTPUT VOLTAGE (Vdc)

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16

8.0

6.0

4.0

2.0

ID, DRAIN CURRENT (mAdc)

Vin, INPUT VOLTAGE (Vdc)

Vout , OUTPUT VOLTAGE (Vdc)

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16

Vin, INPUT VOLTAGE (Vdc)

ID, DRAIN CURRENT (mAdc)

-8.0

-6.0

-4.0

-2.0

-10

-10 -8.0 -6.0 -4.0 -2.0 0

VDS, DRAIN VOLTAGE (Vdc)

ID, DRAIN CURRENT (mAdc)

2.0

4.0

6.0

8.0

VDS, DRAIN VOLTAGE (Vdc)

2.0 4.0 6.0 8.0 10

TA = -55°C

TA = +25°C

TA = +125°C

VGS = -5.0 Vdc b

a a

-10 Vdc

-15 Vdc

bca

5.0 Vdc

VGS = 10 Vdc

15 Vdc

TA = -55°C

TA = +25°C

TA = +125°C

VDD = 15 Vdc

TA = +125°C

TA = -55°C

TA = +25°C

Unused input

connected to

VSS.

One input only

Both inputs

10 Vdc

5.0 Vdc

15 Vdc

10 Vdc

Unused input

connected to

VSS.

VDD = 15 Vdc

5.0 Vdc

10 Vdc

MC14001UB, MC14011UB

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PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

14 8

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

HG D

SEATING

PLANE

−T−

14 PL

0.13 (0.005)

0.290 0.310 7.37 7.87

MC14001UB, MC14011UB

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PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

−T−

RX 45

SEATING

PLANE D14 PL K

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC14001UB/D

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