© Semiconductor Components Industries, LLC, 2011
December, 2011 − Rev. 5
1Publication Order Number:
A5191HRT/D
A5191HRT
HART Modem
Description
The A5191HRT is a single−chip, CMOS modem for use in highway
addressable remote transducer (HART) field instruments and masters.
The modem and a few external passive components provide all of the
functions needed to satisfy HART physical layer requirements
including modulation, demodulation, receive filtering, carrier detect,
and transmit−signal shaping.
The A5191HRT uses phase continuous frequency shift keying
(FSK) at 1200 bits per second. To conserve power the receive circuits
are disabled during transmit operations and vice versa. This provides
the half−duplex operation used in HART communications.
Features
•Single−chip, Half−duplex 1200 Bits per Second FSK Modem
•Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz
•3.0 V − 5.5 V Power Supply
•Transmit−signal Wave Shaping
•Receive Band−pass Filter
•Low Power: Optimal for Intrinsically Safe Applications
•Compatible with 3.3 V or 5 V Microcontroller
•Internal Oscillator Requires 460.8 kHz Crystal or Ceramic Resonator
•Meets HART Physical Layer Requirements
•Industrial Temperature Range of −40°C to +85°C
•Available in 28−pin PLCC, 32−pin QFN and 32−pin LQFP Packages
•These are Pb−Free Devices
Applications
•HART Multiplexers
•HART Modem Interfaces
•4 − 20 mA Loop Powered Transmitters
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See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
PLCC−28
P SUFFIX
CASE 776AA
QFN−32
N SUFFIX
CASE 488AM
LQFP−32
L SUFFIX
CASE 561AB
MARKING DIAGRAMS
XXXXYZZ
A5191HRTPG
XXXXYZZ
A5191
HRTLG
A5191HRTxx = Specific Device Code
xx = P (PLCC), L (LQFP) or N (QFN)
XXXX = Date Code
Y = Plant Identifier
ZZ = Traceability Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G= Pb−Free Package
(Top Views)
A5191
HRTNG
AWLYYWW
G
1
1
32
128
A5191HRT
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BLOCK DIAGRAM
Demodulator
Logic
Rx HP Filter
Rx Comp
Carrier Detect
Counter
Carrier Comp
Wave
Shaper
Numeric
Controlled
Oscillator
DEMODULATOR
MODULATOR
Crystal
Oscillator BIAS A5191HRT
RxAFVDD
RxA
RxAFI
RxD
AREF
CDREF
TxA
CD
TxD
RTS
CBIAS
VDDA
VSS VSSA
FSK_OUT
FSK_IN
XINXOUT
RESET
Figure 1. Block Diagram A5191HRT
ELECTRICAL SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)
Symbol Parameter Min Max Units
TAAmbient −40 +85 °C
TSStorage Temperature −55 150 °C
VDD Supply Voltage −0.3 6.0 V
VIN, VOUT DC Input, Output −0.3 VDD + 0.3 V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. CMOS devices are damaged by high−energy electrostatic discharge. Devices must be stored in conductive foam or with all pins shunted.
Precautions should be taken to avoid application of voltages higher than the maximum rating. Stresses above absolute maximum ratings
may result in damage to the device.
2. Remove power before insertion or removal of this device.
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Table 2. DC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, VSS = 0 V, TA = −40°C to +85°C)
Symbol Parameter VDD Min Typ Max Units
VIL Input Voltage, Low 3.0 – 5.5 V 0.3 * VDD V
VIH Input Voltage, High 3.0 – 5.5 V 0.7 * VDD V
VOL Output Voltage, Low (IOL = 0.67 mA) 3.0 – 5.5 V 0.4 V
VOH Output Voltage, High (IOH = −0.67 mA) 3.0 – 5.5 V 2.4 V
CIN Input Capacitance of:
Analog Input
RXA
Digital Input
2.9
25
3.5
pF
pF
pF
IIL/IIH Input Leakage Current ±500 nA
IOLL Output Leakage Current ±10 mA
IDDA Power Supply Current
(RBIAS = 500 kW, AREF = 1.235 V)
3.3 V
5.0 V
150
150
330
300
450
600
mA
mA
IDDD Dynamic Digital Current 5.0 V 25 200 mA
AREF Analog Reference 3.3 V
5.0 V
1.2 1.235
2.5
2.6 V
V
CDREF
(Note 3)
Carrier Detect Reference (AREF – 0.08 V) 3.3 V
5.0 V
1.15
2.42
V
CBIAS Comparator Bias Current
(RBIAS = 500 kW, AREF = 1.235 V)
2.5 mA
3. The HART specification requires carrier detect (CD) to be active between 80 and 120 mVp−p. Setting CDREF at AREF − 0.08 VDC will set
the carrier detect to a nominal 100 mVp−p.
Table 3. AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, VSS = 0 V, TA = −40°C to +85°C) (Note 4)
Pin Name Description Min Typ Max Units
RxA Receive analog input
Leakage current
Frequency – mark (logic 1)
Frequency – space (logic 0)
1190
2180
1200
2200
±150
1210
2220
nA
Hz
Hz
RxAF Output of the high−pass filter
Slew rate
Gain bandwidth (GBW)
Voltage range
150
0.15
0.025
VDD – 0.15
V/ms
kHz
V
RxAFI Carrier detect and receive filter input
Leakage current ±500 nA
TxA Modulator output
Frequency – mark (logic 1)
Frequency – space (logic 0)
Amplitude (AREF 1.235 V)
Slew Rate − mark (logic 1)
Slew Rate − space (logic 0)
Loading (AREF = 1.235 V) 30
1196.9
2194.3
500
1860
3300
Hz
Hz
mV
V/s
V/s
kW
RxD Receive digital output
Rise/fall time 20
ns
CD Carrier detect output
Rise/fall time 20
ns
4. The modular output frequencies are proportional to the input clock frequency (460.8 kHz).
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Table 4. MODEM CHARACTERISTICS (VDD = 3.0 V to 5.5 V, VSS = 0 V, TA = −40°C to +85°C)
Parameter Min Typ Max Units
Demodulator jitter
Conditions
1. Input frequencies at 1200 Hz ± 10 Hz, 2200 Hz ± 20 Hz
2. Clock frequency of 460.8 kHz ± 0.1%
3. Input (RxA) asymmetry, 0
12 % of 1 bit
Table 5. CERAMIC RESONATOR − External Clock Specifications (VDD = 3.0 V to 5.5 V, VSS = 0 V, TA = −40°C to +85°C)
Parameter Min Typ Max Units
Resonator
Tolerance
Frequency 460.8
1.0 %
kHz
External
Clock frequency
Duty cycle
Amplitude
456.2
40
460.8
50
VOH − VOL
465.4
60
kHz
%
V
TYPICAL APPLICATION
A5191HRT
XOUT XIN
CX
CX
640.8 kHz
CBIAS VSS VSSA
mC
VDDA
S
4 – 20 mA
DAC OUT
HART &
4–20mA OUT
HART IN
POWER
3.0 to 5.5 V
TxA
CDREF
AREF
RxA
RxAFRxAFIVDDAVDD
RxD
CD
TxD
RTS
CAT808
LM285
RESET
Figure 2. Application Diagram A5191HRT
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8
9
10
11
7
6
5
12 13 14 15 16 17 18
22
21
20
19
23
24
25
4 3 2 1 28 27 26
TEST4
TEST3
TEST2
TEST1
TEST12
CD
RxD
A5191HRT
RESET
TEST5
TEST7
TEST8
TEST9
TxA
AREF
CDREF
CBIAS
TEST10
VDDA
RxA
RxAF
RxAFI
TEST11
TxD
RTS
VDD
VSS
XIN
XOUT
Figure 3. Pin Out A5191HRT in 28-pin PLCC
Table 6. PIN OUT SUMMARY 28−PIN PLCC
Pin No. Signal Name Type Pin Description
1 TEST1 Input Connect to VSS
2, 3, 4 TEST2, 3, 4 −Do Not Connect
5 TEST5 Input Connect to VSS
6 RESETB Input Reset all digital logic when low
7, 8, 9 TEST7, 8, 9 Input Connect to VSS
10 TxA Output Transmit Data Modulator output
11 AREF Input Analog reference voltage
12 CDREF Input Carrier detect reference voltage
13 CBIAS Output Comparator bias current
14 TEST10 Input Connect to VSS
15 VDDA Power Analog supply voltage
16 RxA Input Receive Data Modulator input
17 RxAF Output Analog receive filter output
18 RxAFI Input Analog receive comparator input
19 XOUT Output Crystal oscillator output
20 XIN Input Crystal oscillator input
21 VSS Ground Ground
22 VDD Power Digital supply voltage
23 RTSB Input Request to send
24 TxD Input Input transmit date, transmitted HART data stream from microcontroller
25 TEST11 −Do Not Connect
26 RxD Output Received demodulated HART data to microcontroller
27 CD Output Carrier detect output
28 TEST12 −Do Not Connect
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A5191HRT
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
TEST5
TEST7
TEST8
TEST9
TxA
AREF
RESET
VSS
CDREF
CBIAS
TEST10
VDDA
RxA
RxAF
RxAFI
VSSA
TEST11
TxD
RTS
VDD
VSS
XIN
XOUT
VSSA
TEST4
TEST3
TEST2
TEST1
TEST12
CD
RxD
VDD
A5191HRT
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
TEST5
TEST7
TEST8
TEST9
TxA
AREF
RESET
VSS
CDREF
CBIAS
TEST10
VDDA
RxA
RxAF
RxAFI
VSSA
TEST11
TxD
RTS
VDD
VSS
XIN
XOUT
VSSA
TEST4
TEST3
TEST2
TEST1
TEST12
CD
RxD
VDD
Figure 4. Pin Out A5191HRT in 32-pin QFN and LQFP (top view)
Table 7. PIN OUT SUMMARY 32−PIN QFN AND LQFP
Pin No. Signal Name Type Pin Description
1 TEST5 Input Connect to VSS
2 RESETB Input Reset all logic when low, connect to VDD for normal operation
3, 4, 5 TEST7, 8, 9 Input Connect to VSS
6 VSS Ground Digital ground
7 TxA Output Transmit Data Modulator output
8 AREF Input Analog reference voltage
9 CDREF Input Carrier detect reference voltage
10 CBIAS Output Comparator bias current
11 TEST10 Input Connect to VSS
12 VSSA Ground Analog ground
13 VDDA Power Analog supply voltage
14 RxA Input Receive Data Modulator input
15 RxAF Output Analog receive filter input
16 RxAFI Input Analog receive comparator input
17 XOUT Output Crystal oscillator output
18 XIN Input Crystal oscillator input
19 VSSA Ground Analog ground
20 VSS Ground Digital ground
21 VDD Power Digital supply voltage
22 RTSB Input Request to send
23 TxD Input Input transmit data, transmit HART data stream from microcontroller
24 TEST11 −Do Not Connect
25 RxD Output Received demodulated HART data to microcontroller
26 CD Output Carrier detect output
27 TEST12 −Do Not Connect
28 TEST1 Input Connect to VSS
29 TEST2 −Do Not Connect
30 VDD Power Digital supply voltage
31, 32 TEST3, 4 −Do Not Connect
EP Exposed Pad Power Connect to VSS
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Pin Descriptions
Table 8. PIN DESCRIPTIONS
Symbol Pin Name Description
AREF Analog reference voltage Receiver Reference Voltage. Normally 1.23 V is selected (in combination with
VDDA = 3.3 V). See Table 2.
CDREF Carrier detect reference voltage Carrier Detect Reference voltage. The value should be 85 mV below AREF to set
the carrier detection to a nominal of 100 mVp−p.
RESETB Reset digital logic When at logic low (VSS) this input holds all the digital logic in reset. During normal
operation RESETB should be at VDD. RESETB should be held low for a minimum
of 10 nS after VDD = 2.5 V as shown in Figure 14.
RTSB Request to send Active−low input selects the operation of the modulator. TxA is enabled when this
signal is low. This signal must be held high during power−up.
RxA Analog receive input Receive Data Demodulator Input. Accepts a HART 1200 / 2200 Hz FSK modu-
lated square wave serial data stream as input.
RxAFI Analog receive comparator input Positive input of the carrier detect comparator and the receiver filter comparator.
TxD Digital transmit input Input to the modulator accepts digital data in NRZ form. When TxD is low, the
modulator output frequency is 2200 Hz. When TxD is high, the modulator output
frequency is 1200 Hz.
XIN Oscillator input Input to the internal oscillator must be connected to a parallel mode 460.8 kHz
ceramic resonator when using the internal oscillator or grounded when using an
external 460.8 kHz clock signal.
CBIAS Comparator bias current Connection to the external bias resistor. RBIAS should be selected such that
AREF / RBIAS = 2.5 mA ± 5 %
CD Carrier detect output Output goes high when a valid input is recognized on RxA. If the received signal
is greater than the threshold specified on CDREF for four cycles of the RxA sig-
nal, the valid input is recognized.
RxAF Analog receive filter output The output of the three pole high pass receive data filter
RxD Digital receive output Signal outputs the digital receive data. When the received signal (RxA) is
1200 Hz, RxD outputs logic high. When the received signal (RxA) is 2200 Hz,
RxD outputs logic low. The HART receive data stream is only active if Carrier
Detect (CD) is high.
TxA Analog transmit output Transmit Data Modulator Output. A trapezoidal shaped waveform with a fre-
quency of 1200 Hz or 2200 Hz corresponding to a data value of 1 or 0 respect-
ively applied to TxD. TxA is active when RTSB is low. TxA equals 0.5 V when
RTSB is high.
XOUT Oscillator output Output from the internal oscillator must be connected to an external 460.8 kHz
clock signal or to a parallel mode 460.8 kHz ceramic resonator when using the
internal oscillator.
TEST(12:1) Factory test Factory test pins; for normal operation, tie these signals as per Tables 6 and 7
VDD Digital power Power for the digital modem circuitry
VDDA Analog supply voltage Power for the analog modem circuitry
VSS Ground Digital ground (and Analog ground in the case of PLCC package)
VSSA Analog ground Analog ground
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Functional Description
The A5191HRT is a single-chip modem for use in
Highway Addressable Remote Transducer (HART) field
instruments and masters. The modem IC contains a transmit
data modulator with signal shaper, carrier detect circuitry, an
analog receiver, demodulator circuitry and a crystal
oscillator, as shown in the block diagram in Figure 1.
The modulator accepts digital data at its digital input TxD
and generates a sine shaped FSK modulated signal at the
analog output TxA. A digital “1” or mark is represented with
a frequency of 1200 Hz. A digital “0” or space is represented
with a frequency of 2200 Hz. The used bit rate is 1200 baud.
The demodulator receives the FSK signal at its analog
input, filters it with a band-pass filter and generates 2 digital
signals: RxD: Received Data and CD: Carrier Detect. At the
digital output RxD the original modulated signal is received.
CD outputs the Carrier Detect signal. It goes logic high if the
received signal is above 100 mVpp during 4 consecutive
carrier periods.
The oscillator provides the modem with a stable time base
using either a simple external resonator or an external clock
source.
Detailed Description
Modulator
The modulator accepts digital data in NRZ form at the
TxD input and generates the FSK modulated signal at the
TxA output.
Sine
Shaper
Numeric
Controlled
Oscillator
MODULATOR
TxA
TxD
RTS
FSK_OUT
Figure 5. Modulator Block Diagram
A logic “1” or mark is represented by a frequency fm =
1200 Hz. A logic “0”or space is represented by a frequency
fs = 2200 Hz.
t
tBIT =833 ms
“1” = Mark
1.2 kHz
“0” = Space
2.2 kHz
tBIT = 454 ms
Figure 6. Modulation Timing
The Numeric Controlled Oscillator NCO works in a phase
continuous mode preventing abrupt phase shifts when
switching between mark and space frequency. The control
signal Request To Send RTSB enables the NCO. When
RTSB is logic low the modulator is active and A5191HRT
is in transmit mode. When RTSB is logic high the modulator
is disabled and A5191HRT is in receive mode.
The digital outputs of the NCO are shaped in the Wave
Shaper block to a trapezoidal signal. This circuit controls the
rising and falling edge to be inside the standard HART
waveshape limits. Figure 7 shows the transmit-signal forms
captured at TxA for mark and space frequency. The slew
rates are SRm = 1860 V/s at the mark frequency and SRs =
3300 V/s at the space frequency. For AREF = 1.235 V, TxA
will have a voltage swing from approximately 0.25 to 0.75
VDC.
t (ms)
0
VTxA
0.5 V
12
t (ms)
VTxA
“1” = Mark; fm=1.2 kHz
“0” = Space; fs=2.2 kHz
012
SRm= 1860 V/s
0.5 V
SRs= 3300 V/s
0.5 V 0.5 V
Figure 7. Modulator shaped output signal for Mark
and Space frequency at TxA pin.
Demodulator
The demodulator accepts a FSK signal at the RxA input
and reconstructs the original modulated signal at the RxD
output. Figure 8 illustrates the demodulation process.
tBIT
IDLE (mark) LSB MSB IDLE (mark)
tBIT
8 data bits
D0Start D1 D2 D3 D4 D5 D6 D7 Stop
Par
“0” “ 1” “0” “1” “0” “1”“0” “0”“0” “1”
FSK_IN
RxD
Figure 8. Modulation Timing
This HART bit stream follows a standard 11-bit UART
frame with Start, Stop, 8 Data – and 1 Parity bit. The
communication speed is 1200 baud.
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Receive Filter and Comparator
The received FSK signal first is filtered using a band-pass
filter build around the low noise receiver operational
amplifier “Rx HP filter”. This filter blocks interferences
outside the HART signal band.
Rx Comp Rx HP Filter
RxAF
RxA
RxAFI
AREF
DEMODULATOR
HART IN
1.235 VDC
C1
C2
C3
R1
R2
R3
R4
R6R5
C4
15 MW
Figure 9. Demodulator Receive Filter and Signal
Comparator
The filter output is fed into the Rx comparator. The
threshold value equals the analog ground making the
comparator to toggle on every zero crossing of the filtered
FSK signal. The maximum demodulator jitter is 12 % of one
bit given the input frequencies are within the HART
specifications, a clock frequency of 460.8 kHz (±1.0 %) and
zero input (RxA) asymmetry.
Carrier Detect Circuitry
Low HART input signal levels increases the risk for the
generation of bit errors. Therefore the minimum signal
amplitude is set to 80 − 120 mVpp. If the received signal is
below this level the demodulator is disabled.
This level detection is done in the Carrier Detector. The
output of the demodulator is qualified with the carrier detect
signal (CD), therefore, only RxA signals large enough to be
detected (100 mVp-p typically) by the carrier detect circuit
produce received serial data at RxD.
RxD
CD
Demodulator
Logic
Rx Comp
Carrier Detect
Counter
Carrier Comp
DEMODULATOR
RxAFI
AREF
CDREF
15 MW
FILTERED
HART IN
1.235 VDC
VAREF –80mV
Figure 10. Demodulator Carrier and Signal
Comparator
The carrier detect comparator shown in Figure 10
generates logic low output if the RxAFI voltage is below
CDREF. The comparator output is fed into a carrier detect
block. The carrier detect block drives the carrier detect
output pin CD high if RTSB is high and four consecutive
pulses out of the comparator have arrived. CD stays high as
long as RTSB is high and the next comparator pulse is
received in less than 2.5 ms. Once CD goes inactive, it takes
four consecutive pulses out of the comparator to assert CD
again. Four consecutive pulses amount to 3.33 ms when the
received signal is 1200 Hz and to 1.82 ms when the received
signal is 2200 HZ.
Miscellaneous Analog Circuitry
Voltage References
The A5191HRT requires two voltage references, AREF
and CDREF. AREF sets the DC operating point of the
internal operational amplifiers and is the reference for the
Rx comparator. If A5191HRT operates at VDD = 3.3 V the
ON Semiconductor LM285D 1.235 V reference is
recommended.
The level at which CD (Carrier Detect) becomes active is
determined by the DC voltage difference (CDREF - AREF).
Selecting a voltage difference of 80 mV will set the carrier
detect to a nominal 100 mVp-p.
Bias Current Resistor
The A5191HRT requires a bias current resistor RBIAS to
be connected between CBIAS and VSS. The bias current
controls the operating parameters of the internal operational
amplifiers and comparators and should be set to 2.5 mA.
BIAS
CBIAS
OPA
AREF
2. 5 mA
RBIAS
Figure 11. Bias Circuit
The value of the bias current resistor is determined by the
reference voltage AREF and the following formula:
RBIAS +AREF
2.5 mA
The recommended bias current resistor is 500 KW when
AREF is equal to 1.235 V.
Oscillator
The A5191HRT requires a 460.8 kHz clock signal. This
can be provided by an external clock or a resonator
connected to the A5191HRT internal oscillator.
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Internal Oscillator Option
The oscillator cell will function with either a 460.8 kHz
crystal or ceramic resonator. A parallel resonant ceramic
resonator can be connected between XIN and XOUT.
Figure 12 illustrates the crystal option for clock generation
using a 460.8 kHz (±1 % tolerance) parallel resonant crystal
and two tuning capacitors Cx. The actual values of the
capacitors may depend on the recommendations of the
manufacturer of the resonator. Typically, capacitors in the
range of 100 pF to 470 pF are used.
XOUT XIN
CX
CX
460.8 kHz
Crystal
Oscillator
Figure 12. Crystal Oscillator
External Clock Option
It may be desirable to use an external 460.8 kHz clock as
shown in Figure 13 rather than the internal oscillator. In
addition, the A5191HRT consumes less current when an
external clock is used. Minimum current consumption
occurs with the clock connected to XOUT and XIN
connected to VSS.
XOUT XIN
Crystal
Oscillator
460.8 kHz
Figure 13. Oscillator with External Clock
Power On Reset
During start-up the RESETB pin should be kept low until
the voltage level on VDD is above the minimum level VDDH
= 2.5 V to guarantee correct operation of the digital circuitry.
As illustrated in Figure 14 RESETB should be kept low for
at least tPOR = 10 ns after this threshold level is reached.
tPOR =10ns
VDDH =2.5V
VDD
t
RESET pin
Figure 14. Power On Reset Timing
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PACKAGE DIMENSIONS
PLCC 28 LEAD
CASE 776AA−01
ISSUE O
A5191HRT
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PACKAGE DIMENSIONS
QFN−32, 5x5
CASE 488AM−01
ISSUE O
SEATING
32 X
K
0.15 C
(A3)
A
A1
D2
b
1
916 17
32
2 X
2 X
E2
32 X
8
24
32 X
L
32 X
BOTTOM VIEW
EXPOSED PAD
TOP VIEW
SIDE VIEW
D
A
B
E
0.15 C
ÉÉ
ÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C
C
25
e
A0.10 B
C
0.05 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PLANE
DIM MIN NOM MAX
MILLIMETERS
A0.800 0.900 1.000
A1 0.000 0.025 0.050
A3 0.200 REF
b0.180 0.250 0.300
D5.00 BSC
D2 2.950 3.100 3.250
E5.00 BSC
E2
e0.500 BSC
K0.200 −−− −−−
L0.300 0.400 0.500
2.950 3.100 3.250
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50 PITCH
3.20
0.28
3.20
32 X
28 X
0.63
32 X
5.30
5.30
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PACKAGE DIMENSIONS
LQFP−32, 7x7
CASE 561AB−01
ISSUE O
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Ordering Information
The A5191HRT is available in a 28−pin plastic leaded chip carrier (PLCC), 32−pin quad flat no−lead (QFN) and 32−pin
low−profile quad flat pack (LQFP). Use the following part numbers when ordering. Contact your local sales representative
for more information: www.onsemi.com.
Table 9. ORDERING INFORMATION
Part Number Package Shipping Configuration Temperature Range
A5191HRTLG−XTD 32−pin LQFP
Green/RoHS compliant
____ Tube/Tray −40°C to +85°C (Industrial)
A5191HRTLG−XTP 32−pin LQFP
Green/RoHS compliant
____ Tape & Reel −40°C to +85°C (Industrial)
A5191HRTPG−XTD 28−pin PLCC
Green/RoHS compliant
____ Tube/Tray −40°C to +85°C (Industrial)
A5191HRTPG−XTP 28−pin PLCC
Green/RoHS compliant
____ Tape & Reel −40°C to +85°C (Industrial)
A5191HRTNG−XTD 32−pin QFN
Green/RoHS compliant
____ Tube/Tray −40°C to +85°C (Industrial)
A5191HRTNG−XTP 32−pin QFN
Green/RoHS compliant
____ Tape & Reel −40°C to +85°C (Industrial)
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