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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
• Designed for Short-Range Wireless Data Communications
• Supports RF Data Transmission Rates Up to 115.2 kbps
• 3 V, Low Current Operation plus Sleep Mode
• Stable, Easy to Use, Low External Parts Count
• Complies with Directive 2002/95/EC (RoHS)
The TR1001 hybrid transceiver is ideal for short-range wireless data applications where robust operation,
small size, low power consumption and low cost are required. The TR1001 employs RF M’s amplifier-
sequenced hybrid (ASH) architecture to achieve this unique blend of character- istics. All critical RF functions
are contained in the hybrid, simplifying and speeding design-in. The receiver section of the TR1001 is
sensitive and stable. A wide dynamic range log detector, in combination with digital AGC and a compound
data slicer, provide robust performance in the presence of on-channel interference or noise. Two stages of
SA W filtering provide excellent receiver out-of-band rejection. The transmitter includes provisions for both on-
off keyed (OOK) and amplitude-shift keyed (ASK) modulation. The transmitter employs SAW filtering to
suppress output harmonics, facilitating compliance with ETSI I-ETS 300 220 and similar regulations.
Absolute Maximum Ratings
Rating Value Units
Power Supply and All Input/Output Pins -0.3 to +4.0 V
Non-Operating Case Temperature -50 to +100 °C
Soldering Temperature (10 seconds / 5 cycles max.) 260 °C
868.35 MHz
Hybrid
Transceiver
TR1001
SM-20H Case
Electrical Characteristics
Characteristic Sym Notes Minimum Typical Maximum Units
Operating Frequency fo868.15 868.55 MHz
Modulation Types OOK & ASK
OOK Data Rate 30 kbps
ASK Data Rate 115.2 kbps
Receiver Performance, High Sensitivity Mode
Sensitivity, 2.4 kbps, 10-3 BER, AM Tes t Method 1 -106 dBm
Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Meth od 1 -100 dBm
Current, 2.4 kbps (RPR = 330 K) 2 3.0 mA
Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method 1 -101 dB m
Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method 1 -95 dBm
Current, 19.2 kbps (RPR = 330 K) 2 3 .1 mA
Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method 1 -97 dBm
Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method 1 -91 dBm
Current, 115.2 kbps 3.8 mA
Receiver Performance, Low Current Mode
Sensitivity, 2.4 kbps, 10-3 BER, AM Tes t Method 1 -104 dBm
Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Meth od 1 -98 dBm
Current, 2.4 kbps (RPR = 1100 K) 2 1.8 mA
Receiver Out-of-Band Rejection, ±5% fo R±5% 380dB
Receiver Ultimate Rejection RULT 3 100 dB
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C)
Characteristic Sym Notes Minimum Typical Maximum Units
Transmitter Perform ance
Peak RF Output Power, 450 µA TXMOD Current PO31.5dBm
Peak Current, 450 µA TXMOD Current ITP 312mA
2nd - 4th Harmonic Outputs 3 -50 dBm
5th - 10th Harmonic Outputs 3 -55 dBm
Non-harmonic Spurious Outputs 3 -50 dBm
OOK Turn On/Turn Off Times tON/tOFF 412/6µs
ASK Output Rise/Fall Times tTR/tTF 4 1.1/1.1 µs
Sleep Mode Current IS0.7 µA
Power Supply Volt age Range VCC 2.2 3.7 Vdc
Power Supply Voltage Ripple 10 mVP-P
Ambient Operating Temperature TA-40 85 °C
1. Typical sensitivity data is ba sed on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK
receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Appendix 3.8 in the ASH
Transceiver Designer’s Guide for th e details of each test method, and for sensit ivity curves for a 2.2 to 3.7 V supply voltage range at five operat ing
temperatures. The app lication/tes t c i rcuit and component values are show n on the next pa ge and in the Desi gner’s Guide.
2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivit y for lower o perating current. Sensitiv ity dat a and rec eiver
current are given at 2.4 kbps for both high sensitivity operation (RPR = 330 K) and low current operation (RPR = 1100 K).
3. Data is gi ven with the ASH radio matched to a 50 ohm load. Matching compo nent values ar e given on the next page.
4. See Table 1 on Page 8 f or additional information on ASH radio event timing.
Dimension mm Inches
Min Nom Max Min Nom Max
A 9.881 10.033 10.135 .389 .395 .400
B 6.731 6.858 6.985 .265 .270 .275
C 1.778 1.930 2.032 .070 .076 .080
D 1.651 1.778 1.905 .065 .070 .075
E 0.381 0.508 0.635 .015 .020 .025
F 0.889 1.016 1.143 .035 .040 .045
G 3.175 3.302 3.429 .125 .130 .135
H 1.397 1.524 1.651 .055 .060 .065
SM-20H Package Drawing
CD
E
F
G
A
B
H
3
4
5
6
7
9
11
12
13
14
15
16
17
19
ASH Transceiver Pin Out
RFIO
8
2
10
201
18
LPFADJ
RREF
THLD2
AGCCAP
PKDET
BBOUT
CMPIN
RXDATA
TXMOD THLD1
PRATE
PWIDTH
GND1
VCC1
GND2
VCC2
GND3
CNTRL0
CNTRL1
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
Notes:
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Modulation I nput
Data Output
TOP VIEW
GND
3CNT
RL0 CNT
RL1 P
WIDTH P
RATE THLD
1THLD
2
RREF
GND2
TX
MOD
RX
DATA LPF
ADJ
CMP
IN
BB
OUT
PK
DET
AGC
CAP
VCC
1
VCC
2
RFIO
GND1
+ 3
VDC
ASH Transceiver Applicati on Circui t
OOK Configuration
1
20
23456789
10
11
1213141516171819
+ 3
VDC
RPW RPR
RTH1
RREF
RLPF
RTXM
CBBO
CRFB2 CDCB
LAT
LESD
CRFB1
LRFB
+
T/R
CLPF
RBBO
Modulation Input
Data Output
TOP VIEW
GND
3CNT
RL0 CNT
RL1 P
WIDTH P
RATE THLD
1THLD
2
RREF
GND2
TX
MOD
RX
DATA LPF
ADJ
CMP
IN
BB
OUT
PK
DET
AGC
CAP
VCC
1
VCC
2
RFIO
GND1
+ 3
VDC
ASH Transceiver Application Circuit
ASK Configuration
1
20
23456789
10
11
1213141516171819
+ 3
VDC
TR Mode
Control RPW RPR
RTH1
RTH2
RREF
RLPF
RTXM
CBBO
CPKD
CAGC
CRFB2 CDCB
LAT
LESD
CRFB1
LRFB
+
Trance iver Set-U p, 3.0 Vdc, -40 to +85 °C
Item Symbol OOK OOK ASK Units Notes
Encoded Data Rate DRNOM 2.4 19.2 115.2 kbps see page 1& 2
Minimum Signal Pulse SPMIN 416.67 52.08 8.68 µs single bit
Maximum Signal Pulse SPMAX 1666.68 208.32 34.72 µs 4 bits of same value
AGCCAP Capacitor CAGC - - 2200 pF ±10% ceramic
PKDET Capacitor CPKD - - 0.001 µ F ±10% ceramic
BBOUT Capacitor CBBO 0.1 0.015 0.0027 µF ±10% ceramic
BBOUT Resi st or RBBO 12 0 0 K ±5%
LPFAUX Capacitor CLPF 0.0047 - - µF ±5%
TXMOD R esi st or RTXM 4.7 4.7 4.7 K ±5%, for 1.5 dBm output
LPFADJ Resistor RLPF 330 100 15 K ±5%
RREF Resistor RREF 100 100 100 K ±1%
TH LD2 Resistor RTH2 - - 100 K ±1%, for 6 dB below peak
TH LD1 Resistor RTH1 0 0 10 K ±1%, typical values
PRATE Resistor RPR 330 330 160 K ±5%
PWIDTH Resi stor RPW 270 to GND 270 to GND 1000 to Vcc K ±5%
DC Bypass Capacitor CDCB 4.7 4.7 4.7 µF tantalum
RF Bypass Capacitor 1 CRFB1 27 27 27 pF ±5% NPO
RF Bypass Capacitor 2 CRFB2 100 100 100 pF ±5% NPO
RF Bypass Bead LRFB Fair-Rite Fair-Rite Fair-Rite vendor 2506033017YO or equivalent
Antenna T uning Inductor LAT 10 10 10 nH 50 ohm antenna
Shunt T uning/ESD Inductor LESD 100 100 100 nH 50 ohm antenna
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
ASH Receiv er Block Diagram & Timing Cycle
Antenna
Pulse
Generator
SAW
Delay Line
SAW Filter RFA1 RFA2 Data
Out
Detector &
Low-Pass
Filter
RF Data Pulse
P1 P2
RFA1 Out
RF Input
P1
Delay Line
Out
P2
tPW2
tPW1 tPRI
tPRC
Figure 1
ASH Transceiver Theory of Operation
Introduction
RFM’s amplifier-sequenced hybrid (ASH) transceiver is specifically
designed for short-range wireless data communication
applications. The transceiver provides rob ust operation, very small
size, low power consumption and low implementation cost. All
critical RF functions are contained in the hybrid, simplifying and
speeding design-in. The ASH transceiver can be readily
configured to support a wide range of data rates and protocol
requirements. The transceiver features excellent suppression of
transmitter harmonics and virtually no RF emissions when
receiving, making it easy to certify to short- range (unlicensed)
radio regulati ons.
Amplifier-Sequenced Receiver Operation
The ASH transceiver’s unique feature set is made possible by its
system architecture. The heart of the transceiver is the amplifier-
sequenced receiver section, which provides more than 100 dB of
stable RF and detector gain without any special shielding or
decoupl ing provisi ons. Stability is achieved by distributi ng the total
RF gain over time. This is in contrast to a superheterodyne
receive r, which ach ieves sta bility by dis tributing to tal RF gain ov er
multiple frequencies.
Figure 1 shows the basic block diagram and timing cycle for an
amplifier-sequenced receiver. Note that the bias to RF amplifiers
RFA1 and RFA2 are independently controlled by a pulse
generator, and that the two amplifiers are coupled by a surface
acoustic wave (SAW) delay line, which has a typical delay of 0.5
µs.
An incom ing RF sig nal is first fi ltered by a narrow-ba nd SAW filte r,
and is then app lied to RFA 1. The pulse gene rato r tu rns R FA1 O N
for 0.5 µs. Th e amplified signal from RFA1 emerges from the SAW
delay line at the input to RFA2. RFA1 is now switched OFF and
RFA2 is switc hed ON for 0.5 5 µs, amplifying th e RF signal f urther.
The ON time for RFA2 is usually set at 1.1 times the ON time for
RFA1, as the filtering effect of the SAW delay line stretches the
signal pulse from RFA1 somewhat. As shown in the timing
diagr am, RFA1 and RF A2 are never on a t the same time, assu ring
excellent receiver stability. Note that the narrow-band SAW filter
eliminates sampling sideband responses outside of the receiver
passband, and the SAW fi lter and delay line act together to provide
very high receiver ultimate rejection.
Amplifier-sequenced receiver operation has several interesting
characteristics that can be exploited in system design. The RF
amplifiers in an amplifier-sequenced receiver can be turned on and
off almost instantly, allowing for very quick power-down (sleep)
and wake-up times. Also, both RF amplifiers can be off between
ON seque nces to trade- off rece iver no ise fi gure for l ower averag e
current consumption. The effect on noise figure can be modeled as
if RFA1 is on continuously, with an attenuator placed in front of it
with a loss equivalent to 10*log10(RFA1 duty factor), where the
duty f actor is the aver age amount of t ime RFA1 is ON (up to 50%).
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Figure 2
Since an amplifier-sequenced receiver is inherently a sampling
receive r, the ov erall cycl e time betwe en the start of one R FA1 ON
sequenc e an d the sta rt o f th e next RF A1 O N sequence s hould be
set to sample the narrowest RF data pulse at least 10 times.
Otherwise, significant edge jitter will be added to the de tected data
pulse.
ASH Transceiver Block Diagram
Figure 2 is the general block diagram of the ASH transceiver.
Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the transceiver are
the antenna and its matching components. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be
satisfactorily matched to the RFIO pin with a series matching coil
and a shunt matching/ESD protection coil. Other antenna
impedances can be matched using two or three components. For
some im pedances , two ind uctors and a capaci tor wil l be requir ed.
A DC path from RFIO to ground is required for ESD protection.
Receiver Chain
The output of the SAW filter drives amplifier RFA1. This amplifier
includes provisions for detecting the onset of saturation (AGC Set),
and for switching between 35 dB of gain and 5 dB of gain (Gain
Select). AGC Set is an input to the AGC Control function, and Gain
Select is the AGC Control function output. ON/OFF control to
RFA1 (an d RFA2) is ge nerated by the Pulse Ge nerator & R F Amp
Bias function. The output of RFA1 drives the SAW delay line, which
has a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below
saturation. The output of RFA2 drives a full-wave detector with
19 dB of threshold gain. The onset of sa turation in eac h section of
RFA2 is detect ed and s umm ed to pro vide a logari thmic response .
This is a dded to the outp ut of the full-w ave detec tor t o produce a n
overall detector response that is square law for low signal levels,
and transitions into a log response for high signal levels. This
combination provides excellent threshold sensitivity and more than
70 dB of detector dy namic range. I n comb ination with the 30 dB of
AGC range in RFA1, more tha n 100 dB of rece iver dynamic range
is achieved.
The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with
excellent group delay flatness and minimal pulse ringing. The 3 dB
bandwi dth of the fil ter c an b e se t from 4.5 kH z to 1.8 MHz w ith a n
external resistor.
The filter is followed by a base-band amplifier which boosts the
detected signal to the BBOUT pin. When the receiver RF amplifiers
are operating at a 50%-50% duty cycle, the BBOUT signal
changes about 10 mV/dB, w ith a peak-to-pe ak signal le vel of up to
685 mV. Fo r lower duty cy cles, the mV/dB slope and pe ak-to-peak
signal level are proportionately less. The detected signal is riding
on a 1.1 Vdc level that varies somewhat with supply voltage,
temperature, etc. BBOUT is coupled to the CMPIN pin or to an
external data recovery process (DSP, etc.) by a series capacitor.
The correct value of the series capacitor depends on data rate,
data run length, and other factors as discussed in the ASH
Transceiver Designer’s Guide.
When an externa l data rec ov ery process is used with AGC ,
BBOUT must be coupled to the external data recovery process
and CMPIN by separate series coupling capacitors. The AGC
reset function is driven by the signal applied to CMPIN.
ASH Transceiver Block Diagram
RFA1 RFA2
TXA1TXA2
SAW
Delay Line
SAW
CR Filter
Log
Antenna
RFIO
Tuning/ESD
Detector Low-Pass
Filter BB
AGC
Control
Peak
Detector
Pulse Generator
& RF Amp Bias
LPFADJ
PRATE PWIDTH
RXDATA
TXMOD
CN
TRL1 CN
TRL0
AGCCAP
RREF
THLD2THLD1
Modulation
& Bias Control Power Down
Control
Gain Select
AGC Set
AGC Res e t Threshold
Control
BBOUT
DS2
DS1
AND
dB Below
Peak Thld
Ref Thld
PKDET
Ref
AGC
CBBO
CPKD
RLPF
CAGC
RPR RPW RTH2
RTH1
RTXM
20
817
18
14 15 3
9
56
4
7
13 11 12
VCC1: P in 2
VCC2: Pin 16
GND1: P in 1
GND2: Pin 10
GND3: Pin 19
RREF: Pin 11
CMPIN: Pin 6
TX
IN
Tuning
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
When the transceiver is placed in the power-down (sleep) or in a
transmit mode, the output impedance of BBOUT becomes very
high. This feature helps preserve the charge on the coupling
capacitor to minimize data slicer stabilization time when the
transceiver switches back to the receive mode.
Data Slicers
The CMPIN pin drives two data slicers, which convert the analog
signal from BBOUT back into a digital stream. T he best d ata slic er
choice depends on the system operating parameters. Data slicer
DS1 is a capacitiv el y-c ou ple d com para tor with prov is io ns for an
adjustable threshold. DS1 provides the best performance at low
signal-to-noise conditions. The threshold, or squelch, offsets the
comparator’s slicing level from 0 to 90 mV, and is set with a resistor
between the RREF and THLD1 pins. This threshold allows a trade-
off betwe en receiver se nsiti vity and output noi se dens ity in the no -
signal condition. For best sensitivity, the threshold is set to 0. In
this case, noise is output continuously when no signal is present.
This, in turn, requires the circuit being driven by the RXDATA pin
to be able to process noise (and signals) continuously.
This can be a problem if RXDATA is driving a circuit that must
“sleep” whe n da ta is no t pres en t to c ons erv e po wer, o r wh en i t its
necess ary to minim ize false inte rrupts to a multi tasking proc essor.
In this case, noise can be greatly reduced by increasing the
threshold level, but at the expense of sensitivity. The best 3 dB
bandwidth for the low-pass filter is also affected by the threshold
level setting of DS1. The bandwidth must be increased as the
threshol d is increa sed to min imize data pu lse-width variations wi th
signal amplitude.
Data slicer DS2 can overcome this compromise once the signal
level is high enough to enable its operation. DS2 is a “dB-below-
peak” slicer. The peak detector charges rapidly to the peak value
of each data pulse, and decays slowly in between data pulses
(1:1000 ratio). The slicer trip point can be set from 0 to 120 mV
below this peak value with a resistor between RREF and THLD2.
A threshold of 60 mV is the most common setting, which equates
to “6 dB below peak” when RFA1 and RFA2 are running a 50%-
50% duty cycle. Slicin g at the “6 dB-below-peak” point reduces the
signal amplitude to data pulse-width variation, allowing a lower 3
dB filter bandwidth to be used for improved sensitivity.
DS2 is best for ASK modulation where the transmitted waveform
has been shaped to minimize signal bandwidth. However, DS2 is
subject to being temporarily “blinded” by strong noise pulses,
which can cause burst data errors. Note that DS1 is active when
DS2 is used, as RXDATA is the logical AND of the DS1 and DS2
outputs. DS2 can be disabled by leaving THLD2 disconnected. A
non-zero DS1 threshold is required for proper AGC operation.
AGC Control
The output of the Peak Detector also provides an AGC Reset
signal to the AGC Control function through the AGC comparator.
The purpose of the AGC function is to extend the dynamic range
of the receiver, so that the receiver can operate close to its
transmitter when running ASK and/or high data rate modulation.
The onset of saturation in the output stage of RFA1 is detected and
generates the AGC Set signal to the AGC Control function. The
AGC Control function then selects the 5 dB gain mode for RFA1.
The AGC Comparator will send a reset signal when the Peak
Detector output (multiplied by 0.8) falls below the threshold voltage
for DS1.
A capacitor at the AGCCAP pin avoids AGC “chattering” during the
time it tak es for the si gnal to pro pagate throu gh the low-pa ss filt er
and charge the peak detec tor. The AGC capacito r al so al lo ws t he
hold-in tim e to be set lo nge r than the pea k de tec tor dec ay tim e to
avoid AGC chattering during runs of “0” bits in the received data
stream. Not e that AGC opera tion requ ires the peak det ector to be
functioni ng, eve n if DS2 is not being u se d. AGC ope rati on c an be
defeated b y connectin g the AGCCAP pin to Vcc. The AG C can be
latched on once engaged by connecting a 150 kilohm resistor
between the AGCCAP pin and ground in lieu of a capacitor.
Receiver Pulse Generator and RF Amplifier Bias
The receiver amplifier-sequence operation is controlled by the
Pulse Generator & RF Amplifier Bias module, which in turn is
controlled by the PRATE and PWIDTH input pins, and the Power
Down (sleep) Control Si gnal from the Bias Control function.
In the lo w d ata rate mod e, the i nte rva l b etwe en the fall ing edge of
one RFA1 ON pu lse to the ri sing edge o f the n ext RF A1 ON pulse
tPRI is set by a resistor between the PRATE pin and ground. The
interval can be adjusted between 0.1 and 5 µs. In the high data rate
mode (selected at the PWIDTH pin) the receiver RF amplifiers
operate at a nominal 50%-50% duty cycle. In this case, the start-
to-start period tPRC for ON pulses to RFA1 are controlled by the
PRATE resistor over a range of 0.1 to 1.1 µs.
In the low data rate mode, the PWIDTH pin sets the width of the
ON pulse tPW1 to RFA1 with a resistor to ground (the ON pulse
width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in
the low data rate mod e). The ON pu lse width tPW1 can be adjusted
between 0.55 and 1 µs. However, when the PWIDTH pin is
connecte d to Vcc through a 1 M resistor, the RF amplifiers operate
at a nominal 50%-50% duty cycle, facilitating high data rate
operation. In this case, the RF amplifiers are controlled by the
PRATE resistor as described above.
Both receiver RF amplifiers are turned off by the Power Down
Control Signal, which is invoked in the sleep and transmit modes.
Transmitter Chain
The transmitter chain consists of a SAW delay line oscillator
followed by a modulated buffer amplifier. The SAW filter
suppresses transmitter harmonics to the antenna. Note that the
same SAW devices used in the amplifier-sequenced receiver are
reused in the transmit modes.
Transmitter operation supports two modulation formats, on-off
keyed (OOK) modulation, and amplitude-shift keyed (ASK)
modulation. When OOK modulation is chosen, the transmitter
output turns completely off between “1 ” data pulses. When ASK
modulation is chosen, a “1” pulse is represented by a higher
transmitted power level, and a “0” is represented by a lower
transmitte d pow er lev el . OOK modul ati on prov id es compatibility
with first-generation ASH technology, and provides for power
conservation. ASK modulation must be used for high data rates
(data pulses less than 30 µs). ASK modulation also reduces the
effects of some types of interference and allows the transmitted
pulses to be shaped to control modulation bandwidth.
The modulation format is chosen by the state of the CNTRL0 and
the CNTRL1 mode control pins, as discussed below. When either
modulati on format is chosen, the r eceiver RF amplifiers are turned
off. In the OOK mode, the de lay li ne os ci lla tor am pli fie r TXA1 and
buffer amplifier TXA2 are turned off when the voltage to the
TXMOD inpu t falls be low 220 mV. In the OOK mode, the data rate
is limited by the turn-on and turn-off times of the delay line
oscillator, which are 12 and 6 µs respectively. In the ASK mode
TXA1 is biased ON continuously, and the output of TXA2 is
modulated by the TXMOD input current. Minimum output power
occurs in the ASK mode when the modulation driver sinks about
10 µA of current from the TXMOD pin.
The transmitter RF output power is proportional to the input current
to the TXMOD pin. A series resistor is used to adjust the peak
transmitte r o utp ut pow e r. 1 .5 dBm o f output pow e r re qui res ab out
450 µA of input current.
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Transceiver Mode Control
The four transceiver operating modes – receive, transmit ASK,
transmit OOK, and power-down (sleep), are controlled by the
Modulation & Bias Control function, and are selected with the
CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0
both high place the unit i n the receive mo de. Setting CNTRL 1 high
and CNTRL0 low plac e the unit in the ASK transmit mod e. Setting
CNTRL 1 low and C NTRL0 hi gh place t he unit in the OOK tr ansmit
mode. Se tting CNTRL1 an d CNTRL0 b oth low place the unit in th e
power-down (sleep) mode. Note that the resistor driving TXMOD
must be l ow in the re ceive and pow er-down modes . The PWIDTH
resistor must also be low in the power down mode to minimize
current. CNTRL1 and CNTRL0 are CMOS compatible inputs.
These inputs must be held at a logic level; they cannot be left
unconnected.
Transceiver Event Timing
Transce iver event timi ng is summarized in Table 1. Pleas e refer to
this table for the fo llowing discussions.
Turn-On Timing
The max imum time tPR requ ired for the receive function to become
operational at turn on is influe nced by tw o facto rs. All receiv er
circuitry will be operational 5 ms after the supply voltage reaches
2.2 Vdc. The BBOUT -CMPIN cou pl ing -ca pac ito r is then DC
stabilized in 3 time constants
(3*tBBC). The total turn-on time t o stable receiver operation for a 10
ms power supply rise time is:
tPR = 15 ms + 3*tBBC
The maximu m time required for either th e OOK or ASK transmitter
mode to become operational is 5 ms after the supply voltage
reaches 2.2 Vdc.
Receive-to-Transmit Timing
After turn on , the max imum time requi red to switc h from rec eive to
either transmit mode is 12 µs. Most of this time is due to the start-
up of the transmitte r osci llat or.
Transmit-to-Receive Timing
The maximum time required to switch from the OOK or ASK
transmit mode to the receive mode is 3*tBBC, where tBBC is the
BBOUT- CMPIN coupling-capacitor time constant. When the
operating temperature is limited to 60 oC, the time required to
switch from transmit to receive is dramatically less for short
transmissions, as less charge leaks away from the
BBOUT-CMPIN coupling capacitor.
Sleep and Wake-Up Timin g
The max im um transition ti me from the r ece iv e mode to the power-
down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are
both low (1 µs fall time).
The maximum transition time from either transmit mode to the
sleep mode (tTOS and tTAS) is 10 µs after CNT RL1 and CN TRL0
are both low (1 µs fall time).
The maximum transition time tSR from the sleep mode to the
receive mode is 3*tBBC, where tBBC is the BBOUT-CMPIN
coupling-capacitor time constant. When the operating temperature
is limited to 60 oC, the time requ ired to switch from sleep to receive
is dramatically less for short sleep times, as less charge leaks
away from the BBOUT- CMPIN coupling capacitor.
The maximum time required to switch from the sleep mode to
either transmit mode (tSTO and tSTA) is 16 µs. Most of this time is
due to the start-up of the transmitter oscillator.
AGC Timing
The max imum AGC enga ge time tAGC i s 5 µs after the rec eption of
a -30 dBm RF signal with a 1 µs envelope rise time.
The minim um AGC hold-in time is set by the val ue of the capacitor
at the AGCCAP pin. The hold-in time tAGH = CAGC/19.1, where
tAGH is in µ s and CAGC is in pF.
Peak Detector Timing
The Peak Detector attack time constant is set by the value of the
capacitor at the PKDET pin. The attack time tPKA = CPKD/4167,
where tPKA is in µs and CPKD is in pF. The Peak Dete ctor decay
time constant tPKD = 1000*tPKA.
Pulse Generator Timing
In the low data rate mode, the interval tPRI between the falling edge
of an ON pulse to the first RF amplifier and the rising edge of the
next ON pulse to the first RF amplifier is set by a resistor RPR
betwee n the PRATE pin and grou nd. The interv al can be adju sted
between 0.1 and 5 µs with a resistor in the range of 51 K to 2000
K. The value of the RPR is given by:
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
In the high data rate mode (selected at the PWIDTH pin) the
receiver RF amplifiers operate at a nominal 50%-50% duty cycle.
In this case, the period tPRC from the start of an ON pulse to the
first RF amplifier to the start of the next ON pulse to the first RF
amplifi er is cont rolled by the PR ATE resist or over a ra nge of 0 .1 to
1.1 µs using a resistor of 11 K to 220 K. In this case RPR is given
by:
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in k i lohm s
In the low data rate mode, the PWIDTH pin sets the width of the
ON pulse to the first RF amplifier tPW1 with a resistor RPW to
ground (the ON pulse w idth to the seco nd RF am plifie r tPW2 is set
at 1.1 ti mes th e p ulse w idth to the fi rst RF am plifi er in t he low data
rate mode). The ON pulse width tPW1 can be adjusted between
0.55 and 1 µs with a res is tor val ue in th e ra nge of 200 K to 39 0 K.
The value of RPW is given by:
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
However, when the PWIDTH pin is connected to Vcc through a 1
M resistor, the RF amplifiers operate at a nominal 50%-50% duty
cycle, facilitating high data rate operation. In this case, the RF
amplifiers are controlled by the PRATE resistor as described
above.
LPF Group Delay
The low-pass filter group delay is a function of the filter 3 dB
bandwidth, which is set by a resistor RLPF to ground at the LPFADJ
pin. The minimu m 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is
in kH z, and RLPF is in kilohms.
The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where
tFGD is in µs, fLPF in kHz, and RLPF in kilohms.
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Transceiver Event T im ing, 3.0 Vdc, -40 to +85 °C
Event Symbol Time Min/Max Test Conditions Notes
Turn On to Receive tPR 3*tBBC + 15 ms max 10 ms supply voltage rise time time until receiver operational
Turn On to TXOOK tPTO 15 ms max 10 ms supply voltage rise time time until TXMOD can modulate transmitter
Turn On to TXASK tPTA 15 ms max 10 ms supply voltage rise time time until TXMOD can modulate transmitter
RX to TXOOK tRTO 12 µs max 1 µs CNTRL1 fall time TXMOD low 1 µs before CNTRL1 falls
RX to TXASK tRTA 12 µs max 1 µs CNTRL0 fall time TXMOD low 1 µs before CNTRL0 falls
TXOOK to RX tTOR 3*tBBC max 1 µ s CNT RL1 rise time t ime until receiver operational
TXASK to RX tTAR 3*tBBC max 1 µs CNTRL0 rise time t ime until receiver operational
Sleep to RX tSR 3*tBBC max 1 µs CNTRL0/CNTROL 1 rise times time until receiver operational
Sleep to TXOOK tSTO 16 µs max 1 µ s CNT RL0 rise time time until TXMOD can modulate transmitter
Sleep to TXASK tSTA 16 µ s max 1 µs CNTRL1 rise time time until TXMOD can modulate transmitter
RX to Sleep tRS 10 µs max 1 µs CNTRL0/CNTROL 1 fall times time until transceiver is in power-downmode
TXOOK to Sleep tTOS 10 µ s max 1 µs CNTRL0 fall time time until transceiver is in power-downmode
TXASK to Sleep tTAS 10 µs max 1 µs CNTRL1 fall time time until transceiver is in power-downmode
AGC Engage tAGC 5 µs max 1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain
AGE Hold-In tAGH CAGC/19.1 min CAGC in pF, tAGH in µs user selected; longer than tPKD
PKDET Attack Time Constant tPKA CPKD/4167 min CPKD i n pF, tPKA in µs user selected
PKDET Decay Ti me Constant tPKD 1000*tPKA min tPKD and tPKA in µs slaved to attack time
PRATE Inter va l tPRI 0.1 to 5 µs range low data rate mode user selected mode
PWIDTH RFA1 tPW1 0.55 to 1 µs range low data rate mode user selected mode
PWIDTH RFA2 tPW2 1.1*tPW1 r ange low data rate mode user selected mode
PRATE Cycle tPRC 0.1 to 1.1 µs range high data rate mode user selected mode
PWIDTH High (RFA 1 & R FA2) tPWH 0.05 to 0.55 µs range high data rate mode user selected mode
LPF Group Delay tFGD 1750/fLPF max tFGD in µs, fLPF in kHz user selected
LPF 3 dB Bandwidth fLPF 1445/RLPF min fLPF in kHz , RLPF in kilohms user selected
BBOUT-CMPIN Time Constant tBBC 0.064*CBBO min tBBC in µs, CBBO in pF user selected
Table 1
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Pin Descriptions
Pin Name Description
1 GND1 GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.
2VCC1
VCC1 is the positive supply voltage pin for the transmitter output amplifier and the receiver base-band circuitry. VCC1 is
usually connected to the positive supply through a ferrite RF decoupling bead, which is bypassed by an RF capacitor on the
supply side. See the ASH Transceiver Designer’s Guide for additional information.
3AGCCAP
This pin controls the AGC reset operation. A capacit or between this pin and ground sets the minimum time the AGC will hold-
in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in t ime tAGH, the cap acitor value CAGC
is:
CAGC = 19.1* tAGH,where tAGH is in µs and CAGC is in pF
A ±10% ceramic capacitor should be used at this pin. The value of CAGC given above provides a hold-in time between tAGH
and 2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride
through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the
peak detector decay time, as discussed below . However, the AGC hold-in time should not be set too long, or the receiver will
be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when
using OOK modulation with data pulses of at least 30 µs. AGC operation can be defeated by connecting this pin to Vcc.
Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The AGC can be
latched on once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation
depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down
(sleep) mode and in the transmit modes.
4PKDET
This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and
decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the
base-band time constant. For a given base-band capacitor CBBO, the capacitor value CPKD is:
CPKD = 0.33* CBBO , where CBBO and CPKD are in pF
A ± 10% ceramic capacitor should be used at this pin. This time constant will vary between tPKA and 1.5* tPKA with variations
in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a 200 K
load. The peak detector is used to drive the “dB-below-peak” dat a slicer and the AGC release function. The AGC hold-in time
can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates
and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin and
the THLD2 pin can be left unconnected, and the AGC pin can be connected to Vcc to reduce the number of external compo-
nents needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode and in the transm it
modes.
5BBOUT
BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for in te r nal
data slicer operation. The time constant tBBC for this connection is:
tBBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF
A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC and
1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circu mstance will depend
on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common crite-
ria is to set the time constant for no more than a 20% voltage droop during SPMAX. For this case:
CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in p F
The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output imped-
ance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak
signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply volt-
age and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in
parallel with no more than 10 pF i s recommended. When an external data recovery process is used with AGC, BBOUT must
be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function
is driven by the signal applied to CMPIN. When the transceiver is in power-down (sleep) or in a transmit mode, the output
impedance of this pin becomes very high, preserving the charge on the coupling capacitor.
6CMPIN
This pin is the input to the internal data slicers. It is dri ven from BBOUT through a coupling capacitor . The input impedance of
this pin is 70 K to 100 K.
7RXDATA
RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this
pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) or transmit modes, this pin
becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state
when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no
greater than Vcc + 200 mV.
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Pin Name Description
8TXMOD
The transmitter RF output voltage is proportional to the input current to this pin. A series resistor is used to adjust the peak
transmitter output voltage. 1.5 dBm of output power requires about 450 µA of input current. In the ASK mode, minimum out-
put power occurs when the modulation driver sinks about 10 µA of current from this pin. In the OOK mode, input signals less
than 220 mV completely turn the transmitter oscillator off. Internally, this pin appears to be a diode in series with a small resis-
tor. Peak transmitter output power PO for a 3 Vdc supply voltage is approximately:
PO = 7*(ITXM)2, where PO is in mW, and the peak modulation current ITXM is in mA
A ±5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input (unshaped
data pulses). OOK modulation is practical for data pulses of 30 µ s or longer. In the ASK mode, this pin accepts analog mod-
ulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs or longer. The resistor driving
this pin must be low in the receive and power-down (sleep) modes. Please refer to the ASH Transceiver Designer’s Guide for
additional information on modulation techniques.
9 LPFADJ
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this pin and
ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from 4.5 kHz to 1.8 MHz.
The resistor value is determined by:
RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz
A ±5% resistor should be used to set the filter bandwidt h. This will provide a 3 dB filter bandwidth between fLPF and 1.3* fLPF
with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response.
The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.
10 GND2 GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
11 RREF
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%
resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less
than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less
that 1.5 K, their node capacitance must be added to the RREF node capacit ance and the total should not exceed 5 pF.
12 THLD2
THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor RTH2
between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value
(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV for
a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:
RTH2 = 1.67*V, where RTH2 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD2 resistor . Leaving the THLD2 pin open disables the dB-below-peak
data slicer operation.
13 THLD1
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is
increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the
resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is 0
to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:
RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1 range
of 0 to 90 mV. The resistor value is given by:
RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for proper
AGC operation.
14 PRATE
The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the
first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be adjusted between 0.1 and
5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by:
RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms
A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers
operate at a nominal 50%-50% duty cycle, facilitating high dat a rate operation. In t his case, the period tPRC from start-to-start
of ON pulses to t he f irst RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K
to 220 K. In this case the value of RPR is given by:
RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in k ilohms
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional
amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5
pF to maintain stability.
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Pin Name Description
15 PWIDTH
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON pulse
width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width tPW1
can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of RPW is given by:
RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms
A ± 5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at
a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by
the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to
less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor
between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.
16 VCC2 VCC2 is the positive supply voltage pin for the receiver RF section and transmitter oscillator. Pin 16 must be bypassed with
an RF capacitor, and must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor. See the ASH Transceiv er
Designer’s Guide for additional information.
17 CNTRL1
CNTRL1 and CNTRL0 select the receive and transmit modes. CNTRL1 and CNTRL0 both high place the unit in the receive
mode. CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode. CNTRL1 low and CNTRL0 high place the
unit in the OOK transmit mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is
a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of
Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to
this pin. A logic high requires a maximum sourc e current of 40 µA. A logic low requires a maximum sink current of 25 µ A (1
µA in sleep mode). This pin must be held at a logic level; it cannot be left unconnected.
18 CNTRL0
CNTRL0 is used with CNTRL1 to control the receive and transmit modes of the transceiver. CNTRL0 is a high-impedance
input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or
greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic
high requires a maximum source current of 40 µA. A logic low requires a maximum sink current of 25 µA (1 µA in sleep
mode). This pin must be held at a logic level; it cannot be left unconnected.
19 GND3 GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
20 RFIO
RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an imped-
ance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some imped-
ances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection.
SM-20H PCB Pad Layout
Dimensions in inches.
.09
.370
0.000
0.000
.065
.105
.145
.185
.225
.265
.305
.345
.090
.435
.1225
.1625
.1475
.1875
.220
.310
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©2008 by RF Monolithics, Inc. TR1001 - 4/3/08
Note: Specifications subject to change without notice.
0 0.050.100.150.200.250.300.350.400.450.50
ITXM in mA
VTXM vs ITXM
0.86
0.88
0.90
0.92
0.94
0.96
0.98
1.00
V
TXM
in V