HD74AC138/HD74ACT138
1-of-8 Decoder/Demultiplexer
ADE-205-368 (Z)
1st. Edition
Sep. 2000
Description
The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally
suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow
parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a 1-of-32
decoder using four HD74AC138/HD74ACT138 devices and one inverter.
Features
Demultiplexing Capability
Multiple Input Enable for Easy Expansion
Active LOW Mutually Exclusive Outputs
Outputs Source/Sink 24 mA
HD74ACT138 has TTL-Compatible Inputs
HD74AC138/HD74ACT138
2
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
E1
E2
O7
E3
GND
VCC
O0
O1
O2
O3
O4
O5
O6
(Top view)
Logic Symbol
A0A1A2E1
O0O1O2O3O4O5O6O7
E2E3
Pin Names
A0 to A2Address Inputs
E1 to E 2 Enable Inputs
E 3 Enable Input
O0 to O 7 Outputs
HD74AC138/HD74ACT138
3
Functional Description
The HD74AC138/HD74ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted
inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0 to O7).
The HD74AC138/HD74ACT138 features three Enable inputs, two active-Low (E1, E2) and one active-High
(E3). All outputs will be High unless E1 and E2 are Low and E3 is High. This multiple enabled function
allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four
HD74AC138/HD74ACT138 devices and one inverter (See Figure a). The HD74AC138/HD74ACT138
can be used as an 8-output demultiplexer by using one of the active Low Enable inputs as the data input
and the other Enable inputs as strobes. The Enables inputs which are not used must be permanently tied to
their appropriate active-High or active-Low state.
Truth Table
Inputs Outputs
E1E 2 E3A0A1A2O0O 1 O 2 O 3 O 4 O 5 O 6 O 7
HXXXXXHHHHHHHH
XHXXXXHHHHHHHH
XXLXXXHHHHHHHH
LLHLLLLHHHHHHH
LLHHLLHLHHHHHH
LLHLHLHHLHHHHH
LLHHHLHHHLHHHH
LLHLLHHHHHLHHH
LLHHLHHHHHHLHH
LLHLHHHHHHHHLH
LLHHHHHHHHHHHL
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
HD74AC138/HD74ACT138
4
Logic Diagram
A2A1A0E1
O0O1O2O3O4O5O6O7
E2E3
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Figure a: Expansion of 1-of-32 Decoding
A0
E
O0O31
H
A1
A2
A3
A4
123
E
123
O0O1O2O3O4O5O6O7
E
123
A0A1A2
O0O1O2O3O4O5O6O7
A0A1A2
O0O1O2O3O4O5O6O7
A0A1A2
O0O1O2O3O4O5O6O7
A0A1A2E
123
’04
HD74AC138/HD74ACT138
5
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current ICC 80 µAV
IN = VCC or ground, VCC = 5.5 V,
Ta = Worst case
Maximum quiescent supply current ICC 8.0 µAV
IN = VCC or ground, VCC = 5.5 V,
Ta = 25°C
Maximum ICC/input (HD74ACT138) ICCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V
Ta = Worst case
AC Characteristics: HD74AC138
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Propagation delay tPLH 3.3 1.0 8.5 13.0 1.0 15.0 ns
An to On5.0 1.0 6.5 9.5 1.0 10.5
Propagation delay tPHL 3.3 1.0 8.0 12.5 1.0 14.0 ns
An to On5.0 1.0 6.0 9.0 1.0 10.5
Propagation delay tPLH 3.3 1.0 11.0 15.0 1.0 16.0 ns
E1 or E 2 to On5.0 1.0 8.0 11.0 1.0 12.0
Propagation delay tPHL 3.3 1.0 9.5 13.5 1.0 15.0 ns
E1 or E 2 to On5.0 1.0 7.0 9.5 1.0 10.5
Propagation delay tPLH 3.3 1.0 11.0 15.5 1.0 16.5 ns
E3 to On5.0 1.0 8.0 11.0 1.0 12.5
Propagation delay tPHL 3.3 1.0 8.5 13.0 1.0 14.0 ns
E3 to On5.0 1.0 6.0 8.0 1.0 9.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
HD74AC138/HD74ACT138
6
AC Characteristics: HD74ACT138
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Propagation delay
An to On
tPLH 5.0 1.0 7.0 10.5 1.0 11.5 ns
Propagation delay
An to On
tPHL 5.0 1.0 6.5 10.5 1.0 11.5 ns
Propagation delay
E1 or E 2 to On
tPLH 5.0 1.0 8.0 11.5 1.0 12.5 ns
Propagation delay
E1 or E 2 to On
tPHL 5.0 1.0 7.5 11.5 1.0 12.5 ns
Propagation delay
E3 to On
tPLH 5.0 1.0 8.0 12.0 1.0 13.0 ns
Propagation delay
E3 to On
tPHL 5.0 1.0 6.5 10.5 1.0 11.5 ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitance CIN 4.5 pF VCC = 5.5 V
Power dissipation capacitance CPD 60.0 pF VCC = 5.0 V
HD74AC138/HD74ACT138
7
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
6.30
19.20
16 9
81 1.3
20.00 Max
7.40 Max
7.62
0.25
+ 0.13
– 0.05
2.54 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.06 Max
0° – 15°
1.11 Max
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-16DA
Conforms
0.24 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
*0.22 ± 0.05
*0.42 ± 0.08
0.12
0.15
M
2.20 Max 5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0° – 8°
0.10 ± 0.10
1.15
1.27
0.40 ± 0.06
0.20 ± 0.04
HD74AC138/HD74ACT138
8
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
1.27
16 9
18
0.15
0.25
M
1.75 Max 3.95
*0.22 ± 0.03
9.9
0° – 8°
10.3 Max
+ 0.10
– 0.30
6.10
+ 0.67
– 0.20
0.60
+ 0.11
– 0.04
0.14
*0.42 ± 0.08
0.635 Max
0.40 ± 0.06
0.20 ± 0.03
1.08
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
TTP-16DA
0.05 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.50 ± 0.10
0° – 8°
*0.17 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
18
16 9
4.40
5.00
5.30 Max
0.07
+0.03
–0.04
0.65 Max
1.0
0.20 ± 0.06
+ 0.08
– 0.07
*0.22
0.15 ± 0.04
HD74AC138/HD74ACT138
9
Cautions
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conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
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