June 2001 1
© 2001 Actel Corporation
v3.0
SX-A Family FPGAs
Leading-Edge Performance
• 250 MHz System Performance
• 3.8ns Clock-to-Out (Pad-to-Pad)
• 350 MHz Internal Performance
Specifications
• 12,000 to 108,000 Available System Gates
• Up to 360 User-Programmable I/O Pins
• Up to 2,012 Dedicated Flip-Flops
• 0.22µ/0.25µ CMOS Process Technology
Features
• Hot-Swap Compliant I/Os
• Power-Up/Down Friendly (No Sequencing Required for
Supply Voltages)
• 66 MHz PCI Compliant
•CPLD and FPGA Integration
• Single-Chip Solution
• Nonvolatile
• Configurable I/O Support for 3.3V/5.0V PCI, 5.0V TTL, and
2.5 V/3.3V LVTTL
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V
Input Tolerance and 5.0V Drive Strength
• Configurable Weak-Resistor Pull-up or Pull-down for
Tristated Outputs at Power Up
• Individual Output Slew Rate Control
• Up to 100% Resource Utilization and 100% Pin Locking
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
SX-A Product Profile
Device A54SX08A A54SX16A A54SX32A A54SX72A
Capacity
Typical Gates
System Gates 8,000
12,000 16,000
24,000 32,000
48,000 72,000
108,000
Logic Mod ules
Combinatorial Cells 768
512 1,452
924 2,880
1,800 6,036
4,024
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops 256
512 528
990 1,080
1,980 2,012
4,024
Maximum User I/Os 130 180 249 360
Global Clocks 3333
Quadrant Clocks 0004
Boundary Scan Testing Yes Yes Yes Yes
3.3V/5.0V PCI Yes Yes Yes Yes
Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns
Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns
Speed Grades –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3 –F, Std, –1, –2, –3
Temperature Grades C, I C, I, M C, I, M C, I, M
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
208
100, 144
—
144
208
100, 144
—
144, 256
208
100, 144, 176
329
144, 256, 484
208
—
—
256, 484
SX-A Family FPGAs
2v3.0
General Description
Actel’s SX-A family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other FPGA
architecture. SX-A devices simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient mapping
of synthesized logic functions. The routing and interconnect
resources are in the metal layers above the logic modules,
providing optimal use of silicon. This enables the entire
floor of the device to be spanned with an uninterrupted grid
of fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX-A devices employ both local and
general routing resources. The high-speed local routing
resources (DirectConnect and FastConnect) enable very
fast local signal propagation that is optimal for fast
counters, state machines, and datapath logic. The general
system of segmented routing tracks allows any logic module
in the array to be connected to any other logic or I/O
module. Within this system, propagation delay is minimized
by limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three or
fewer antifuses). The unique local and general routing
structure featured in SX-A devices gives fast and predictable
performance, allows 100 percent pin-locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX-A’s flexible routing structure is a
hard-wired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
set-up times. SX-A devices have easy-to-use I/O cells that do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
Ordering Information
Applic ation (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
PP = Pre-production
Package Type
BG = 1.27mm Plastic Ball Grid Array
FG = 1.0mm Fine Pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A54SX08 = 12,000 System Gates
A54SX16 = 24,000 System Gates
A54SX32 = 48,000 System Gates
A54SX72 = 108,000 System Gates
Package Lead Count
A54SX16 – PQ 2082
A = 0.22µ/0.25µ CMOS Technology
A
v3.0 3
SX-A Family FPGAs
Product Plan
Speed Gra de* Applic atio n
–FStd–1–2–3CI
†M•
A54SX08A Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔P✔✔—
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔P✔✔—
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔P✔✔—
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔P✔✔—
A54SX16A Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔P
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔P
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔P
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ PP—
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ PP—
A54SX32A Device
100-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔P
144-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔P
176-Pin Thin Quad Flat Pack (TQFP) ✔✔✔✔✔ ✔✔P
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔P
144-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔—
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔—
329-Pin Plastic Ball Grid Array (PBGA) ✔✔✔✔✔ ✔✔—
484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔—
A54SX72A Device
208-Pin Plastic Quad Flat Pack (PQFP) ✔✔✔✔✔ ✔✔P
256-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔—
484-Pin Fine Pitch Ball Grid Array (FBGA) ✔✔✔✔✔ ✔✔—
Contact your Actel sales representative for product availability.
Applications: C = Commercial Availability: ✔= Available *Speed Grade: –1 = Approx. 15% faster than Standard
I = Industrial P = Planned –2 = Approx. 25% faster than Standard
M = Military — = Not Planned –3 = Approx. 35% faster than Standard
–F = Approx. 40% slower than Standard
† Only Std, –1, –2 Speed Grade
• Only Std, –1 Speed Grade
Plastic Device Resources
User I/Os (including clock buffers)
Device PQFP
208-Pin TQFP
100-Pin TQFP
144-Pin TQFP
176-Pin PBGA
329-Pin FBGA
144-Pin FBGA
256-Pin FBGA
484-Pin
A54SX08A 130 81 113 ——111 ——
A54SX16A 175 81 113 ——111 180 —
A54SX32A 174 81 113 147 249 111 203 249
A54SX72A 171 —————203 360
Contact your Actel sales representative for product availability.
Package Definitions
PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = 1.27mm Plastic Ball Grid Array, FBGA = 1.0mm Fine Pitch Ball
Grid Array.
SX-A Family FPGAs
4v3.0
SX-A Family Architecture
The SX-A family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
The SX-A family provides efficient use of silicon by locating
the routing interconnect resources between the top two
metal layers (Figure 1). This completely eliminates the
channels of routing and interconnect resources between
logic modules (as implemented on SRAM FPGAs and
previous generations of antifuse FPGAs), and enables the
entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX-A family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed and
unprogrammed antifuses, and since SX-A is a nonvolatile,
single-chip solution, there is no configuration bitstream to
intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Note: A54SX72A has 4 layers of metal with the antifuse between Metal 3 and Metal 4.
Figure 1 • SX-A Family Interconnect Elements
Silicon Substrate
Tungsten Plug
Contact
Metal 1
Metal 2
Metal 3
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
v3.0 5
SX-A Family FPGAs
Logic Module Design
The SX-A family architecture is described as a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX-A family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 2). The R-cell registers
feature programmable clock polarity selectable on a
register-by-register basis. This provides additional flexibility
while allowing mapping of synthesized functions into the
SX-A FPGA. The clock source for the R-cell can be chosen
from either the hard-wired clock, the routed clocks, or
internal logic.
The C-cell implements a range of combinatorial functions up
to 5 inputs (Figure 3 on page 6). Inclusion of the DB input
and its associated inverter function increases the number of
combinatorial functions that can be implemented in a single
module from 800 options (as in previous architectures) to
more than 4,000 in the SX-A architecture. An example of the
improved flexibility enabled by the inversion capability is
the ability to integrate a 3-input exclusive-OR function into
a single C-cell. This facilitates construction of 9-bit
parity-tree functions with 1.9 ns propagation delays. At the
same time, the C-cell structure is extremely synthesis
friendly, simplifying the overall design and reducing
synthesis time.
Chip Architecture
The SX-A family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of new
and emerging applications.
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into
SuperClusters
(Figure 4 on page 6). SuperCluster 1 is a two-wide grouping
of Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX-A
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
significantly more combinatorial logic than flip-flops.
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 5 and Figure 6 on
page 7). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
Figure 2 •R-Cell
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLR
PRE
Y
DQ
Routed
Data Input
S0 S1
SX-A Family FPGAs
6v3.0
Figure 3 •C-Cell
Figure 4 •Cluster Organization
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
Type 1 SuperCluster Type 2 SuperCluster
Cluster 1 Cluster 1 Cluster 2 Cluster 1
R-Cell C-Cell
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
DirectConnect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS CKP
CLR
PRE
YDQ
Routed
Data Input
S0
S1
v3.0 7
SX-A Family FPGAs
Figure 5 •DirectConnect and FastConnect for Type 1 SuperClusters
Figure 6 •DirectConnect and FastConnect for Type 2 SuperClusters
Type 1 SuperClusters
DirectConnect
• No antifuses
• 0.1 ns routing dela
y
FastConnect
• One antifuse
• 0.3 ns routing delay
Routing Segments
• Typically 2 antifuse
s
• Max. 5 antifuses
Type 2 SuperClusters
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
FastConnect
• One antifuse
• 0.3 ns routing delay
DirectConnect
• No antifuses
• 0.1 ns routing delay
SX-A Family FPGAs
8v3.0
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering a maximum pin-to-pin propagation time of
0.3 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place-and-route software to minimize signal
propagation delays.
Clock Resources
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from the
HCLK buffer to the clock select MUX in each R-cell. HCLK
cannot be connected to combinational logic. This provides a
fast propagation path for the clock signal, enabling the 3.8ns
clock-to-out (pad-to-pad) performance of the SX-A devices.
The hard-wired clock is tuned to provide clock skew less than
0.3ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then the
external clock pin cannot be used for any other input and
must be tied low or high. Figure 7 describes the clock circuit
used for the constant load HCLK. Figure 8 describes the
CLKA and CLKB circuit used in SX-A devices with the
exception of A54SX72A.
In addition, the A54SX72A device provides four quadrant
clocks (QCLKA, QCLKB, QCLKC, QCLKD), which can be
sourced from external pins or from internal logic signals
within the device. Each of these clocks can individually drive
up to a quarter of the chip, or they can be grouped together to
drive multiple quadrants. The CLKA, CLKB, and QCLK
circuits for A54SX72A are shown in Figure 9. For more
information, refer to “Pin Description” on page 50.
Figure 7 •SX-A HCLK Clock Pad
Figure 8 •SX-A Routed Clock Structure (Excluding
SX72A)
Constant Load
Clock Network
HCLKBUF
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 9 •SX-A Routed Clock and QClock Structure
Clock Network
From Internal Logic
From Internal Logic
OE
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
v3.0 9
SX-A Family FPGAs
Other Architectural Features
Technology
Actel’s SX-A family is implemented on a high-voltage
twin-well CMOS process using 0.22µ/0.25µ design rules. The
metal-to-metal antifuse is made up of a combination of
amorphous silicon and dielectric material with barrier
metals and has a programmed (“on” state) resistance of
25Ω with capacitance of 1.0 fF for low signal impedance.
Performance
The combination of architectural features described above
enables SX-A devices to operate with internal clock
frequencies of 350 MHz, enabling very fast execution of even
complex logic functions. Thus, the SX-A family is an optimal
platform upon which to integrate the functionality
previously contained in multiple CPLDs. In addition,
designs that previously would have required a gate array to
meet performance goals can now be integrated into an SX-A
device with dramatic improvements in cost and
time-to-market. Using timing-driven place-and-route tools,
designers can achieve highly deterministic device
performance.
I/O Modules
Each I/O on an SX-A device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve
clock-to-output-pad timing as fast as 3.8ns. I/O cells that
have embedded latches and flip-flops require instantiation in
HDL code; this is a design complication not encountered in
SX-A FPGAs. Fast pin-to-pin timing ensures that the device
will have little trouble interfacing with any other device in
the system, which in turn enables parallel design of system
components and reduces overall design time. See Table 1 for
more information.
SX-A inputs should be driven by high-speed push-pull devices
with a low-resistance pull-up device. If the input voltage is
greater than VCCI and a fast push-pull device is NOT used, the
high-resistance pull-up of the driver and the internal circuitry
of the SX-A I/O may create a voltage divider. This voltage
divider could pull the input voltage below spec for some
devices connected to the driver. A logic '1' may not be
correctly presented in this case. For example, if an open
drain driver is used with a pull-up resistor to 5.0V to provide
the logic '1' input, and VCCI is set to 3.3V on the SX-A device,
the input signal may be pulled down by the SX-A input.
Hot Swapping
SX-A I/Os can be configured to be hot swappable in
compliance with Compact PCI Specification. During
power-up/down (or partial up/down), all I/Os are tristated.
VCCA and VCCI do not have to be stable during power
up/down, and they do not require a specific power-up or
power-down sequence in order to avoid damage to the SX-A
devices. After the SX-A device is plugged into an electrically
active system, the device will not degrade the reliability of
or cause damage to the host system. The device’s output
pins are driven to a high impedance state until normal chip
operating conditions are reached. Please see Actel’s web
site for future Application Notes concerning Hot Swapping.
Power Requirements
The SX-A family supports 2.5V/3.3V/5.0V mixed voltage
operation and is designed to tolerate 5.0V inputs in each
case (Table 2). Power consumption is extremely low due to
the very short distances signals are required to travel to
complete a circuit. Power requirements are further reduced
because of the small number of low-resistance antifuses in
the path. The antifuse architecture does not require active
circuitry to hold a charge (SRAM or EPROM do), making it
the lowest-power architecture FPGA available today.
Table 1 •I/O Features
Function Description
Input Buf fer
Threshold
Selections
•LVTT L/5.0 V PCI/TTL
•3.3V PCI
Flexible
Output
Driver
•2.5V/3.3V LVTTL
•3.3V PCI
•5.0V CMOS
•5.0V PCI/TTL
Output
Buffer “Hot-Swap” Capability
•I/O on an unpowered device does not
sink current
•Can be used for “cold-sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power-Up Individually selectable pull-ups and
pull-downs during power up (default is to
power up in tristate)
Enables deterministic power up of device
VCCA and VCCI can be powered in any order
Table 2 •Supply Voltages
VCCA VCCI
Maximum
Input
Tolerance
Maximum
Output
Drive
A54SX08A
A54SX16A
A54SX32A
A54SX72A
2.5V 2.5V 5.0V 2.5V
2.5V 3.3V 5.0V 3.3V
2.5V 5.0V 5.0V 5.0V
SX-A Family FPGAs
10 v3.0
Boundary Scan Testing (BST)
All SX-A devices are IEEE 1149.1 compliant. SX-A devices
offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in Table 3. In the
dedicated test mode, TCK, TDI and TDO are dedicated pins
and cannot be used as regular I/Os. In flexible mode, TMS
should be set HIGH through a pull-up resistor of 10kΩ. TMS
can be pulled LOW to initiate the test sequence.
Configuring Diagnostic Pins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel's Designer software.
TRST pin
When the “Reserve JTAG Reset” box is checked (default
setting in Designer software), the TRST pin will become a
Boundary Scan Reset pin. In this mode, the TRST pin will
function as an asynchronous, active-low input to initialize or
reset the BST circuit. An internal pull-up resistor will be
automatically enabled on the TRST pin.
The TRST pin will function as a user I/O when “Reserve
JTAG Reset” box is not checked. The internal pull-up
resistor will be disabled in this mode.
Dedicated Test mode
When the “Reserve JTAG” box is checked, the SX-A is placed
in Dedicated Test mode, which configures the TDI, TCK, and
TDO pins for BST or in-circuit verification with Silicon
Explorer II. An internal pull-up resistor is automatically
enabled on both the TMS and TDI pins. In Dedicated test
mode, TCK, TDI, and TDO are dedicated test pins and
become unavailable for pin assignment in the Pin Editor.
The TMS pin will function as specified in the IEEE 1149.1
(JTAG) Specification.
Flexible mode
When the “Reserve JTAG” box is not selected (default
setting in Designer software), the SX-A is placed in Flexible
mode, which allows the TDI, TCK, and TDO pins to function
as user I/Os or BST pins. In this mode the internal pull-up
resistors on the TMS and TDI pins are disabled. An external
10kΩ pull-up resistor to VCCI is required on the TMS pin.
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set to logical HIGH.
The Program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
Development Tool Support
The SX-A devices are fully supported by Actel’s line of FPGA
development tools, including the Actel Designer Series suite
and Libero, the FPGA design tool suite. Designer Series,
Actel’s suite of FPGA development tools for PCs and
Workstations, includes the ACTgen Macro Builder, timing
driven place-and-route, timing analysis tools, and fuse file
generation. Libero is a design management environment
that integrates the needed design tools, streamlines the
design flow, manages all design and log files, and passes
necessary design data between tools. Libero includes,
Synplify, ViewDraw, Actel’s Designer Series, ModelSim HDL
Simulator, WaveFormer Lite, and Actel Silicon Explorer.
In addition, the SX-A devices contain internal probe
circuitry that provides built-in access to the output of every
C-cell, R-cell, and routed clock in the design, enabling
100-percent real-time observation and analysis of a device's
internal logic nodes without design iteration. The probe
circuitry is accessed by Silicon Explorer II, an easy-to-use
integrated verification and logic analysis tool that can
sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
SX-A Probe Circuit Control Pins
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 10 on page 11
illustrates the interconnection between Silicon Explorer II
and the FPGA to perform in-circuit verification. The TRST
pin is equipped with an internal pull-up resistor. To remove
the boundary scan state machine from the reset state during
probing, it is recommended that the TRST pin be left
floating.
Table 3 •Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode) Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated BST pins T CK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor
for TMS Use a pull-up resistor of
10kΩ on TMS
v3.0 11
SX-A Family FPGAs
Design Considerations
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the security fuse should not be programmed
during prototyping because doing so disables the probe
circuitry.
2.5V/3.3V/5.0V Operating Conditions
Figure 10 •Probe Setup
Absolute Maximum Ratings1
Symbol Parameter Limits Units
VCCI DC Supply V olta ge –0.3 to +6.0 V
VCCA DC Supply V olta ge –0.3 to +3.0 V
VIInput Voltage –0.5 to +5.5 V
VOOutput Voltage –0.5 to +VCCI + 0.5 V
TSTG Storage Temperature –65 to +150 °C
Note:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute
maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the Recommended
Operating Conditions.
Recommended Operating Conditions
Parameter Commercial Industrial Military Units
Temperature Range10 to +70 –40 to +85 –55 to +125 °C
2.5V Power Supply Range 2.25 to 2.75 2.25 to 2.75 2.25 to 2.75 VCCI
3.3V Power Supply Range 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 VCCI
5.0V Power Supply Range 4.5 to 5.5 4.5 to 5.5 4.5 to 5.5 VCCI
Note:
1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used
for military.
Silicon Explorer II
TDI
TCK
TDO
TMS
PRA
PRB
Serial Connection
16
Additional
Channels
SX-A FPGA
SX-A Family FPGAs
12 v3.0
3.3V and 5.0V Electrical Specifications
2.5V Electrical Specifications
Symbol
Commercial Industrial
Parameter Min. Max. Min. Max. Units
VOH
VDD = MIN,
VI = VIH or VIL
(IOH = -1mA) 0.9 VCCI 0.9 VCCI V
VDD = MIN,
VI = VIH or VIL
(IOH = -8mA) 2.4 2.4 V
VOL
VDD = MIN,
VI = VIH or VIL
(IOL= 1mA) 0.1 VCCI 0.1 VCCI V
VDD = MIN,
VI = VIH or VIL
(IOL= 12mA) 0.4 0.4 V
VIL Input Low Voltage 0.8 0.8 V
VIH Input High Voltage 2.0 2.0 V
IIL/ IIH Input Leakage Current, VIN = VCCI or GND –10 10 –10 10 µA
IOZ 3-State Output Leakage Current, VOUT = VCCI or GND –10 10 –10 10 µA
tR, tFInput Transition Time tR, tF10 10 ns
CIO I/O Capacitance 10 10 pF
ICC Standby Current 10 20 mA
IV Curve1Can be derived from the IBIS model on the web.
Note:
1. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.
Symbol
Commercial Industrial
Parameter Min. Max. Min. Max. Units
VOH
VDD = MIN,
VI = VIH or VIL
(IOH = -100µA) 2.1 2.1 V
VDD = MIN,
VI = VIH or VIL
(IOH = -1 mA) 2.0 2. 0 V
VDD = MIN,
VI = VIH or VIL
(IOH = -2 mA) 1.7 1. 7 V
VOL
VDD = MIN,
VI = VIH or VIL
(IOL= 100µA) 0.2 0.2 V
VDD = MIN,
VI = VIH or VIL
(IOL= 1mA) 0.4 0.4 V
VDD = MIN,
VI = VIH or VIL
(IOL= 2 mA) 0.7 0.7 V
VIL Input Low Voltage, VOUT ≤ VVOL(max) -0.3 0.7 -0.3 0.7 V
VIH Input High Voltage, VOUT ≥ VVOH(min) 1.7 VDD + 0.3 1 .7 VDD + 0.3 V
IOZ 3-State Output Leakage Current, VOUT = VCCI or GND –10 10 –10 10 µA
tR, tFInput Tr ansition Time tR, tF10 10 ns
CIO I/O Capacitance 10 10 pF
ICC Standby Current 10 20 mA
IV Curve1Can be derived from the IBIS model on the web.
Note:
1. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.
v3.0 13
SX-A Family FPGAs
PCI Compliance for the SX-A Family
The SX-A family supports 3.3V and 5.0V PCI and is
compliant with the PCI Local Bus Specification Rev. 2.1.
DC Specifications (5.0V PCI Operation)
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 2.3 2.7 V
VCCI Supply Voltage for I/Os 4.75 5.25 V
VIH Input High Voltage 2.0 VCCI + 0.5 V
VIL Input Low Voltage –0.5 0.8 V
IIH Input High Leakage Current1VIN = 2.7 70 µA
IIL Input Low Leakage Current1VIN = 0.5 –70 µA
VOH Output High Voltage IOUT = –2 mA 2.4 V
VOL Output Low Voltage2IOUT = 3 mA, 6 mA 0.55 V
CIN Input Pin Capacitance310 pF
CCLK CLK Pin Cap acitance 5 12 pF
Notes:
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter includes,
FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
SX-A Family FPGAs
14 v3.0
AC Specifications (5.0V PCI Operation)
Symbol Parameter Condition Min. Max. Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 1.4 1–44 mA
1.4 ≤ VOUT < 2.4 1, 2 (–44 + (VOUT – 1.4)/0.024) mA
3.1 < VOUT < VCCI 1, 3 E quation A
on page 15
(Test Point) VOUT = 3.1 3–142 mA
IOL(AC)
Switching Current Low VOUT ≥ 2.2 195 mA
2.2 > VOUT > 0 .55 1(VOUT/0.023) mA
0.71 > VOUT > 0 1, 3 Equat ion B
on page 15
(Test Point) VOUT = 0.71 3206 mA
ICL Low Clamp Current –5 < VIN ≤ –1–25 + (VIN + 1)/0.015 mA
slewROutput Rise Slew Rate 0.4V to 2.4V load 415V/ns
slewFOutput Fall Slew Rate 2.4V to 0.4V load 415V/ns
Notes:
1. Refer to the V/I curves in Figure 11 on page 15. Switching current characteristics for REQ# and GNT# are permitted to be one half of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain
outputs.
2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the
voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up.
3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B)
are provided with the respective diagrams in Figure 11 on page 15. The equation defined maxima should be met by design. In order to
facilitate component testing, a maximum current test point is defined for each side of the output driver.
4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is
now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to
revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard
designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity
modeling accounts for this. Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
50 pF
pin
v3.0 15
SX-A Family FPGAs
Figure 11 shows the 5.0V PCI V/I curve and the minimum
and maximum PCI drive characteristics of the SX-A
family.
Equation A
IOH = 11.9 * (VOUT – 5.25) * (VOUT + 2.45)
for VCCI > VOUT > 3.1V
Equation B
IOL = 78.5 * VOUT * (4.4 – VOUT)
for 0V < VOUT < 0.71V
DC Specifications (3.3V PCI Operation)
Figure 11 •5.0V PCI V/I Curve for SX-A Family
–200.0
–150.0
–100.0
–50.0
0.0
50.0
100.0
150.0
200.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Voltage Out (V)
Current (mA)
IOH
IOL
IOH MIN Spec
IOH MAX Spec
IOL MIN Spec
IOL MAX Spec
Symbol Parameter Condition Min. Max. Units
VCCA Supply Voltage for Array 2.3 2.7 V
VCCI Supply Voltage for I/Os 3.0 3.6 V
VIH Input High Voltage 0.5VCCI VCCI + 0.5 V
VIL Input Low Voltage –0.5 0.3VCCI V
IIPU Input Pull-up Voltage10.7VCCI V
IIL Input Leakage Current20 < VIN < VCCI –10 +10 µA
VOH Output High Voltage IOUT = –500 µA 0.9VCCI V
VOL Output Low Voltage IOUT = 1500 µA 0.1VCCI V
CIN Input Pin Capacitance310 pF
CCLK CLK Pin Cap acitance 5 12 pF
Notes:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated
network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input
voltage.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
SX-A Family FPGAs
16 v3.0
AC Specifications (3.3V PCI Operation)
Symbol Parameter Condition Min. Max. Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VCCI 1–12VCCI mA
0.3VCCI ≤ VOUT < 0.9VCCI 1(–17.1 + (VCCI – VOUT)) mA
0.7VCCI < VOUT < VCCI 1, 2 Equation C
on page 17
(Test Point) VOUT = 0.7VCC 2–32VCCI mA
IOL(AC)
Switching Current Low
VCCI > VOUT ≥ 0.6VCCI 116VCCI mA
0.6VCCI > VOUT > 0.1VCCI 1(26.7VOUT)mA
0.18VCCI > VOUT > 0 1, 2 Equa tion D
on page 17
(Test Point) VOUT = 0.18VCC 2 38VCCI mA
ICL Low Clamp Current –3 < VIN ≤ –1–25 + (V IN + 1)/0.015 mA
ICH High Clamp Current VCCI + 4 > VIN ≥ VCCI + 1 25 + (VIN – VCCI – 1)/0.015 mA
slewROutput Rise Slew Rate 0.2VCCI to 0.6VCCI load 314V/ns
slewFOutput Fall Slew Rate 0.6VCCI to 0.2VCCI load 314V/ns
Notes:
1. Refer to the V/I curves in Figure 12 on page 17. Switching current characteristics for REQ# and GNT# are permitted to be one half of that
specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are
system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain
outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D)
are provided with the respective diagrams in Figure 12 on page 17. The equation defined maxima should be met by design. In order to
facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point
within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an
unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum
parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
output
buffer
1/2 in. max.
10 pF
1k/25Ω
pin
1k/25Ω
pin
buffer
output
10 pF
v3.0 17
SX-A Family FPGAs
Figure 12 shows the 3.3V PCI V/I curve and the minimum
and maximum PCI drive characteristics of the SX-A family.
Equation C
IOH = (98.0/VCCI) * (VOUT – VCCI) * (VOUT + 0.4VCCI)
for 0.7 VCCI < VOUT < VCCI
Equation D
IOL = (256/VCCI) * VOUT * (VCCI – VOUT)
for 0V < VOUT < 0.18 VCCI
Figure 12 •3.3V PCI V/I Curve for SX-A Family
–150.0
–100.0
–50.0
0.0
50.0
100.0
150.0
0 0.5 1 1.5 2 2.5 3 3.5 4
Voltage Out (V)
Current (mA)
IOH
IOL
IOH MIN Spec
IOH MAX Spec
IOL MIN Spec
IOL MAX Spec
SX-A Family FPGAs
18 v3.0
Junction Temperature (TJ)
The temperature variable in the Designer Series software
refers to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is usually
hotter than the ambient temperature. Equation 9, shown
below, can be used to calculate junction temperature.
Junction Temperature = ∆T + Ta(9)
Where:
Ta = Ambient Temperature
∆T = Temperature gradient between junction (silicon) and
ambient
∆T = θja * P (10)
P = Power
θja = Junction to ambient of package. θja numbers are
located in the Package Thermal Characteristics table below.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
The maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 176-pin package at
commercial temperature and still air is as follows:
Package Thermal Characteristics
Package Type Pin Count θjc
θja
Still Air θja
300 ft/min Units
Thin Quad Flat Pack (TQFP ) 100 12 37.5 30 °C/W
Thin Quad Flat Pack (TQFP ) 144 11 32 24 °C/W
Thin Quad Flat Pack (TQFP ) 176 11 28 21 °C/W
Plastic Quad Flat Pack (PQFP)1208 8 30 23 °C/W
Plastic Quad Flat Pack (PQFP) with Heat Spreader2208 3.8 20 17 °C/W
Plastic Ball Grid Array (PBGA) 329 3 18 13.5 °C/W
Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 °C/W
Fine Pitch Ball Grid Array (FBGA) 256 3.3 3 0 25 °C/W
Fine Pitch Ball Grid Array (FBGA) 484 3 20 15 °C/W
1. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.
2. The A54SX08A PQ208 has no heat spreader.
Maximum Power Allowed Max. junction temp. ( °C) Max. ambient temp. (°C)–
θja(°C/W)
--------------------------------------------------------------------------------------------------------------------------------- 150°C70°C–
28°C/W
-----------------------------------2.86W===
v3.0 19
SX-A Family FPGAs
SX-A Timing Model*
Hard-Wired Clock
External Setup = (tINYH + tRD1 + tSUD) – tHCKL
= 0.5 + 0.3 + 0.7 – 1.0 = 0.5 ns
Clock-to-Out (Pad-to-Pad)
=t
HCKL + tRCO + tRD1 + tDHL
= 1.0 + 0.6 + 0.3 + 2.0= 3.9 ns
Routed Clock
External Setup = (tINYH + tRD1 + tSUD) – tRCKH
= 0.5 + 0.3 + 0.7– 1.1= 0.4 ns
Clock-to-Out (Pad-to-Pad)
=t
RCKH + tRCO + tRD1 + tDHL
= 1.1+ 0.6 + 0.3 + 2.0 = 4.0 ns
*Values shown for A54SX08A–3, worst-case commercial conditions at 3.3V PCI, with standard place-and-route.
Output DelaysInternal DelaysInput Delays
Hard-Wired
I/O Module
FHMAX = 350 MHz
tINYH = 0.5 ns tIRD2 = 0.4 ns
Combinatorial
Cell
tPD =0.8ns
Register
Cell
I/O Module
tRD1 = 0.3 ns tDHL = 2.0 ns
I/O Module
Routed
Clock
FMAX = 250 MHz
DQDQ
tDHL = 2.0 ns
tENZL = 1.4 ns
tRD1 = 0.3 ns
tRCO = 0.6 ns
tSUD = 0.7 ns
tHD = 0.0 ns
tRD4 = 0.7 ns
tRD8 = 1.2 ns
Predicted
Routing
Delays
tRCKH = 1.1 ns
tRD1 = 0.3 ns
Register
Cell
tRCO = 0.6 ns
Clock tHCKL = 1.0 ns