Si8660/61/62/63 Data Sheet
Low Power Six-Channel Digital Isolator
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and
5 kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products >1 kVRMS are safety certified by UL, CSA, VDE, and CQC, and
products in wide-body packages support reinforced insulation withstanding up to 5
kVRMS.
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
KEY FEATURES
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage
2.5–5.5 V
Up to 5000 VRMS isolation
60-year life at rated working voltage
High electromagnetic immunity
Ultra low power (typical)
5 V Operation
1.6 mA per channel at 1 Mbps
5.5 mA per channel at 100 Mbps
2.5 V Operation
1.5 mA per channel at 1 Mbps
3.5 mA per channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output (ordering
option)
Precise timing (typical)
10 ns propagation delay
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient Immunity 50 kV/µs
AEC-Q100 qualification
Wide temperature range
–40 to 125 °C
RoHS-compliant packages
SOIC-16 wide body
SOIC-16 narrow body
QSOP-16
Automotive-grade OPNs available
AIAG compliant PPAP documentation
support
IMDS and CAMDS listing support
Industrial Applications
Industrial automation systems
Medical electronics
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
Safety Regulatory Approvals
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 62368-1, 60601-1 (re-
inforced insulation)
VDE certification conformity
VDE 0884-10
EN60950-1 (reinforced insulation)
CQC certification approval
GB4943.1
Automotive Applications
On-board chargers
Battery management systems
Charging stations
Traction inverters
Hybrid Electric Vehicles
Battery Electric Vehicles
silabs.com | Building a more connected world. Rev. 1.72
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs 1,2, 3
Ordering Part Num-
ber (OPN)
Number of
Inputs
VDD1 Side
Number of
Inputs
VDD2 Side
Max Data
Rate
(Mbps)
Default
Output
State
Isolation Rating
(kV)
Temp (°C) Package
QSOP-16 Packages
Si8660BB-B-IU 6 0 150 Low 2.5 –40 to 125 °C QSOP-16
Si8660EB-B-IU 6 0 150 High 2.5 –40 to 125 °C QSOP-16
Si8661BB-B-IU 5 1 150 Low 2.5 –40 to 125 °C QSOP-16
Si8661EB-B-IU 5 1 150 High 2.5 –40 to 125 °C QSOP-16
Si8662BB-B-IU 4 2 150 Low 2.5 –40 to 125 °C QSOP-16
Si8662EB-B-IU 4 2 150 High 2.5 –40 to 125 °C QSOP-16
Si8663BB-B-IU 3 3 150 Low 2.5 –40 to 125 °C QSOP-16
Si8663EB-B-IU 3 3 150 High 2.5 –40 to 125 °C QSOP-16
SOIC-16 Packages
Si8660BA-B-IS1 6 0 150 Low 1.0 –40 to 125 °C NB SOIC-16
Si8660BB-B-IS1 6 0 150 Low 2.5 –40 to 125 °C NB SOIC-16
Si8660BC-B-IS1 6 0 150 Low 3.75 –40 to 125 °C NB SOIC-16
Si8660EC-B-IS1 6 0 150 High 3.75 –40 to 125 °C NB SOIC-16
Si8660BD-B-IS 6 0 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8660ED-B-IS 6 0 150 High 5.0 –40 to 125 °C WB SOIC-16
Si8661BB-B-IS1 5 1 150 Low 2.5 –40 to 125 °C NB SOIC-16
Si8661BC-B-IS1 5 1 150 Low 3.75 –40 to 125 °C NB SOIC-16
Si8661EC-B-IS1 5 1 150 High 3.75 –40 to 125 °C NB SOIC-16
Si8661BD-B-IS 5 1 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8661ED-B-IS 5 1 150 High 5.0 –40 to 125 °C WB SOIC-16
Si8661BD-B-IS2 5 1 150 Low 5.0 –40 to 125 °C WB SOIC-16
(8 mm cree-
page)4
Si8662BB-B-IS1 4 2 150 Low 2.5 –40 to 125 °C NB SOIC-16
Si8662BC-B-IS1 4 2 150 Low 3.75 –40 to 125 °C NB SOIC-16
Si8662EC-B-IS1 4 2 150 High 3.75 –40 to 125 °C NB SOIC-16
Si8662BD-B-IS 4 2 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8662ED-B-IS 4 2 150 High 5.0 –40 to 125 °C WB SOIC-16
Si8663BB-B-IS1 3 3 150 Low 2.5 –40 to 125 °C NB SOIC-16
Si8663BC-B-IS1 3 3 150 Low 3.75 –40 to 125 °C NB SOIC-16
Si8663EC-B-IS1 3 3 150 High 3.75 –40 to 125 °C NB SOIC-16
Si8663BD-B-IS 3 3 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8660/61/62/63 Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 1.72 | 2
Ordering Part Num-
ber (OPN)
Number of
Inputs
VDD1 Side
Number of
Inputs
VDD2 Side
Max Data
Rate
(Mbps)
Default
Output
State
Isolation Rating
(kV)
Temp (°C) Package
Si8663ED-B-IS 3 3 150 High 5.0 –40 to 125 °C WB SOIC-16
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. The package designated IS2 has a design that eliminates tie bars, thus allowing for extra creepage distance while maintaining
standard WB SOIC-16 package dimensions and land pattern.
Si8660/61/62/63 Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 1.72 | 3
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part
Number (OPN)
Number of
Inputs
VDD1 Side
Number of
Inputs
VDD2 Side
Max Data
Rate
(Mbps)
Default
Output
State
Isolation rating
(kV)
Temp (°C) Package
SOIC-16 Packages
Si8660BC-AS1 6 0 150 Low 3.75 –40 to 125 °C NB SOIC-16
Si8660BD-AS 6 0 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8661BB-AS1 5 1 150 Low 2.5 –40 to 125 °C NB SOIC-16
Si8661BD-AS 5 1 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8662BB-AS1 4 2 150 Low 2.5 –40 to 125 °C NB SOIC-16
Si8662BC-AS1 4 2 150 Low 3.75 –40 to 125 °C NB SOIC-16
Si8662BD-AS 4 2 150 Low 5.0 –40 to 125 °C WB SOIC-16
Si8663BD-AS 3 3 150 Low 5.0 –40 to 125 °C WB SOIC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
Si8660/61/62/63 Data Sheet
Ordering Guide
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Table of Contents
1. Ordering Guide ..............................2
2. Functional Description............................6
2.1 Theory of Operation ............................6
2.2 Eye Diagram...............................7
3. Device Operation ..............................8
3.1 Device Startup ..............................8
3.2 Undervoltage Lockout ...........................9
3.3 Layout Recommendations ..........................9
3.3.1 Supply Bypass ............................9
3.3.2 Output Pin Termination..........................9
3.4 Fail-Safe Operating Mode ..........................9
3.5 Typical Performance Characteristics.......................10
4. Electrical Specifications ..........................12
5. Pin Descriptions .............................28
6. Package Outline (16-Pin Wide Body SOIC) ...................29
7. Land Pattern (16-Pin Wide-Body SOIC)..................... 31
8. Package Outline (16-Pin Narrow Body SOIC) ..................32
9. Land Pattern (16-Pin Narrow Body SOIC) ....................34
10. Package Outline (16-Pin QSOP) .......................35
11. Land Pattern (16-Pin QSOP) ........................37
12. Top Marking (16-Pin Wide Body SOIC) ....................38
13. Top Marking (16-Pin Narrow Body SOIC) ...................39
14. Top Marking (16-Pin QSOP) ........................40
15. Revision History............................. 41
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2. Functional Description
2.1 Theory of Operation
The operation of an Si866x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si866x channel is shown in the figure below.
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Output Signal
Modulation Signal
Figure 2.2. Modulation Scheme
Si8660/61/62/63 Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.72 | 6
2.2 Eye Diagram
The figure below illustrates an eye-diagram taken on an Si8660. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8660 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
Si8660/61/62/63 Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.72 | 7
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 9, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to
determine outputs when power supply (VDD) is not present.
Table 3.1. Si866x Logic Operation
VI Input 1,2 VDDI State1,3,4 VDDO State1,3,4 VO Output1,2 Comments
H P P H Normal operation.
L P P L
X 5UP P L6
H6
Upon transition of VDDI from unpowered to pow-
ered, VO returns to the same state as VI in less
than 1 µs.
X5P UP Undetermined Upon transition of VDDO from unpowered to pow-
ered, VO returns to the same state as VI within 1
µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See 1. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default
output state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devi-
ces, the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/
outputs.
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
Si8660/61/62/63 Data Sheet
Device Operation
silabs.com | Building a more connected world. Rev. 1.72 | 8
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
INPUT
VDD1
UVLO-
VDD2
UVLO+
UVLO-
UVLO+
OUTPUT
tSTART tSTART tSTART tPHL tPLH
tSD
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.5 Regulatory Information 1 on
page 23 and Table 4.6 Insulation and Safety-Related Specifications on page 23 detail the working voltage and creepage/clearance
capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted
by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1,
60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si866x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series
with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3.4 Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si866x Logic Operation on page 8 and
1. Ordering Guide for more information.
Si8660/61/62/63 Data Sheet
Device Operation
silabs.com | Building a more connected world. Rev. 1.72 | 9
3.5 Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to the electrical
characteristics tables for actual specification limits.
Figure 3.2. Si8660 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
Figure 3.3. Si8661 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 3.4. Si8662 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 3.5. Si8660 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
Si8660/61/62/63 Data Sheet
Device Operation
silabs.com | Building a more connected world. Rev. 1.72 | 10
Figure 3.6. Si8661 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 3.7. Si8662 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
(15 pF Load)
Figure 3.8. Si8663 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 3.9. Propagation Delay vs. Temperature
Si8660/61/62/63 Data Sheet
Device Operation
silabs.com | Building a more connected world. Rev. 1.72 | 11
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Junction Operating Temperature TJ 150 °C
Ambient Operating Temperature 1TA–40 25 125 °C
Supply Voltage
VDD1 2.375 5.5 V
VDD2 2.375 5.5 V
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Undervoltage
Hysteresis VDDHYS 50 70 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going
Input Threshold VT– All inputs falling 1.0 1.23 1.4 V
Input Hysteresis VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 V
Low Level Output Voltage VOL lol = 4 mA 0.2 0.4 V
Input Leakage Current IL ±10 µA
Output Impedance 1ZO 50 Ω
DC Supply Current (All Inputs 0 V or at Supply)
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
mA
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 12
Parameter Symbol Test Condition Min Typ Max Unit
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
mA
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
mA
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on all Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
4.2
7.0
5.9
mA
Si8661Bx, Ex
VDD1
VDD2
4.9
4.6
6.9
6.4
mA
Si8662Bx, Ex
VDD1
VDD2
5.1
4.7
7.1
6.6
mA
Si8663Bx, Ex
VDD1
VDD2
4.9
4.9
6.8
6.8
mA
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on all Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
5.9
7.0
8.3
mA
Si8661Bx, Ex
VDD1
VDD2
5.2
6.1
7.3
8.5
mA
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 13
Parameter Symbol Test Condition Min Typ Max Unit
Si8662Bx, Ex
VDD1
VDD2
5.6
5.9
7.9
8.2
mA
Si8663Bx, Ex
VDD1
VDD2
5.7
5.7
8.0
8.0
mA
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
26.2
7.0
34.1
mA
Si8661Bx, Ex
VDD1
VDD2
8.8
23
11.8
29.8
mA
Si8662Bx, Ex
VDD1
VDD2
12.8
19.4
16.6
25.2
mA
Si8663Bx, Ex
VDD1
VDD2
16.4
16.4
21.3
21.3
mA
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate 0 150 Mbps
Minimum Pulse Width 5.0 ns
Propagation Delay tPHL, tPLH See Figure 4.1 Propagation
Delay Timing on page 15 5.0 8.0 13 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 4.1 Propagation
Delay Timing on page 15 0.2 4.5 ns
Propagation Delay Skew 2 tPSK(P-P) 2.0 4.5 ns
Channel-Channel Skew tPSK 0.4 2.5 ns
All Models
Output Rise Time tr
CL = 15 pF
(See Figure 4.1 Propagation
Delay Timing on page 15)
2.5 4.0 ns
Output Fall Time tf
CL = 15 pF
(See Figure 4.1 Propagation
Delay Timing on page 15)
2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See 350 ps
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 14
Parameter Symbol Test Condition Min Typ Max Unit
Common Mode
Transient Immunity CMTI
VI = VDD or 0 V
VCM = 1500 V
(See Figure 4.2 Common
Mode Transient Immunity
Test Circuit on page 16)
35 50 kV/µs
Startup Time 3tSU 15 40 µs
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Typical
Input
tPLH tPHL
Typical
Output
trtf
90%
10%
90%
10%
1.4 V
1.4 V
Figure 4.1. Propagation Delay Timing
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 15
Oscilloscope
3 to 5 V
Isolated
Supply
Si86xx
VDD2
OUTPUT
3 to 5 V
Supply
High Voltage
Surge Generator
Vcm Surge
Output
High Voltage
Differential
Probe
GND2GND1
VDD1
INPUT
Input
Signal
Switch
Input
Output
Isolated
Ground
Figure 4.2. Common Mode Transient Immunity Test Circuit
Table 4.3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V
Input Hysteresis VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 V
Low Level Output Voltage VOL lol = 4 mA 0.2 0.4 V
Input Leakage Current IL ±10 µA
Output Impedance ZO 50 Ω
DC Supply Current (All Inputs 0 V or at Supply)
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 16
Parameter Symbol Test Condition Min Typ Max Unit
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
mA
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
mA
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
mA
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
4.2
7.0
5.9
mA
Si8661Bx, Ex
VDD1
VDD2
4.9
4.6
6.9
6.4
mA
Si8662Bx, Ex
VDD1
VDD2
5.1
4.7
7.1
6.6
mA
Si8663Bx, Ex
VDD1
VDD2
4.9
4.9
6.8
6.8
mA
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 17
Parameter Symbol Test Condition Min Typ Max Unit
Si8660Bx, Ex
VDD1
VDD2
5.0
5.0
7.0
7.0
mA
Si8661Bx, Ex
VDD1
VDD2
5.0
5.3
7.0
7.4
mA
Si8662Bx, Ex
VDD1
VDD2
5.3
5.2
7.4
7.3
mA
Si8663Bx, Ex
VDD1
VDD2
5.2
5.2
7.3
7.3
mA
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
18.3
7.0
23.8
mA
Si8661Bx, Ex
VDD1
VDD2
7.4
16.4
9.9
21.3
mA
Si8662Bx, Ex
VDD1
VDD2
10
14.1
13
18.3
mA
Si8663Bx, Ex
VDD1
VDD2
12.3
12.3
15.9
15.9
mA
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate 0 150 Mbps
Minimum Pulse Width 5.0 ns
Propagation Delay tPHL, tPLH See Figure 4.1 Propagation
Delay Timing on page 15 5.0 8.0 13 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 4.1 Propagation
Delay Timing on page 15 0.2 4.5 ns
Propagation Delay Skew 2tPSK(P-P) 2.0 4.5 ns
Channel-Channel Skew tPSK 0.4 2.5 ns
All Models
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 18
Parameter Symbol Test Condition Min Typ Max Unit
Output Rise Time tr
CL = 15 pF
See Figure 4.1 Propagation
Delay Timing on page 15
2.5 4.0 ns
Output Fall Time tf
CL = 15 pF
See Figure 4.1 Propagation
Delay Timing on page 15
2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 2.3 Eye Diagram
on page 7 350 ps
Common Mode Transient
Immunity CMTI
VI = VDD or 0 V
VCM = 1500 V (See Figure
4.2 Common Mode Transi-
ent Immunity Test Circuit on
page 16)
35 50 kV/µs
Startup Time 3tSU 15 40 µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 19
Table 4.4. Electrical Characteristics
(VDD1 = 2.5 V ±5%, VDD2 = 2.5 V ±5%, TA = –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V
VDD Undervoltage Threshold VDDUV– VDD1, VDD2 falling 1.88 2.16 2.325 V
VDD Undervoltage
Hysteresis VDDHYS 50 70 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.0 1.23 1.4 V
Input Hysteresis VHYS 0.38 0.44 0.50 V
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 2.3 V
Low Level Output Voltage VOL lol = 4 mA 0.2 0.4 V
Input Leakage Current IL ±10 µA
Output Impedance1ZO 50 Ω
DC Supply Current (All Inputs 0 V or at Supply)
Si8660Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.2
3.5
8.8
3.7
1.9
5.3
12.3
5.6
mA
Si8661Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
1.7
3.4
7.9
4.8
2.7
5.1
11.1
7.2
mA
Si8662Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.2
3.0
7.5
5.6
3.3
4.5
10.5
8.4
mA
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 20
Parameter Symbol Test Condition Min Typ Max Unit
Si8663Bx, Ex
VDD1
VDD2
VDD1
VDD2
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
2.6
2.6
6.5
6.5
3.9
3.9
9.1
9.1
mA
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
4.2
7.0
5.9
mA
Si8661Bx, Ex
VDD1
VDD2
4.9
4.6
6.9
6.4
mA
Si8662Bx, Ex
VDD1
VDD2
5.1
4.7
7.1
6.6
mA
Si8663Bx, Ex
VDD1
VDD2
4.9
4.9
6.8
6.8
mA
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
4.6
7.0
6.4
mA
Si8661Bx, Ex
VDD1
VDD2
5.0
4.9
6.9
6.9
mA
Si8662Bx, Ex
VDD1
VDD2
5.2
4.9
7.2
6.9
mA
Si8663Bx, Ex
VDD1
VDD2
5.0
5.0
7.0
7.0
mA
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8660Bx, Ex
VDD1
VDD2
5.0
14.7
7.0
19.1
mA
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 21
Parameter Symbol Test Condition Min Typ Max Unit
Si8661Bx, Ex
VDD1
VDD2
6.7
13.4
9.1
17.4
mA
Si8662Bx, Ex
VDD1
VDD2
8.7
11.7
11.3
15.2
mA
Si8663Bx, Ex
VDD1
VDD2
10.3
10.3
13.4
13.4
mA
Timing Characteristics
Si866xBx, Ex
Maximum Data Rate 0 150 Mbps
Minimum Pulse Width 5.0 ns
Propagation Delay tPHL, tPLH See Figure 4.1 Propagation
Delay Timing on page 15 5.0 8.0 14 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 4.1 Propagation
Delay Timing on page 15 0.2 5.0 ns
Propagation Delay Skew2tPSK(P-P) 2.0 5.0 ns
Channel-Channel Skew tPSK 0.4 2.5 ns
All Models
Output Rise Time tr
CL = 15 pF
See Figure 4.1 Propagation
Delay Timing on page 15
2.5 4.0 ns
Output Fall Time tf
CL = 15 pF
See Figure 4.1 Propagation
Delay Timing on page 15
2.5 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 2.3 Eye Diagram
on page 7 350 ps
Common Mode
Transient Immunity CMTI
VI = VDD or 0 V
VCM = 1500 V
(See Figure 4.2 Common
Mode Transient Immunity
Test Circuit on page 16)
35 50 kV/µs
Startup Time3tSU 15 40 µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 22
Table 4.5. Regulatory Information 1
CSA
The Si866x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si866x is certified according to VDE 0884-10. For more details, see certificate 40018443.
0884-10: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si866x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si866x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-
cations apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see 1. Ordering Guide.
Table 4.6. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition
Value
Unit
WB SOIC-16 NB SOIC-16 QSOP-16
Nominal External Air Gap (Clearance)1CLR 8.0 4.9 3.6 mm
Nominal External Tracking (Creepage) 1 CPG 8.0 4.01 3.6 mm
Minimum Internal Gap
(Internal Clearance)
DTI 0.014 0.014 0.014 mm
Tracking Resistance CTI or PTI IEC60112 600 600 600 VRMS
Erosion Depth ED 0.019 0.019 0.031 mm
Resistance (Input-Output)2RIO 1012 1012 1012 Ω
Capacitance (Input-Output)2CIO f = 1 MHz 2.0 2.0 2.0 pF
Input Capacitance3CI4.0 4.0 4.0 pF
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 23
Parameter Symbol Test Condition
Value
Unit
WB SOIC-16 NB SOIC-16 QSOP-16
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 package and QSOP-16 packages and 8.5 mm minimum for the WB SOIC-16
package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance
and creepage of the WB SOIC-16 package with designation "IS2" as 8 mm minimum. CSA certifies the clearance and creepage
limits as 3.9 mm minimum for the NB SOIC 16, 3.6 mm minimum for the QSOP-16, and 7.6 mm minimum for the WB SOIC-16
package with package designation "IS" as listed in the data sheet.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form
the first termina and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between
these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 Ratings
Parameter Test Conditions
Specification
WB SOIC-16 NB SOIC-16 QSOP-16
Basic Isolation Group Material Group I I I
Installation Classification
Rated Mains Voltages < 150
VRMS I-IV I-IV I-IV
Rated Mains Voltages < 300
VRMS I-IV I-III I-III
Rated Mains Voltages < 400
VRMS I-III I-II I-II
Rated Mains Voltages < 600
VRMS I-III I-II I-II
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 24
Table 4.8. VDE 0884-10 Insulation Characteristics for Si86xxxx1
Parameter Symbol Test Condition
Characteristic
Unit
WB SOIC-16 NB SOIC-16 QSOP-16
Maximum Working Insulation
Voltage VIORM 1200 630 630 Vpeak
Input to Output Test Voltage VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
2250 1182 1182 Vpeak
Transient Overvoltage VIOTM t = 60 sec 6000 6000 6000 Vpeak
Surge Voltage VIOSM
Tested per IEC 60065 with surge
voltage of 1.2 µs/50 µs
Si866xxB/C/D tested with 4000 V 3077 3077 3077
Vpeak
Pollution Degree
(DIN VDE 0110, Table 1)
2 2 2
Insulation Resistance at TS, VIO
= 500 V RS>109>109>109Ω
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. VDE 0884-10 Safety Limiting Values1
Parameter Symbol Test Condition
Max
Unit
WB SOIC-16 NB SOIC-16 QSOP-16
Case Temperature TS150 150 150 °C
Safety Input, Output, or Supply
Current IS
θJA = 100 °C/W (WB SOIC-16)
105 °C/W (NB SOIC-16, QSOP-16)
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
220 215 215 mA
Device Power Dissipation2PD415 415 415 mW
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.3 (WB SOIC-16) Thermal Derat-
ing Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 26 and Figure 4.4 (NB
SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10
on page 26.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
Table 4.10. Thermal Characteristics
Parameter Symbol WB SOIC-16 NB SOIC-16/QSOP-16 Unit
IC Junction-to-Air Thermal Resistance θJA 100 105 °C/W
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 25
0 20015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
450
300
370
220
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
Figure 4.3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE
0884-10
0 20015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
430
300
360
215
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V
Figure 4.4. (NB SOIC-16, QSOP-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per VDE 0884-10
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 26
Table 4.11. Absolute Maximum Ratings 1
Parameter Symbol Min Max Unit
Storage Temperature 2 TSTG –65 150 °C
Ambient Temperature Under Bias TA–40 125 °C
Junction Temperature TJ 150 °C
Supply Voltage VDD1, VDD2 –0.5 7.0 V
Input Voltage VI–0.5 VDD + 0.5 V
Output Voltage VO–0.5 VDD + 0.5 V
Output Current Drive Channel IO 10 mA
Lead Solder Temperature (10 s) 260 °C
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16, QSOP-16 4500 VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16 6500 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Si8660/61/62/63 Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.72 | 27
5. Pin Descriptions
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
Si8660
A5
RF
XMITR
RF
RCVR
B5
B6A6 RF
XMITR
RF
RCVR
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
Si8661
RF
XMITR
RF
RCVR
A5 B5
RF
XMITR
RF
RCVR B6
A6
RF
XMITR
RF
RCVR
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
Si8662
RF
XMITR
RF
RCVR
A5 B5
B6A6
RF
XMITR
RF
RCVR
VDD1
A1
A3
A4
GND1
A2
VDD2
B2
B1
B4
B3
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
Si8663
RF
XMITR
RF
RCVR
A5 B5
B6A6
RF
XMITR
RF
RCVR
Figure 5.1. Si866x Pinout
Table 5.1. Si866x Pin Descriptions
Name SOIC-16 Pin# Type Description
VDD1 1 Supply Side 1 power supply.
A1 2 Digital Input Side 1 digital input.
A2 3 Digital Input Side 1 digital input.
A3 4 Digital Input Side 1 digital input.
A4 5 Digital I/O Side 1 digital input or output.
A5 6 Digital I/O Side 1 digital input or output.
A6 7 Digital I/O Side 1 digital input or output.
GND1 8 Ground Side 1 ground.
GND2 9 Ground Side 2 ground.
B6 10 Digital I/O Side 2 digital input or output.
B5 11 Digital I/O Side 2 digital input or output.
B4 12 Digital I/O Side 2 digital input or output.
B3 13 Digital Output Side 2 digital output.
B2 14 Digital Output Side 2 digital output.
B1 15 Digital Output Side 2 digital output.
VDD2 16 Supply Side 2 power supply.
Si8660/61/62/63 Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.72 | 28
6. Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the Si86xx digital isolator in a 16-pin wide-body SOIC package. The table below lists
the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Wide Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 29
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions
Dimension Min Max
A 2.65
A1 0.10 0.30
A2 2.05
b 0.31 0.51
c 0.20 0.33
D 10.30 BSC
E 10.30 BSC
E1 7.50 BSC
e 1.27 BSC
L 0.40 1.27
h 0.25 0.75
θ
ααα 0.10
bbb 0.33
ccc 0.10
ddd 0.25
eee 0.10
fff 0.20
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Wide Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 30
7. Land Pattern (16-Pin Wide-Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC package. The table below
lists the values for the dimensions shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC PCB Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Si8660/61/62/63 Data Sheet
Land Pattern (16-Pin Wide-Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 31
8. Package Outline (16-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC package. The table below lists the values
for the dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 32
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions
Dimension Min Max
A 1.75
A1 0.10 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.90 BSC
E 6.00 BSC
E1 3.90 BSC
e 1.27 BSC
L 0.40 1.27
L2 0.25 BSC
h 0.25 0.50
θ
aaa 0.10
bbb 0.20
ccc 0.10
ddd 0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin Narrow Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 33
9. Land Pattern (16-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC package. The table
below lists the values for the dimensions shown in the illustration.
Figure 9.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Si8660/61/62/63 Data Sheet
Land Pattern (16-Pin Narrow Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 34
10. Package Outline (16-Pin QSOP)
The figure below illustrates the package details for the Si86xx in a 16-pin QSOP package. The table lists the values for the dimensions
shown in the illustration.
Figure 10.1. 16-Pin QSOP Package
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin QSOP)
silabs.com | Building a more connected world. Rev. 1.72 | 35
Table 10.1. 16-Pin QSOP Package Diagram Dimensions1, 2, 3, 4
Dimension Min Max
A 1.75
A1 0.10 0.25
A2 1.25
b 0.20 0.30
c 0.17 0.25
D 4.89 BSC
E 6.00 BSC
E1 3.90 BSC
e 0.635 BSC
L 0.40 1.27
L2 0.25 BSC
h 0.25 0.50
θ
aaa 0.10
bbb 0.20
ccc 0.10
ddd 0.25
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si8660/61/62/63 Data Sheet
Package Outline (16-Pin QSOP)
silabs.com | Building a more connected world. Rev. 1.72 | 36
11. Land Pattern (16-Pin QSOP)
The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin QSOP package. The table lists the values
for the dimensions shown in the illustration.
Figure 11.1. 16-Pin QSOP PCB Land Pattern
Table 11.1. 16-Pin QSOP Land Pattern Dimensions1, 2
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 0.635
X1 Pad Width 0.40
Y1 Pad Length 1.55
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOP63P602X173-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
Si8660/61/62/63 Data Sheet
Land Pattern (16-Pin QSOP)
silabs.com | Building a more connected world. Rev. 1.72 | 37
12. Top Marking (16-Pin Wide Body SOIC)
Si86XYSV
YYWWRTTTTT
TW
e4
Figure 12.1. 16-Pin Wide Body SOIC Top Marking
Table 12.1. 16-Pin Wide Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
(See 1. Ordering Guide for more information.)
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade
A = 1 Mbps
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking:
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking:
Circle = 1.7 mm Diameter
(Center-Justified)
“e4” Pb-Free Symbol
Country of Origin ISO Code Abbreviation TW = Taiwan as shown, TH = Thailand
Si8660/61/62/63 Data Sheet
Top Marking (16-Pin Wide Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 38
13. Top Marking (16-Pin Narrow Body SOIC)
Si86XYSV
YYWWRTTTTT
e3
Figure 13.1. 16-Pin Narrow Body SOIC Top Marking
Table 13.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
(See 1. Ordering Guide for more information.)
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade
A = 1 Mbps
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking:
Circle = 1.2 mm Diameter “e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
RTTTTT = Mfg Code
Manufacturing code from assembly house.
“R” indicates revision.
Circle = 1.2 mm diameter “e3” Pb-Free Symbol.
Si8660/61/62/63 Data Sheet
Top Marking (16-Pin Narrow Body SOIC)
silabs.com | Building a more connected world. Rev. 1.72 | 39
14. Top Marking (16-Pin QSOP)
Figure 14.1. 16-Pin QSOP Top Marking
Table 14.1. 16-Pin QSOP Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
(See 1. Ordering Guide for more information).
86 = Isolator product series
XY = Channel Configuration
X = # of data channels (6)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
Si8660/61/62/63 Data Sheet
Top Marking (16-Pin QSOP)
silabs.com | Building a more connected world. Rev. 1.72 | 40
15. Revision History
Revision 1.72
October 2018
Added new Automotive-Grade OPN options.
Revision 1.71
January 2018
Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 1.7
October 18, 2017
Added new OPNs in Ordering Guide for IU (QSOP) and IS2 (8 mm creepage WB SOIC) package options.
Added 62368-1 references throughout.
Removed 61010-1 references throughout.
Added QSOP-16 package information.
Revision 1.6
June 18, 2015
Updated Table 4.5 Regulatory Information 1 on page 23.
Added CQC certificate numbers.
Updated 1. Ordering Guide.
Removed references to moisture sensitivity levels.
Removed Note 2.
Added note to Table 1.1 Ordering Guide for Valid OPNs 1,2, 3 on page 2 for denoting tape and reel marking.
Revision 1.5
September 25, 2013
Added Figure 4.2 Common Mode Transient Immunity Test Circuit on page 16.
Added references to CQC throughout.
Added references to 2.5 kVRMS devices throughout.
Updated 1. Ordering Guide.
Updated 12. Top Marking (16-Pin Wide Body SOIC).
Revision 1.4
June 26, 2012
Updated Table 4.11 Absolute Maximum Ratings 1 on page 27.
Added junction temperature spec.
Updated 3.3.1 Supply Bypass.
Removed “3.3.2. Pin Connections”.
Updated 1. Ordering Guide.
Removed Rev A devices.
Updated 6. Package Outline (16-Pin Wide Body SOIC).
Updated Top Marks.
Added revision description.
Revision 1.3
March 21, 2012
Updated 1. Ordering Guide to include MSL2A.
Si8660/61/62/63 Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 1.72 | 41
Revision 1.2
September 14, 2011
Reordered spec tables to conform to new convention.
Removed “pending” throughout document.
Revision 1.1
July 14, 2011
Reordered spec tables to conform to new convention.
Removed “pending” throughout document.
Revision 1.0
March 31, 2011
Added chip graphics on front page.
Updated features list on front page.
Moved Table 4.1 Recommended Operating Conditions on page 12 and Table 4.11 Absolute Maximum Ratings 1 on page 27.
Updated 4. Electrical Specifications.
Moved Table 3.1 Si866x Logic Operation on page 8.
Moved and updated 3.5 Typical Performance Characteristics.
Updated Table 5.1 Si866x Pin Descriptions on page 28.
Updated 1. Ordering Guide.
Removed references to QSOP-16 package.
Revision 0.1
September 15, 2010
Initial release.
Si8660/61/62/63 Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 1.72 | 42
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