Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
DESCRIPTION QUICK REFERENCE DATA
Monolithic temperature and SYMBOL PARAMETER MAX. UNIT
overload protected logic level power
MOSFET in a 5 pin surface VDS Continuous drain source voltage 50 V
mounting plastic envelope, intended IDContinuous drain current 15 A
as a general purpose switch for Ptot Total power dissipation 40 W
automotive systems and other TjContinuous junction temperature 150 ˚C
applications. RDS(ON) Drain-source on-state resistance
VIS = 5 V 125 mΩ
APPLICATIONS VIS = 7 V 100 mΩ
General controller for driving SYMBOL PARAMETER NOM. UNIT
lamps
motors VPSN Protection supply voltage
solenoids BUK114-50L 5V
heaters BUK114-50S 10 V
FEATURES FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Low on-state resistance
Logic and protection supply
from separate pin
Low operating supply current
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by protection supply
Protection circuit condition
indicated by flag pin
5 V logic compatible input level
Separate input pin
for higher frequency drive
ESD protection on input, flag
and protection supply pins
Over voltage clamping for turn
off of inductive loads
Both linear and switching
operation are possible Fig.1. Elements of the TOPFET.
PINNING - SOT426 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input
2 flag
3 (connected to mb)
4 protection supply
5 source
Fig. 2. Fig. 3.
mb drain
POWER
MOSFET
DRAIN
SOURCE
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
PROTECTION SUPPLY
FLAG
mb
12 45
3
D
S
I
TOPFET
P
F
P
September 1996 1 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Voltages
VDSS Continuous off-state drain source VIS = 0 V - 50 V
voltage1
VIS Continuous input voltage - 0 11 V
VFS Continuous flag voltage - 0 11 V
VPS Continuous supply voltage - 0 11 V
Currents VIS = - 7 5 V
IDContinuous drain current Tmb ≤ 25 ˚C - 15 13 A
IDContinuous drain current Tmb ≤ 100 ˚C - 9.5 8.5 A
IDRM Repetitive peak on-state drain current Tmb ≤ 25 ˚C - 60 54 A
Thermal
Ptot Total power dissipation Tmb = 25 ˚C - 40 W
Tstg Storage temperature - -55 150 ˚C
TjJunction temperature2continuous - 150 ˚C
Tsold Lead temperature during soldering - 250 ˚C
OVERLOAD PROTECTION LIMITING VALUES
With the protection supply An n-MOS transistor turns on For internal overload protection to
connected, TOPFET can protect between the input and source to remain latched while the control
itself from two types of overload - quickly discharge the power circuit is high, external series input
over temperature and short circuit MOSFET gate capacitance. resistance must be provided. Refer
load. to INPUT CHARACTERISTICS.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VIS =75 - V
V
PSP Protection supply voltage3for valid protection
BUK114-50L 4.4 4 - V
BUK114-50S 5.4 5 - V
Over temperature protection VPS = VPSN
VDDP(T) Protected drain source supply voltage VIS = 10 V; RI ≥ 2 kΩ-50V
V
IS = 5 V; RI ≥ 1 kΩ-50V
Short circuit load protection VPS = VPSN; L ≤ 10 µH
VDDP(P) Protected drain source supply voltage4VIS = 10 V; RI ≥ 2 kΩ-25V
V
IS = 5 V; RI ≥ 1 kΩ-45V
P
DSM Instantaneous overload dissipation - 0.8 kW
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCElectrostatic discharge capacitor Human body model; - 2 kV
voltage C = 250 pF; R = 1.5 kΩ
1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy.
2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
3 The minimum supply voltage required for correct operation of the overload protection circuits.
4 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.
September 1996 2 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
OVERVOLTAGE CLAMPING LIMITING VALUES
At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
IDRRM Repetitive peak clamping drain current RIS ≥ 100 Ω1-15A
E
DSM Non-repetitive inductive turn-off IDM = 15 A; RIS ≥ 100 Ω- 200 mJ
energy2
EDRM Repetitive inductive turn-off energy RIS ≥ 100 Ω; Tmb ≤ 95 ˚C; - 20 mJ
IDM = 4 A; VDD ≤ 20 V;
f = 250 Hz
IDIRM Repetitive peak drain to input current3RIS = 0 Ω; tp ≤ 1 ms - 50 mA
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
ISContinuous forward current Tmb = 25 ˚C; - 15 A
VIS = VPS = VFS = 0 V
THERMAL CHARACTERISTIC
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
Rth j-mb Junction to mounting base - - 2.5 3.1 K/W
STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(CL)DSR Drain-source clamping voltage RIS = 100 Ω; ID = 10 mA 50 - 65 V
V(CL)DSR Drain-source clamping voltage RIS = 100 Ω; IDM = 1 A; tp ≤ 300 µs; 50 - 70 V
δ ≤ 0.01
IDSS Zero input voltage drain current VDS = 12 V; VIS = 0 V - 0.5 10 µA
IDSR Drain source leakage current VDS = 50 V; RIS = 100 Ω;-120µA
I
DSR Drain source leakage current VDS = 40 V; RIS = 100 Ω;
Tj = 125 ˚C - 10 100 µA
RDS(ON) Drain-source on-state IDM = 7.5 A; VIS = 7 V - 75 100 mΩ
resistance tp ≤ 300 µs; δ ≤ 0.01 VIS = 5 V - 95 125 mΩ
1 The input pin must be connected to the source pin by a specified external resistance to allow the power MOSFET gate source voltage to
become sufficiently positive for active clamping. Refer to INPUT CHARACTERISTICS.
2 While the protection supply voltage is connected, during overvoltage clamping it is possible that the overload protection may operate at
energies close to the limiting value. Refer to OVERLOAD PROTECTION CHARACTERISTICS.
3 Shorting the input to source with low resistance inhibits the internal overvoltage protection by preventing the power MOSFET gate source
voltage becoming positive.
September 1996 3 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
OVERLOAD PROTECTION CHARACTERISTICS
With adequate protection supply Provided there is adequate input Refer also to OVERLOAD
voltage TOPFET detects when one series resistance it switches off PROTECTION LIMITING VALUES
of the overload thresholds is and remains latched off until reset and INPUT CHARACTERISTICS.
exceeded. by the protection supply pin.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load protection1VPS = VPSN2; Tmb = 25 ˚C; L ≤ 10 µH;
RI ≥ 2 kΩ
EDS(TO) Overload threshold energy VDD = 13 V; VIS = 10 V - 150 - mJ
td sc Response time VDD = 13 V; VIS = 10 V - 375 - µs
Over temperature protection VPS = VPSN; RI ≥ 2 kΩ
Tj(TO) Threshold junction temperature from ID ≥ 0.65 A3150 - - ˚C
TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 10 V; IDM = 7.5 A tp ≤ 300 µs; 5 9 - S
δ ≤ 0.01
IDDrain current4VDS = 13 V; VIS = 5 V - 25 - A
VIS = 10 V 40 - A
PROTECTION SUPPLY CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Protection supply
IPS, Protection supply current normal operation or
IPSL protection latched
BUK114-50L VPS = 5 V - 0.2 0.35 mA
BUK114-50S VPS = 10 V - 0.4 1.0 mA
VPSR Protection reset voltage51.5 2.5 3.5 V
Tj = 150 ˚C 1.0 - - V
V(CL)PS Protection clamp voltage IP = 1.35 mA 11 13 - V
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VSDS Forward voltage IS = 15 A; VIS = VPS = VFS = 0 V; - 1.0 1.5 V
tp = 300 µs
trr Reverse recovery time not applicable6----
1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum.
2 At the appropriate nominal protection supply voltage for each type. Refer to QUICK REFERENCE DATA.
3 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
4 During overload condition. Refer also to OVERLOAD PROTECTION LIMITING VALUES and CHARACTERISTICS.
5 The supply voltage below which the overload protection circuits will be reset.
6 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
September 1996 4 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Normal operation
VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA 1.0 1.5 2.0 V
Tmb = 150 ˚C 0.5 - - V
IIS Input current VIS = 10 V - 10 100 nA
V(CL)IS Input clamp voltage II = 1 mA 11 13 - V
Overload protection latched
RISL Input resistance1VPS = 5 V II = 5 mA; - 55 - Ω
Tmb = 150 ˚C - 95 - Ω
VPS = 10 V II = 5 mA; - 35 - Ω
Tmb = 150 ˚C - 60 - Ω
Application information
External input resistances for (see figure 29)
RIS internal overvoltage clamping2RI = ∞ Ω;V
DS > 30 V 100 - - Ω
RIinternal overload protection3RIS = ∞ Ω;V
II = 5 V 1 - - kΩ
VII = 10 V 2 - - kΩ
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C; RI = 50 Ω; RIS = 50 Ω (see figure 29); resistive load RL = 10 Ω. For waveforms see figure 28.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
td on Turn-on delay time VDD = 15 V; VIS: 0 V ⇒ 10 V - 8 - ns
trRise time - 13 - ns
td off Turn-off delay time VDD = 15 V; VIS: 10 V ⇒ 0 V - 100 - ns
tfFall time - 45 - ns
CAPACITANCES
Tmb = 25 ˚C; f = 1 MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ciss Input capacitance VDS = 25 V; VIS = 0 V - 415 600 pF
Coss Output capacitance VDS = 25 V; VIS = 0 V - 275 400 pF
Crss Reverse transfer capacitance VDS = 25 V; VIS = 0 V - 55 80 pF
Cpso Protection supply pin VPS = 10 V - 30 - pF
capacitance
Cfso Flag pin capacitance VFS = 10 V; VPS = 0 V - 20 - pF
1 The resistance of the internal transistor which discharges the power MOSFET gate capacitance when overload protection operates.
The external drive circuit should be such that the input voltage does not exceed VIS(TO) minimum when the overload protection has
operated. Refer also to figure for latched input characteristics.
2 Applications using a lower value for RIS would require external overvoltage protection.
3 For applications requiring a lower value for RI, an external overload protection strategy is possible using the flag pin to ‘tell’ the control circuit to
switch off the input.
September 1996 5 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
FLAG DESCRIPTION TRUTH TABLE
The flag pin provides a means to CONDITION DESCRIPTION FLAG
detect the presence of the
protection supply and indicate the NORMAL Normal operation and adequate LOGIC LOW
state of the overload detectors. protection supply voltage
The flag is the open drain of an
n-MOS transistor and requires an OVER TEMP. Over temperature detected LOGIC HIGH
external pull-up resistor1. It is
suitable for both 5 V and 10 V logic.
Flag may be used to implement an SHORT CIRCUIT Overload condition detected LOGIC HIGH
external protection strategy2 for
applications which require low input
drive impedance. SUPPLY FAULT Inadequate protection supply LOGIC HIGH
voltage
FLAG CHARACTERISTICS
Tmb = 25 ˚C unless otherwise stated
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Flag ‘low’ normal operation
VFS Flag voltage IF = 1.6 mA - 0.15 0.4 V
IFSS Flag saturation current VFS = 10 V - 15 - mA
Flag ‘high’ overload or fault
IFS Flag leakage current VFS = 10 V - - 10 µA
VPSF Protection supply threshold VFF = 5 V; RF = 3 kΩ;
voltage BUK114-50L 2.5 3.3 4 V
BUK114-50S 3.3 4.2 5 V
V(CL)FS Flag clamping voltage IF = 1 mA; VPS = 0 V 11 13 - V
Application information
RFSuitable external pull-up VFF =5 V 1 10 50 kΩ
resistance VFF =10 V 2 20 100 kΩ
1 Even if the flag pin is not used, it is recommended that it is connected to the protection supply via a pull-up resistor. It should not be left
floating.
2 Low pass filtering of the flag signal may be advisable to prevent false tripping.
September 1996 6 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
Fig.4. Normalised limiting power dissipation.
P
D
% = 100
⋅
P
D
/P
D
(25 ˚C) = f(T
mb
)
Fig.5. Normalised continuous drain current.
I
D
% = 100
⋅
I
D
/I
D
(25 ˚C) = f(T
mb
); conditions: V
IS
= 5 V
Fig.6. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.7. Transient thermal impedance.
Z
th
j-mb
= f(t); parameter D = t
p
/T
Fig.8. Typical output characteristics, T
j
= 25 ˚C.
ID = f(V
DS
); parameter V
IS
; t
p
= 250
µ
s & t
p
< t
d sc
Fig.9. Typical on-state characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
IS
; t
p
= 250
µ
s
0 20 40 60 80 100 120 140
Tmb / C
PD% Normalised Power Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
1E-07 1E-05 1E-03 1E-01 1E+01
t / s
Zth / (K/W)
10
1
0.1
0.01
0
0.5
0.2
0.1
0.05
0.02
D =
tptp
T
T
P
t
D
D =
BUK114-50L/S
0 20 40 60 80 100 120 140
Tmb / C
ID% Normalised Current Derating
120
110
100
90
80
70
60
50
40
30
20
10
0
0 4 8 12 16 20 24 28 32
VDS / V
ID / A BUK114-50L/S
50
40
30
20
10
0
VIS / V =10
98
76
5
4
3
2
1 100
VDS / V
100
10
1
0.1
BUK114-50L/S
10
ID & IDM / A
DC
Overload protection characteristics not shown
100 us
1 ms
10 ms
100 ms
10 us
tp =
RDS(ON) = VDS/ID
012
VDS / V
ID / A BUK114-50L/S
20
15
10
5
0
4
5
6
3
10 7VIS / V =
September 1996 7 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
Fig.10. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
IS
; t
p
= 250
µ
s
Fig.11. Typical transfer characteristics, T
j
= 25 ˚C.
I
D
= f(V
IS
) ; conditions: V
DS
= 10 V; t
p
= 250
µ
s
Fig.12. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 10 V; t
p
= 250
µ
s
Fig.13. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)
25 ˚C = f(T
j
); I
D
= 7.5 A; V
IS
≥
5 V
Fig.14. Typical over temperature protection threshold
T
j(TO)
= f(V
PS
); conditions: V
DS
> 0.1 V
Fig.15. Normalised limiting overload dissipation.
P
DSM
% =100
⋅
P
DSM
/P
DSM
(25 ˚C) = f(T
mb
)
0 2 4 6 8 10 12 14 16 18 20
ID / A
RDS(ON) / mOhm BUK114-50L/S
150
100
50
0
10
7
6
5
4VIS / V =
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
aNormalised RDS(ON) = f(Tj)
1.5
1.0
0.5
0
0 2 4 6 8 10 12
VIS / V
ID / A BUK114-50L/S
50
40
30
20
10
0 0 2 4 6 8 10
VPS / V
Tj(TO) / C BUK114-50L/S
230
220
210
200
190
180
170
160
150
BUK114-50S
BUK114-50L
0 20 40
ID / A
gfs / S BUK114-50L/S
10
9
8
7
6
5
4
3
2
1
0 10 30 50
-60 -40 -20 0 20 40 60 80 100 120 140
Tmb / C
PDSM%
120
100
80
60
40
20
0
September 1996 8 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
Fig.16. Maximum drain source supply voltage for
SC load protection. V
DDP(P)
= f(V
IS
); T
mb
≤
150 ˚C
Fig.17. Minimum protection supply voltage
for SC load protection. V
PSP
= f(V
IS
); T
mb
≥
25 ˚C
Fig.18. Typical overload protection characteristics.
t
d sc
= f(P
DS
); conditions: V
PS
≥
V
PSP
; V
IS
≥
5 V
Fig.19. Typical overload protection characteristics.
Conditions: V
DD
= 13 V; V
PS
= V
PSN
, V
IS
= 7 V; SC load
Fig.20. Typical overload protection energy, T
j
= 25 ˚C
E
SC(TO)
= f(V
PS
); conditions: V
DS
= 13 V, parameter V
IS
Fig.21. Typical clamping characteristics, 25 ˚C.
I
D
= f(V
DS
); conditions: R
IS
= 100
Ω
; t
p
≤
50
µ
s
0 2 4 6 8 10
VIS / V
VDDP(P) / V BUK114-50L/S
50
40
30
20
10
0
max
-60 -20 20 60 100 140 180 220
Tmb / C
BUK114-50L/S
0.5
0
Energy / J
Time / ms
Tj(TO)
Energy & Time
0.4
0.3
0.2
0.1
0 2 4 6 8 10
VIS / V
VPSP / V BUK114-50L/S
10
8
6
4
2
0
min
BUK114-50L
BUK114-50S
0 2 4 6 8 10
VPS / V
ESC(TO) / J BUK114-50L/S
0.4
0.3
0.2
0.1
0
BUK114-50L
BUK114-50S
VIS / V = 5
10
5
10
0.1 1 10
POWER / kW
TIME / ms BUK114-50L/S
10
1
0.1
PDSM
50 60 70
BUK114-50L/S
VDS / V
ID / A
20
15
10
5
0
typ.
September 1996 9 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
Fig.22. Input threshold voltage.
V
IS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= 5 V
Fig.23. Typical DC protection supply characteristics.
I
PS
= f(V
PS
); normal or overload operation; T
j
= 25 ˚C
Fig.24. Typical latched input characteristics, 25 ˚C.
I
ISL
= f(V
IS
); after overload protection latched
Fig.25. Typical reverse diode current, T
j
= 25 ˚C.
I
S
= f(V
SDS
); conditions: V
IS
= 0 V; t
p
= 250
µ
s
Fig.26. Normalised limiting clamping energy.
E
DSM
% = f(T
mb
); conditions: I
D
= 15 A
Fig.27. Clamping energy test circuit, R
IS
= 100
Ω
.
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
VIS(TO) / V
2
1
0
max.
typ.
min.
00.5 1
VSD / V
IS / A BUK114-50L/S
20
15
10
5
0 1.5
0 2 4 6 8 10 12 14
BUK114-50L/S
VPS / V
IPS / mA
1.0
0.5
0
0 20 40 60 80 100 120 140
Tmb / C
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 2 4 6 8 10
VIS / V
IISL / mA BUK114-50L/S
100
50
0
4
5
6
7
8
9
VPS / V = 11
150 10
L
D.U.T.
VDD
RI = RIS R 01
VDS
-ID/100
+
-
shunt
VIS
0
ID
0
VDS
0VDD
V(CL)DSR
D
S
I
TOPFET
P
F
P
RF
VPS
+
EDSM =0.5 ⋅LID
2⋅V(CL)DSR/(V(CL)DSR −VDD)
September 1996 10 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
Fig.28. Typical resistive load switching waveforms
R
I
= R
IS
= 50
Ω
; R
L
= 10
Ω
; V
DD
= 15 V; T
j
= 25 ˚C
Fig.29. External input resistances R
I
and R
IS
,
generator voltage V
II
and input voltage V
IS
.
Fig.30. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
IS
= 0 V; f = 1 MHz
Fig.31. Typical off-state leakage current.
I
DSR
= f(T
j
); Conditions: V
DS
= 40 V; R
IS
= 100
Ω
.
Fig.32. Normalised protection supply current.
I
PS
/I
PS
25 ˚C = f(T
j
); V
PS
= V
PSN
0 0.5 1
time / us
VIS / V & VDS / V BUK114-50L/S
15
10
5
0
VDS
VIS
0 20 40 60 80 100 120 140
Tj / C
Idsr
1 mA
100 uA
10 uA
1 uA
100 nA
typ.
D
S
I
TOPFET
P
F
P
VII
RI
RIS
VIS
-60 -20 20 60 100 140 180
Tj / C
Ips normalised to 25 C
1.5
1
0.5
0 20 40
VDS / V
Capacitance / pF BUK114-50L/S
10000
1000
100
10 503010
Ciss
Coss
Crss
September 1996 11 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.5 g
Fig.33. SOT426
mounting base connected to centre pin (cropped short)
MOUNTING INSTRUCTIONS
Dimensions in mm
Fig.34. SOT426
soldering pattern for surface mounting.
10.3 MAX
11 MAX
15.4
2.5
0.5
1.4 MAX
4.5 MAX
0.85 MAX
(x4)
3.4
3.4
1.7
1.7
11.5
9.0
3.8
1.3 (x4)
1.7
3.4
1.7
17.5
September 1996 12 Rev 1.000
Philips Semiconductors Product specification
Logic level TOPFET BUK114-50L/S
SMD version of BUK104-50L/S
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
September 1996 13 Rev 1.000
