CYWB022XX Family (R) West Bridge : AstoriaTM USB and Mass Storage Peripheral Controller West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Features SPI (slave mode) interface Direct memory access (DMA) slave support Multimedia device support Up to two SD, SDIO, MMC, MMC+, and CE-ATA devices Supports Microsoft(R) Media Transfer Protocol (MTP) with optimized data throughput FlexBoot Processor can boot from the processor interface port Ultra low power, 1.8-V core operation Low power modes Small footprint: 3.91 x 3.91 x 0.55 mm 81-ball WLCSP (SP and Lite SP) 6 x 6 x 1.0 mm 100-ball VFBGA 10 x 10 x 1.20 mm 121-ball FBGA Simultaneous Link to Independent Multimedia (SLIM(R)) architecture, enabling simultaneous and independent data paths between the processor and USB, and between the USB and mass storage High-speed USB at 480 Mbps USB 2.0 compliant Integrated USB switch Integrated USB 2.0 transceiver, smart serial interface engine 16 programmable endpoints GPIF (General Programmable Interface) Allows direct connection to most parallel interface Programmable waveform descriptors and configuration registers to define waveforms Supports multiple Ready (RDY) inputs and Control (CTL) outputs Flexible processor interface that supports: Multiplexing and nonmultiplexing address and data interface SRAM interface Pseudo cellular random access memory (CRAM) interface (Antioch interface) Pseudo NAND flash interface Supports USB Boot, I2C Boot and Processor Boot Selectable clock input frequencies 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz Applications Cellular phones Portable media players Personal digital assistants Portable navigation devices Digital cameras POS terminals Portable video recorders Data cards and wireless dongles Logic Block Diagram West BridgeTM AstoriaTM Control Registers uC P High-Speed USB 2.0 XCVR Flexible Processor Interface Access Control SLIMTM SD/SDIO/ MMC+/ CEATA Block U Cypress N-XpressTM Engine Configurable Storage Interface S Cypress Semiconductor Corporation Document Number: 001-13805 Rev. *Q * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised March 29, 2018 CYWB022XX Family Contents Functional Overview ........................................................ 3 Turbo-MTP Support ..................................................... 3 SLIM Architecture ........................................................ 3 8051 Microprocessor ................................................... 3 Configuration and Status Registers ............................. 3 Processor Interface (P-Port) ........................................ 3 FlexBoot ...................................................................... 3 USB Interface (U-Port) ................................................ 3 Mass Storage Support (S-Port) ................................... 4 Clocking ....................................................................... 5 Power Domains ........................................................... 6 Power Modes .............................................................. 7 Packages and Interface Options ..................................... 8 Pin Assignments .............................................................. 9 Absolute Maximum Ratings .......................................... 32 Operating Conditions ..................................................... 32 DC Characteristics ......................................................... 33 AC Timing Parameters ................................................... 35 P Port Interface ......................................................... 35 Document Number: 001-13805 Rev. *Q S Port Interface AC Timing Parameters .................... 72 Reset and Standby Timing Parameters .................... 74 AC Test Loads and Waveforms ..................................... 75 Ordering Information ...................................................... 76 Ordering Code Definitions ......................................... 76 Package Diagrams .......................................................... 77 Acronyms ........................................................................ 80 Document Conventions ................................................. 80 Units of Measure ....................................................... 80 Document History Page ................................................. 81 Sales, Solutions, and Legal Information ...................... 87 Worldwide Sales and Design Support ....................... 87 Products .................................................................... 87 PSoC(R) Solutions ...................................................... 87 Cypress Developer Community ................................. 87 Technical Support ..................................................... 87 Page 2 of 87 CYWB022XX Family Functional Overview P-Port of the WLCSP package only supports PNAND and SPI interface. Turbo-MTP Support The memory address is decoded to access any of the multiple endpoint buffers inside Astoria. These endpoints serve as buffers for data between each pair of ports, for example, between the processor port and the USB port. The processor writes and reads into these buffers through the memory interface. Turbo-MTP is an implementation of Microsoft's MTP enabled by West Bridge. In the current generation of MTP-enabled mobile phones, all protocol packets needs to be handled by the main processor. West Bridge Turbo-MTP switches these packet types and sends only control packets to the processor, while data payloads are written directly to mass storage, thereby bringing the high performance of West Bridge to MTP. For more information refer to the application note Optimizing Performance using West Bridge(R) Controllers with Turbo-MTP. SLIM Architecture The SLIM architecture enables three different interfaces (P-port, S-port, and U-port) to connect to one another independently. With this architecture, connecting a device using Astoria to a PC through USB does not disturb any of the functions of the device. The device can still access mass storage at the same time as the PC synchronizes with the main processor. The SLIM architecture enables new usage models in which a PC can access a mass storage device independent of the main processor or enumerate access to both the mass storage and the main processor at the same time. In a handset, this typically enables using the phone as a thumb drive, downloading media files to the phone while still having full functionality available on the phone, or using the same phone as a modem to connect the PC to the web. 8051 Microprocessor The 8051 microprocessor embedded in Astoria does basic transaction management for all the transactions between P-Port, S-Port, and U-Port. The 8051 does not reside in the data path; it manages the path. The data path is optimized for performance. The 8051 executes firmware that supports SD, SDIO, MMC+, and CE-ATA devices at the S-Port. Configuration and Status Registers The West Bridge Astoria device includes configuration and status registers that are accessible as memory mapped registers through the processor interface. The configuration registers allow the system to specify certain Astoria behaviors. For example, it is able to mask certain status registers from raising an interrupt. The status registers convey various status such as the addresses of buffers for read operations. Processor Interface (P-Port) Communication with the external processor is realized through a dedicated processor interface. This interface is configured to support different interface standards. This interface supports multiplexing and nonmultiplexing address or data bus in both synchronous and asynchronous pseudo CRAM-mapped, and nonmultiplexing address or data asynchronous SRAM-mapped memory accesses. The interface also can be configured to a pseudo NAND interface to support the processor's NAND interface. In addition, this interface can be configured to support SPI slave. Asynchronous accesses can reach a bandwidth of up to 66.7 MBps. Synchronous accesses can be performed at 33 MHz across 16 bits for up to 66.7 MBps bandwidth. The Document Number: 001-13805 Rev. *Q Access to these buffers is controlled by either using a DMA protocol or using an interrupt to the main processor. These two modes are configurable by the external processor. The 81-ball WLCSP package only supports interrupt. As a DMA slave, Astoria generates a DMA request signal to signify to the main processor that a specific buffer is ready to be read from or written to. The external processor monitors this signal and polls Astoria for the specific buffers ready for read or write. It then performs the appropriate read or write operations on the buffer through the processor interface. This way, the external processor only deals with the buffers to access a multitude of storage devices connected to Astoria. In the interrupt mode, Astoria communicates important buffer status changes to the external processor using an interrupt signal. The external processor then polls Astoria for the specific buffers ready for read or write and it performs the appropriate read or write operations through the processor interface. FlexBoot FlexBoot is an optional feature that Astoria emulates a NAND Flash device. In this optional feature, the P-Port is configured as pseudo NAND interface. The processor can download its boot image through the P-Port. When P-Port is configured to pseudo NAND interface, it supports two operation modes: Logic NAND Access (LNA) mode Non-Logic NAND Access (non-LNA) mode LNA refers to the mode of operation where Astoria emulates a NAND flash device. This mode is designed for systems that require booting of the system processor from a NAND Flash device. In this type of application, the system processor can communicate to Astoria using common NAND commands to boot from a NAND Flash connected to Astoria's S-port. In this mode of operation, Astoria mimics a real NAND device and allows the system processor to use its internal boot-ROM to boot from Astoria, as it boots from a NAND Flash. In the non-LNA mode of operation, the system processor interfaces with Astoria using standard NAND interface, but does not use standard NAND commands. In this mode, Astoria responds to a subset of NAND commands. The system processor uses a set of APIs provided by Cypress to communicate through its NAND controller to Astoria. For details, refer to the application note "Interfacing To West BridgeTM Astoria'sTM Pseudo-NAND Processor Port". USB Interface (U-Port) In accordance with the USB 2.0 specification, Astoria can operate in both full speed and high speed USB modes. The USB interface consists of the USB transceiver and can be accessed by both the P-Port and the S-Port. Page 3 of 87 CYWB022XX Family SWD+ SWD- USB 2.0 XCVR USB Switch and Control Block USB Port (U Port) D+ D- Mass Storage Support (S-Port) The S-Port is configurable in five different interface modes: Figure 3. Dual SD/SDIO/MMC/CE-ATA Interface Mode P Port UVALID USBALLO Simultaneously supporting an SD/SDIO/MMC+/CE-ATA port and an GPIF SD SDIO MMC MMC+ CE-ATA U Port Figure 1. U-Port With Switch and Control Block The dual SD/SDIO/MMC/MMC+/CE-ATA interface mode configures the S-Port for up to two SD/SDIO/MMC/MMC+/CE-ATA port as shown in Figure 3. Each SD/SDIO/MMC/MMC+/CE-ATA port is independent and supports different SD, SDIO, MMC, MMC+, or CE-ATA devices. Astoria S Port OR OR SD_D[7:0] Astoria also has an integrated USB switch (see Figure 1) that allows interfacing to an external full speed USB PHY. Dual SD/SDIO/MMC/CE-ATA Interface Mode SD2_D[7:0] The Astoria USB interface supports programmable CONTROL/BULK/INTERRUPT/ISOCHRONOUS endpoints. OR OR OR OR OR OR SD SDIO MMC MMC+ CE-ATA Supporting two SD/SDIO/MMC+/CE-ATA ports Supporting SD/SDIO/MMC+/CE-ATA port and GPIO Supporting GPIF and GPIO SD/SDIO/MMC/CE-ATA and GPIO Interface Supporting GPIO The SD/SDIO/MMC/MMC+/CE-ATA and GPIO interface mode configures the S-Port to support SD/SDIO/MMC/MMC+/CE-ATA device and GPIOs as shown in Figure 4. Each GPIO is configured as either input or output independently. The processor accesses those GPIO through the P-Port driver's API. GPIF and SD/SDIO/MMC/CE-ATA interface mode Dual SD/SDIO/MMC/CE-ATA interface mode SD/SDIO/MMC/CE-ATA and GPIO interlace mode GPIF and GPIO interface mode GPIO interface mode Figure 4. SD/SDIO/MMC/CE-ATA and GPIO Interface Mode GPIF and SD/SDIO/MMC/CE-ATA Interface Mode This mode configures the S-Port into GPIF and SD/SDIO/MMC/MMC+/CE-ATA ports as shown in Figure 2. The SD/SDIO/MMC/MMC+/CE-ATA port supports either SD, SDIO, MMC, MMC+, or CE-ATA device. GPIO Astoria U Port S Port SD_D[7:0] The S Port is configurable in six different interface modes: PB[7:0] S-Port Configuration Modes P Port These configurations are controlled by the 8051 firmware. OR OR SD SDIO MMC MMC+ CE-ATA OR OR Figure 2. GPIF and SD/SDIO/MMC/CE-ATA Interface Mode Document Number: 001-13805 Rev. *Q Page 4 of 87 CYWB022XX Family GPIF and GPIO Interface The GPIF and GPIO interface mode configure the S-Port to support GPIF and GPIO as shown in Figure 5. Each GPIO is configured as either input or output independently. The processor accesses those GPIO through the P-Port driver's API. SD Specifications - Part E1 SDIO Specification, Version 1.10, August 18, 2004 CE-ATA Specification - CE-ATA Digital Protocol, CE-ATA Committee, Version 1.1, September, 2005 Figure 5. GPIF and GPIO Interface Mode West Bridge Astoria provides support for 1-bit and 4-bit SD; SDIO cards; 1-bit, 4-bit, and 8-bit MMC; MMC+ cards; and CE-ATA drive. For the SD, SDIO, MMC/MMC Plus, and CE-ATA, this block supports one card for one physical bus interface. Astoria supports SD commands including the multisector program command that are handled by the API. GPIO Port (S-Port) The GPIO in S-Port is configurable as either input or output direction independently. The processor accesses the GPIO through the P-Port driver's API. Clocking GPIO Interface Mode The GPIO interface mode configures the S-Port to all GPIO as shown in Figure 6. Each GPIO is configured as either input or output independently. The processor accesses those GPIO through the P-Port driver's API. Astoria U Port P Port Figure 6. GPIO Interface Mode Note Clock inputs at 3.3 V level are not supported. Astoria's 100-ball VFBGA package supports external crystal and clock inputs at 19.2, 24, and 26 MHz frequencies. At 48 MHz, only clock inputs are supported. The 81-ball SPWLCSP only supports 19.2 and 26 MHz external clock input. The 81-ball Lite SP WLCSP only supports 26 MHz external clock or crystal input. The crystal or clock frequency selection is shown in Table 1 on page 6, Table 2 on page 6, and Table 3 on page 6. The XTALIN frequency is independent of the clock and data rate of the 8051 microprocessor or any of the device interfaces (including P-Port and S-Port). The internal PLL applies the proper clock multiply option depending on the input frequency. S Port GPIO SD/SDIO/MMC+/CE-ATA Port (S-Port) When Astoria is configured with firmware to support SD, SDIO, MMC+, and CE-ATA, this interface supports: The Multimedia Card System Specification, MMCA Technical Committee, Version 4.1 SD Memory Card Specification - Part 1, Physical Layer Specification, SD Group, Version 1.10, October 15, 2004 SD Memory Card Specification - Part 1, Physical Layer Specification, SD Group, Version 2.0, May 9, 2006 Document Number: 001-13805 Rev. *Q Astoria allows connection of a crystal between the XTALIN and XTALOUT pins or an external clock at the XTALIN pin. The 81-ball WLCSP package only supports the external clock. The power supply level at the crystal supply XVDDQ determines whether a crystal or a clock is provided. If XVDDQ is detected to be 1.8 V, Astoria assumes that a clock input is provided. For a crystal to be connected, XVDDQ must be 3.3 V. For applications that use an external clock source to drive XTALIN, the XTALOUT pin must be left floating. The external clock source must also stop high or low and not toggle, to achieve the lowest possible current consumption. The requirements for an external clock source are shown in Table 4 on page 6. Astoria has an on-chip oscillator circuit that uses an external 19.2, 24, and 26 MHz (150 ppm) crystal with the following characteristics: Parallel resonant Fundamental mode 1 mW drive level 12 pF (5% tolerance) load capacitors 150 ppm Page 5 of 87 CYWB022XX Family Figure 7. Crystal Configuration Table 1. 100-ball FVBGA Clock Selection Astoria XTALSLC[1] XTALSLC[0] Freq Crystal/Clock 0 0 19.2 MHz Crystal/Clock 0 1 24 MHz Crystal/Clock XTALOUT 1 0 48 MHz Clock 12pf 1 1 26 MHz Crystal/Clock XTALIN XTAL PLL 12pf * 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA Table 2. 81-ball SP WLCSP Clock Selection XTALSLC Freq Crystal/Clock 0 19.2 MHz Clock 1 26 MHz Clock Table 3. 81-ball Lite SP WLCSP Clock Supports 26 MHz XTALSLC Freq Crystal/Clock NA 26 MHz Clock or Crystal Table 4. External Clock Requirements Specification Parameter Description Vn (AVDDQ) Supply voltage noise at frequencies < 50 MHz - 20 mV p-p PN_100 Input phase noise at 100 Hz - -75 dBc/Hz PN_1k Input phase noise at 1 kHz offset - -104 dBc/Hz PN_10k Input phase noise at 10 kHz offset - -120 dBc/Hz Min Max Unit PN_100k Input phase noise at 100 kHz offset - -128 dBc/Hz PN_1M Input phase noise at 1 MHz offset - -130 dBc/Hz Duty cycle 30 70 % Maximum frequency deviation - 150 ppm Overshoot - 3 % Undershoot - -3 % Power Domains VDD is the supply voltage for the logic core. The nominal supply voltage level is 1.8 V. This supplies the core logic circuits. The same supply must also be used for AVDDQ AVDDQ is the 1.8 V supply for PLL and USB serializer analog components. The same supply must also be used for VDD. The maximum permitted noise on AVDDQ is 20 mV p-p XVDDQ is the clock I/O supply; 3.3 V for XTAL or 1.8 V for an external clock Astoria has multiple power domains that serve different purposes within the chip. VDDQ refers to a group of four independent supply domains for the digital I/Os. The nominal voltage level on these supplies are 1.8 V, 2.5 V, or 3.3 V. The three separate I/O power domains are: PVDDQ - P-Port Processor interface I/O SNVDDQ - S-Port GPIF interface I/O SSVDDQ - S-Port SD interface I/O GVDDQ - Other miscellaneous I/O UVDDQ is the 3.3-V nominal supply for the USB I/O and some analog circuits. It also supplies power to the USB transceiver VDD33 supply is required for the power sequence control circuits. For more details, see Pin Assignments on page 9. Document Number: 001-13805 Rev. *Q Noise guideline for all supplies except AVDDQ is a maximum of 100 mV p-p. All I/O supplies of Astoria must be ON when a system is active even if Astoria is not in use. The core VDD can also be deactivated at any time to preserve power if there is a minimum impedance of 1 k between the VDD pin and ground. All I/Os tristate when the core is disabled. Page 6 of 87 CYWB022XX Family Figure 8. Astoria Power Supply Domains VDD *VDDQ UVDDQ D+ I/O D-CORE USB-IO D- This mode is entered through the deassertion of the WAKEUP input pin or through internal register settings. To leave this mode, assert the WAKEUP, CE#, and RESET#; change state of GPIO[0]/SD_CD, GPIO[1]/SD2_CD, SD_D3, and SD2_D3. In this mode all configuration register settings and program RAM contents are preserved. However, data in the buffers or other parts of the data path, if any, is not guaranteed in values. Therefore, the external processor must ensure that the required data is read before placing Astoria in the standby mode. In the standby mode: The program counter is reset on waking up from standby mode All outputs are tristated and I/O is placed in input only configuration. Values of I/Os in standby mode are listed in the pin assignments table Core power supply must be retained Hard Reset can be performed by asserting the RESET# input, and Astoria is initialized Power Modes PLL is disabled In addition to the normal operating mode, Astoria contains several low power states when normal operation is not required. USB switches the SWD+/SWD- to D+/D- Power Supply Sequence The power supplies are independently sequenced without damaging the part. All power supplies must be up and stable before the device operates. If the supplies are not stable, the remaining domains are in low power (standby) state. Normal Mode Normal mode is the mode in which Astoria is fully functional. In this mode, data transfer functions described in this document are performed. Suspend Mode This mode is entered internally by 8051 (the external processor only initiates entry into this mode through Mailbox commands). This mode is exited by the D+ bus going low, GPIO[0] going to a pre-determined state or by asserting CE# LOW. In Astoria's suspend mode: The clocks are shut off All I/Os maintain their previous state Core power supply must be retained The states of the configuration registers, endpoint buffers, and the program RAM are maintained. All transactions must be complete before Astoria enters suspend mode (state of outstanding transactions are not preserved) Core Power Down Mode The core power supply VDD is powered down in this state. Because AVDDQ is tied to the same supply as VDD, it is also powered down. The endpoint buffers, configuration registers, and program RAM do not maintain state. All VDDQ power supplies (except AVDDQ) must be ON and not power down in this mode. VDD33 must also remain ON. It has an option that the UVDDQ can be powered down or stay ON while VDD is powered down when SWD+/SWD- are not connected. The UVDDQ cannot be powered down when SWD+/SWD- is connected, or VDD is active. When UVDDQ is powered down, D+/D- cannot be driven by an external device. In the WLCSP package, AVDDQ is internally tied to XVDDQ. Due to this, the clock input at XTALIN must be brought to a steady low level prior to entry into Core Power Down Mode. In the WLCSP package, VDD33 is tied to UVDDQ internally. UVDDQ must be ON during the core power down mode The core power down mode has two power down options: Core only power down - VDD power down The firmware resumes its operation from where it was suspended because the program counter is not reset Core and USB power down - VDD and UVDDQ are both powered down. In this option, SWD+/SWD- are not connected and cannot be driven by an external device Only inputs that are sensed are RESET#, GPIO[0]/SD_CD, GPIO[1]/SD2_CD, SD_D3, SD2_D3, D+, and CE#. The last three are wake up sources (each can be individually enabled or disabled) In these power down options, the endpoint buffers, configuration registers, or the program RAM do not maintain state. It is necessary to reload the firmware on exiting from this mode. All VDDQ power supplies must be ON and not powered down in this mode. Hard Reset can be performed by asserting the RESET# input, and Astoria is initialized In the 82-ball WLCSP package, in the core power down mode, the USB switches the SWD+/SWD- to D+/D-. Standby Mode Standby mode is a low-power state. This is the lowest power mode of Astoria while still maintaining external supply levels. Document Number: 001-13805 Rev. *Q Page 7 of 87 CYWB022XX Family Packages and Interface Options Astoria provides one 100-ball VFBGA, one 100-ball BGA, one 121-ball FBGA and two types of 81-ball WLCSP packages. The two WLCSP packages are SP WLCSP and Lite SP WLCSP. These two packages have different interface options as listed in Table 5. The 100-ball VFBGA/BGA package pin list is listed in Table 6 on page 9, the 81-ball SP CSP package is listed in Table 10 on page 21, and the 81-ball Lite SP CSP package in Table 11 on page 24. Table 5. Interface Options for 100-ball VFBGA, 81-ball SP, and 81-ball Lite SP P-Port Package PCRAM SRAM S-Port Clock ADM PNAN D I2C SPI SD1 SD2 GPIF GPIO Ext CLK Freq. Crystal (MHz) 100-ball BGA / VFBGA 19.2, 24, 26, 48 121-ball FBGA 19.2, 24, 26, 48 81-ball SP WLCSP 81-ball Lite SP WLCSP Document Number: 001-13805 Rev. *Q 19.2, 26 26 Page 8 of 87 CYWB022XX Family Pin Assignments Table 6. Astoria 100-ball VFBGA Package Pin Assignments U-Port DRQ & Int P-Port Pin Name SRAM Pin Description Ball # PCRAM I/O Address / Data I/O Non-Multiplexing bus Multiplexing (ADM) I/O PNAND I/O SPI J2 CLK (pull low in Asyn mode) I CLK (pull low in Async mode) I Ext pull low I Ext pull low I SCK I Clock G1 CE# I CE# I CE# I CE# I SS# I CE# or SPI Slave Select H3 A7 I Ext pull up I A7 I A7 > 1:SBD A7 > 0:LBD I Ext pull up I Addr. Bus 7 I/O H2 A6 I SDA I A6 I SDA I/O SDA I/O A6 or I2C data H1 A5 I SCL I A5 I SCL I/O SCL I/O A5 or I2C clock PVDDQ VGND J3 A4 I Ext pull up I A4 I WP# I Ext pull up I A4 or PNAND WP J1 A3 I A3 = 0 (Ext pull low) I A3 I A3 = 0 (Ext pull low) I A3 = 1 (Ext pull up) I A3 K3 A2 I A2 = 1 (Ext pull up) I A2 I A2 = 0 (Ext pull low) I A2 = 0 (Ext pull low) I A2 K2 A1 I Ext pull up I A1 I RB# O Ext pull up I A1 or PNAND R/B# K1 A0 I Ext pull up I A0 I CLE I Ext pull up I A0 or PNAND CLE G2 DQ[15] I/O AD[15] I/O DQ[15] I/O I/O[15] I/O Ext pull up I D15, AD15, or I/O15 G3 DQ[14] I/O AD[14] I/O DQ[14] I/O I/O[14] I/O Ext pull up I D14, AD14, or I/O14 F1 DQ[13] I/O AD[13] I/O DQ[13] I/O I/O[13] I/O Ext pull up I D13, AD13, or I/O13 F2 DQ[12] I/O AD[12] I/O DQ[12] I/O I/O[12] I/O Ext pull up I D12, AD12, or I/O12 F3 DQ[11] I/O AD[11] I/O DQ[11] I/O I/O[11] I/O Ext pull up I D11, AD11, or I/O11 E1 DQ[10] I/O AD[10] I/O DQ[10] I/O I/O[10] I/O Ext pull up I D10, AD10, or I/O10 E2 DQ[9] I/O AD[9] I/O DQ[9] I/O I/O[9] I/O Ext pull up I D9, AD9, or I/O9 E3 DQ[8] I/O AD[8] I/O DQ[8] I/O I/O[8] I/O Ext pull up I D8, AD8, or I/O8 D1 DQ[7] I/O AD[7] I/O DQ[7] I/O I/O[7] I/O Ext pull up I D7, AD7, or I/O7 D2 DQ[6] I/O AD[6] I/O DQ[6] I/O I/O[6] I/O Ext pull up I D6, AD6, or I/O6 D3 DQ[5] I/O AD[5] I/O DQ[5] I/O I/O[5] I/O Ext pull up I D5, AD5, or I/O5 C1 DQ[4] I/O AD[4] I/O DQ[4] I/O I/O[4] I/O Ext pull up I D4, AD4, or I/O4 C2 DQ[3] I/O AD[3] I/O DQ[3] I/O I/O[3] I/O Ext pull up I D3, AD3, or I/O3 C3 DQ[2] I/O AD[2] I/O DQ[2] I/O I/O[2] I/O Ext pull up I D2, AD2, or I/O2 B1 DQ[1] I/O AD[1] I/O DQ[1] I/O I/O[1] I/O SDO O SPI SDO, AD1or D1 B2 DQ[0] I/O AD[0] I/O DQ[0] I/O I/O[0] I/O SDI I SPI SDI, AD0, or D0 A1 ADV# I ADV# I B3 OE# I OE# I A2 WE# I WE# I A3 INT# O INT# O INT# O INT# A4 DRQ# O DRQ# O DRQ# B4 DACK# I I A5 D+ I/O/Z USB D+ A6 D- I/O/Z USB D- A7 SWD+ I/O/Z USB Switch DP C6 SWD- I/O/Z USB Switch DM DACK# Document Number: 001-13805 Rev. *Q I ALE I Ext pull up I Address Valid OE# I RE# I Ext pull up I Output Enable WE# I WE# I Ext pull up I WE# O SINT# O INT Request O DRQ# O N/C O DMA Request I I I DMA Acknowledgement DACK# DACK# Ext pull up Power Domain GVDDQ VGND UVDDQ UVSSQ Page 9 of 87 CYWB022XX Family Table 6. Astoria 100-ball VFBGA Package Pin Assignments (continued) Pin Name Ball # Other S-Port G9 Double SDIO Configuration I/O SDIO & GPIO Configuration I/O GPIO Configuration I/O GPIF Configuration I/O GPIF & GPIO Configuration Pin Description Power Domain SSVDDQ VGND I/O SD_D[7] I/O SD_D[7] I/O PD[7] (GPIO) I/O GPIF_DATA[15] I/O PD[7] (GPIO) I/O SD Data or GPIO or GPIF Data G10 SD_D[6] I/O SD_D[6] I/O PD[6] (GPIO) I/O GPIF_DATA[14] I/O PD[6] (GPIO) I/O SD Data or GPIO or GPIF Data F9 SD_D[5] I/O SD_D[5] I/O PD[5] (GPIO) I/O GPIF_DATA[13] I/O PD[5] (GPIO) I/O SD Data or GPIO or GPIF Data F10 SD_D[4] I/O SD_D[4] I/O PD[4] (GPIO) I/O GPIF_DATA[12] I/O PD[4] (GPIO) I/O SD Data or GPIO or GPIF Data E9 SD_D[3] I/O SD_D[3] I/O PD[3] (GPIO) I/O GPIF_DATA[11] I/O PD[3] (GPIO) I/O SD Data or GPIO or GPIF Data E10 SD_D[2] I/O SD_D[2] I/O PD[2] (GPIO) I/O GPIF_DATA[10] I/O PD[2] (GPIO) I/O SD Data or GPIO or GPIF Data D9 SD_D[1] I/O SD_D[1] I/O PD[1] (GPIO) I/O GPIF_DATA[9] I/O PD[1] (GPIO) I/O SD Data or GPIO or GPIF Data D10 SD_D[0] I/O SD_D[0] I/O PD[0] (GPIO) I/O GPIF_DATA[8] I/O PD[0] (GPIO) I/O SD Data or GPIO or GPIF Data F8 SD_CLK O SD_CLK O PC[7] (GPIO) I/O PC[7] (GPIO) I/O PC[7] (GPIO) I/O SD Clock or GPIO G8 SD_CMD I/O SD_CMD I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O SD CMD or GPIO H8 SD_POW PC[6] (GPIO) I/O PC[6] (GPIO) I/O PC[6] (GPIO) I/O H10 SD_WP K7 SD2_D[7] I/O PB[7] (GPIO) I/O PB[7] (GPIO) I/O GPIF_DATA[7] I/O GPIF_DATA[7] I/O SD2 Data or GPIO or SNVDDQ GPIF Data VGND K8 SD2_D[6] I/O PB[6] (GPIO) I/O PB[6] (GPIO) I/O GPIF_DATA[6] I/O GPIF_DATA[6] I/O SD2 Data or GPIO or GPIF Data J8 SD2_D[5] I/O PB[5] (GPIO) I/O PB[5] (GPIO) I/O GPIF_DATA[5] I/O GPIF_DATA[5] I/O SD2 Data or GPIO or GPIF Data K9 SD2_D[4] I/O PB[4] (GPIO) I/O PB[4] (GPIO) I/O GPIF_DATA[4] I/O GPIF_DATA[4] I/O SD2 Data or GPIO or GPIF Data J9 SD2_D[3] I/O PB[3] (GPIO) I/O PB[3] (GPIO) I/O GPIF_DATA[3] I/O GPIF_DATA[3] I/O SD2 Data or GPIO or GPIF Data H9 SD2_D[2] I/O PB[2] (GPIO) I/O PB[2] (GPIO) I/O GPIF_DATA[2] I/O GPIF_DATA[2] I/O SD2 Data or GPIO or GPIF Data K10 SD2_D[1] I/O PB[1] (GPIO) I/O PB[1] (GPIO) I/O GPIF_DATA[1] I/O GPIF_DATA[1] I/O SD2 Data or GPIO or GPIF Data J10 SD2_D[0] I/O PB[0] (GPIO) I/O PB[0] (GPIO) I/O GPIF_DATA[0] I/O GPIF_DATA[0] I/O SD2 Data or GPIO or GPIF Data SD_POW I SD_WP I N/C N/C PC[5] (GPIO) SD Power or GPIO SD Write Protect K6 SD2_CLK O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O SD2 Clock or GPIO J6 SD2_CMD I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O SD2 CMD or GPIO J5 SD2_POW O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O SD2 Power or GPIO K4 N/C O N/C O N/C O GPIF_CTL[1] O GPIF_CTL[1] O GPIF Control Signal GPIF Control Signal H6 N/C O N/C O N/C O GPIF_CTL[0] O GPIF_CTL[0] O J7 PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O GPIO J4 N/C I GPIF_RDY[0] O GPIF_RDY[0] O GPIF Ready Signal K5 SD2_WP O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O SD Write Protect or GPIO B10 RESETOUT O RESETOUT O RESETOUT O RESETOUT / GPIF_RDY[1] O RESETOUT / GPIF_RDY[1] O Reset Out C9 SD2_CD I/O PC-5 (GPIO[1]) I I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O GPIO or SD2 CD D8 PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) SD_CD I SD_CD I I/O PC-4 (GPIO[0]) I/O PC-4 (GPIO[0]) I/O GPIO or SD CD N/C I N/C I GVDDQ VGND C10 RESET# I RESET C7 WAKEUP I Wake Up Signal Document Number: 001-13805 Rev. *Q Page 10 of 87 CYWB022XX Family Table 6. Astoria 100-ball VFBGA Package Pin Assignments (continued) Power Clock Conf Pin Name C5 XTALSLC[1] C4 XTALSLC[0] E8 TEST[2] C8 TEST[1] Pin Description I Clock Select 1 GVDDQ VGND Clock Select 0 I Test Cfg 2 Test Cfg 1 D7 TEST[0] A8 XTALIN I Crystal/Clock IN B8 XTALOUT O Crystal Out D4, H4 PVDDQ Power Processor I/F VDD H5 SNVDDQ Power GPIF VDD B5 UVDDQ Power USB VDD H7 SSVDDQ Power SDIO VDD D6 GVDDQ Power Misc I/O VDD B9 AVDDQ Power Analog VDD B7 XVDDQ Power Crystal VDD D5, G4, G5, G6, G7, F7 VDD Power Core VDD A10 VDD33 Power Independent 3.3 V B6 UVSSQ Power USB GND A9 AVSSQ Power Analog GND E4, E5, E6, E7, F4, F5, F6 VGND Power Core GND Document Number: 001-13805 Rev. *Q Power Domain Test Cfg 0 XVDDQ VGND Page 11 of 87 CYWB022XX Family Table 7. Astoria CYWB0224ABS 121-ball FBGA Package Pin Assignments Pin Description Pin Name U-Port DRQ & Int P-Port Ball # PCRAM Non Multiplexing I/O Addr/Data bus Multiplexing (ADM) I/O SRAM I/O PNAND I/O SPI I/O J2 CLK (pull-low in Asyn mode) I CLK (pull-low in Async mode) I Ext pull-low I Ext pull-low I SCK I Clock G1 CE# I CE# I CE# I CE# I SS# I CE# or SPI Slave Select H3 A7 I Ext pull-up I A7 I A7 > 1:SBD A7 > 0: LBD I Ext pull-up I Addr. Bus 7 H2 A6 I SDA I A6 I SDA I/O SDA I/O A6 or I2C data H1 A5 I SCL I A5 I SCL I/O SCL I/O A5 or I2C clock PVDDQ VGND J3 A4 I Ext pull-up I A4 I WP# I Ext pull-up I A4 or PNAND WP J1 A3 I A3 = 0 (Ext pull-low) I A3 I A3 = 0 (Ext pull-low) I A3 = 1 (Ext pull-up) I A3 K3 A2 I A2 = 1 (Ext pull-up) I A2 I A2 = 0 (Ext pull-low) I A2 = 0 (Ext pull-low) I A2 K2 A1 I Ext pull-up I A1 I RB# O Ext pull-up I A1 or PNAND R/B# K1 A0 I Ext pull-up I A0 I CLE I Ext pull-up I A0 or PNAND CLE G2 DQ[15] I/O AD[15] I/O DQ[15] I/O I/O[15] I/O Ext pull-up I D15, AD15, or I/O15 G3 DQ[14] I/O AD[14] I/O DQ[14] I/O I/O[14] I/O Ext pull-up I D14, AD14, or I/O14 F1 DQ[13] I/O AD[13] I/O DQ[13] I/O I/O[13] I/O Ext pull-up I D13, AD13, or I/O13 F2 DQ[12] I/O AD[12] I/O DQ[12] I/O I/O[12] I/O Ext pull-up I D12, AD12, or I/O12 F3 DQ[11] I/O AD[11] I/O DQ[11] I/O I/O[11] I/O Ext pull-up I D11, AD11, or I/O11 E1 DQ[10] I/O AD[10] I/O DQ[10] I/O I/O[10] I/O Ext pull-up I D10, AD10, or I/O10 E2 DQ[9] I/O AD[9] I/O DQ[9] I/O I/O[9] I/O Ext pull-up I D9, AD9, or I/O9 E3 DQ[8] I/O AD[8] I/O DQ[8] I/O I/O[8] I/O Ext pull-up I D8, AD8, or I/O8 D1 DQ[7] I/O AD[7] I/O DQ[7] I/O I/O[7] I/O Ext pull-up I D7, AD7, or I/O7 D2 DQ[6] I/O AD[6] I/O DQ[6] I/O I/O[6] I/O Ext pull-up I D6, AD6, or I/O6 D3 DQ[5] I/O AD[5] I/O DQ[5] I/O I/O[5] I/O Ext pull-up I D5, AD5, or I/O5 C1 DQ[4] I/O AD[4] I/O DQ[4] I/O I/O[4] I/O Ext pull-up I D4, AD4, or I/O4 C2 DQ[3] I/O AD[3] I/O DQ[3] I/O I/O[3] I/O Ext pull-up I D3, AD3, or I/O3 C3 DQ[2] I/O AD[2] I/O DQ[2] I/O I/O[2] I/O Ext pull-up I D2, AD2, or I/O2 B1 DQ[1] I/O AD[1] I/O DQ[1] I/O I/O[1] I/O SDO O SPI SDO, AD1or D1 B2 DQ[0] I/O AD[0] I/O DQ[0] I/O I/O[0] I/O SDI I SPI SDI, AD0, or D0 A1 ADV# I ADV# I B3 OE# I OE# I A2 WE# I WE# I A3 INT# O INT# O INT# O INT# A4 DRQ# O DRQ# O DRQ# B4 DACK# I I A5 D+ I/O/Z USB D+ A6 D- I/O/Z USB D- A7 SWD+ I/O/Z USB Switch DP C6 SWD- I/O/Z USB Switch DM DACK# Document Number: 001-13805 Rev. *Q I ALE I Ext pull-up I Address Valid OE# I RE# I Ext pull-up I Output Enable WE# I WE# I Ext pull-up I WE# O SINT# O INT Request O DRQ# O N/C O DMA Request I I I DMA Acknowledgement DACK# DACK# Ext pull-up Power Domain GVDDQ VGND UVDDQ UVSSQ Page 12 of 87 CYWB022XX Family Table 7. Astoria CYWB0224ABS 121-ball FBGA Package Pin Assignments (continued) Pin Name Ball # Other S-Port G9 Double SDIO Configuration I/O SDIO & GPIO Configuration I/O GPIO Configuration I/O GPIF Configuration I/O GPIF & GPIO Configuration Pin Description Power Domain SSVDDQ VGND I/O SD_D[7] I/O SD_D[7] I/O PD[7] (GPIO) I/O GPIF_DATA[15] I/O PD[7] (GPIO) I/O SD Data or GPIO or GPIF Data G10 SD_D[6] I/O SD_D[6] I/O PD[6] (GPIO) I/O GPIF_DATA[14] I/O PD[6] (GPIO) I/O SD Data or GPIO or GPIF Data F9 SD_D[5] I/O SD_D[5] I/O PD[5] (GPIO) I/O GPIF_DATA[13] I/O PD[5] (GPIO) I/O SD Data or GPIO or GPIF Data F10 SD_D[4] I/O SD_D[4] I/O PD[4] (GPIO) I/O GPIF_DATA[12] I/O PD[4] (GPIO) I/O SD Data or GPIO or GPIF Data E9 SD_D[3] I/O SD_D[3] I/O PD[3] (GPIO) I/O GPIF_DATA[11] I/O PD[3] (GPIO) I/O SD Data or GPIO or GPIF Data E10 SD_D[2] I/O SD_D[2] I/O PD[2] (GPIO) I/O GPIF_DATA[10] I/O PD[2] (GPIO) I/O SD Data or GPIO or GPIF Data D9 SD_D[1] I/O SD_D[1] I/O PD[1] (GPIO) I/O GPIF_DATA[9] I/O PD[1] (GPIO) I/O SD Data or GPIO or GPIF Data D10 SD_D[0] I/O SD_D[0] I/O PD[0] (GPIO) I/O GPIF_DATA[8] I/O PD[0] (GPIO) I/O SD Data or GPIO or GPIF Data F8 SD_CLK O SD_CLK O PC[7] (GPIO) I/O PC[7] (GPIO) I/O PC[7] (GPIO) I/O SD Clock or GPIO G8 SD_CMD I/O SD_CMD I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O SD CMD or GPIO H8 SD_POW PC[6] (GPIO) I/O PC[6] (GPIO) I/O PC[6] (GPIO) I/O SD Power or GPIO H10 SD_WP K7 SD2_D[7] I/O PB[7] (GPIO) I/O PB[7] (GPIO) I/O GPIF_DATA[7] I/O GPIF_DATA[7] I/O SD2 Data or GPIO or SNVDDQ GPIF Data VGND K8 SD2_D[6] I/O PB[6] (GPIO) I/O PB[6] (GPIO) I/O GPIF_DATA[6] I/O GPIF_DATA[6] I/O SD2 Data or GPIO or GPIF Data J8 SD2_D[5] I/O PB[5] (GPIO) I/O PB[5] (GPIO) I/O GPIF_DATA[5] I/O GPIF_DATA[5] I/O SD2 Data or GPIO or GPIF Data K9 SD2_D[4] I/O PB[4] (GPIO) I/O PB[4] (GPIO) I/O GPIF_DATA[4] I/O GPIF_DATA[4] I/O SD2 Data or GPIO or GPIF Data J9 SD2_D[3] I/O PB[3] (GPIO) I/O PB[3] (GPIO) I/O GPIF_DATA[3] I/O GPIF_DATA[3] I/O SD2 Data or GPIO or GPIF Data H9 SD2_D[2] I/O PB[2] (GPIO) I/O PB[2] (GPIO) I/O GPIF_DATA[2] I/O GPIF_DATA[2] I/O SD2 Data or GPIO or GPIF Data K10 SD2_D[1] I/O PB[1] (GPIO) I/O PB[1] (GPIO) I/O GPIF_DATA[1] I/O GPIF_DATA[1] I/O SD2 Data or GPIO or GPIF Data J10 SD2_D[0] I/O PB[0] (GPIO) I/O PB[0] (GPIO) I/O GPIF_DATA[0] I/O GPIF_DATA[0] I/O SD2 Data or GPIO or GPIF Data SD_POW I SD_WP I N/C I N/C PC[5] (GPIO) SD Write Protect K6 SD2_CLK O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O SD2 Clock or GPIO J6 SD2_CMD I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA [7] (GPIO) I/O SD2 CMD or GPIO J5 SD2_POW O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O SD2 Power or GPIO K4 N/C O N/C O N/C O GPIF_CTL[1] O GPIF_CTL[1] O GPIF Control Signal GPIF Control Signal H6 N/C O N/C O N/C O GPIF_CTL[0] O GPIF_CTL[0] O J7 PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O GPIO J4 N/C I GPIF_RDY[0] O GPIF_RDY[0] O GPIF Ready Signal K5 SD2_WP O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O SD Write Protect or GPIO B10 RESETOUT O RESETOUT O RESETOUT O RESETOUT / GPIF_RDY[1] O RESETOUT / GPIF_RDY[1] O RESETOUT C9 SD2_CD I/O PC-5 (GPIO[1]) I I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O GPIO or SD2 CD D8 PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) SD_CD I SD_CD I I/O PC-4 (GPIO[0]) I/O PC-4 (GPIO[0]) I/O GPIO or SD CD N/C I N/C I GVDDQ VGND C10 RESET# I RESET C7 WAKEUP I Wake Up Signal Document Number: 001-13805 Rev. *Q Page 13 of 87 CYWB022XX Family Table 7. Astoria CYWB0224ABS 121-ball FBGA Package Pin Assignments (continued) Pin Description Power Clock Conf Pin Name C5 XTALSLC[1] C4 XTALSLC[0] E8 TEST[2] C8 TEST[1] I Clock Select 1 GVDDQ VGND Clock Select 0 I Test Cfg 2 Test Cfg 1 D7 TEST[0] A8 XTALIN I Crystal / Clock IN B8 XTALOUT O Crystal Out D4 H4 PVDDQ Power Processor I/F VDD H5 SNVDDQ Power GPIF VDD B5 UVDDQ Power USB VDD H7 SSVDDQ Power SDIO VDD D6 GVDDQ Power Misc I/O VDD B9 AVDDQ Power Analog VDD B7 XVDDQ Power Crystal VDD D5, G4, G5, G6, G7, F7 VDD Power Core VDD A10 VDD33 Power Independent 3.3 V B6 UVSSQ Power USB GND A9 AVSSQ Power Analog GND E4, E5, E6, E7, F4, F5, F6 VGND Power Core GND Document Number: 001-13805 Rev. *Q Power Domain Test Cfg 0 XVDDQ VGND Page 14 of 87 CYWB022XX Family Table 8. Astoria CYWB0220ABS 121-ball FBGA Package Pin Assignments Pin Name DRQ & Int P-Port Ball # PCRAM Non Multiplexing I/O Addr/Data bus Multiplexing (ADM) I/O SRAM Pin Description I/O PNAND I/O SPI I/O J2 CLK (pull-low in Asyn mode) I CLK (pull-low in Async mode) I Ext pull-low I Ext pull-low I SCK I Clock G1 CE# I CE# I CE# I CE# I SS# I CE# or SPI Slave Select H3 A7 I Ext pull-up I A7 I A7 > 1:SBD A7 > 0: LBD I Ext pull-up I Addr. Bus 7 H2 A6 I SDA I A6 I SDA I/O SDA I/O A6 or I2C data H1 A5 I SCL I A5 I SCL I/O SCL I/O A5 or I2C clock PVDDQ VGND J3 A4 I Ext pull-up I A4 I WP# I Ext pull-up I A4 or PNAND WP J1 A3 I A3 = 0 (Ext pull-low) I A3 I A3 = 0 (Ext pull-low) I A3 = 1 (Ext pull-up) I A3 K3 A2 I A2 = 1 (Ext pull-up) I A2 I A2 = 0 (Ext pull-low) I A2 = 0 (Ext pull-low) I A2 K2 A1 I Ext pull-up I A1 I RB# O Ext pull-up I A1 or PNAND R/B# K1 A0 I Ext pull-up I A0 I CLE I Ext pull-up I A0 or PNAND CLE G2 DQ[15] I/O AD[15] I/O DQ[15] I/O I/O[15] I/O Ext pull-up I D15, AD15, or I/O15 G3 DQ[14] I/O AD[14] I/O DQ[14] I/O I/O[14] I/O Ext pull-up I D14, AD14, or I/O14 F1 DQ[13] I/O AD[13] I/O DQ[13] I/O I/O[13] I/O Ext pull-up I D13, AD13, or I/O13 F2 DQ[12] I/O AD[12] I/O DQ[12] I/O I/O[12] I/O Ext pull-up I D12, AD12, or I/O12 F3 DQ[11] I/O AD[11] I/O DQ[11] I/O I/O[11] I/O Ext pull-up I D11, AD11, or I/O11 E1 DQ[10] I/O AD[10] I/O DQ[10] I/O I/O[10] I/O Ext pull-up I D10, AD10, or I/O10 E2 DQ[9] I/O AD[9] I/O DQ[9] I/O I/O[9] I/O Ext pull-up I D9, AD9, or I/O9 E3 DQ[8] I/O AD[8] I/O DQ[8] I/O I/O[8] I/O Ext pull-up I D8, AD8, or I/O8 D1 DQ[7] I/O AD[7] I/O DQ[7] I/O I/O[7] I/O Ext pull-up I D7, AD7, or I/O7 D2 DQ[6] I/O AD[6] I/O DQ[6] I/O I/O[6] I/O Ext pull-up I D6, AD6, or I/O6 D3 DQ[5] I/O AD[5] I/O DQ[5] I/O I/O[5] I/O Ext pull-up I D5, AD5, or I/O5 C1 DQ[4] I/O AD[4] I/O DQ[4] I/O I/O[4] I/O Ext pull-up I D4, AD4, or I/O4 C2 DQ[3] I/O AD[3] I/O DQ[3] I/O I/O[3] I/O Ext pull-up I D3, AD3, or I/O3 C3 DQ[2] I/O AD[2] I/O DQ[2] I/O I/O[2] I/O Ext pull-up I D2, AD2, or I/O2 B1 DQ[1] I/O AD[1] I/O DQ[1] I/O I/O[1] I/O SDO O SPI SDO, AD1or D1 B2 DQ[0] I/O AD[0] I/O DQ[0] I/O I/O[0] I/O SDI A1 ADV# I ADV# I I ALE I I SPI SDI, AD0, or D0 Ext pull-up I Address Valid Output Enable B3 OE# I OE# I OE# I RE# I Ext pull-up I A2 WE# I WE# I WE# I WE# I Ext pull-up I WE# A3 INT# O INT# O INT# O INT# O SINT# O INT Request A4 DRQ# O DRQ# O DRQ# O DRQ# O N/C O DMA Request B4 DACK# I I I I I DMA Acknowledgement DACK# Document Number: 001-13805 Rev. *Q DACK# DACK# Ext pull-up Power Domain GVDDQ VGND Page 15 of 87 CYWB022XX Family Table 8. Astoria CYWB0220ABS 121-ball FBGA Package Pin Assignments (continued) Pin Name Double SDIO Configuration Other S-Port G9 I/O SDIO & GPIO Configuration I/O GPIO Configuration I/O GPIF Configuration I/O GPIF & GPIO Configuration Pin Description Power Domain SSVDDQ VGND I/O SD_D[7] I/O SD_D[7] I/O PD[7] (GPIO) I/O GPIF_DATA[15] I/O PD[7] (GPIO) I/O SD Data or GPIO or GPIF Data G10 SD_D[6] I/O SD_D[6] I/O PD[6] (GPIO) I/O GPIF_DATA[14] I/O PD[6] (GPIO) I/O SD Data or GPIO or GPIF Data F9 SD_D[5] I/O SD_D[5] I/O PD[5] (GPIO) I/O GPIF_DATA[13] I/O PD[5] (GPIO) I/O SD Data or GPIO or GPIF Data F10 SD_D[4] I/O SD_D[4] I/O PD[4] (GPIO) I/O GPIF_DATA[12] I/O PD[4] (GPIO) I/O SD Data or GPIO or GPIF Data E9 SD_D[3] I/O SD_D[3] I/O PD[3] (GPIO) I/O GPIF_DATA[11] I/O PD[3] (GPIO) I/O SD Data or GPIO or GPIF Data E10 SD_D[2] I/O SD_D[2] I/O PD[2] (GPIO) I/O GPIF_DATA[10] I/O PD[2] (GPIO) I/O SD Data or GPIO or GPIF Data D9 SD_D[1] I/O SD_D[1] I/O PD[1] (GPIO) I/O GPIF_DATA[9] I/O PD[1] (GPIO) I/O SD Data or GPIO or GPIF Data D10 SD_D[0] I/O SD_D[0] I/O PD[0] (GPIO) I/O GPIF_DATA[8] I/O PD[0] (GPIO) I/O SD Data or GPIO or GPIF Data F8 SD_CLK O SD_CLK O PC[7] (GPIO) I/O PC[7] (GPIO) I/O PC[7] (GPIO) I/O SD Clock or GPIO G8 SD_CMD I/O SD_CMD I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O SD CMD or GPIO H8 SD_POW PC[6] (GPIO) I/O PC[6] (GPIO) I/O PC[6] (GPIO) I/O H10 SD_WP K7 SD2_D[7] I/O PB[7] (GPIO) I/O PB[7] (GPIO) I/O GPIF_DATA[7] I/O GPIF_DATA[7] I/O SD2 Data or GPIO or SNVDDQ GPIF Data VGND K8 SD2_D[6] I/O PB[6] (GPIO) I/O PB[6] (GPIO) I/O GPIF_DATA[6] I/O GPIF_DATA[6] I/O SD2 Data or GPIO or GPIF Data J8 SD2_D[5] I/O PB[5] (GPIO) I/O PB[5] (GPIO) I/O GPIF_DATA[5] I/O GPIF_DATA[5] I/O SD2 Data or GPIO or GPIF Data K9 SD2_D[4] I/O PB[4] (GPIO) I/O PB[4] (GPIO) I/O GPIF_DATA[4] I/O GPIF_DATA[4] I/O SD2 Data or GPIO or GPIF Data J9 SD2_D[3] I/O PB[3] (GPIO) I/O PB[3] (GPIO) I/O GPIF_DATA[3] I/O GPIF_DATA[3] I/O SD2 Data or GPIO or GPIF Data H9 SD2_D[2] I/O PB[2] (GPIO) I/O PB[2] (GPIO) I/O GPIF_DATA[2] I/O GPIF_DATA[2] I/O SD2 Data or GPIO or GPIF Data K10 SD2_D[1] I/O PB[1] (GPIO) I/O PB[1] (GPIO) I/O GPIF_DATA[1] I/O GPIF_DATA[1] I/O SD2 Data or GPIO or GPIF Data J10 SD2_D[0] I/O PB[0] (GPIO) I/O PB[0] (GPIO) I/O GPIF_DATA[0] I/O GPIF_DATA[0] I/O SD2 Data or GPIO or GPIF Data SD2 Clock or GPIO SD_POW I SD_WP I N/C N/C PC[5] (GPIO) SD Power or GPIO SD Write Protect K6 SD2_CLK O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O J6 SD2_CMD I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O SD2 CMD or GPIO J5 SD2_POW O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O SD2 Power or GPIO K4 N/C O N/C O N/C O GPIF_CTL[1] O GPIF_CTL[1] O GPIF Control Signal H6 N/C O N/C O N/C O GPIF_CTL[0] O GPIF_CTL[0] O GPIF Control Signal J7 PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O GPIO J4 N/C I GPIF_RDY[0] O GPIF_RDY[0] O GPIF Ready Signal K5 SD2_WP O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O SD Write Protect or GPIO B10 RESETOUT O RESETOUT O RESETOUT O RESETOUT / GPIF_RDY[1] O RESETOUT / GPIF_RDY[1] O Reset Out C9 SD2_CD I/O PC-5 (GPIO[1]) I I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O GPIO or SD2 CD D8 PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) SD_CD I SD_CD I I/O PC-4 (GPIO[0]) I/O PC-4 (GPIO[0]) I/O GPIO or SD CD N/C I N/C I GVDDQ VGND C10 RESET# I RESET C7 WAKEUP I Wake Up Signal Document Number: 001-13805 Rev. *Q Page 16 of 87 CYWB022XX Family Table 8. Astoria CYWB0220ABS 121-ball FBGA Package Pin Assignments (continued) Power Clock Conf Pin Name C5 XTALSLC[1] C4 XTALSLC[0] E8 TEST[2] C8 TEST[1] Pin Description I Clock Select 1 GVDDQ VGND Clock Select 0 I Test Cfg 2 Test Cfg 1 D7 TEST[0] A8 XTALIN I Crystal / Clock IN B8 XTALOUT O Crystal Out D4 H4 PVDDQ Power Processor I/F VDD H5 SNVDDQ Power GPIF VDD B5 UVDDQ Power USB VDD H7 SSVDDQ Power SDIO VDD D6 GVDDQ Power Misc I/O VDD B9 AVDDQ Power Analog VDD B7 XVDDQ Power Crystal VDD D5, G4, G5, G6, G7, F7 VDD Power Core VDD A10 VDD33 Power Independent 3.3 V B6 UVSSQ Power USB GND A9 AVSSQ Power Analog GND E4, E5, E6, E7, F4, F5, F6 VGND Power Core GND Document Number: 001-13805 Rev. *Q Power Domain Test Cfg 0 XVDDQ VGND Page 17 of 87 CYWB022XX Family Table 9. Astoria CYWB0216ABS 121-ball FBGA Package Pin Assignments Pin Name U-Port I2C Pins Unused Pins Ball # Pull Direction Pin Description I/O J2 P/D I Pull-down G1 P/U I Pull-up H3 P/U I Pull-up J3 P/U I Pull-up J1 P/U I Pull-up K3 P/D I Pull-down K2 P/U I Pull-up K1 P/U I Pull-up G2 P/U I Pull-up G3 P/U I Pull-up F1 P/U I Pull-up F2 P/U I Pull-up F3 P/U I Pull-up E1 P/U I Pull-up E2 P/U I Pull-up E3 P/U I Pull-up D1 P/U I Pull-up D2 P/U I Pull-up D3 P/U I Pull-up C1 P/U I Pull-up C2 P/U I Pull-up C3 P/U I Pull-up B1 P/U O Pull-up B2 P/U I Pull-up A1 P/U I Pull-up B3 P/U I Pull-up A2 P/U I Pull-up A3 N/C O No Connect A4 N/C O No Connect B4 P/U I Pull-up Interface Pins PVDDQ VGND GVDDQ VGND I/O Pin Description H2 SDA I/O I2C data H1 SCL I/O I2C clock A5 D+ I/O/Z USB D+ A6 D- I/O/Z USB D- A7 SWD+ I/O/Z USB Switch DP C6 SWD- I/O/Z USB Switch DM Document Number: 001-13805 Rev. *Q Power Domain PVDDQ VGND UVDDQ UVSSQ Page 18 of 87 CYWB022XX Family Table 9. Astoria CYWB0216ABS 121-ball FBGA Package Pin Assignments (continued) Pin Name Double SDIO Configuration Other S-Port G9 I/O SDIO & GPIO Configuration I/O GPIO Configuration I/O GPIF Configuration I/O GPIF & GPIO Configuration Pin Description Power Domain SSVDDQ VGND I/O SD_D[7] I/O SD_D[7] I/O PD[7] (GPIO) I/O GPIF_DATA[15] I/O PD[7] (GPIO) I/O SD Data or GPIO or GPIF Data G10 SD_D[6] I/O SD_D[6] I/O PD[6] (GPIO) I/O GPIF_DATA[14] I/O PD[6] (GPIO) I/O SD Data or GPIO or GPIF Data F9 SD_D[5] I/O SD_D[5] I/O PD[5] (GPIO) I/O GPIF_DATA[13] I/O PD[5] (GPIO) I/O SD Data or GPIO or GPIF Data F10 SD_D[4] I/O SD_D[4] I/O PD[4] (GPIO) I/O GPIF_DATA[12] I/O PD[4] (GPIO) I/O SD Data or GPIO or GPIF Data E9 SD_D[3] I/O SD_D[3] I/O PD[3] (GPIO) I/O GPIF_DATA[11] I/O PD[3] (GPIO) I/O SD Data or GPIO or GPIF Data E10 SD_D[2] I/O SD_D[2] I/O PD[2] (GPIO) I/O GPIF_DATA[10] I/O PD[2] (GPIO) I/O SD Data or GPIO or GPIF Data D9 SD_D[1] I/O SD_D[1] I/O PD[1] (GPIO) I/O GPIF_DATA[9] I/O PD[1] (GPIO) I/O SD Data or GPIO or GPIF Data D10 SD_D[0] I/O SD_D[0] I/O PD[0] (GPIO) I/O GPIF_DATA[8] I/O PD[0] (GPIO) I/O SD Data or GPIO or GPIF Data F8 SD_CLK O SD_CLK O PC[7] (GPIO) I/O PC[7] (GPIO) I/O PC[7] (GPIO) I/O SD Clock or GPIO G8 SD_CMD I/O SD_CMD I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O PC[3] (GPIO) I/O SD CMD or GPIO H8 SD_POW PC[6] (GPIO) I/O PC[6] (GPIO) I/O PC[6] (GPIO) I/O H10 SD_WP K7 SD2_D[7] I/O PB[7] (GPIO) I/O PB[7] (GPIO) I/O GPIF_DATA[7] I/O GPIF_DATA[7] I/O SD2 Data or GPIO or SNVDDQ GPIF Data VGND K8 SD2_D[6] I/O PB[6] (GPIO) I/O PB[6] (GPIO) I/O GPIF_DATA[6] I/O GPIF_DATA[6] I/O SD2 Data or GPIO or GPIF Data J8 SD2_D[5] I/O PB[5] (GPIO) I/O PB[5] (GPIO) I/O GPIF_DATA[5] I/O GPIF_DATA[5] I/O SD2 Data or GPIO or GPIF Data K9 SD2_D[4] I/O PB[4] (GPIO) I/O PB[4] (GPIO) I/O GPIF_DATA[4] I/O GPIF_DATA[4] I/O SD2 Data or GPIO or GPIF Data J9 SD2_D[3] I/O PB[3] (GPIO) I/O PB[3] (GPIO) I/O GPIF_DATA[3] I/O GPIF_DATA[3] I/O SD2 Data or GPIO or GPIF Data H9 SD2_D[2] I/O PB[2] (GPIO) I/O PB[2] (GPIO) I/O GPIF_DATA[2] I/O GPIF_DATA[2] I/O SD2 Data or GPIO or GPIF Data K10 SD2_D[1] I/O PB[1] (GPIO) I/O PB[1] (GPIO) I/O GPIF_DATA[1] I/O GPIF_DATA[1] I/O SD2 Data or GPIO or GPIF Data J10 SD2_D[0] I/O PB[0] (GPIO) I/O PB[0] (GPIO) I/O GPIF_DATA[0] I/O GPIF_DATA[0] I/O SD2 Data or GPIO or GPIF Data SD_POW I SD_WP I N/C N/C PC[5] (GPIO) SD Power or GPIO SD Write Protect K6 SD2_CLK O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA[6] (GPIO) I/O SD2 Clock or GPIO J6 SD2_CMD I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O SD2 CMD or GPIO J5 SD2_POW O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC[0] (GPIO) I/O SD2 Power or GPIO K4 N/C O N/C O N/C O GPIF_CTL[1] O GPIF_CTL[1] O GPIF Control Signal GPIF Control Signal H6 N/C O N/C O N/C O GPIF_CTL[0] O GPIF_CTL[0] O J7 PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O PA[5] (GPIO) I/O GPIO J4 N/C I GPIF_RDY[0] O GPIF_RDY[0] O GPIF Ready Signal K5 SD2_WP O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O PC[2] (GPIO) I/O SD Write Protect or GPIO B10 RESETOUT O RESETOUT O RESETOUT O RESETOUT / GPIF_RDY[1] O RESETOUT / GPIF_RDY[1] O Reset Out C9 SD2_CD I/O PC-5 (GPIO[1]) I I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O GPIO or SD2 CD D8 PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) SD_CD I SD_CD I I/O PC-4 (GPIO[0]) I/O PC-4 (GPIO[0]) I/O GPIO or SD CD N/C I N/C I GVDDQ VGND C10 RESET# I RESET C7 WAKEUP I Wake Up Signal Document Number: 001-13805 Rev. *Q Page 19 of 87 CYWB022XX Family Table 9. Astoria CYWB0216ABS 121-ball FBGA Package Pin Assignments (continued) Power Clock Conf Pin Name C5 XTALSLC[1] C4 XTALSLC[0] E8 TEST[2] C8 TEST[1] Pin Description I Clock Select 1 GVDDQ VGND Clock Select 0 I Test Cfg 2 Test Cfg 1 D7 TEST[0] A8 XTALIN I Crystal/Clock IN B8 XTALOUT O Crystal Out D4 H4 PVDDQ Power Processor I/F VDD H5 SNVDDQ Power NAND VDD B5 UVDDQ Power USB VDD H7 SSVDDQ Power SDIO VDD D6 GVDDQ Power Misc I/O VDD B9 AVDDQ Power Analog VDD B7 XVDDQ Power Crystal VDD D5, G4, G5, G6, G7, F7 VDD Power Core VDD A10 VDD33 Power Independent 3.3 V B6 UVSSQ Power USB GND A9 AVSSQ Power Analog GND E4, E5, E6, E7, F4, F5, F6 VGND Power Core GND Document Number: 001-13805 Rev. *Q Power Domain Test Cfg 0 XVDDQ VGND Page 20 of 87 CYWB022XX Family Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments Pin Name U-Port Int P-Port Ball # PNAND Pin Description I/O SPI I/O H9 Ext pull low I SCK I Clock F9 CE# I SS# I CE# or SPI Slave Select E7 SDA I/O SDA I/O H8 SCL I/O SCL I/O J9 WP# G8 A[3]=0; (Ext pull low) E6 A[2]=0; (Ext pull low) G9 RB# F8 CLE D9 I/O[7] D8 I/O[6] C9 I I2C clock I PNAND WP I A[3]=0; (Ext pull up) I A[3] I A[2]=0; (Ext pull low) I A[2] O Ext pull up I PNAND R/B# I Ext pull up I PNAND CLE I/O Ext pull up I IO7 I/O Ext pull up I IO6 I/O[5] I/O Ext pull up I IO5 B9 I/O[4] I/O Ext pull up I IO4 C8 I/O[3] I/O Ext pull up I IO3 C7 I/O[2] I/O Ext pull up I IO2 B8 I/O[1] I/O SDO O IO1 or SPI SDO A8 I/O[0] I/O SDI B7 ALE B6 RE# I Ext pull up I Output Enable A7 WE# I Ext pull up I WE# C1 INT# O SINT# O INT Request A4 D+ I/O/Z USB D+ A5 D- I/O/Z USB D- C4 SWD+ I/O/Z USB Switch D+ C5 SWD- I/O/Z USB Switch D- Document Number: 001-13805 Rev. *Q Ext pull up PVDDQ VGND I2C data Ext pull up I Power Domain I IO0 or SPI SDI I Address Valid GVDDQ VGND UVDDQ UVSSQ Page 21 of 87 CYWB022XX Family Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments (continued) Pin Name Other S-Port Ball # Double SDIO Configuration I/O SDIO & GPIO Configuration I/O GPIO Configuration I/O GPIF Configuration I/O GPIF & GPIO Configuration Pin Description Power Domain SSVDDQ VGND I/O H2 SD_D[7] I/O SD_D[7] I/O PD[7] (GPIO) I/O GPIF_DATA [15] I/O PD[7] (GPIO) I/O SD Data or GPIO or GPIF Data H1 SD_D[6] I/O SD_D[6] I/O PD[6] (GPIO) I/O GPIF_DATA [14] I/O PD[6] (GPIO) I/O SD Data or GPIO or GPIF Data G3 SD_D[5] I/O SD_D[5] I/O PD[5] (GPIO) I/O GPIF_DATA [13] I/O PD[5] (GPIO) I/O SD Data or GPIO or GPIF Data G2 SD_D[4] I/O SD_D[4] I/O PD[4] (GPIO) I/O GPIF_DATA [12] I/O PD[4] (GPIO) I/O SD Data or GPIO or GPIF Data F2 SD_D[3] I/O SD_D[3] I/O PD[3] (GPIO) I/O GPIF_DATA [11] I/O PD[3] (GPIO) I/O SD Data or GPIO or GPIF Data F3 SD_D[2] I/O SD_D[2] I/O PD[2] (GPIO) I/O GPIF_DATA [10] I/O PD[2] (GPIO) I/O SD Data or GPIO or GPIF Data E3 SD_D[1] I/O SD_D[1] I/O PD[1] (GPIO) I/O GPIF_DATA [9] I/O PD[1] (GPIO) I/O SD Data or GPIO or GPIF Data E2 SD_D[0] I/O SD_D[0] I/O PD[0] (GPIO) I/O GPIF_DATA [8] I/O PD[0] (GPIO) I/O SD Data or GPIO or GPIF Data G1 SD_CLK O SD_CLK PC-7 (GPIO) I/O PC-7 (GPIO) I/O PC-7 (GPIO) I/O SD Clock or GPIO F4 SD_CMD I/O SD_CMD I/O PC-3 (GPIO) I/O PC-3 (GPIO) I/O PC-3 (GPIO) I/O SD CMD or GPIO J1 SD_POW O SD_POW O PC-6 (GPIO) I/O PC-6 (GPIO) I/O PC-6 (GPIO) I/O SD Power or GPIO E1 SD_WP I I I/O SD Write Protect H5 SD2_D[7] I/O PB[7] (GPIO) I/O PB[7] (GPIO) I/O GPIF_DATA [7] I/O GPIF_DATA [7] I/O SD2 Data or GPIO or SNVDDQ GPIF Data VGND J4 SD2_D[6] I/O PB[6] (GPIO) I/O PB[6] (GPIO) I/O GPIF_DATA [6] I/O GPIF_DATA [6] I/O SD2 Data or GPIO or GPIF Data G5 SD2_D[5] I/O PB[5] (GPIO) I/O PB[5] (GPIO) I/O GPIF_DATA [5] I/O GPIF_DATA [5] I/O SD2 Data or GPIO or GPIF Data H4 SD2_D[4] I/O PB[4] (GPIO) I/O PB[4] (GPIO) I/O GPIF_DATA [4] I/O GPIF_DATA [4] I/O SD2 Data or GPIO or GPIF Data J3 SD2_D[3] I/O PB[3] (GPIO) I/O PB[3] (GPIO) I/O GPIF_DATA [3] I/O GPIF_DATA [3] I/O SD2 Data or GPIO or GPIF Data G4 SD2_D[2] I/O PB[2] (GPIO) I/O PB[2] (GPIO) I/O GPIF_DATA [2] I/O GPIF_DATA [2] I/O SD2 Data or GPIO or GPIF Data H3 SD2_D[1] I/O PB[1] (GPIO) I/O PB[1] (GPIO) I/O GPIF_DATA [1] I/O GPIF_DATA [1] I/O SD2 Data or GPIO or GPIF Data J2 SD2_D[0] I/O PB[0] (GPIO) I/O PB[0] (GPIO) I/O GPIF_DATA [0] I/O GPIF_DATA [0] I/O SD2 Data or GPIO or GPIF Data SD_W N/C I N/C I PC-5 (GPIO) F7 SD2_CLK O PA[6] (GPIO) I/O PA[6] (GPIO) I/O PA-6 (GPIO) I/O PA-6 (GPIO) I/O SD2 Clock or GPIO H6 SD2_CMD I/O PA[7] (GPIO) I/O PA[7] (GPIO) I/O PA-7 (GPIO) I/O PA-7 (GPIO) I/O SD2 CMD or GPIO G7 SD2_POW O PC[0] (GPIO) I/O PC[0] (GPIO) I/O PC-0 (GPIO) I/O PC-0 (GPIO) I/O SD2 Power or GPIO J8 N/C O N/C O N/C O GPIF_CTL[1] O GPIF_CTL[1] O GPIF Control Signal J5 N/C O N/C O N/C O GPIF_CTL[0] O GPIF_CTL[0] O GPIF Control Signal G6 PA-5 (GPIO) I/O PA-5 (GPIO) I/O PA-5 (GPIO) I/O PA-5 (GPIO) I/O PA-5 (GPIO) I/O GPIO H7 N/C I O GPIF_RDY[0] O GPIF Ready Signal J7 SD2_WP O PC-2 (GPIO) I/O PC-2 (GPIO) I/O PC-2 (GPIO) I/O PC-2 (GPIO) I/O SD Write Protect or GPIO C2 RESETOUT O RESETOUT O RESETOUT O RESETOUT / GPIF_RDY[1] O RESETOUT / GPIF_RDY[1] O RESETOUT or GPIF D2 PC-5 (GPIO[1]) or I/O PC-5 (GPIO[1]) SD2_CD I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O PC-5 (GPIO[1]) I/O GPIO or SD2 CD D1 PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) or I/O PC-4 (GPIO[0]) SD_CD I SD_CD I I/O PC-4 (GPIO[0]) I/O PC-4 (GPIO[0]) I/O GPIO or SD CD N/C I N/C I GPIF_RDY[0] C3 RESET# I RESET D4 WAKEUP I Wake Up Signal Document Number: 001-13805 Rev. *Q GVDDQ VGND Page 22 of 87 CYWB022XX Family Table 10. Astoria 81-ball SP WLCSP Package Pin Assignments (continued) Power CLK Conf Pin Name Pin Description A1 XTALSLC I Clock Select B1 TEST[2] I Test Cfg 2 C6 TEST[1] I Test Cfg 1 B4 TEST[0] I Test Cfg 0 A2 XTALIN I Crystal / Clock IN A9, E8 PVDDQ Power Processor I/F VDD J6 SNVDDQ Power GPIF VDD B5 UVDDQ Power USB VDD F1 SSVDDQ Power SDIO VDD D3 GVDDQ Power Misc I/O VDD B3 AVDDQ Power Analog VDD A6, D6, E5, F6 VDD Power Core VDD A3 UVSSQ Power USB GND B2 AVSSQ Power Analog GND D5, D7, E4, E9, F5 VGND Power Core GND Document Number: 001-13805 Rev. *Q Power Domain GVDDQ VGND XVDDQ VGND Page 23 of 87 CYWB022XX Family Table 11. Astoria 81-ball Lite SP WLCSP Package Pin Assignments Pin Name P-Port Ball # SRAM Interface Int I/O PNAND I/O Pin Description G9 CE# I CE# I CE# I CE# H5 A7 I External Pull Up I A7 > 1:SBD A7 > 0: LBD I A7 J8 A6 I SDA I/O SDA I/O A7 or SDA A5 I SCL I/O SCL I/O A6 or SCL H7 A4 I External Pull Up I WP# I A4 or WP# J9 A3 I External Pull Low I External Pull Low I A3 H8 A2 I External Pull Up I External Pull Low I A2 H9 A1 I External Pull Up I R/B# I A1 or R/B# G8 A0 I External Pull Up I CLE I A0 or CLE G6 DQ[15] I/O AD[15] I/O I/O[15] I/O D15, AD15, or IO15 F9 DQ[14] I/O AD[14] I/O I/O[14] I/O D14, AD14, or IO14 F8 DQ[13] I/O AD[13] I/O I/O[13] I/O D13, AD13, or IO13 F7 DQ[12] I/O AD[12] I/O I/O[12] I/O D12, AD12, or IO12 E9 DQ[11] I/O AD[11] I/O I/O[11] I/O D11, AD11, or IO11 E8 DQ[10] I/O AD[10] I/O I/O[10] I/O D10, AD10, or IO10 D9 DQ[9] I/O AD[9] I/O I/O[9] I/O D9, AD9, or IO9 D7 DQ[8] I/O AD[8 I/O I/O[8] I/O D8, AD8, or IO8 D8 DQ[7] I/O AD[7] I/O I/O[7] I/O D7, AD7, or IO7 C9 DQ[6] I/O AD[6] I/O I/O[6] I/O D6, AD6, or IO6 D6 DQ[5] I/O AD[5] I/O I/O[5] I/O D5, AD5, or IO5 B9 DQ[4] I/O AD[4] I/O I/O[4] I/O D4, AD4, or IO4 C8 DQ[3] I/O AD[3] I/O I/O[3] I/O D3, AD3, or IO3 C7 DQ[2] I/O AD[2] I/O I/O[2] I/O D2, AD2, or IO2 B8 DQ[1] I/O AD[1] I/O I/O[1] I/O D1, AD1, or IO1 A8 DQ[0] I/O AD[0] I/O I/O[0] I/O D0I, AD0, or IO0 I ADV# I ALE I Address Valid B6 OE# I OE# I RE# I Output Enable A7 WE# I WE# I WE# I WE# C1 INT# O INT# O INT# O INT Request D4 DRQ# O DRQ# O DRQ# O DMA Request D3 DACK# I I I DMA ACK A4 D+ I/O/Z USB D+ A5 D- I/O/Z USB D- DACK# DACK# C4 SWD+ I/O/Z USB Switch DP C5 SWD- I/O/Z USB Switch DM Document Number: 001-13805 Rev. *Q Power Domain PVDDQ VGND H6 B7 U-Port ADM (Address/Data Multiplexing) GVDDQ VGND UVDDQ UVSSQ Page 24 of 87 CYWB022XX Family Table 11. Astoria 81-ball Lite SP WLCSP Package Pin Assignments (continued) CLK Conf Other S-Port S-Port Interface SD_D[7] I/O SD Data or GPIO H1 SD_D[6] I/O SD Data or GPIO G2 SD_D[5] I/O SD Data or PIO E3 SD_D[4] I/O SD Data or GPIO F2 SD_D[3] I/O SD Data or GPIO F1 SD_D[2] I/O SD Data or GPIO E2 SD_D[1] I/O SD Data or GPIO E1 SD_D[0] I/O SD Data or GPIO G1 SD_CLK I/O SD Clock or GPIO J1 SD_CMD I/O SD CMD or GPIO J5 PB[7] (GPIO) I/O GPIOI J4 PB[6] (GPIO) I/O GPIOI H4 PB[5] (GPIO) I/O GPIOI J3 PB[4] (GPIO) I/O GPIOI H3 PB[3] (GPIO) I/O GPIOI G4 PB[2] (GPIO) I/O GPIOI GPIOI J2 PB[1] (GPIO) I/O H2 PB[0] (GPIO) I/O GPIOI J7 GPIF_RDY O Test Mode J6 GPIF_CTL I Test Mode (Ext Pull-High) D1 SD_CD I SD CD C2 RESET# I RESET E5 WAKEUP I Wake Up Signal TEST[2] I Test Cfg 2 D5 TEST[1] I Test Cfg 1 B1 TEST[0] I Test Cfg 0 A2 XTALIN I Clock IN A1 XTALOUT O Clock OUT UVDDQ Power USBVDD E4 SSVDDQ Power SDIO VDD D2 GVDDQ Power Misc I/O VDD B3 AVDDQ Power Analog VDD B4 XVDDQ Power Crystal VDD UVSSQ Power USB GND B2 AVSSQ Power Analog GND Document Number: 001-13805 Rev. *Q XVDDQ VGND Power Core VDD A3 G7, E6, VGND G5, F4, G3 GVDDQ VGND Power Processor I/F VDD B5 E7, A6, VDD C6, F5 SSVDDQ VGND GVDDQ VGND C3 A9, F6 PVDDQ Power I/O F3 Power Core GND Page 25 of 87 CYWB022XX Family Figure 9. Astoria 100-ball VFBGA Ball Map - Top View 1 2 3 4 5 6 7 8 9 10 ADV# WE# INT# DRQ# D+ D SWD+ XTALIN AVSSQ VDD33 A B DQ[1] DQ[0] OE# DACK# UVDDQ UVSSQ XVDDQ XTALOUT AVDDQ RESETOUT B C DQ[4] DQ[3] DQ[2] XTALSLC[0] XTALSLC[1] SWD WAKEUP TEST[1] GPIO[1] RESET# C D DQ[7] DQ[6] DQ[5] PVDDQ VDD GVDDQ TEST[0] GPIO[0] SD_D[1] SD_D[0] D E DQ[10] DQ[9] DQ[8] VGND VGND VGND VGND TEST[2] SD_D[3] SD_D[2] E F DQ[13] DQ[12] DQ[11] VGND VGND VGND VDD SD_CLK SD_D[5] SD_D[4] F G CE# DQ[15] DQ[14] VDD VDD VDD VDD SD_CMD SD_D[7] H A[5] A[6] A[7] PVDDQ SNVDDQ GPIF_CTL[0] SSVDDQ SD_POW GPIF_DATA[2] J A[3] CLK A[4] GPIF_RDY[0] PC[0] PA[7] PA[5] GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0] J K A[0] A[1] A[2] GPIF_CTL[1] PC[2] PA[6] GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[4] GPIF_DATA[1] K 1 2 3 4 5 6 7 8 9 A SD_D[6] SD_WP G H 10 POWER DOMAIN KEY UVDDQ UVSSQ GVDDQ SSVDDQ VDDQ/AVDDQ VGND/AVSSQ PVDDQ SNVDDQ XVDDQ VDD33 Document Number: 001-13805 Rev. *Q Page 26 of 87 CYWB022XX Family Figure 10. Ball map_CYWB0216 - Top View Top View 1 2 3 4 5 6 7 8 9 10 A P/U P/ U N/C N/C D+ D- SWD+ XTALIN AVSSQ VDD33 11 B P/U P/U P/U P/U UVDDQ UVSSQ XVDDQ XTALOUT AVDDQ RESETOUT C P/U P/U P/U XTALSLC[0] XTALSLC[1] SWD- WAKEUP TEST[1] GPIO[1] RESET# N/C C D P/U P/U P/U PVDDQ VDD GVDDQ TEST[0] GPIO[0] SD_D[1] SD_D[0] N/C D E P/U P/U P/U VGND VGND VGND VGND TEST[2] SD_D[3] SD_D[2] F P/U P/U P/U VGND VGND VGND VDD SD_CLK SD_D[5] SD_D[4] N/C F G P/U P/U P/U VDD VDD VDD VDD SD_CMD SD_D[7] SD_D[6] N/C G H SCL SDA P/U PVDDQ SNVDDQ GPIF_CTL [0] SSVDDQ SD_POW GPIF_DATA[2] SD_WP N/C H J P/U P/D P/U GPIF_RDY [0] PC [0] PA [7] PA [5] GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0] N/C J K P/U P/U P/D GPIF_CTL [1] PC [2] PA [6] GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[ 4] GPIF_DATA[1] N/C K L N/C N/C N/C N/C N/C N/C N/C N/C N/C N/ C N/C L 1 2 3 4 5 6 7 8 9 10 11 N/C N/C N/C A B E POWER DOMAIN KEY UVDDQ UVSSQ GVDDQ SSVDDQ VDDQ/AVDDQ VGNDAVSSQ PVDDQ SNVDDQ XVDDQ VDD33 P/U P/D N/C Document Number: 001-13805 Rev. *Q Page 27 of 87 CYWB022XX Family Figure 11. Ball map_CYWB0220 - Top View Top View 1 2 3 4 5 6 7 8 9 10 11 A ADV# WE# INT# DRQ# N/C N/C N/C XTALIN AVSSQ VDD33 N/C B DQ[1] DQ[0] OE# DACK# UVDDQ UVSSQ XVDDQ XTALOUT AVDDQ RESETOUT N/C B C DQ[4] DQ[3] DQ[2] XTALSLC[0] XTALSLC[1] N/C WAKEUP TEST[1] GPIO[1] RESET# N/C C A D DQ[7] DQ[6] DQ[5] PVDDQ VDD GVDDQ TEST[0] GPIO[0] SD_D[1] SD_D[0] N/C D E DQ[10] DQ[9] DQ[8] VGND VGND VGND VGND TEST[2] SD_D[3] SD_D[2] N/C E F DQ[13] DQ[12] DQ[11] VGND VGND VGND VDD SD_CLK SD_D[5] SD_D[4] N/C F G CE# DQ[15] DQ[14] VDD VDD VDD VDD SD_CMD SD_D[7] SD_D[6] N/C G H A[5] A[6] A[7] PVDDQ SNVDDQ GPIF_CTL[0] SSVDDQ SD_POW GPIF_DATA[2] SD_WP N/C H J A[3] CLK A[4] GPIF_RDY[0] PC [0] PA [7] PA[5] GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0] N/C J K A[0] A[1] A[2] GPIF_CTL[1] PC [2] PA [6] GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[4] GPIF_DATA[1] N/C K L N/C N/C N/C N/C N/C N/C N/C N/C N/C N/ C N/C L 1 2 3 4 5 6 7 8 9 10 11 POWER DOMAIN KEY UVDDQ UVSSQ GVDDQ SSVDDQ VDDQ/AVDDQ VGNDAVSSQ PVDDQ SNVDDQ XVDDQ VDD33 N/C Document Number: 001-13805 Rev. *Q Page 28 of 87 CYWB022XX Family Figure 12. Ball map_CYWB0224 - Top View Top View 1 2 3 4 5 6 7 8 9 10 11 A ADV# WE# INT# DRQ# D+ D- SWD+ XTALIN AVSSQ VDD33 N/C A B DQ[1] DQ[0] OE# DACK# UVDDQ UVSSQ XVDDQ XTALOUT AVDDQ RESETOUT N/C B C DQ[4] DQ[3] DQ[2] XTALSLC[0] XTALSLC[1] SWD- WAKEUP TEST[1] GPIO[1] RESET# N/C C D DQ[7] DQ[6] DQ[5] PVDDQ VDD GVDDQ TEST[0] GPIO[0] SD_D[1] SD_D[0] N/C D E DQ[10] DQ[9] DQ[8] VGND VGND VGND VGND TEST[2] SD_D[3] SD_D[2] N/C E F DQ[13] DQ[12] DQ[11] VGND VGND VGND VDD SD_CLK SD_D[5] SD_D[4] N/C F G CE# DQ[15] DQ[14] VDD VDD VDD VDD SD_CMD SD_D[7] SD_D[6] N/C G H H A[5] A[6] A[7] PVDDQ SNVDDQ GPIF_CTL [0] SSVDDQ SD_POW GPIF_DATA[2] SD_WP N/C J A[3] CLK A[4] GPIF_RDY[0] PC[0] PA[7] PA[5] GPIF_DATA[5] GPIF_DATA[3] GPIF_DATA[0] N/C J K A[0] A[1] A[2] GPIF_CTL[1] PC[2] PA[6] GPIF_DATA[7] GPIF_DATA[6] GPIF_DATA[4] GPIF_DATA[1] N/C K L N/C N/C N/C N/C N/C N/C N/C N/C N/C N/ C N/C L 1 2 3 4 5 6 7 8 9 10 11 POWER DOMAIN KEY UVDDQ UVSSQ GVDDQ SSVDDQ VDDQ/AVDDQ VGNDAVSSQ PVDDQ SNVDDQ XVDDQ VDD33 N/C Document Number: 001-13805 Rev. *Q Page 29 of 87 CYWB022XX Family Figure 13. Astoria 81-ball SP WLCSP Ball Map - Top View 1 2 3 4 5 6 7 8 9 A XTALSLC XTALIN UVSSQ D+ D VDD WE# IO[0] PVDDQ A B TEST[2] AVSSQ AVDDQ TEST[0] UVDDQ RE# ALE IO[1] IO[4] B C INT# RESETOUT RESET# SWD+ SWD TEST[1] IO[2] IO[3] IO[5] C D GPIO[0] GPIO[1] GVDDQ WAKEUP VGND VDD VGND IO[6] IO[7] D E SD_WP SD_D[0] SD_D[1] VGND VDD A[2] SDA PVDDQ VGND E F SSVDDQ SD_D[3] SD_D[2] SD_CMD VGND VDD PA[6] CLE CE# F G SD_CLK SD_D[4] SD_D[5] GPIF_DATA[2] GPIF_DATA[5] PA[5] PC[0] A[3] R/B# G H SD_D[6] SD_D[7] GPIF_DATA[1] GPIF_DATA[4] GPIF_DATA[7] PA[7] GPIF_RDY[0] SCL GPIF_CTL [0] SNVDDQ PC [2] GPIF_CTL [1] WP# 5 6 7 8 9 J POW 1 GPIF_DATA[0] GPIF_DATA[3] GPIF_DATA[6] 2 3 4 PullLow H J POWER DOMAIN KEY UVDDQ UVSSQ GVDDQ SSVDDQ VDDQ/AVDDQ VGND/AVSSQ PVDDQ SNVDDQ XVDDQ Document Number: 001-13805 Rev. *Q Page 30 of 87 CYWB022XX Family Figure 14. Astoria 81-ball Lite SP WLCSP Ball Map - Top View A B C D E F G H J 1 2 3 4 5 6 7 8 9 XTALOUT XTALIN UVSSQ D+ D- VDD WE# DQ[0] PVDDQ TEST[0] AVSSQ AVDDQ XVDDQ UVDDQ OE# ADV# DQ[1] DQ[4] DQ[6] INT# RESET# TEST[2] SWD+ SWD- VDD DQ[2] DQ[3] GPIO[0] GVDDQ DACK# DRQ# TEST[1] DQ[5] DQ[8] DQ[7] DQ[9] SD_D[0] SD_D[1] SD_D[4] SSVDDQ WAKEUP VGND VDD DQ[10] DQ[11] SD_D[2] SD_D[3] SD_D[7] VGND VDD PVDDQ DQ[12] DQ[13] DQ[14] SD_CLK SD_D[5] VGND PB[2] (GPIO) VGND DQ[15] VGND A[0] CE# A[7] A[5] A[4] SD_D[6] PB[0] (GPIO) PB[3] (GPIO) PB[5] (GPIO) SD_CMD PB[1] (GPIO) PB[4] (GPIO) PB[6] (GPIO) 1 2 3 4 PB[7] (GPIO) GPIF_RDY GPIF_CTL 5 6 7 A[2] A[1] A[6] A[3] 8 9 A B C D E F G H J POWER DOMAIN KEY UVDDQ UVSSQ GVDDQ SSVDDQ VDD/AVDDQ VGND/AVSSQ PVDDQ XVDDQ Document Number: 001-13805 Rev. *Q Page 31 of 87 CYWB022XX Family Absolute Maximum Ratings Operating Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. TA (ambient temperature under bias) Industrial .................................................... -40 C to +85 C Storage temperature ................................ -65 C to +150 C VDD, AVDDQ supply voltage ..........................1.7 V to 1.9 V Ambient temperature with power supplied (Industrial) ................. -40 C to +85 C UVDDQ supply voltage ....................................3.0 V to 3.6 V Supply voltage to ground potential VDD, AVDDQ ..............................................-0.5 V to +2.0 V GVDDQ, PVDDQ, SSVDDQ, SNVDDQ, UVDDQ, and VDD33 and XVDDQ ..............-0.5 V to +4.0 V PVDDQ, GVDDQ, SNVDDQ, SSVDDQ supply voltage ..................................................1.7 V to 3.6 V XVDDQ (Crystal I/O) supply voltage ...............3.0 V to 3.6 V XVDDQ (Ext. Clock I/O) supply voltage ..........1.7 V to 1.9 V DC input voltage to any input pin (Depends on I/O supply voltage. Inputs are not overvoltage tolerant.) ..............1.89 V to 3.6 V DC voltage applied to outputs in High Z state .................... -0.5 V to VDDQ + 0.5 V Static discharge voltage (ESD) from JESD22-A114 ...................................... > 2000 V Latch up current ..................................................... > 200 mA Maximum output short circuit current for all I/O configurations. (Vout = 0 V) [1] ................. -100 mA Note 1. Do not test more than one output at a time. Duration of the short circuit must not exceed one second. Tested initially and after any design or process changes that may affect these parameters Document Number: 001-13805 Rev. *Q Page 32 of 87 CYWB022XX Family DC Characteristics Table 12. DC Specifications for All Voltage Supplies (Except USB Switch) Parameter VDD Min Typ Max Unit AVDDQ XVDDQ XVDDQ PVDDQ[4] Core voltage supply Analog voltage supply Crystal voltage supply Clock voltage supply Processor interface I/O 1.7 1.7 3.0 1.7 1.7 1.8 1.8 3.3 1.8 1.8, 2.5, 3.3 1.9 1.9 3.6 1.9 3.6 V V V V V GVDDQ[4] Miscellaneous I/O voltage supply 1.7 1.8, 2.5, 3.3 3.6 V SNVDDQ[3, 4] S-Port GPIF voltage supply 1.7 3.6 V SSVDDQ[3, 4] S-Port SD I/O voltage supply 1.7 1.8, 2.5, 3.3 1.8, 2.5, 3.3 3.6 V UVDDQ[6] VDD33 VIH1[5] USB voltage supply Power sequence control supply Input HIGH voltage 1 3.0 3.0 3.6 3.6 VCC + 0.3 V V V VIH2[5] Input HIGH voltage 2 VIL VOH VOL IIX IOZ ICC Core Input LOW voltage Output HIGH voltage Output LOW voltage Input leakage current Output leakage current Operating current of core voltage supply (VDD) and analog voltage supply (AVDDQ) ICC Crystal ICC USB ISB1 (For 100-ball VFBGA and 81-ball SP WLCSPPackages) Description Operating current of crystal voltage supply (XVDDQ)[8] Conditions All ports except USB, 2.0 V < VCC < 3.6 V 0.625 x VCC 3.3 3.3 - All ports except USB, 1.7 V < VCC < 2.0 V VCC - 0.4 - VCC + 0.3 -0.3 0.9 x VCC 0.25 x VCC -1 -1 - - - - - - - 0.1 x VCC 1 1 110 V V V A A mA - - 115 mA - - 5 mA - - - N/A 25 mA - - 300[2] - - 3000 A A IOH(MAX) = -0.1 mA IOL(MIN) = 0.1 mA All I/O signals held at VDDQ All I/O signals held at VDDQ VFBGA package outputs tri-stated WLCSP package outputs tri-stated VFBGA package XTALOUT floating WLCSP package Operating current of USB voltage Operating and terminated for high speed supply (UVDDQ)[8] mode Total standby current of Astoria 1. *VDDQ = 3.3 V nominal 25 C when device is in suspend mode (3.0-3.6 V) 85 C 2. Outputs and Bidirs high or floating[7] 3. XTALOUT floating 4. D+ floating, D-grounded 5. Device in suspend mode Notes 2. Isb1 typical value is not a maximum specification but a typical value. Isb1 maximum current value specified for 85C. 3. The SSVDDQ I/O voltage can be dynamically changed (for example, from high range to low range) as long as the supply voltage undershoot does not surpass the lower minimum voltage limit. SSVDDQ and SNVDDQ levels for SD modes: 2.0 V3.6 V, MMC modes: 1.7 V3.6 V. 4. Interfaces with a voltage range are adjustable with respect to the I/O voltage and supports multiple I/O voltages. 5. VCC = pertinent VDDQ value. 6. When U-Port is in a disabled state, UVDDQ can go down to 2.4 V, provided UVDDQ is still the highest supply voltage level. 7. The Outputs and Bidirs that are forced low in standby mode can increase I/O supply standby current beyond specified value. 8. Active Current Conditions: -UVDDQ: USB transmitting 50% of the time, receiving 50% of the time. -PVDDQ/SNVDDQ/SSVDDQ/GVDDQ: Active current depends on I/O activity, bus load and supply level. -XVDDQ: Assume highest frequency clock (48 MHz) or crystal (26 MHz). Document Number: 001-13805 Rev. *Q Page 33 of 87 CYWB022XX Family Table 12. DC Specifications for All Voltage Supplies (Except USB Switch) (continued) Parameter Description Conditions Total standby current of Astoria 6. *VDDQ = 3.3 V nominal when device is in suspend mode (3.0-3.6 V) (For 81-ball Lite 7. Outputs and Bidirs high or SP WLCSP) floating[7] 8. XTALOUT floating 9. D+ floating, D- grounded 10.Device in suspend mode Total standby current of Astoria 1. *VDDQ = 3.3 V Nominal ISB2 when device is in standby mode (3.0-3.6 V) ISB1 Min Typ Max Unit 25 C 85 C TBD TBD TBD TBD TBD TBD A A 25 C - - 52 A 85 C - - 450 A 25 C 85 C - - - - 28 139 A A Min Typ Max Unit 1.6 - - V 2. Outputs and Bidirs High or Floating[7] 3. XTALOUT Floating 4. D+ Floating, D- Grounded ISB3 Total standby current of Astoria when device is in core power-down mode 1. Outputs and Bidirs High or Floating[7] 2. XTALOUT Floating 3. D+ Floating, D- Grounded 4. Core Powered Down Table 13. USB Switch DC Specifications Parameter Description Conditions VIH Input voltage HIGH VIL Input voltage LOW - - 0.8 V RON On resistance 4.5 7 10 ROFF Off resistance 1M - - CDP/DM_ON D+/D- on capacitance (with Full-Speed switch On) - - 25 pF CDP/DM_OFF D+/D- off capacitance - - 20 pF Table 14. Capacitance Parameter CIN COUT Description Typ Max Unit - 9 pF Input pin capacitance, D+/D- - 15 pF Output pin capacitance - 10 pF Input pin capacitance, except D+/D- Document Number: 001-13805 Rev. *Q Conditions TA = 25 C, f = 1 MHz, VCC = VCCIO Page 34 of 87 CYWB022XX Family AC Timing Parameters P Port Interface PCRAM Non Multiplexing Asynchronous Mode Table 15. Asynchronous Mode Timing Parameters Parameter Description Min Max Unit Read Timing Parameters Interface bandwidth (MBPS) - 66.7 MBps tAA Address to data valid - 30 ns tOH Data output hold from address change 3 - ns tEA Chip enable to data valid - 30 ns tAADV ADV# to data valid access time - 30 ns tAVS Address valid to ADV# HIGH 5 - ns tAVH ADV# HIGH to address hold 2[10] - ns tCVS CE# low setup time to ADV# HIGH 5 - ns tVPH ADV# HIGH time 15[9] - ns tVP ADV# pulse width LOW 7.5 - ns tOE OE# LOW to data valid - 22.5 ns tOLZ OE# LOW to Low Z 3 - ns tOHZ OE# HIGH to High Z 0 22.5 ns tLZ CE# LOW to Low Z 3 - ns tHZ CE# HIGH to High Z - 22.5 ns Write Timing Parameters tCW CE# LOW to write end 30 - ns tAW Address Valid to write end 30 - ns tAS Address setup to write start 0 - ns tADVS ADV# setup to write start 0 - ns tWP WE# pulse width 22 - ns tWPH WE# HIGH time 10 - ns tCPH CE# HIGH time 10 - ns tAVS Address valid to ADV# HIGH 5 - ns tAVH ADV# HIGH to address hold 2[10] - ns tCVS CE# LOW setup time to ADV# HIGH 5 - ns tVPH ADV# HIGH time 15[9] - ns tVP ADV# pulse width LOW 7.5 - ns tVS ADV# LOW to end of write 30 - ns tDW Data setup to write end 18 - ns tDH Data hold from write end 0 - ns tWHZ Write to DQ High Z output - 22.5 ns tOW End of write to Low Z output 3 - ns Notes 9. In applications where access cycle time is at least 60 ns, tVPH can be relaxed to 12 ns. 10. In applications where back-to-back accesses are not performed on different endpoint addresses, the minimum tAVH spec. can be relaxed to 0 ns. Document Number: 001-13805 Rev. *Q Page 35 of 87 CYWB022XX Family Figure 15. Non Multiplexing Asynchronous Pseudo CRAM Mode Single Read Time Parameters A Valid Address tAA tVPH tAVH tAVS tOH ADV# tVP tHZ tAADV tCVS CE# tEA tOE OE# tOHZ R/W# DQ tOLZ tLZ High-Z Valid Output Figure 16. Non Multiplexing Asynchronous Pseudo CRAM mode Back to Back Read Timing Parameters A Valid Address Valid Address tAA tVPH tAVS tAVH ADV# tHZ tVP CE# tAADV tEA OE# tOHZ WE# DQ High-Z Valid Output Valid Output tLZ Document Number: 001-13805 Rev. *Q Page 36 of 87 CYWB022XX Family Figure 17. Non Multiplexing Asynchronous Pseudo CRAM Mode Back to Back Write Timing Parameters A Valid Address tAVS tVPH ADV# Valid Address tAVH tVP tCPH tVS CE# tCW OE# tAW tWPH tWP WE# tAS DQ_IN tOW tDH tDW tADVS High-Z Valid Input tWHZ tLZ Valid Input DQ_OUT Figure 18. Non Multiplexing Asynchronous Pseudo CRAM Mode Read to Write Timing Parameters Valid Address A Valid Address tAA tVPH tAVS tAVS tVPH tAVH Valid Address tAVH tVP ADV# tVP CE# tVS tAADV tEA tOE OE# tOHZ tAW tWP WE# tAS DQ_IN DQ_OUT High-Z tOLZ High-Z tLZ Document Number: 001-13805 Rev. *Q tWHZ tDW tDH Valid Input tOW Valid Input Valid Output Page 37 of 87 CYWB022XX Family Figure 19. Non Multiplexing Asynchronous Pseudo CRAM Mode Write to Read Timing Parameters A Valid Address Valid Address tAVS tAVH tAA tAVS tAVH tVP ADV# tVP tVS CE# tAADV tOE OE# tAW tWP WE# tAS DQ_IN tWHZ DQ_OUT Document Number: 001-13805 Rev. *Q tDW tDH Valid Input tOLZ Valid Output Page 38 of 87 CYWB022XX Family Address Data Multiplexing Asynchronous Mode Table 16. Address Data Multiplexing Asynchronous Mode Timing Parameters Parameter Description Min Max Unit Read Timing Parameters Interface bandwidth - 50 MBps tAA Address to data valid - 30 ns tEA Chip enable access time - 30 ns tAADV ADV# to data valid access time - 30 ns tAVS Address valid to ADV# HIGH 5 - ns tAVH ADV# HIGH to address hold 2 - ns tCVS CE# LOW setup time to ADV# HIGH 5 - ns tVPH ADV# HIGH time 15 - ns tVP ADV# pulse width LOW 7.5 - ns tAVDOE ADV# HIGH to OE# LOW 0 - ns tOE OE# LOW to data valid - 22.5 ns tOLZ OE# LOW to Low Z 3 - ns tOHZ OE# HIGH to High Z - 22.5 ns tLZ CE# LOW to Low Z 3 - ns tHZ CE# HIGH to High Z - 22.5 ns Write Timing Parameters tCW CE# LOW to write end 30 - ns tAW Address valid to write end 30 - ns tAVDWE ADV# HIGH to write start 0 - ns tWP WE# pulse width 22 - ns tAVS Address valid to ADV# HIGH 5 - ns tAVH ADV# HIGH to address hold 2 - ns tCVS CE# LOW setup time to ADV# HIGH 5 - ns tVPH ADV# HIGH time 15 - ns tVP ADV# pulse width LOW 7.5 - ns tVS ADV# LOW to end of write 30 - ns tDS Data setup to write end 18 - ns tDH Data hold from write end 0 - ns Document Number: 001-13805 Rev. *Q Page 39 of 87 CYWB022XX Family Figure 20. Address Data Multiplexing Asynchronous Single Read Timing Parameters tAA tAVH tAVS A<7:0>/ DQ<15:0> Valid Address tVPH High-Z Valid Data High-Z tAADV tVP ADV# tHZ tCVS tLZ tEA CE# tOHZ tAVDOE tOLZ tOE OE# Logic High WE# Figure 21. Address Data Multiplexing Asynchronous Single Write Timing Parameters tAW tAVS A<7:0>/ DQ<15:0> tAVH tDS Valid Address tVPH High-Z tVS tVP ADV# tCVS CE# Valid Input tDH tCW tAVDWE WE# Document Number: 001-13805 Rev. *Q tWP Page 40 of 87 CYWB022XX Family Non Multiplexing Synchronous Mode Timing Parameters Table 17. Non Multiplexing Synchronous Mode Timing Parameters Min Max Unit FREQ Parameter Interface clock frequency Description - 33 MHz tCLK Clock period 30 - ns tCLKH Clock HIGH time 12 - ns tCLKL Clock LOW time 12 - ns tWH Address hold time (write to the register) for the first time that processor configures the P-Port from non-ADM asynchronous mode to non-ADM synchronous mode 0 - ns tS CE#/WE#/ADDR/DQ setup time 7.5 - ns tH CE#/WE#/ADDR/DQ hold time 1.5 - ns tCO Clock to valid data - 18 ns tOH Clock to data hold time 2 - ns tOLZ OE# LOW to data Low Z 3 - ns tOHZ OE# HIGH to data High Z - 22.5 ns tOE OE# LOW to data valid - 22.5 ns tCKHZ Clock to data High Z - 18 ns tCKLZ Clock to data Low Z 3 - ns Document Number: 001-13805 Rev. *Q Page 41 of 87 CYWB022XX Family Figure 22. Non Multiplexing Synchronous Pseudo CRAM Mode Write Timing Parameters tCLKH tCLKL tCLK CLK tH tS CE# A[7:0] An+1 An An+2 An+3 tWH WE# OE# DQ[15:0] (input) DQ[15:0] (output) Dn+1 Dn Dn+2 Dn+3 High-Z Note: - Assumes previous cycle had CE# deselected - OE# is don't care during write operations Figure 23. Non Multiplexing Synchronous Pseudo CRAM Mode Read Timing Parameters tCLKH tCLKL tCLK CLK tS CE# A[7:0] tH An An+1 An+2 An+4 An+3 WE# OE# DQ[15:0] High-Z (input) DQ[15:0] High-Z (output) tCO tOHZ tOH Dn tOLZ Dn+1 tOE tCKLZ Note: - Assumes previous cycle had CE # deselected Document Number: 001-13805 Rev. *Q Page 42 of 87 CYWB022XX Family Figure 24. Non Multiplexing Synchronous Mode Read (OE# Fixed LOW) Timing Parameters CLK tS CE# A[7:0] tH Ax+1 Ax Ax+2 WE# OE# DQ[15:0] (output) Dx-2 tCKHZ tOH tCO Dx-1 Dx Dx Dx+1 Note: - Ass umes previous s everal c ycles w ere Read Figure 25. Non Multiplexing Synchronous Mode Read to Write (OE# Controlled) Timing Parameters tCLKH tCLKL tCLK CLK tS CE# A[7:0] tH Ax Ax+1 An An+1 An+2 WE# OE# DQ[15:0] (input) DQ[15:0] (output) tS High-Z Dn tOH Dx-2 Dx-1 tH Dn+1 Dn+2 tOHZ Dx tCO Note: - Assumes previous several cycles were Read - (Ax) and (Ax+1) cycles are turnaround . (A x+1) operation does not cross pipeline . Document Number: 001-13805 Rev. *Q Page 43 of 87 CYWB022XX Family Figure 26. Non Multiplexing Synchronous Mode Read to Write (OE# Fixed LOW) Timing Parameters tCLKH tCLKL tCLK CLK tH tS CE# A[7:0] Ax+1 Ax Ax+2 An+1 An WE# OE# DQ[15:0] (input) tS High-Z tCO DQ[15:0] (output) tH Dn Dn+1 tOH Dx-2 Dx Dx-1 tCO Note: - Assumes previous several cycles were Read - In this scenario, OE# is held LOW - (Ax) and (Ax+1) cycles are turnaround. (Ax+1) operation does not cross pipeline. - No operation is performed during the Ax+2 cycle (true turnaround operation) Figure 27. Non Multiplexing Synchronous Mode Write to Read Timing Parameters tCLKH tCLKL tCLK CLK tH tS CE# A[7:0] An An+1 An+2 An+3 tWH WE# OE# DQ[15:0] (input) DQ[15:0] (output) Dn Dn+1 Dn+2 Dn+3 High-Z Note: - Assumes previous cycle had CE# deselected - OE# is don't care during write operations Document Number: 001-13805 Rev. *Q Page 44 of 87 CYWB022XX Family Address Data Multiplexing Synchronous Mode Table 18. Address Data Multiplexing Synchronous Mode Parameters Min Max Unit FREQ Parameter Interface clock frequency Description - 33 MHz tAVH Address hold time (write to the register) for the first time that processor configures the P-Port from ADM asynchronous mode to ADM synchronous mode 2 - ns tCLK Clock period 30 - ns tCLKH Clock High time 12 - ns tCLKL Clock Low time 12 - ns tS CE#/WE#/DQ setup time 7.5 - ns tH CE#/WE#/DQ hold time 1.5 - ns tCO Clock to valid data - 18 ns tOH Clock to data hold time 2 - ns tAVDOE ADV# HIGH to OE# LOW 0 - ns tAVDWE ADV# HIGH to WE# LOW 0 - ns tHZ CE# HIGH to data High Z - 22.5 ns tOHZ OE# HIGH to data High Z - 22.5 ns tOLZ OE# LOW to data Low Z 3 - ns tOE OE# LOW to data Valid - 22.5 ns Document Number: 001-13805 Rev. *Q Page 45 of 87 CYWB022XX Family Figure 28. Address Data Multiplexing Synchronous Burst Read Timing Parameters (Burst of 4 with Latency=2, WE#=HIGH) tCLKH tCLKL CLK tCLK tS A<7:0>/ DQ<15:0> tOH tH Valid Address tAVH * tS tCO D0 D1 D2 D3 tH ADV# tHZ tS CE# tAVDOE tOLZ tOHZ tOE OE# Logic High WE# * tAVH is the ADM address hold time (write to the register) for the first time that Processor configure the P-Port Astoria from ADM Async mode to ADM Sync mode Figure 29. Address Data Multiplexing Synchronous Burst Write Timing Parameters (Burst of 4 with Latency=2, OE# is Ignored) tCLKH tCLKL CLK tCLK tS A<7:0>/ DQ<15:0> tDS tH Valid Address tAVH * tS tDH D0 tDH D1 D2 D3 tH ADV# tS tS CE# tAVDWE WE# * tAVH is the ADM address hold time (write to the register) for the first time that Processor configure the P-Port Astoria from ADM Async mode to ADM Sync mode Document Number: 001-13805 Rev. *Q Page 46 of 87 CYWB022XX Family Non Multiplexing Asynchronous SRAM Mode Table 19. Asynchronous SRAM Mode Timing Parameters Parameter Description Interface bandwidth (MBPS) Min Max Unit - 66.7 MBP S Read Timing Parameters tRC Read cycle time 30 - ns tAA Address to data valid - 30 ns tOH Data output hold from address change 3 - ns tEA Chip enable to data valid - 30 ns tOE OE# LOW to data valid - 22.5 ns tOLZ OE# LOW to Low Z 3 - ns tOHZ OE# HIGH to High Z 0 22.5 ns tLZ CE# LOW to Low Z 3 - ns tHZ CE# HIGH to High Z - 22.5 ns Write Timing Parameters tWC Write cycle time 30 - ns tCW CE# LOW to write end 30 - ns tAW Address valid to WE# end 30 - ns tAS Address setup to WE# or CE# start 0 - ns tAH Address hold time from WE# or CE# end for PCRAM to SRAM changes (Astoria is default in the PCRAM mode after RESET. This timing is the requirement for the first time to access the P-Port Interface Configuration Register to change the Astoria to PSRAM mode) 2 - ns Address hold time from WE# or CE# end for PSRAM mode 0 - tWP WE# pulse width 22 - ns tWPH WE# HIGH time 10 - ns tCPH CE# HIGH time 10 - ns tDS Data setup to write end 18 - ns tDH Data hold from write end 0 - ns tWHZ Write to DQ High Z output - 22.5 ns tOW End of write to Low Z output 3 - ns tDPW DRQ# pulse width 110 - ns Document Number: 001-13805 Rev. *Q Page 47 of 87 CYWB022XX Family Figure 30. Non Multiplexing Asynchronous SRAM Read Timing Parameters Endpoint Read - Address Transition Controlled Timing (OE# is asserted ) tRC ADDRESS tAA tOH DATA OUT PREVIOUS DATA VALID DATA VALID OE# Controlled Timing ADDRESS tRC CE# tEA tHZ OE# tOHZ tOE tOLZ DATA OUT HIGH IMPEDANCE tLZ Document Number: 001-13805 Rev. *Q DATA VALID HIGH IMPEDANCE Page 48 of 87 CYWB022XX Family Figure 31. Non Multiplexing Asynchronous SRAM Write Timing (WE# and CE# Controlled) Write Cycle 1 WE# Controlled, OE# High During Write tWC ADDRESS tCW CE# tAW WE# tAH tWP tAS tWPH OE# tDS DATA I/O tDH VALID DATA VALID DATA tWHZ Write Cycle 2 CE# Controlled , OE# High During W rite tWC ADDRESS tAS tCW tCPH CE# tAW tAH tWP WE# OE# tDS DATA I/O VALID DATA tDH VALID DATA tWHZ Document Number: 001-13805 Rev. *Q Page 49 of 87 CYWB022XX Family Figure 32. Non Multiplexing Asynchronous SRAM Write Timing (WE# Controlled, OE# LOW) Write Cycle 3 WE# Controlled. OE# Low tWC tCW CE# tAW tAH tAS tWP WE# tDS DATA I/O VALID DATA tWHZ Document Number: 001-13805 Rev. *Q tDH tOW Page 50 of 87 CYWB022XX Family Pseudo NAND (PNAND) Mode Table 20. PNAND Mode Parameters Parameter tADL Description Address to data loading time Min Max Unit Non LNA Mode Register Write 100 - ns Non LNA Mode EP Write 100 - ns LNA Mode 450 - ns tALH ALE hold time 5 - ns tALS ALE setup time 15 - ns tAR ALE to RE# delay 10 - ns tBERS Block erase time tCEA CE# access time - 35 ns tCH CE# hold time 5 - ns tCHZ CE# HIGH to O/P HI-Z - 40 ns tCLH CLE hold time 5 - ns tCLR CLE to RE# time 10 - ns tCLS CLE setup time 15 - ns tCS CE# setup time 20 - ns tDH Data hold time 5 - ns tDS Data setup time 15 - ns tOH Data output hold time 15 - ns tPROG Program time for LNA mode Program time for register write in non LNA mode tR Depends on MCU/S-Port/NAND ns 130 - ns Program time for EP write in non LNA mode 130 - ns Busy duration during Non LNA register read using page read 130 - ns Busy duration during non LNA EP read using page read 130 - ns Busy duration during LNA page read (SBD/SLD) tRC MCU/S-Port NAND dependent Depends on MCU/S-Port/NAND ns Read cycle time (VFBGA Package) 30 - Read cycle time (WLCSP package) 33 - RE# for register access time - 30 ns RE# for EP access time - 30 ns tREH RE# HIGH hold time 10 - ns tRHW RE# HIGH to WE LOW 40 - ns tREA ns tRHZ RE# HIGH to output High Z - 40 ns tRP RE# pulse width 15 - ns tRR Ready to RE LOW 20 - ns tRST Device reset time tWB WE# HIGH to busy - 100 ns tWC Write cycle time (VFBGA package) 30 - ns Write Cycle Time (WLCSP package) 33 - Document Number: 001-13805 Rev. *Q Depends on MCU/S-Port/NAND ns Page 51 of 87 CYWB022XX Family Table 20. PNAND Mode Parameters (continued) Parameter Description Min Max Unit tWH WE# HIGH hold time 10 - ns tWHR WE# HIGH to RE LOW in non LNA mode 30 - ns WE# HIGH to RE LOW in LNA mode 450 - ns WE# pulse width 15 - ns tWP Figure 33. PNAND Mode Command Latch Cycle CLE CE# tCLS tCLH tCS tCH tWP WE# tALH tALS ALE tDS tDH Command I/Ox Figure 34. PNAND Mode Address Latch Cycle CLE tCLS tCS tWC CE# tWC tWP WE# tWC tWP tWH tALS tWC tWP tWH tALS tWP tWH tWH tALS tALS tALS tALH ALE tALH tDS I/Ox Document Number: 001-13805 Rev. *Q tDH Col.Add1 tALH tDS tDH Col.Add2 tALH tALH tDS tDH tDS tDH Row.Add1 Row.Add2 tDS tDH Row.Add3 Page 52 of 87 CYWB022XX Family Figure 35. PNAND Mode Input Data Latch Cycle tCLH CLE tCH CE# tWC ALE tALS tWP WE# tWP tWP tWH tDS I/Ox tDH tDS DIN 0 tDH DIN 1 tDS tDH DIN final Figure 36. PNAND Mode Serial Access Cycle After Read tCEA tCHZ CE# tOH tREH tREA tREA tREA RE# tRHZ tRHZ tOH Dout I/Ox tRR Dout Dout tRC R/B# Document Number: 001-13805 Rev. *Q Page 53 of 87 CYWB022XX Family Figure 37. PNAND Mode Status Read Cycle tCLR CLE tCLH tCLS tCS CE# tWP WE# tCHZ tCEA tOH tWHR RE# tRHZ tDS I/Ox tDH tIR tREA 70h tOH Status Output Figure 38. PNAND LBD Read Operation tCLR CLE CE# tWC WE# tWB tAR ALE tR tRR tRP tRC tRHZ RE# Column Address I/Ox 00h Col Add1 Col Add2 R/B# Document Number: 001-13805 Rev. *Q Row Address Row Add1 Row Add2 Row Add3 Dout N 30h Dout N+1 Dout M Busy Page 54 of 87 CYWB022XX Family Table 21. Page-Read Command Sequence for Large-Block Devices Cycle type IO bus Comments CMD0 00h Page-read command - 1st cycle CA0 EP_Offset[7:0]/ REG_Addr[7:0] CA1 {4'b0000, EP_Offset[11:8]} REG_Sel field determines how the two column address cycles are interpreted EP_Offset[11:10] = REG_Sel = 2b11 Register EP_Offset[11:10] = REG_Sel = 2b0x, 2b10 EP buffer offset EP_Offset[11:0] = EP buffer offset RA0 Row address byte 0 First row-address cycle RA0[4:0] = default EPA - Endpoint address RA1 Row address byte 1 RA2 Row address byte 2 The number row-address bytes present in Page-read command depend on RA_COUNT configuration parameter setting. LNA row addresses are interpreted by firmware; RA3 Row address byte 3 CMD1 30h Page-read command - 2nd cycle Data[0-2111] Data Data is returned by Astoria delay tR beyond the second command. Figure 39. Large Block Device mode address cycles 7 REG_Sel[1:0] 0 EP_Offset[7:0]/ REG_Addr[7:0] Reserved EP_Offset[11:8] EPA[4:0] CA0 CA1 RA0 (default EPA position) RA1 RA2 RA3 Document Number: 001-13805 Rev. *Q Page 55 of 87 CYWB022XX Family Figure 40. PNAND SBD Read Operation CLE CE# tWC WE# tWB tAR ALE tR tRR tRP tRC tRHZ RE# Column Address 00h, 01h, Col Add1 or *50h I/Ox Row Address Row Add2 Row Add1 Row Add3 R/B# Dout N Dout N+1 Dout M Busy * For the Command 50h, A[3:0] in Col Add1 are valid address and A [7:4] are Don't care Document Number: 001-13805 Rev. *Q Page 56 of 87 CYWB022XX Family Table 22. Page-Read Command Sequence for Small-Block Devices Cycle type IO bus Comments CMD0 00h/01h/50h Sets base-address within page as 0, 256, or 512, for read operation. CA0 EP_Offset[7:0]/ REG_Addr[7:0] EP_Offset[7:0] = EP buffer offset for non-register accesses. REG_Addr[7:0] specifies register address when EPA[4:0] field = 5b10000. RA0 Row address byte 0 First row-address cycle RA0[4:0] = default EPA - Endpoint address EPA may be specified in any other row-address byte. RA1 Row address byte 1 RA2 Row address byte 2 The number row-address bytes present in Page-read command depend on RA_COUNT configuration parameter setting. LNA row addresses are interpreted by firmware; RA3 Row address byte 3 Data[0-527] Data Data is returned by Astoria delay tR beyond the second command. Figure 41. Small Block Device Mode Address Cycles 7 0 EP_Offset[7:0]/ REG_Addr[6:0] EPA[4:0] CA0 RA0 - default EPA position RA1 RA2 RA3 Document Number: 001-13805 Rev. *Q Page 57 of 87 CYWB022XX Family Figure 42. PNAND Mode LBD Random Data Operation (CASDO) CLE tCLR CE# WE# tRHW tWB tWHR tAR ALE tR tRP tRC tREA RE# tRR I/Ox 00h Col Add1 Col Add2 Row Add1 Column Address Row Row Add2 Add3 Row Address 30h Dout N+1 Dout N 05h Col Add1 Col Add2 E0h Dout M Dout M+1 Column Address Busy R/B# Figure 43. PNAND Mode Register Read Using CASDO in 8-Bit Mode CLE tCLR CE# tCH WE# tWHR ALE tREA RE# 05h I/Ox R/B# Col Col Add1 Add2 Column Address E0h DOUT1 *DOUT2 * This timing diagram shows the 8-bit register read. For 16-bit register read, DOUT2 is not available Document Number: 001-13805 Rev. *Q Page 58 of 87 CYWB022XX Family Figure 44. PNAND Mode LBD Read Operation (With CE# Don't Care) CLE CE# WE# tWB ALE tR RE# I/Ox 00h Col Add1 Col Add2 Column Address Row Add1 R ow Add2 Row Add3 Dout N Dout N+1 30h Dout M Row Address Busy R/B# CE# tCEA tREA RE# I/Ox Document Number: 001-13805 Rev. *Q Dout Page 59 of 87 CYWB022XX Family Figure 45. PNAND Mode SBD Read Operation (With CE# Don't Care) CLE CE# WE# tWB ALE tR RE# I/Ox 00h Col Add1 Column Address Row Add1 Row Add2 Row Add3 D out N Dout N+1 Dout M Row Address Busy R/B# CE# tCEA tREA RE# I/Ox Document Number: 001-13805 Rev. *Q Dout Page 60 of 87 CYWB022XX Family Figure 46. PNAND Mode LBD Page Program Operation CLE CE# tWC WE# tADL tWB tWHR tPROG ALE RE# Col Col Row Row Row Din Din 10 Add1 Add2 Add1 Add2 Add3 N h M 1 up to m Byte Program Serial Data Input Column Row Address Address Serial Input Command Command I/Ox 80h R/B# M = 2112byte in 8-bit interface M = 1056 in 16-bit interface 70h I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program Note: tADL is the time from WE rising edge of final address cycle to the WE rising edge of first data cycle Document Number: 001-13805 Rev. *Q Page 61 of 87 CYWB022XX Family Figure 47. PNAND Mode SBD Page Program Operation CLE CE# tWC WE# tADL tWB tPROG ALE RE# Column Address Col Row Row Row I/Ox 80h Add1 Add1 Add2 Add3 Row Address Serial Data Input Command R/B# Document Number: 001-13805 Rev. *Q Din N 1 up to m Byte Serial Input Din M 10h Program Command M = 528 byte in 8-bit interface M = 264 byte in 16-bit interface 70h I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program Page 62 of 87 CYWB022XX Family Figure 48. PNAND Mode LBD Page Program Operation with Random Data Input (CASDI) CLE CE# tWC WE# tADL tWB tPROG tWHR ALE RE# Col Col Row Row Row Add1 Add2 Add1 Add2 Add3 Serial Data Input Column Row Address Address Command I/Ox 80h Din N Din M 85h Col Col Add1 Add2 Column Address Serial Input R/B# Din J Din K Serial Input 10h 70h Program Command Read Status Command I/O0 Random Data Input Command *Random Programming (CASDI) to endpoint is only supported during logical NAND emulation (LNA mode) of LBD device. Partial page programming is not supported Figure 49. PNAND Mode Register Write Using CASDI in 8-Bit Mode CLE CE# tWC WE# tADL ALE RE# I/Ox Col Col Add1 Add2 DIN1 *DIN2 Serial Input Random Data Input Command 85h R/B# * This timing diagram shows the 8-bit register write. For 16-bit register write, DIN2 should not be available Document Number: 001-13805 Rev. *Q Page 63 of 87 CYWB022XX Family Figure 50. PNAND Mode LBD Page Program Operation (With CE# Don't Care) CLE CE# tWC WE# tADL tWB tPROG tWHR ALE RE# 1 up to M Byte Serial Input Col Col Row Row Row Add1 Add2 Add1 Add2 Add3 Serial Data Input Column Row Address Address Command I/Ox 80h Din N Din M 10h 70h Program Command M = 2112 byte in 8-bit interface M = 1056 byte in 16-bit interface Note: tADL is the time from WE rising edge of final address cycle to the WE rising edge of first data cycle Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program R/B# CE# I/O0 tCS tCH tWP WE# Document Number: 001-13805 Rev. *Q Page 64 of 87 CYWB022XX Family Figure 51. PNAND Mode SBD Page Program Operation (With CE# Don't Care) CLE CE# tWC WE# tADL tWB tPROG ALE RE# Column Address Col Row Row Row I/Ox 80h Add1 Add1 Add2 Add3 Row Address Serial Data Input Command R/B# Din N 1 up to m Byte Serial Input Din M 10h 70h Program Command M = 528 byte in 8-bit interface M = 264 byte in 16-bit interface CE# I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program tCS tCH tWP WE# Document Number: 001-13805 Rev. *Q Page 65 of 87 CYWB022XX Family Figure 52. PNAND Mode Block Erase Operation CLE CE# tWC WE# tWB ALE tBERS RE# I/Ox R/B# 60h Row Row Row Add1 Add2 Add3 Row Address Auto Block Erase Setup Command D0h 70h Busy Erase Command I/O 0 Read Status I/O0=0 Successful Erase Command I/O0=1 Error in Erase Figure 53. PNAND Mode Multi-Blocks (up to 4) Erase CLE CE# tWC WE# tWB tBERS ALE RE# I/Ox 60h 1 st Block Erase Row Row Row Add1 Add2 Add3 2nd and 3 rd Block Erase D0h 60h 4 th Block Erase Row Row Row Add1 Add2 Add3 Row Address R/B# Auto Block Erase Setup Command D0h 70h I/O 0 Row Address Erase Command Auto Block Erase Setup Command Erase Command Busy Read Status Command I/O 0= 0 Successful Erase I/O0=1 Error in Erase Note: The multi-block erase can support up to 4 blocks erase Document Number: 001-13805 Rev. *Q Page 66 of 87 CYWB022XX Family Figure 54. PNAND Mode Read ID Operation CLE CE# WE# tAR ALE RE# tREA I/Ox 90h Read ID Command 00h Byte 0 Byte 1 Address 1cycle Byte 2 Byte 3 Byte 4 Byte 5 Can up to six bytes Byte 0 - Byte 5 are the values of registers of PNAD_RD_ID0 to PNAND_RD_ID5. Figure 55. PNAND Mode Read ID2 Operation CLE CE# WE# tAR ALE RE# tREA I/Ox 91h Read ID Command Document Number: 001-13805 Rev. *Q 00h Ext_ID Address 1cycle Page 67 of 87 CYWB022XX Family Figure 56. PNAND Mode Reset Operation CLE CE# tWB WE# tRST R/B# I/Ox Document Number: 001-13805 Rev. *Q FFh Page 68 of 87 CYWB022XX Family SPI and PI2C Interface Table 23. SPI Mode Parameters Parameter Description Min Max Units 0 26 MHz fOP Operating frequency tCYC Cycle time 38.5 - ns tLead Enable lead time 19.23 - ns tLag Enable lag time 19.23 - ns tSCKH Clock high time 17.33 - ns tSCKL Clock low time 17.33 tSU Data setup time (inputs) - tH Data hold time (inputs) tV Data valid time, after enable edge tHO Data hold time, after enable edge ns 7 ns - 7 ns - 18 ns 0 - ns Figure 57. SPI Timing Diagram SS# tCYC tSCKL SCK tSCKH tLead MISO (MSB) BIT-7 OUT tSU MOSI tLag tH (MSB) BIT-7 IN (LSB) BIT-7 OUT BIT-6 OUT tV tHO BIT-6 IN Note tHO (LSB) BIT-0 IN Note: Not defined but normal MSB of character just received Document Number: 001-13805 Rev. *Q Page 69 of 87 CYWB022XX Family Table 24. PI2C Interface Standard Mode Parameters Parameter F Description Operating frequency Min Max Units 0 82 kHz tBUF Bus free time (between stop and start conditions) 4.7 - s tHD:STA Hold time after (Repeated) start condition. After this period the first clock is generated 4.0 - s tSU:STA Repeated start condition setup time 4.7 - s tSU:STO Stop condition setup time 4.0 - s tHD:DAT Data hold time 0 - ns tSU:DAT Data setup time 250 tTIMEOUT Detect clock low timeout - NA ns ms tLOW Clock low period 4.7 - s tHIGH Clock high period 4.0 - s tLOW:SEXT Cumulative clock low extend time (slave device) tr Rise time - NA 1000 ms ns tf Fall time - 300 ns Min Max Units 0 312 kHz Table 25. PI2C Interface Fast Mode Parameters Parameter F Description Operating frequency tBUF Bus free time (between stop and start condition) 1.3 - s tHD:STA Hold time after (Repeated) start condition. After this period the first clock is generated 0.6 - s tSU:STA Repeated start condition setup time 0.6 - s tSU:STO Stop condition setup time 0.6 - s tHD:DAT Data hold time 0 0.9 ns tSU:DAT Data setup time 100 tTIMEOUT Detect clock low timeout - NA ns ms tLOW Clock low period 1.3 - s tHIGH Clock high period 0.6 - s tLOW:SEXT Cumulative clock low extend time (slave device) tr Rise time - 300 ns tf Fall time - 300 ns Document Number: 001-13805 Rev. *Q NA ms Page 70 of 87 CYWB022XX Family Figure 58. PI2C Timing Diagram tf 70% SDA 50% 30% tr SCL tBUF tHIGH 70% tSU;DAT 50% tLOW tHD;STA 50% 30% tHD;DAT tSU;STA S Other P-Port Timings DRQ# Min Pulse Width (tDPW): The minimum duration that DRQ# is deasserted following a DRQ acknowledgement (clear of DMAVAL) is 110 ns in Async mode or five P-Port clock (CLK) cycles in Sync mode. Same Register Write-to-Read Holdoff (tWRHO): A read of a particular register must wait for a holdoff period following a write operation to that same register address to ensure that valid updated data is read. In Async mode, this holdoff time is 150 ns. Document Number: 001-13805 Rev. *Q tHD;STA Sr tSU;STO P S In Sync mode, this holdoff time is seven P-Port clock (CLK) cycles. Register Update-to-Read Holdoff (tURHO): Same status registers are updated as side effect from accesses to other registers. For example, clearing the DMAVAL field automatically clears the associated endpoint buffer bit within the DRQ status register. A holdoff time must elapse from the first register access before the update is reflected in a subsequent read operation. This holdoff time is identical to the tWRHO. Page 71 of 87 CYWB022XX Family S Port Interface AC Timing Parameters SD/MMC/MMC+/CE-ATA Timing Parameters For all conditions, SD/MMC data is driven and sampled on the rising edge of SD_CLK. Note that CE-ATA electrical and timing parameters are equivalent to MMC. Figure 59. SD/MMC/CE-ATA Timing Waveform - All Modes tSDCLKH tSDCLK SD_CLK tSDCLKL SD_CMD/ SD_D0-D3 tSDOS tSDCKLZ tSDOH tSDCKHZ Output SD_CMD/ SD_D0-D3 Input tSDIS tSDIH Table 26. Common Timing Parameters for SD/MMC/CE-ATA - During Identification Mode Parameter Description Min Max Units SDFREQ SD_CLK interface clock frequency 0 400 kHz tSDCLK Clock period 2.5 - s tSDCLKH Clock high time 1.0 - s tSDCLKL Clock low time 1.0 - s Min Max Units Table 27. Common Timing Parameters for SD/MMC/CE-ATA - During Data Transfer Mode Parameter Description SDFREQ SD_CLK interface clock frequency tSDCLK Clock period 5 48 MHz 20.8 200 ns tSDCLKOD tSCLKR Clock duty cycle 40 60 % Clock rise time - 3 ns tSCLKF Clock fall time - 3 ns Document Number: 001-13805 Rev. *Q Page 72 of 87 CYWB022XX Family Table 28. Timing Parameters for SD - All Modes Min Max Units tSDIS Parameter Input setup time Description 4 - ns tSDIH Input hold time 2.5 - ns tSDOS Output setup time 7 - ns tSDOH Output hold time 6 - ns tSDCKHZ Clock to data High Z - 18 ns tSDCKLZ Clock to data Low Z 3 - ns Table 29. Timing Parameters for MMC/CE-ATA - All Modes Min Max Units tSDIS Parameter Input setup time Description 4 - ns tSDIH Input hold time 4 - ns tSDOS Output setup time 6 - ns tSDOH Output hold time 6 - ns tSDCKHZ Clock to data High Z - 18 ns tSDCKLZ Clock to data Low Z 3 - ns Document Number: 001-13805 Rev. *Q Page 73 of 87 CYWB022XX Family Reset and Standby Timing Parameters The Astoria reset mechanism and the standby mode are described in this section. Minimum RESET# pulse width (tRPW): 5 ms when a crystal is used as clock or 1 ms when an external clock is used. Minimum WAKEUP pulse width (tWPW): 5 ms. Sleep Time (tSLP): The maximum time from deassertion of WAKEUP to when Astoria enters low power state (sleep mode) is 1 ms. Minimum HIGH on RESET# and WAKEUP (tRH, TWH): The WAKEUP and RESET# pins must be held HIGH for a minimum of 5 ms. Wakeup Time (tWU): The minimum time from assertion of WAKEUP pin (or initial power on with WAKEUP HIGH) to when any register operation is conducted is 1 ms if an external clock is present, or 5 ms if a crystal is used. The CY_AN_MEM_PWR_MAGT_STAT.WAKEUP field can only be polled after wakeup time following reset deassertion or WAKEUP assertion. Reset Recovery Time (tRR): A minimum 1 ms reset recovery time must be allowed before Astoria registers can be accessed for read or write. Figure 60. Reset and Standby Timing Diagram Core Power-Down VDD (core) VDDQ (I/O) XTALIN up & stable before WAKEUP asserted XTALIN tWPW tWH WAKEUP Standby Mode Mandatory Reset Pulse RESET# RESETOUT Hard Reset Mandatory Reset Pulse tRH Firmware Init Complete Firmware Init Complete Firmware Init Complete High-Z tRPW tSLP CY_AN_MEM_PMU_UPDATE.UVALID bit is set to `0' CY_AN_MEM_PMU_UPDATE.UVALID bit is set to `1' CY_AN_MEM_PMU_UPDATE.UVALID bit is set to `0' Table 30. Reset and Standby Timing Parameters Parameter Description Conditions tSLP Sleep time tWU Wakeup time from standby mode Clock on XTALIN Crystal on XTALIN-XTALOUT Min Max Units - 1 ms 1 - ms 5 - ms tWH WAKEUP high time 5 - ms tWPW WAKEUP pulse width 5 - ms tRH RESET# high time tRPW RESET# pulse width tRP RESET# recovery time Document Number: 001-13805 Rev. *Q 5 - ms Clock on XTALIN 1 - ms Crystal on XTALIN-XTALOUT 5 - ms 1 - ms Page 74 of 87 CYWB022XX Family AC Test Loads and Waveforms Figure 61. AC Test Loads and Waveforms (Except SD and MMC, SD and MMC are comply with the SD/MMC specification) Document Number: 001-13805 Rev. *Q Page 75 of 87 CYWB022XX Family Ordering Information Astoria provides many options with multiple ordering part numbers as shown in the following table: Ordering Code Optional Features Package Type FlexBootTM USB Switch Turbo MTP Clock Input Frequencies (MHz) Status CYWB0220ABSX2-FDXIT 81-ball WLCSP (Pb-free) 26 Sample CYWB0224ABM-BVXIES 100-ball VFBGA (Pb-free) 19.2, 24, 26, 48 Sample CYWB0224ABS-BZXI 121-ball FBGA (Pb-free) 19.2, 24, 26, 48 Production Release CYWB0224ABS-BVXI 100-ball VFBGA (Pb-free) 19.2, 24, 26, 48 Production Release CYWB0224ABS-BVXIT 100-ball VFBGA (Pb-free) 19.2, 24, 26, 48 Production Release CYWB0224ABS-BVXIES 100-ball VFBGA (Pb-free) 19.2, 24, 26, 48 Sample CYWB0226ABS-BVXI 100-ball VFBGA (Pb-free) 19.2, 24, 26, 48 Production Release CYWB0226ABS-BVXIT 100-ball VFBGA (Pb-free) 19.2, 24, 26, 48 Production Release Ordering Code Definitions CY WB XXXX ABS X X - XX X I Temperature range: I = Industrial = -40 C to +85 C X = Pb-free Package Type: XX = BV or BB or BZ or FD BV = 100-ball VFBGA BZ = 121-ball FBGA FD = 81-ball WLCSP Fixed value: X = 2 Fixed value ABS = GPIF support Base Part Number: XXXX = 0224 or 0226 or 0216 or 0220 Marketing Code: WB = West Bridge Astoria Company ID: CY = Cypress Document Number: 001-13805 Rev. *Q Page 76 of 87 CYWB022XX Family Package Diagrams Figure 62. 100-ball VFBGA (6 x 6 x 1.0 mm) BZ100 Package Outline, 51-85209 E1 2X 0.10 C E B (datum B) A1 CORNER A 10 9 8 7 6 5 4 3 2 1 7 A1 CORNER A B C D E F G H J K 6 SD D eD 0.10 C 2X 6 D1 (datum A) eE SE TOP VIEW BOTTOM VIEW DETAIL A 0.10 C A1 0.08 C A C 100XOb 5 SIDE VIEW O0.15 M C A B O0.05 M C DETAIL A NOTES: SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS MIN. NOM. MAX. A - - 1.00 A1 0.16 - - 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. D 6.00 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. E 6.00 BSC N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX D1 4.50 BSC E1 4.50 BSC MD 10 ME 10 N 100 b 0.30 0.25 eD 0.50 BSC eE 0.50 BSC SD 0.25 BSC SE 0.25 BSC SIZE MD X ME. 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. 0.35 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 9. JEDEC SPECIFICATION NO. REF. : MO-195C. 51-85209 *F 100-ball VFBGA Package Outline Number Revision Date Released 51-85209 *E 12/10/2014 Document Number: 001-13805 Rev. *Q Page 77 of 87 CYWB022XX Family Figure 63. 121-ball FBGA (10 x 10 x 1.20 mm) (0.30 Ball Diameter) Package Outline, 001-54471 2X 0.10 C E1 E B A 11 10 9 8 7 6 5 (datum B) 4 3 2 A1 CORNER 1 7 A1 CORNER A B C D 6 E SD D1 F D (datum A) G H J K eD 0.10 C 2X L 6 eE SE TOP VIEW BOTTOM VIEW 0.20 C DETAIL A A1 0.08 C C 121XOb 5 A O0.15 M C A B O0.08 M C SIDE VIEW DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS SYMBOL MIN. NOM. MAX. A - - 1.20 A1 0.15 - - D 10.00 BSC E 10.00 BSC D1 8.00 BSC E1 8.00 BSC MD 11 ME 11 N 121 b 0.30 0.25 eD 0.80 BSC eE 0.80 BSC SD SE 0.00 0.00 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. 0.35 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 001-54471 *F 121-ball FBGA Package Outline Number Revision Date Released 001-54471 *D 08/30/2012 Document Number: 001-13805 Rev. *Q Page 78 of 87 CYWB022XX Family Figure 64. Astoria WLCSP (3.91 x 3.91x 0.55 mm) FN81B Package Outline, 001-45618 001-45618 *D Astoria WLCSP Package Outline Number Revision Date Released 001-45618 *D 03/11/2015 Document Number: 001-13805 Rev. *Q Page 79 of 87 CYWB022XX Family Acronyms Acronym Document Conventions Description Units of Measure CRAM Cellular Random Access Memory DMA Direct Memory Access C degree Celsius ECC Error Correction Code A microampere GPIF General Purpose Interface s microsecond MMC Multimedia Card mA milliampere MTP Media Transfer Protocol Mbps mega bytes per second MHz megahertz ms millisecond ns nanosecond ohm pF picofarad V volt PLL Phase-Locked Loop SD Secure Digital SDIO Secure Digital Input / Output SLC Single-Level Cell SPI Serial Peripheral Interface USB Universal Serial Bus VFBGA Very Fine-Pitch Ball Grid Array WLCSP Wafer Level Chip Scale Package Document Number: 001-13805 Rev. *Q Symbol Unit of Measure Page 80 of 87 CYWB022XX Family Document History Page Document Title: CYWB022XX Family, West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Document Number: 001-13805 Rev. ECN No. Orig. of Change Submission Date ** 866960 VSO / PSZ 03/22/2007 New data sheet. *A 2208371 JYEE / VSO 03/14/2008 Updated Document Title to read as "CYWB0224ABS/CYWB0224ABM/ CYWB0226ABS/CYWB0226ABM, West BridgeTM: AstoriaTM USB and Mass Storage Peripheral Controller". Updated Features: Updated description. Updated Logic Block Diagram. Updated Functional Overview: Updated USB Interface (U-Port): Updated description. Added Figure 1. Updated Mass Storage Support (S-Port): Updated description. Added "N-Xpress NAND Controller (S-Port)". Updated Pin Assignments: Updated Figure 9. Updated Table 6. Updated DC Characteristics: Updated Table 12: Updated details in "Conditions", "Min", "Typ", "Max" columns corresponding to ISB1, ISB2, ISB3 parameters. Added Table 13. Updated AC Timing Parameters: Updated S Port Interface AC Timing Parameters: Updated PCRAM Non Multiplexing Asynchronous Mode: Updated Figure 15. Updated Figure 16. Updated Figure 17. Updated Figure 18. Updated Figure 19. Updated Table 15. Updated Address Data Multiplexing Asynchronous Mode: Updated Figure 20. Updated Figure 21. Updated Table 16. Updated Non Multiplexing Synchronous Mode Timing Parameters: Updated Figure 22. Updated Figure 23. Added Figure 24. Updated Figure 25. Updated Figure 26. Updated Figure 27. Updated Table 17. Updated Address Data Multiplexing Synchronous Mode: Updated Figure 28. Updated Figure 29. Updated Table 18. Updated Non Multiplexing Asynchronous SRAM Mode: Updated Figure 30. Updated Figure 31. Updated Figure 32. Added Table 19. Document Number: 001-13805 Rev. *Q Description of Change Page 81 of 87 CYWB022XX Family Document History Page (continued) Document Title: CYWB022XX Family, West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Document Number: 001-13805 Rev. ECN No. Orig. of Change Submission Date Description of Change *A (cont.) 2208371 JYEE / VSO 03/14/2008 Updated Pseudo NAND (PNAND) Mode: Updated Figure 33. Updated Figure 34. Updated Figure 35. Updated Figure 36. Updated Figure 37. Removed figure "PNAND Read Operation". Added Figure 38. Added Figure 40. Removed figure "PNAND Random Data Output in a Page". Removed figure "PNAND Mode Read Operation (Intercepted by CE#)". Removed figure "PNAND Mode Page Program Operation". Removed figure "PNAND Page Program Operation with Random Data Input". Added Figure 42. Added Figure 43. Added Figure 44. Added Figure 45. Added Figure 46. Added Figure 47. Added Figure 48. Added Figure 49. Added Figure 50. Added Figure 51. Updated Figure 52. Added Figure 53. Updated Figure 54. Added Figure 55. Added Figure 56. Updated Table 20. Updated SPI and PI2C Interface: Updated Figure 58. Updated Table 23. Updated Table 24. Updated Table 25. Updated SD/MMC/MMC+/CE-ATA Timing Parameters: Updated Figure 59. Updated Table 26. Updated Table 27. Removed table "Timing Parameters for SD/MMC/CE-ATA - All Modes". Added Table 28. Added Table 29. Updated Reset and Standby Timing Parameters: Updated Figure 60. Added Table 30. Updated Ordering Information: Updated part numbers. Updated to new template. *B 2503171 VSO / AESA 05/13/2008 Updated Features: Updated description (Added "3.91 x 3.91 mm 81-ball WLCSP" under "Small footprint". Document Number: 001-13805 Rev. *Q Page 82 of 87 CYWB022XX Family Document History Page (continued) Document Title: CYWB022XX Family, West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Document Number: 001-13805 Rev. ECN No. Orig. of Change Submission Date Description of Change *B (cont.) 2503171 VSO / AESA 05/13/2008 Updated Functional Overview: Updated Processor Interface (P-Port): Updated description. Updated Clocking: Updated description. Added Table 1. Added Table 2. Updated Pin Assignments: Updated Table 6: Added a column "Ball #" and added details under the column. Added Table 10. Updated Figure 9 (Removed the grid line). Added Figure 13. Updated AC Timing Parameters: Updated P Port Interface: Updated Pseudo NAND (PNAND) Mode: Updated Table 20: Splitted tRC parameter into two rows namely "Read Cycle Time (VFBGA Package)" and "Read Cycle Time (WLCSP Package)". Retained the original values for tRC parameter corresponding to "Read Cycle Time (VFBGA Package)" and added new values for tRC parameter corresponding to "Read Cycle Time (WLCSP Package)". Splitted tWC parameter into two rows namely "Write Cycle Time (VFBGA Package)" and "Write Cycle Time (WLCSP Package)". Retained the original values for tWC parameter corresponding to "Write Cycle Time (VFBGA Package)" and added new values for tWC parameter corresponding to "Write Cycle Time (WLCSP Package)". Updated SPI and PI2C Interface: Updated Figure 57. Updated Ordering Information: Updated part numbers. *C 2521024 VSO / AESA 06/25/2008 Changed status from "Preliminary" to "Confidential". Updated Functional Overview: Updated Power Modes: Updated Core Power Down Mode: Updated description. Updated DC Characteristics: Updated Table 12: Updated Note 3. Document Number: 001-13805 Rev. *Q Page 83 of 87 CYWB022XX Family Document History Page (continued) Document Title: CYWB022XX Family, West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Document Number: 001-13805 Rev. ECN No. Orig. of Change Submission Date *C (cont.) 2521024 VSO / AESA 06/25/2008 Updated AC Timing Parameters: Updated P Port Interface: Updated Non Multiplexing Synchronous Mode Timing Parameters: Updated Table 17: Added tWH parameter and its details. Updated Figure 22. Updated Figure 27. Updated Address Data Multiplexing Synchronous Mode: Updated Table 18: Added tAVH parameter and its details. Updated Figure 28. Updated Figure 29. Updated Pseudo NAND (PNAND) Mode: Updated Table 20: Replaced "140 ns" with "130 ns" in "Min" column corresponding to "tPROG" parameter. Replaced "140 ns" with "130 ns" in "Min" column corresponding to "tR" parameter. Updated SPI and PI2C Interface: Updated Table 23: Removed "tA" parameter and its details. Updated Figure 58. *D 2663942 VSO / AESA 02/24/2009 Updated Features: Updated description. Updated Functional Overview: Updated Clocking: Updated description. Added Table 3. Added Packages and Interface Options. Updated Pin Assignments: Updated Table 10 (Replaced "WLCSP" with "SP WLCSP" in caption). Added Table 11. Updated Figure 13 (Replaced "WLCSP" with "SP WLCSP" in caption; changed the color of AVDDQ). Added Figure 14. Updated DC Characteristics: Updated Table 12: Updated Note 2. Updated Ordering Information: Updated part numbers. *E 2905597 VSO 04/05/2010 Updated Ordering Information: Updated part numbers. Updated Package Diagrams: spec 51-85209 - Changed revision from *B to *C. spec 001-45618 - Changed revision from ** to *B. *F 2920278 VSO / AESA 04/21/2010 Updated DC Characteristics: Updated Table 12: Splitted ISB1 parameter into two rows namely "ISB1 (For 100-pin VFBGA and 81-pin SP WLCSPPackages)" and "ISB1 (For 81-pin Lite SP WLCSP)". Retained the original values for "ISB1 (For 100-pin VFBGA and 81-pin SP WLCSPPackages)" and added TBD for "ISB1 (For 81-pin Lite SP WLCSP)". Updated to new template. *G 2954592 ESH 06/17/2010 Updated Ordering Information: Updated part numbers. Document Number: 001-13805 Rev. *Q Description of Change Page 84 of 87 CYWB022XX Family Document History Page (continued) Document Title: CYWB022XX Family, West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Document Number: 001-13805 Rev. ECN No. Orig. of Change Submission Date *H 3057588 ODC 10/13/2010 Removed "MLC NAND Flash" related information in all instances across the document. Updated Ordering Information: Updated part numbers. Added Ordering Code Definitions. *I 3164752 ANOP 02/07/2011 Updated Pin Assignments: Updated Table 11: Added `#' to DRQ under "SRAM Interface", "ADM" and "PNAND" columns in "D4" row. Added "#" to "DACK" under "SRAM Interface", "ADM" and "PNAND" columns in "D3" row. *J 3191625 ANOP 03/09/2011 Updated AC Timing Parameters: Updated P Port Interface: Updated Pseudo NAND (PNAND) Mode: Added Figure 39. Added Figure 41. Added Table 21. Added Table 22. Updated Package Diagrams: spec 51-85209 - Changed revision from *C to *D. Completing Sunset Review. *K 3465771 SIRK 12/22/2011 Changed status from Confidential to Final. Updated Functional Overview: Updated USB Interface (U-Port): Updated Mass Storage Support (S-Port): Updated description. Removed "N-Xpress NAND Controller (S-Port)". Removed "NAND Flash and SD/SDIO/MMC/CE-ATA Interface Mode". Added GPIF and SD/SDIO/MMC/CE-ATA Interface Mode. Removed "NAND Flash Interface Mode". Removed "NAND Flash and GPIO Interface". Added GPIF and GPIO Interface. Removed "NAND Port (S-Port)". Updated Pin Assignments: Updated Table 6. Added Table 7. Added Table 8. Added Table 9. Updated Table 10. Updated Table 11. Updated Figure 9. Added Figure 10. Added Figure 11. Added Figure 12. Updated Figure 13. Updated Figure 14. Updated Ordering Information: Updated part numbers. Updated Package Diagrams: Added spec 51-85107 *D. Added spec 001-54471 *C Document Number: 001-13805 Rev. *Q Description of Change Page 85 of 87 CYWB022XX Family Document History Page (continued) Document Title: CYWB022XX Family, West Bridge(R): AstoriaTM USB and Mass Storage Peripheral Controller Document Number: 001-13805 Rev. ECN No. Orig. of Change Submission Date *L 3539318 SIRK 03/01/2012 Updated Package Diagrams: spec 001-45618 - Changed revision from *B to *C. Posted to external web. Completing Sunset Review. *M 3665980 AASI 07/06/2012 Updated Features: Removed 100-ball BGA package related information. Updated Ordering Information: Updated part numbers. Updated Package Diagrams: Removed spec 51-85107 *D. *N 3847849 DBIR 12/19/2012 Updated Ordering Information: Updated part numbers. Updated Package Diagrams: spec 001-54471 - Changed revision from *C to *D. *O 4584086 GAYA 12/01/2014 Updated Features: Replaced "Supports I2C Boot and Processor Boot" with "Supports USB Boot, I2C Boot and Processor Boot". Updated Ordering Information: Updated part numbers. Updated to new template. *P 4776800 DBIR 06/01/2015 Updated Package Diagrams: spec 51-85209 - Changed revision from *D to *E. spec 001-45618 - Changed revision from *C to *D. Updated to new template. Completing Sunset Review. *Q 6114093 DBIR 03/29/2018 Updated Package Diagrams: spec 51-85209 - Changed revision from *E to *F. spec 001-54471 - Changed revision from *D to *F. Updated to new template. Completing Sunset Review. Document Number: 001-13805 Rev. *Q Description of Change Page 86 of 87 CYWB022XX Family Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-13805 Rev. *Q Revised March 29, 2018 West Bridge, Astoria, Antioch, and SLIM are trademarks of Cypress Semiconductor Corporation. Page 87 of 87