1. General description
The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ out pu ts. Data at the nD-input, th at mee ts the set-u p and ho ld time
requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at
the nQ output. Schmitt-trigge r actio n in the clo ck input, makes the circuit highly tolerant to
slower clock rise and fall times. Inputs include clamp diodes tha t enable the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Input levels:
For 74HC74: CMOS level
For 74HCT74: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Spe cified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 20 0 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 5 — 3 December 2015 Product data sheet
Tabl e 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC74D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74HCT74D
74HC74DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT74DB
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 2 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
4. Functional diagram
74HC74PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT74PW
74HC74BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
74HCT74BQ
Tabl e 1. Ordering information …continued
Type number Package
Temperature range Name Description Version
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram
PQD
5'
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6'
44
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4
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Fig 4. Logic diagram for one flip-flop
PQD
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 3 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVQFN14
+&
+&7
5' 9
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Table 2. Pin description
Symbol Pin Description
1RD 1 asynchronous reset-direct input (active LOW)
1D 2 data input
1CP 3 clock input (LOW-to-HIGH, edge-triggered)
1SD 4 asynchronous set-direct input (active LOW)
1Q 5 output
1Q 6 complement output
GND 7 ground (0 V)
2Q 8 complement output
2Q 9 output
2SD 10 asynchronous set-direct input (active LOW)
2CP 11 clock input (LOW-to-HIGH, edge-triggered)
2D 12 data input
2RD 13 asynchronous reset-direct input (active LOW)
VCC 14 supply voltage
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 4 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
7. Limiting values
[1] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
Table 3. Function table[1]
Input Output
nSDnRDnCP nD nQ nQ
LHXXHL
HLXXLH
LLXXHH
Table 4. Function table[1]
Input Output
nSDnRDnCP nD nQn+1 nQn+1
HHLLH
HHHHL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO14, (T)SSOP14 and DHVQFN14
packages [1] - 500 mW
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 5 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
9. Static characteristics
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC74 74HCT74 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V i nput transition rise and fall rate V CC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC74
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=4.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=4.0mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V --40 - 80A
CIinput
capacitance -3.5- - -pF
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 6 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
74HCT74
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=4 mA 3.84 4.32 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO= 4.0 mA - 0.15 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V --40 - 80A
ICC additional
supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; nD, nRD
inputs - 70 315 - 343 A
per input pin; nSD, nCP
input - 80 360 - 392 A
CIinput
capacitance -3.5- - -pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 7 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC74
tpd propagation
delay nCP to nQ, nQ; see
Figure 7 [2]
VCC = 2.0 V - 47 220 - 265 ns
VCC = 4.5 V - 17 44 - 53 ns
VCC =5V; C
L=15pF - 14 - - - ns
VCC = 6.0 V - 14 37 - 45 ns
nSD to nQ, nQ; see
Figure 8 [2]
VCC = 2.0 V - 50 250 - 300 ns
VCC = 4.5 V - 18 50 - 60 ns
VCC =5V; C
L=15pF - 15 - - - ns
VCC = 6.0 V - 14 43 - 51 ns
nRD to nQ, nQ; see
Figure 8 [2]
VCC = 2.0 V - 52 250 - 300 ns
VCC = 4.5 V - 19 50 - 60 ns
VCC =5V; C
L=15pF - 16 - - - ns
VCC = 6.0 V - 15 43 - 51 ns
tttransition
time nQ, nQ; see Figure 7 [3]
VCC = 2.0 V - 19 95 - 110 ns
VCC = 4.5 V - 7 19 - 22 ns
VCC = 6.0 V - 6 16 - 19 ns
tWpulse width nCP HIGH or LOW;
see Figure 7
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
nSD, nRD LOW;
see Figure 8
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
trec recovery
time nSD, nRD; see Figure 8
VCC = 2.0 V 40 3 - 45 - ns
VCC = 4.5 V 8 1 - 9 - ns
VCC = 6.0 V 7 1 - 8 - ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 8 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
tsu set-up time nD to nCP; see Figure 7
VCC = 2.0 V 75 6 - 90 - ns
VCC = 4.5 V 15 2 - 18 - ns
VCC = 6.0 V 13 2 - 15 - ns
thhold time nD to nCP; see Figure 7
VCC = 2.0 V 3 6- 3 -ns
VCC = 4.5 V 3 2- 3 -ns
VCC = 6.0 V 3 2- 3 -ns
fmax maximum
frequency nCP; see Figure 7
VCC = 2.0 V 4.8 23 - 4.0 - MHz
VCC = 4.5 V 24 69 - 20 - MHz
VCC =5V; C
L=15pF - 76 - - - MHz
VCC = 6.0 V 28 82 - 24 - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -24 - - -pF
74HCT74
tpd propagation
delay nCP to nQ, nQ; see
Figure 7 [2]
VCC = 4.5 V - 18 44 - 53 ns
VCC =5V; C
L=15pF - 15 - - - ns
nSD to nQ, nQ; see
Figure 8 [2]
VCC = 4.5 V - 23 50 - 60 ns
VCC =5V; C
L=15pF - 18 - - - ns
nRD to nQ, nQ; see
Figure 8 [2]
VCC = 4.5 V - 24 50 - 60 ns
VCC =5V; C
L=15pF - 18 - - - ns
tttransition
time nQ, nQ; see Figure 7 [3]
VCC = 4.5 V - 7 19 - 22 ns
tWpulse width nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V 23 9 - 27 - ns
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V 20 9 - 24 - ns
trec recovery
time nSD, nRD; see Figure 8
VCC = 4.5 V 8 1 - 9 - ns
tsu set-up time nD to nCP; see Figure 7
VCC = 4.5 V 15 5 - 18 - ns
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 9 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time nD to nCP; see Figure 7
VCC = 4.5 V 3 3- 3 -ns
fmax maximum
frequency nCP; see Figure 7
VCC = 4.5 V 22 54 - 18 - MHz
VCC =5V; C
L=15pF - 59 - - - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC - 1.5 V [4] -29 - - -pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 10 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Input to output propagation delay, output transition time, cloc k in pu t puls e width and maximum
frequency
WK
WVX WVX
WK
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 11 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Set an d reset propogation delays, pulse widths and recovery time
PQD
WUHF
W3+/
W3+/
W:
W3/+
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Table 9. Measurement points
Type Input Output
VMVM
74HC74 0.5VCC 0.5VCC
74HCT74 1.3 V 1.3 V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 12 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 9. Test circuit for measuring switching times
DDK
W:
W:
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WU
WI
90
9,
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90
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57
9,92
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Table 10. Test data
Type Input Load Test
VItr, tfCLRL
74HC74 VCC 6ns 15pF, 50 pF 1ktPLH, tPHL
74HCT74 3V 6ns 15pF, 50 pF 1ktPLH, tPHL
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 13 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
12. Package outline
Fig 10. Package outline SOT108-1 (SO14)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 14 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 11. Package outline SOT337-1 (SSOP14)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 15 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 12. Package outline SOT402-1 (TSSOP14)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 5 — 3 December 2015 16 of 20
Nexperia 74HC74; 74HCT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 13. Package outline SOT762-1 (DHVQFN14)
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