PDU16F
Doc #97004 DATA DELAY DEVICES, INC. 1
1/13/97 3 Mt. Prospect Ave. Clifton, NJ 07013
6-BIT PROGRAMMABLE
DELAY LINE
(SERIES PDU16F)
FEATURES PACKAGES
• Digitally programmable in 64 delay steps
• Monotonic delay-versus-address variation
• Two separate outputs: inverting & non-inverting
• Precise and stable delays
• Input & outputs fully TTL interfaced & buffered
• 10 T2L fan-out capability
• Fits standard 24-pin DIP socket
• Auto-insertable
FUNCTIONAL DESCRIPTION
The PDU16F-series device is a 6-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)
depends on the address code (A5-A0) according to the following formula:
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The
enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state
and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced
into LOW and HIGH states, respectively. The address is not latched and must remain asserted during
normal operation.
SERIES SPECIFICATIONS
• Programmed delay tolerance: 5% or 1ns,
whichever is greater
• Inherent delay (TD0): 9ns typical (OUT)
8ns typical (OUT/)
• Setup time and propagation delay:
Address to input setup (TAIS): 5ns
Disable to output delay (TDISO): 6ns typ. (OUT)
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VCC: 5VDC ± 5%
• Supply current: ICCH = 74ma
ICCL = 30ma
• Minimum pulse width: 10% of total delay 1997 Data Delay Devices
data
delay
devices, inc.
3
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
OUT/
OUT
EN/
GND
N/C
IN
N/C
GND
N/C
N/C
EN/
GND
VCC
A0
A1
A2
VCC
N/C
N/C
N/C
VCC
A3
A4
A5
PDU16F-xx
DIP
PDU16F-xxA4
Gull-Wing
PDU16F-xxB4
J-Lead
PDU16F-xxM
Military DIP
PDU16F-xxMC4
Military Gull-Wing
PIN DESCRIPTIONS
IN Delay Line Input
OUT Non-inverted Output
OUT/ Inverted Output
A0-A5 Address Bits
EN/ Output Enable
VCC +5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number Incremental Delay
Per Step (ns) Total Delay
Change (ns)
PDU16F-.5 .5 ± .3 31.5 ± 1.6
PDU16F-1 1 ± .5 63 ± 3.2
PDU16F-2 2 ± .5 126 ± 6.3
PDU16F-3 3 ± 1.0 189 ± 9.5
PDU16F-4 4 ± 1.0 252 ± 12.6
PDU16F-5 5 ± 1.0 315 ± 15.8
PDU16F-6 6 ± 1.0 378 ± 18.9
PDU16F-8 8 ± 1.0 504 ± 25.2
PDU16F-10 10 ± 1.5 630 ± 31.5
NOTE: Any dash number between .5 and 10 not
shown is also available.
PDU16F
Doc #97004 DATA DELAY DEVICES, INC. 2
1/13/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
ADDRESS UPDATE
The PDU16F is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
TOAX, is required before the address lines can
change. This time is given by the following
relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
A similar situation occurs when using the EN/
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the EN/ signal high and
the IN signal low for a time given by:
TDISH = Ai * TINC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
possibility of spurious signals persists until the
required TDISH has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
TDISO
TOAX
TAENS
TENIS PWIN
TDAPWOUT
TDISH
A5-A0
EN/
IN
OUT
OUT/
Figure 1: Timing Diagram
A i-1 Ai
TSKEW
TAIS
PDU16F
Doc #97004 DATA DELAY DEVICES, INC. 3
1/13/97 3 Mt. Prospect Ave. Clifton, NJ 07013
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP UNITS
Total Programmable Delay TDT63 TINC
Inherent Delay TD09.0 ns
Output Skew TSKEW 1.5 ns
Disable to Output Low Delay TDISO 6.0 ns
Address to Enable Setup Time TAENS 2.0 ns
Address to Input Setup Time TAIS 5.0 ns
Enable to Input Setup Time TENIS 2.5 ns
Output to Address Change TOAX See Text
Disable Hold Time TDISH See Text
Absolute PERIN 20 % of TDT
Input Period Suggested PERIN 40 % of TDT
Recommended PERIN 200 % of TDT
Absolute PWIN 10 % of TDT
Input Pulse Width Suggested PWIN 20 % of TDT
Recommended PWIN 100 % of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage VCC -0.3 7.0 V
Input Pin Voltage VIN -0.3 VDD+0.3 V
Storage Temperature TSTRG -55 150 C
Lead Temperature TLEAD 300 C10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
High Level Output Voltage VOH 2.5 3.4 V VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage VOL 0.35 0.5 V VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
High Level Output Current IOH -1.0 mA
Low Level Output Current IOL 20.0 mA
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
Input Clamp Voltage VIK -1.2 V VCC = MIN, II = IIK
Input Current at Maximum
Input Voltage IIHH 0.1 mA VCC = MAX, VI = 7.0V
High Level Input Current IIH 20 µAVCC = MAX, VI = 2.7V
Low Level Input Current IIL-0.6 mA VCC = MAX, VI = 0.5V
Short-circuit Output Current IOS -60 -150 mA VCC = MAX
Output High Fan-out 25 Unit
Output Low Fan-out 12.5 Load
PDU16F
Doc #97004 DATA DELAY DEVICES, INC. 4
1/13/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PACKAGE DIMENSIONS
1.270
12345678
16 15 14 13
1211109
.290
MAX.
.015 TYP.
.070 MAX.
.018 TYP. 1.100
.280
MAX.
.350
MAX.
.010±.002
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
20 19 18 1724 23 22 21
Commercial DIP (PDU16F-xx)
1.290 MAX.
.430
TYP.
.020 TYP.
.040 TYP.
.100.110
1.100
.300
MAX.
.270
TYP.
.010 TYP.
.050
TYP.
123456789101112
131415161718192021222324
Commercial Gull-Wing (PDU16F-xxA4)
1.290 MAX.
12345678
.320
TYP.
.020 TYP.
.040 TYP.
.100
.110
1.100 .350
MAX.
.270
TYP.
.050 TYP.
.110
TYP.
9 10 11 12
17181920 1314151621222324
Commercial J-Lead (PDU16F-xxB4)
.130
MIN.
1.300 TYP.
1 4 6
.300
MAX.
.018 TYP.
.410
MAX.
.300
TYP.
.012 TYP.
1.100 TYP. .100 TYP.
1211
15 1324 22
2 3 8
16 1423 21 20
.100
Military DIP (PDU16F-xxM)
1.280±.020
.882
±.005
.020 TYP. .040 TYP.
.100.090 1.100 .280
MAX.
.590
MAX.
.050
±.010
.710
±.005 .007
±.005
123456789101112
131415161718192021222324
Military Gull-Wing (PDU16F-xxMC4)
PDU16F
Doc #97004 DATA DELAY DEVICES, INC. 5
1/13/97 3 Mt. Prospect Ave. Clifton, NJ 07013
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oCLoad: 1 FAST-TTL Gate
Supply Voltage (Vcc): 5.0V ± 0.1V Cload:5pf ± 10%
Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise/Fall Time: 3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width: PWIN = 1.5 x Total Delay
Period: PERIN = 4.5 x Total Delay
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUT
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT) TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
Timing Diagram For Testing
TDAR TDAF
PERIN
PWIN
TRISE TFALL
0.6V
0.6V
1.5V
1.5V
2.4V
2.4V
1.5V
1.5V
VIH VIL
VOH VOL
INPUT
SIGNAL
OUTPUT
SIGNAL