Parameter CL10K30A CL10K50V CL10K100A
Typical Gates
(Logic and RAM)
30,000 50,000 100,000
Maximum System Gates 69,000 116,000 158,000
Logic Elements 1,728 2,880 4,992
Logic Blocks 216 360 624
Embedded Array Blocks 610 12
Total RAM Bits 12,288 20,480 24,576
Max User I/O Pins 189 274 406
Speed Grades
-1, -2, -3 -1, -2, -3, -4 -1, -2, -3
10KA tbl 01A
Packages
144-pin TQFP
208-pin PQFP
240-pin PQFP
256-pin FBGA
240-pin PQFP
240-pin RQFP
356-pin SBGA
240-pin PQFP
240-pin RQFP
356-pin SBGA
484-pin FBGA
600-pin SBGA
June 2001 Page 1
uFully Compatible to the Altera®FLEX®10KA Family
uPrototype Your System With Altera FPGAs
uSeamlessly Migrate Production To Clear Logic
uNo ASIC Engineering, No NRE, And No Test Vector
Development
uVery Fast, Dense Signal Routing Using Vertical Link
Interconnect
u"Gate Array" Option Eliminates Configuration EPROMs
uFabricated Using 0.35 Micron CMOS Process
uVery Low Power Consumption (Active And Standby)
uHigh Density
- 100,000 Usable Gates
- 4,992 Logic Elements
- 24,576 RAM Bits
- 406 Maximum User I/O Pins
CL10KA Product Family Overview
LIBERATOR
CL10K100A
Key Features
The LIBERATORCL10KA family offers you all of the time-to-
market benefits of designing with programmable logic. Simply
use Altera FLEX 10KA FPGAs to prototype and verify the
design. Then, take five minutes to submit the bitstream using
Clear Logic's web site! Within eight weeks, your system can be
in volume production using compatible Clear Logic devices.
LIBERATOR technology frees you to completely design,
prototype, and verify your custom logic using Altera FLEX 10KA
products. Clear Logic's innovative technology eliminates NRE
costs, test vector development, ordering minimums, and long lead
times. No re-simulation or re-layout is required, because Clear
Logic offers an architecture that is exactly compatible to the
functionality of the FPGA prototype. Clear Logic's NoFault®test
technology ensures complete test coverage through the use of
special scan test registers.
The LIBERATOR family is based upon an array of logic
elements. Each logic element contains a configurable look-up
table for combinatorial functions and a register for sequential
operations. Eight logic elements in a group form a block. Logic
functions and signal routing are defined by Clear Logic's
proprietary vertical metal links.
Laser-based configuration allows quick-turn prototyping and
eliminates NRE costs for photomasks. Inherent CL10KA family
performance benefits include extremely consistent propagation
delays, reduced power consumption, and improved immunity to
noise and upset events.
The "Gate Array" configuration mode eliminates the need for
external EPROMs or software configuration. The LIBERATOR
device is already factory-configured when it is shipped. When
using the device in the "Gate Array" mode, it powers up fully
configured. In this mode, if the customer selects INIT_DONE
option, this pin will always be high.
Description
LIBERATOR CL10K100A
Page 2
Configuration
For further information on designing with the LIBERATOR
family, please refer to these documents:
uAN-01: Requesting a First Article. This document provides
instructions on how to request first articles by submitting a
bitstream file to Clear Logic's web site.
uAN-02: Clear Logic Packaging Guide. This document provides
specifications and drawings for packages used by the CL10K
family and other Clear Logic devices.
uAN-13: LIBERATOR -- A New Way To Design. This document
describes the most efficient path for custom logic designs up
to 200K gates using FPGA design techniques and going to
production with Clear Logic.
uAN-14: CL10K Technology White Paper. This document
outlines the technologies employed by the LIBERATOR
family.
uAN-15: LIBERATOR System Configuration. This document
contains a detailed discussion of all aspects of configuring
CL10K-based systems.
uAN-16: Introduction to the Clear Logic Verilog Model
Generator. Clear Logic now has Verilog models of your FPGA
converted design. Learn what it is and how it can help you.
uAN-17: Clear Logic LIBERATOR Design Models. This
document outlines the capabilities and freedom available in
the Clear Logic Verilog and VHDL design models.
uAN-18: Debugging Designs Using Clear Logic Models. This
document shows the enhanced troubleshooting capabilities
that the Clear Logic LIBERATOR Verilog/VHDL design
models bring to the system debugging process.
Additional
Information
LIBERATOR CL10K100A
Page 3
LIBERATOR CL10K100A
Page 4
IOE IOE IOE IOE IOE IOE
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE IOE IOE IOE
Row
Interconnect
Column
Interconnect
Logic
Array
I/O Element
(IOE)
Embedded Array Block (EAB)
Logic Array
Logic Building
Block (LBB)
Logic Element (LE)
Local Interconnect
EAB
EAB
Logical Memory Array (LMA)
10KA drw 01
Block Diagram
LIBERATOR CL10K100A
Page 5
Pin Configuration
Pin Name
240-Pin
PQFP/RQFP
356-Pin SBGA 484-Pin FBGA 600-Pin SBGA
MSEL0
124 D4 U4 F5
MSEL1
123 D3 V4 C1
nSTATUS
60 D24 W19 D32
nCONFIG
121 D2 T7 D4
DCLK
179 AC5 E5 AP1
CONF_DONE
2 AC24 F18 AM32
INIT_DONE
26 T24 K19 AE32
nCE
178 AC2 E4 AN2
nCEO
3 AC22 E19 AP35
nWS
238 AE24 E17 AR29
nRS
236 AE23 F17 AM28
nCS
240 AD24 D19 AL29
CS
239 AD23 D18 AN29
RDYnBSY
23 U22 K17 AG35
CLKUSR
11 AA24 G18 AM34
DATA7
190 AF4 E8 AM13
DATA6
188 AD8 G7 AR12
DATA5
186 AE5 D7 AN12
DATA4
185 AD6 E7 AP11
DATA3
183 AF2 F6 AM11
DATA2
182 AD5 D5 AR10
DATA1
181 AD4 E6 AN10
DATA0
180 AD3 D4 AM4
TDI
177 AC3 F5 AN1
TDO
4 AC23 F19 AN34
TCK
1 AD25 E18 AL31
TMS
58 D22 U18 C35
TRST
59 D23 V19 C34
Dedicated Inputs
90, 92, 210, 212 A13, B14, AF14, AE13 E12, H11, R12, V11 C18, D18, AM18, AN18
Dedicated Clock Pins
91, 211 A14, AF13 D12, P11 AL18, E18
LOCK
----
10K100A tbl 01A
LIBERATOR CL10K100A
Page 6
Pin Configuration
Pin Name
240-Pin
PQFP/RQFP
356-Pin SBGA 484-Pin FBGA 600-Pin SBGA
GCLK1
----
DEV_CLRn
209 AD13 G11 AR17
DEV_OE
213 AE14 F12 AR19
VCCINT
5, 16, 27, 37, 47, 57,
77, 89, 96, 112, 122,
130, 140, 150, 160,
170, 189, 205, 224
A1, A26, C14, C26, D5,
F1, H22, J1, M26, N1,
T26, U5, AA1, AD26,
AF1, AF26
C11, C15, H14, J8,
J10, J12, J15, L9, L10,
L13, M10, M13, M14,
N12, P8, P10, P12,
P15, R14, V5, W21, Y8,
AA12
A11, A19, B1, B18,
D24, E2, F31, F35, H1,
K32, M2, N34, P5, T35,
U3, V32, Y2, AA33,
AB5, AD35, AE4, AF32,
AG5, AK31, AK35, AL3,
AP24, AR11, AR18
VCCIO
-
A7, A23, B3, C15, D25,
F4, H24, K5, M23, P2,
T25, V2, W22, AB1,
AC25, AD18M AF3,
AF7, AF16
A6, A13, B5, E1, G1,
G15, H9, H20, J11,
J13, K9, K11, K14,
K20, L14, M9, N3, N9,
N11, N14, N20, P13,
R1, R9, T3, T15, T22,
V22, AB13
A20, A27, C2, C3, C4,
C8, C15, C23, C32,
C33, D5, D31, E5, E12,
E31, AL5, AL12, AM5,
AM19, AM26, AM31,
AN3, AN4, AN8, AN15,
AN32, AN33, AP34,
AR23
VCC_CKLK
- - -
GNDINT
10, 22, 32, 42, 52, 69,
85, 93, 104, 125, 135,
145, 155, 165, 176,
197, 216, 232
A2, A10, A20, B1, B13,
B22, B25, B26, C2, C9,
C13, C25, H23, J26,
K1, M1, N26, R1, R26,
T1, U26, W1, AD2,
AD14, AD20, AE1, AE2,
AE7, AE25, AE26,
AF11, AF19, AF25
A1, A8, A22, B1, B2,
B17, B21, B22, C2,
C21, E21, G3, G21,
H2, H8, H15, J9, J14,
J20, K3, K10, K12,
K13, L11, L12, M11,
M12, M20, N10, N13,
P9, P14, R8, R15, R22,
T1, V3, W11, W20, Y1,
Y2, Y3, Y21, Y22, AA1,
AA6, AA22, AB11, AB16
A1, A2, A3, A4, A5, A18,
A31, A32, A33, A34,
A35, B2, B3, B4, B5,
B6, B31, B32, B33,
B34, B35, C5, C6, C30,
C31, D6, D30, E6,
AN35
GNDIO
---
E30, AL6, AL30, AM6,
AM30, AN5, AN6,
AN30, AN31, AP2, AP3,
AP4, AP5, AP6, AP30,
AP31, AP32, AP33,
AR1, AR2, AR3, AR4,
AR5, AR30, AR31,
AR32, AR33, AR34,
AR35
VGND_CKLK
----
10K100A tbl 01B
LIBERATOR CL10K100A
Page 7
Pin Configuration
Pin Name
240-Pin
PQFP/RQFP
356-Pin SBGA 484-Pin FBGA 600-Pin SBGA
No connect
---
D1, D2, D3, D33, D34,
D35, E1, E3, E4, E32,
E33, E34, E35, F1, F2,
F3, F4, F32, F33, F34,
G1, G2, G3, G4, G5,
G31, G32, G33, G34,
G35, H5, H31, AB31,
AB32, AB33, AB34, D1,
D2, D3, D33, D34,
D35, E1, E3, E4, E32,
E33, E34, E35, F1, F2,
F3, F4, F32, F33, F34,
G1, G2, G3, G4, G5,
G31, G32, G33, G34,
G35, H5, H31, AB31,
AB32, AB33, AB34,
AC31, AC32, AC33,
AC34, AC35, AD31,
AD32, AD33, AD34,
AE33, AE34, AE35,
AH5, AJ2, AJ3, AJ4,
AJ5, AK1, AK2, AK3,
AK4, AK5, AL1, AL2,
AL4, AM1, AM2,
AM3AC35, AH5, AJ2,
AJ3, AJ4, AJ5, AK1,
AK2, AK3, AK4, AK5,
AL1, AL2, AL4, AM1,
AM2, AM3
Total user I/O Pins 189 274 369 406
10K100A tbl 01C
LIBERATOR CL10K100A
Page 8
Absolute Maximum Ratings
Recommended Operating Conditions [2]
DC Electrical Specifications
Symbol Parameter Conditions Min Max Unit
VCCINT Supply Voltage, Internal Logic and Input Buffers
Commercial Grade Devices 3.00 3.60 V
Industrial Grade Devices 3.00 3.60 V
VCCIO DC Input Voltage for 3.3V Operation
Commercial Grade Devices 3.00 3.60 V
Industrial Grade Devices 3.00 3.60 V
VCCIO DC Input Voltage for 2.5V Operation
Commercial Grade Devices 2.30 2.70 V
Industrial Grade Devices 2.30 2.70 V
VIInput Voltage -0.5 5.75 V
VOOutput Voltage 0 VCCIO V
TAOperating Temperature
Commercial Temperature Range 0 70 °C
Industrial Temperature Range -40 85 °C
tRInput Signal Rise Time 40 ns
tFInput Signal Fall Time 40 ns
10KA tbl 03B
10KA tbl 02
LIBERATOR CL10K100A
Page 9
Capacitance[4]
DC Electrical Specifications cont.
Symbol Parameter Conditions Min Max Unit
CIN Input Capacitance VIN = 0 V, f = 1.0 MHz 10 pF
COUT Output Capacitance VOUT = 0 V, f = 1.0 MHz 10 pF
10KA tbl 05A
DC Electrical Characteristics (over the operating range)
Symbol Parameter Conditions Min
Typ[3] Max Unit
VIH Input HIGH Voltage
Lower of
1.7 or 0.5
x VCCINT
5.75 V
VIL Input LOW Voltage -0.5 0.3 x VCCINT V
3.3-V High-Level TTL Output
Voltage
IOH = -8 mA DC, VCCIO = 3.00 V 2.4 V
3.3-V High-Level CMOS
Output Voltage
IOH = -0.1 mA DC, VCCIO = 3.00 V VCCIO-0.2 V
3.3-V High-Level PCI Output
Voltage
IOH = -0.5 mA DC, VCCIO = 3 to 3.60 V 0.9 x VCCIO V
IOH = -0.1 mA DC, VCCIO = 2.30 V 2.1 V
IOH = -1 mA DC, VCCIO = 2.30 V 2.0 V
IOH = -2 mA DC, VCCIO = 2.30 V 1.7 V
3.3-V Low-Level TTL Output
Voltage
IOL = 9 mA DC, VCCIO = 3.00 V 0.45 V
3.3-V Low-Level CMOS
Output Voltage
IOL = 0.1 mA DC, VCCIO = 3.00 V 0.2 V
3.3-V Low-Level PCI Output
Voltage
IOL = 1.5 mA DC, VCCIO = 3 to 3.60 V 0.1 x VCCIO V
IOL = 0.1 mA DC, VCCIO = 2.30 V 0.2 V
IOL = 1 mA DC, VCCIO = 2.30 V 0.4 V
IOL = 2 mA DC, VCCIO = 2.30 V 0.7 V
IIN Input Leakage Current VI = 5.3V to -0.3V -10 10 µA
IOZ Output Leakage Current VO = 5.3V to -0.3V -10 10 µA
ICC0 Standby Current VI = GND, no load 0.3 10 mA
10KA tbl 04B
VOH
2.5-V High-Level Output
Voltage
VOL
2.5-V Low-Level Output
Voltage
LIBERATOR CL10K100A
Page 10
AC Electrical Specifications
Symbol
Parameter Min Max Min Max Min Max Unit
tIOD IOE Register Data Delay 2.5 2.9 3.4 ns
tIOC IOE Register Control Signal Delay 0.3 0.3 0.4 ns
tIOCO IOE Register Clock to Output Delay 0.2 0.2 0.3 ns
tIOCOMB IOE Combinatorial Delay 0.5 0.6 0.7 ns
tIOSU IOE Register Setup Time Before Clock 1.3 1.7 1.8 ns
tIOH IOE Register Hold Time After Clock 0.2 0.2 0.3 ns
tIOCLR IOE Register Clear Delay 1.0 1.2 1.4 ns
tZX Output Buffer Disable Delay[6] 2.7 3.1 3.7 ns
tINREG
IOE Input Pad and Buffer to IOE Register
Delay
5.3 6.1 7.2 ns
tIOFD IOE Register Feedback Delay 4.7 5.5 6.4 ns
tINCOMB IOE Input Pad and Buffer to Interconnect Delay 4.7 5.5 6.4 ns
5.8
6.8
tZX2
Output Buffer Disable Delay
Slow Slew Rate = off, VCCIO = Low Voltage[6]
5.0
10KA tbl 06B
tOD2
Output Buffer and Pad Delay
Slow Slew Rate = off, VCCIO = Low Voltage
4.5
5.3
6.1
ns
6.8
2.7
tZX3
Output Buffer Disable Delay
Slow Slew Rate = on[6]
8.4
7.3
3.7
ns
10.0
ns
ns
tZX1
Output Buffer Disable Delay
Slow Slew Rate = off, VCCIO = VCCINT[6]
3.1
ns
tOD3
Output Buffer and Pad Delay
Slow Slew Rate = on
7.9
9.3
ns
2.2
Speed: -2
Speed: -3
tOD1
Output Buffer and Pad Delay
Slow Slew Rate = off, VCCIO = VCCINT
2.6
3.0
Speed: -1
I/O Element Timing Parameters [5]
LIBERATOR CL10K100A
Page 11
Symbol
Parameter Min Max Min Max Min Max Unit
tLUT Look-up Table Delay for Data-in 1.0 1.2 1.4 ns
tCLUT Look-up Table Delay for Carry-in 0.8 0.9 1.1 ns
tRLUT
Look-up Table Delay for LE Register
Feedback
1.4 1.6 1.9 ns
tPACKED Data-in to Packed Register Delay 0.4 0.5 0.5 ns
tEN LE Register Enable Delay 0.6 0.7 0.8 ns
tCICO Carry-in to Carry-out Delay 0.2 0.2 0.3 ns
tCGEN Data-in to Carry-out Delay 0.4 0.4 0.6 ns
tCGENR LE Register Feedback to Carry-out Delay 0.6 0.7 0.8 ns
tCASC Cascade Chain Routing Ddelay 0.7 0.9 1.0 ns
tCLE Register Control Signal Delay 0.9 1.0 1.2 ns
tCO LE Register Clock-to-output Delay 0.2 0.3 0.3 ns
tCOMB Combinatorial Delay 0.6 0.7 0.8 ns
tSU LE Register Setup Time Before Clock 0.8 1.0 1.2 ns
tHLE Register Hold Time After Clock 0.3 0.5 0.5 ns
tPRE LE Register Preset Delay 0.3 0.3 0.4 ns
tCLR LE Register Clear Delay 0.3 0.3 0.4 ns
tCH Clock High Time 2.5 3.5 4.0 ns
tCL Clock Low Time 2.5 3.5 4.0 ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 08B
AC Electrical Specifications cont.
Logic Element Timing Parameters[5]
Symbol
Parameter Min Max Min Max Min Max Unit
tDRR
Register to Register Delay via Four LEs,
Three Row Interconnects, and Four Local
Interconnects
12.5 14.5 17.0 ns
tINSU
Setup Time with Global Clock at IOE
Register 3.7 4.5 5.1 ns
tINH Hold time with Global Clock at IOE Register 0.0 0.0 0.0 ns
tOUTCO Output Data Hold Time After Clock 2.0 5.3 2.0 6.1 2.0 7.2 ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 07B
External Timing Parameters[4]
LIBERATOR CL10K100A
Page 12
AC Electrical Specifications cont.
Symbol
Parameter Min Max Min Max Min Max Unit
tDIN2IOE
Delay from Dedicated Input Pin to IOE
Control Input
4.8 5.4 6.0 ns
tDIN2LE
Delay from Dedicated Input Pin to LE or EAB
Control Input
2.0 2.4 2.7 ns
tDIN2DATA
Delay from Dedicated Input or Clock Pin to
LE or EAB Data
2.4 2.7 2.9 ns
tDCLK2IOE Delay from Dedicated Clock Pin to IOE Clock 2.6 3.0 3.5 ns
tDCLK2LE
Delay from Dedicated Clock Pin to LE or EAB
Clock
2.0 2.4 2.7 ns
tSAMELAB Delay from an LE to LE in Same LAB 0.1 0.1 0.1 ns
tSAMEROW
Delay for Driving a Row IOE, LE or EAB to a
Row IOE, LE or EAB in the Same Row
1.5 1.7 1.9 ns
tSAMECOLUMN
Delay from an LE to IOE in the Same
Column 5.5 6.5 7.4 ns
tDIFFROW
Delay for Driving a Column IOE, LE or EAB to
an LE or EAB in a Different Row
7.0 8.2 9.3 ns
tTWOROWS
Delay for Driving a Row IOE or EAB to an LE
or EAB in a Different Row
8.5 9.9 11.2 ns
tLEPERIPH
Delay from an LE to IOE Control Signal via
the Peripheral Dontol Bus
3.9 4.2 4.5 ns
tLABCARRY
Delay from an LE Carry-out Signal to an LE
Carry-in Signal in a Different LAB
0.2 0.2 0.3 ns
tLABCASC
Delay from an LE Cascade-out Signal to an
LE Cascade-in Signal in a Different LAB
0.4 0.5 0.6 ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 09B
Interconnect Timing Parameters[5]
LIBERATOR CL10K100A
Page 13
AC Electrical Specifications cont.
Symbol
Parameter Min Max Min Max Min Max Unit
tEABDATA1
Delay from Data or Address to EAB for
Combinatorial Input
1.8 2.1 2.4 ns
tEABDATA2
Delay from Data or Address to EAB for
Registered Input
3.2 3.7 4.4 ns
tEABWE1 WE Delay to EAB for Combinatorial Input 0.8 0.9 1.1 ns
tEABWE2 WE Delay to EAB for Registered Input 2.3 2.7 3.1 ns
tEABCLK EAB Register Clock Delay 0.8 0.9 1.1 ns
tEABCO EAB Register Clock-to-output Delay 1.0 1.1 1.4 ns
tEABBYPASS Bypass Register Delay 0.3 0.3 0.4 ns
tEABSU EAB Register Setup Time 1.3 1.5 1.8 ns
tEABH EAB Register Hold Time 0.4 0.5 0.5 ns
tAA Address Access Delay 4.1 4.8 5.6 ns
tWP Write Pulse Width 3.2 3.7 4.4 ns
tWDSU
Data Setup Time Before Falling Edge of
Write Pulse
2.4 2.8 3.3 ns
tWDH
Data Hold Time After Falling Edge of Write
Pulse
0.2 0.2 0.3 ns
tWASU
Address Setup Time Before Rising Edge of
Write Pulse
0.2 0.2 0.3 ns
tWAH
Address Hold After Falling Edge of Write
Pulse
0.0 0.0 0.0 ns
tWO Write Enable to Date Output Delay 3.4 3.9 4.6 ns
tDD Data-in to Date-out Delay 3.4 3.9 4.6 ns
tEABOUT Data-out Delay 0.3 0.3 0.4 ns
tEABCH Clock High Time 2.5 3.5 4.0 ns
tEABCL Clock Low Time 3.2 3.7 4.4 ns
10KA tbl 10B
Speed: -1
Speed: -2
Speed: -3
EAB Timing Parameters[5]
LIBERATOR CL10K100A
Page 14
AC Electrical Specifications cont.
EAB Timing Parameters[5]
Symbol
Parameter Min Max Min Max Min Max Unit
tEABAA EAB Address Access Delay 6.8 7.8 9.2 ns
tEABRCCOMB EAB Asynchronous Read Cycle Time 6.8 7.8 9.2 ns
tEABRCREG EAB Synchronous Read Cycle Time 5.4 6.2 7.4 ns
tEABWP EAB Write Pulse Width 3.2 3.7 4.4 ns
tEABWCCOMB EAB Asynchronous Write Cycle Time 3.4 3.9 4.7 ns
tEABWCREG EAB Synchronous Write Cycle Time 9.4 10.8 12.8 ns
tEABDD EAB Data-in to Data-out Delay 6.1 6.9 8.2 ns
tEABDATACO
EAB Clock-to-output Delay Using Output
Registers
2.1 2.3 2.9 ns
tEABDATASU
EAB Data/Address Setup Time Using Input
Register
3.7 4.3 5.1 ns
tEABDATAH
EAB Data/Address Hold Time Using Input
Register
0.0 0.0 0.0 ns
tEABWESU EAB WE Setup When Using Input Register 2.8 3.3 3.8 ns
tEABWESH
EAB WE Hold Time When Using Input
Register
0.0 0.0 0.0 ns
tEABWDSU
EAB Data Setup Time to Falling Edge of
Write Pulse When Not Using Input Registers
3.4 4.0 4.6 ns
tEABWDH
EAB Data Hold Time After Falling Edge of
Write Pulse When Not Using Input Registers
0.0 0.0 0.0 ns
tEABWASU
EAB Address Setup Time to Rising Edge of
Write Pulse When Not Using Input Registers
1.9 2.3 2.6 ns
tEABWAH
EAB Address Hold Time After Falling Edge
of Write Pulse When Not Using Input
Registers
0.0 0.0 0.0 ns
tEABWO EAB WE to Data Output Delay 5.1 5.7 6.9 ns
10KA tbl 11B
Speed: -1
Speed: -2
Speed: -3
LIBERATOR CL10K100A
Page 15
AC Electrical Specifications cont.
External Bi-Directional Timing Parameters[5]
Symbol
Parameter Min Max Min Max Min Max Unit
tINSUBIDIR
Setup for Bi-directional Pins with Global
Clock at Adjacent LE Registers
4.9 5.8 6.8 ns
tINHBIDIR
Hold Time for Bi-directional Pins with Global
Glock at Adjacent LE Registers
0.0 0.0 0.0 ns
tOUTCOBIDIR
Clock-to-output Delay for Bi-directional Pins
with Global Clock at IOE Register
2.0 5.3 2.0 6.1 2.0 7.2 ns
tXZBIDIR
Synchronous IOE Output Buffer Disable
Delay
7.4 8.6 10.1 ns
tZXBIDIR
Synchronous IOE Output Buffer Disable
Delay, Slow Slew Rate = off
7.4 8.6 10.1 ns
Speed: -1
Speed: -2
Speed: -3
10KA tbl 12B
20 Apr. 2000: Created new document
01 Dec. 2000: Updated package availability and additional literature available
22 May 2001: Corrected GNDINT table
AC Test Conditions
703 Ω
8.06k Ω35 pF
V
CCIO
OUTPUT
Includes jig
capacitance
703 Ω
8.06k Ω5 pF
V
CCIO
OUTPUT
Includes jig
capacitance
(A) (B)
≤ 3ns
≤ 3ns
3.0V 90%
10%
GND
90%
10%
All Input Pulses
10KA drw 02
Notes to Tables
Revision History
1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for
periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V.
2. Device inputs may be driven before VCCINT and VCCIO are powered.
3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 ºC.
4. Guaranteed but not tested. Characterized initially, and after any design changes
which may affect these parameters.
5. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
6. Use AC Test Conditions set-up B for these parameters.
A: Test fixture set-up A is for general testing.
B: Test fixture set-up B is for high Z testing (tZX#).
LIBERATOR CL10K100A
Page 16
Ordering Information
Part Number Temperature Range Package Type Speed Altera Equivalent
CL10K100AQC240-3 Commercial 240-pin Plastic QFP -3 EPF10K100AQC240-3
CL10K100AQC240-2 -2 EPF10K100AQC240-2
CL10K100AQC240-1 -1 EPF10K100AQC240-1
CL10K100AQI240-3 Industrial -3 EPF10K100AQI240-3
CL10K100ARC240-3 Commercial 240-pin Power QFP -3 EPF10K100ARC240-3
CL10K100ARC240-2 -2 EPF10K100ARC240-2
CL10K100ARC240-1 -1 EPF10K100ARC240-1
CL10K100ARI240-3 Industrial -3 EPF10K100ARI240-3
CL10K100ABC356-3 Commercial 356-pin SBGA -3 EPF10K100ABC356-3
CL10K100ABC356-2 -2 EPF10K100ABC356-2
CL10K100ABC356-1 -1 EPF10K100ABC356-1
CL10K100ABI356-3 Industrial -2 EPF10K100ABI356-3
CL10K100ABI356-2 -2 EPF10K100ABI356-2
CL10K100AFC484-3 Commercial 484-pin FBGA -3 EPF10K100AFC484-3
CL10K100AFC484-2 -2 EPF10K100AFC484-2
CL10K100AFC484-1 -1 EPF10K100AFC484-1
CL10K100ABC600-3 Commercial 600-pin SBGA -3 EPF10K100ABC600-3
CL10K100ABC600-2 -2 EPF10K100ABC600-2
CL10K100ABC600-1 -1 EPF10K100ABC600-1
CL10K100ABI600-2 Industrial -2 EPF10K100ABI600-2
10K100A tbl 02