¨
1
FEATURES
DESCRIPTION
APPLICATIONS
RELATED PRODUCTS
1/4
OPA4830
VIN
750W562W
2.26kW
374W
22pF
+3.3V
100W
+3.3V
1/4
ADS5240
12-Bit
40MSPS
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Quad, Low-Power, Single-Supply, Wideband Operational Amplifier
2
•HIGH BANDWIDTH:
The OPA4830 is a quad, low-power, single-supply,280MHz (G = +1)
wideband, voltage-feedback amplifier designed to120MHz (G = +2)
operate on a single +3V or +5V supply. Operation on•LOW SUPPLY CURRENT:
± 5V or +10V supplies is also supported. The input3.9mA/ch (V
S
= +5V)
range extends below the negative supply and to•FLEXIBLE SUPPLY RANGE:
within 1.8V of the positive supply. Using± 1.4V to ± 5.5V Dual Supply
complementary common-emitter outputs provides anoutput swing to within 220mV of either supply while+2.8V to +11V Single Supply
driving 150 Ω. High output drive current ( ± 80mA) and•INPUT RANGE INCLUDES GROUND ON
low differential gain and phase errors also make thisSINGLE SUPPLY
amplifier an excellent choice for single-supply•4.91V OUTPUT SWING ON +5V SUPPLY
consumer video products.•HIGH SLEW RATE: 560V/ µs
Low distortion operation is ensured by the high gain•LOW INPUT VOLTAGE NOISE: 9.2nV/ √Hz
bandwidth product (110MHz) and slew rate(560V/ µs), making the OPA4830 an ideal input buffer•AVAILABLE IN A TSSOP-14 PACKAGE
stage to 3V and 5V CMOS analog-to-digitalconverters (ADCs). Unlike other low-power,single-supply amplifiers, distortion performance•SINGLE-SUPPLY ANALOG-TO-DIGITAL
improves as the signal swing is decreased. A lowCONVERTER (ADC) INPUT BUFFERS
9.2nV/ √Hz input voltage noise supports wide dynamic•SINGLE-SUPPLY VIDEO LINE DRIVERS
range operation.•CCD IMAGING CHANNELS
The OPA4830 is available in an industry-standard•ACTIVE FILTERS
quad pinout TSSOP-14 package.•PLL INTEGRATORS
•PORTABLE CONSUMER ELECTRONICS
DESCRIPTION SINGLES DUALS TRIPLES QUADS
Rail-to-Rail OPA830 OPA2830 — —
Rail-to-Rail Fixed-Gain OPA832 OPA2832 OPA3832 —
General-Purpose
OPA690 OPA2690 OPA3690 —(1800V/ µs slew rate)
Low-Noise,
OPA820 OPA2822 — OPA4820High DC Precision
Figure 1. DC-Coupled, +3.3V ADC Driver
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OutputD
-InputD
+InputD
-V
+InputC
-InputC
OutputC
OutputA
-InputA
+InputA
+V
+InputB
-InputB
OutputB
A D
B C
OPA4830
TopView TSSOP
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA,PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER QUANTITY
OPA4830IPW Rail, 90OPA4830 TSSOP-14 PW – 40 °C to +85 °C OPA4830
OPA4830IPWR Tape and Reel, 2000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Power Supply 12V
DC
Internal Power Dissipation See Thermal AnalysisDifferential Input Voltage ± 2.5VInput Voltage Range (Single Supply) – 0.5V to +V
S
+ 0.3VStorage Temperature Range: D, PW – 65 °C to +125 °CLead Temperature (soldering, 10s) +300 °CMaximum Junction Temperature (T
J
):Peak +150 °CContinuous Operation, Long-Term Reliability +140 °CESD Rating:
Human Body Model (HBM) 2000VCharge Device Model (CDM) 1500VMachine Model (MM) 200V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress Ratings only, and functional operations of the device at these and any other conditionsbeyond those specified is not supported.
PIN CONFIGURATION
2Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
ELECTRICAL CHARACTERISTICS: V
S
= ± 5V
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Boldface limits are tested at +25 °C.At T
A
= +25 °C, G = +2, R
F
= 750 Ω, and R
L
= 150 Ωto GND, unless otherwise noted.
OPA4830IPW
TYP MIN/MAX OVER TEMPERATURE
0°C to – 40 °C to MIN/ TESTPARAMETER CONDITIONS +25 °C +25 °C
(2)
+70 °C
(3)
+85 °C
(3)
UNITS MAX LEVEL
(1)
AC PERFORMANCE (see Figure 74 )
Small-Signal Bandwidth G = +1, V
O
≤0.2V
PP
280 MHz typ C
G = +2, V
O
≤0.2V
PP
120 66 64 61 MHz min B
G = +5, V
O
≤0.2V
PP
23 16 14 13 MHz min B
G = +10, V
O
≤0.2V
PP
11 8 7 6 MHz min B
Gain-Bandwidth Product G ≥+10 110 80 77 75 MHz min B
Peaking at a Gain of +1 V
O
≤0.2V
PP
6 dB typ C
Slew Rate G = +2, 2V Step 560 275 265 255 V/ µs min B
Rise Time 0.5V Step 3.4 5.9 5.95 6.0 ns max B
Fall Time 0.5V Step 3.6 6.0 6.05 6.1 ns max B
Settling Time to 0.1% G = +2, 1V Step 43 64 66 67 ns max B
Harmonic Distortion V
O
= 2V
PP
, f = 5MHz
2nd-Harmonic R
L
= 150 Ω– 60 – 53 – 51 – 50 dBc max B
R
L
≥500 Ω– 68 – 58 – 57 – 56 dBc max B
3rd-Harmonic R
L
= 150 Ω– 59 – 50 – 49 – 48 dBc max B
R
L
≥500 Ω– 77 – 65 – 62 – 55 dBc max B
Input Voltage Noise f > 1MHz 9.5 10.6 11.1 11.6 nV/ √Hz max B
Input Current Noise f > 1MHz 3.7 4.8 5.3 5.8 pA/ √Hz max B
NTSC Differential Gain 0.07 % typ C
NTSC Differential Phase 0.17 °typ C
DC PERFORMANCE
(4)
R
L
= 150 Ω
Open-Loop Voltage Gain 74 66 65 64 dB min A
Input Offset Voltage ± 2 ± 8 ± 9.4 ± 9.8 mV max A
Average Offset Voltage Drift ± 30 ± 30 µV/ °C max B
Input Bias Current V
CM
= 0V +5 +10 +12 +13 µA max A
Input Bias Current Drift ± 44 ± 46 nA/ °C max B
Input Offset Current V
CM
= 0V ± 0.2 ± 1.1 ± 1.3 ± 1.5 µA max A
Input Offset Current Drift — ± 5 ± 5 nA/ °C max B
INPUT
Negative Input Voltage
(5)
– 5.5 – 5.4 – 5.3 – 5.2 V max A
Positive Input Voltage
(5)
3.2 3.1 3.0 2.9 V min A
Common-Mode Rejection Ratio (CMRR) Input-Referred 80 76 74 71 dB min A
Input Impedance
Differential Mode 10 || 2.1 k Ω|| pF typ C
Common-Mode 400 || 1.2 k Ω|| pF typ C
OUTPUT
Output Voltage Swing G = +2, R
L
= 1k Ωto GND ± 4.88 ± 4.86 ± 4.85 ± 4.84 V min A
G = +2, R
L
= 150 Ωto GND ± 4.64 ± 4.60 ± 4.58 ± 4.56 V min A
Current Output, Sinking and Sourcing ± 82 ± 63 ± 58 ± 53 mA min A
Short-Circuit Current Output Shorted to Ground ± 150 mA typ C
Closed-Loop Output Impedance G = +2, f ≤100kHz 0.06 Ωtyp C
(1) Test levels: (A) 100% tested at +25 °C. Over temperature limits set by characterization and simulation. (B) Limits set by characterizationand simulation. (C) Typical value only for information.(2) Junction temperature = ambient for +25 °C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +19 °C at high temperature limit for overtemperature specifications.(4) Current is considered positive out of pin.(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): OPA4830
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= ± 5V (continued)Boldface limits are tested at +25 °C.At T
A
= +25 °C, G = +2, R
F
= 750 Ω, and R
L
= 150 Ωto GND, unless otherwise noted.
OPA4830IPW
TYP MIN/MAX OVER TEMPERATURE
0°C to – 40 °C to MIN/ TESTPARAMETER CONDITIONS +25 °C +25 °C
(2)
+70 °C
(3)
+85 °C
(3)
UNITS MAX LEVEL
(1)
POWER SUPPLY
Minimum Operating Voltage ± 1.4 V typ C
Maximum Operating Voltage ± 5.5 ± 5.5 ± 5.5 V max A
Maximum Quiescent Current V
S
= ± 5V, All Channels 17 19 21.4 23.8 mA max A
Minimum Quiescent Current V
S
= ± 5V, All Channels 17 16 14.4 13.2 mA min A
Power-Supply Rejection Ratio ( – PSRR) Input-Referred 66 61 60 59 dB min A
THERMAL CHARACTERISTICS
Specification: IPW – 40 to +85 °C typ C
Thermal Resistance, θ
JA
PW TSSOP-14 95 °C/W typ C
4Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
ELECTRICAL CHARACTERISTICS: V
S
= +5V
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Boldface limits are tested at +25 °C.At T
A
= +25 °C, G = +2, R
F
= 750 Ω, and R
L
= 150 Ωto V
S
/2, unless otherwise noted.
OPA4830IPW
TYP MIN/MAX OVER TEMPERATURE
0°C to – 40 °C to MIN/ TESTPARAMETER CONDITIONS +25 °C +25 °C
(2)
+70 °C
(3)
+85 °C
(3)
UNITS MAX LEVEL
(1)
AC PERFORMANCE (see Figure 72 )
Small-Signal Bandwidth G = +1, V
O
≤0.2V
PP
230 MHz typ C
G = +2, V
O
≤0.2V
PP
100 70 68 66 MHz min B
G = +5, V
O
≤0.2V
PP
21 15 14 13 MHz min B
G = +10, V
O
≤0.2V
PP
10 7 6 5 MHz min B
Gain-Bandwidth Product G ≥+10 100 75 65 59 MHz min B
Peaking at a Gain of +1 V
O
≤0.2V
PP
5 dB typ C
Slew Rate G = +2, 2V Step 500 270 260 250 V/ µs min B
Rise Time 0.5V Step 3.4 5.8 5.9 6.0 ns max B
Fall Time 0.5V Step 3.4 5.8 5.9 6.0 ns max B
Settling Time to 0.1% G = +2, 1V Step 44 65 67 68 ns max B
Harmonic Distortion V
O
= 2V
PP
, f = 5MHz
2nd-Harmonic R
L
= 150 Ω– 56 – 50 – 49 – 48 dBc max B
R
L
≥500 Ω– 62 – 56 – 55 – 54 dBc max B
3rd-Harmonic R
L
= 150 Ω– 58 – 50 – 49 – 48 dBc max B
R
L
≥500 Ω– 84 – 65 – 62 – 60 dBc max B
Input Voltage Noise f > 1MHz 9.2 10.3 10.8 11.3 nV/ √Hz max B
Input Current Noise f > 1MHz 3.5 4.6 5.1 5.6 pA/ √Hz max B
NTSC Differential Gain 0.08 % typ C
NTSC Differential Phase 0.09 °typ C
All Hostile Crosstalk, Input-Referred 3 Channels Driven at 5MHz, – 62 dB typ C1V
PP
, 4th Channel Measured
DC PERFORMANCE
(4)
R
L
= 150 Ω
Open-Loop Voltage Gain 72 66 65 64 dB min A
Input Offset Voltage ± 0.5 ± 6 ± 7 ± 7.5 mV max A
Average Offset Voltage Drift ± 24 ± 24 µV/ °C max B
Input Bias Current V
CM
= 2.5V +5 +10 +12 +13 µA max A
Input Bias Current Drift ± 44 ± 46 nA/ °C max B
Input Offset Current V
CM
= 2.5V ± 0.2 ± 0.9 ± 1.1 ± 1.3 µA max A
Input Offset Current Drift ± 5 ± 6 nA/ °C max B
INPUT
Least Positive Input Voltage
(5)
– 0.5 – 0.4 – 0.3 – 0.2 V max A
Most Positive Input Voltage
(5)
3.2 3.1 3.0 2.8 V min A
Common-Mode Rejection Ratio (CMRR) Input-Referred 80 76 74 71 dB min A
Input Impedance
Differential-Mode 10 || 2.1 k Ω|| pF typ C
Common-Mode 400 || 1.2 k Ω|| pF typ C
OUTPUT
Least Positive Output Voltage G = +5, R
L
= 1k Ωto 2.5V 0.09 0.11 0.12 0.13 V max A
G = +5, R
L
= 150 Ωto 2.5V 0.21 0.24 0.25 0.26 V max A
Most Positive Output Voltage G = +5, R
L
= 1k Ωto 2.5V 4.91 4.89 4.88 4.87 V min A
G = +5, R
L
= 150 Ωto 2.5V 4.78 4.75 4.73 4.72 V min A
Current Output, Sourcing and Sinking ± 75 ± 58 ± 53 ± 50 mA min A
Short-Circuit Output Current Output Shorted to Either ± 140 mA typ CSupply
Closed-Loop Output Impedance G = +2, f ≤100kHz 0.06 Ωtyp C
(1) Test levels: (A) 100% tested at +25 °C. Over temperature limits set by characterization and simulation. (B) Limits set by characterizationand simulation. (C) Typical value only for information.(2) Junction temperature = ambient for +25 °C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +9 °C at high temperature limit for overtemperature specifications.(4) Current considered positive out of pin.(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): OPA4830
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= +5V (continued)Boldface limits are tested at +25 °C.At T
A
= +25 °C, G = +2, R
F
= 750 Ω, and R
L
= 150 Ωto V
S
/2, unless otherwise noted.
OPA4830IPW
TYP MIN/MAX OVER TEMPERATURE
0°C to – 40 °C to MIN/ TESTPARAMETER CONDITIONS +25 °C +25 °C
(2)
+70 °C
(3)
+85 °C
(3)
UNITS MAX LEVEL
(1)
POWER SUPPLY
Minimum Operating Voltage +2.8 V typ C
Maximum Operating Voltage +11 +11 +11 V max A
Maximum Quiescent Current V
S
= +5V, All Channels 15.6 16.6 19.4 22.2 mA max A
Minimum Quiescent Current V
S
= +5V, All Channels 15.6 14.8 13.6 12.0 mA min A
Power-Supply Rejection Ratio (PSRR) Input-Referred 66 61 60 59 dB min A
THERMAL CHARACTERISTICS
Specification: IPW – 40 to +85 °C typ C
Thermal Resistance, θ
JA
PW TSSOP-14 95 °C/W typ C
6Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
ELECTRICAL CHARACTERISTICS: V
S
= +3V
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Boldface limits are tested at +25 °C.At T
A
= +25 °C, G = +2, and R
L
= 150 Ωto V
S
/3, unless otherwise noted.
OPA4830IPW
TYP MIN/MAX OVER TEMPERATURE
0°C to MIN/PARAMETER CONDITIONS +25 °C +25 °C
(2)
+70 °C
(3)
UNITS MAX TEST LEVEL
(1)
AC PERFORMANCE (see Figure 73 )
Small-Signal Bandwidth G = +2, V
O
≤0.2V
PP
100 70 66 MHz min B
G = +5, V
O
≤0.2V
PP
21 15 14 MHz min B
G = +10, V
O
≤0.2V
PP
10 7.5 6.5 MHz min B
Gain-Bandwidth Product G ≥+10 100 75 65 MHz min B
Slew Rate 1V Step 220 135 105 V/ µs min B
Rise Time 0.5V Step 3.4 5.6 5.7 ns max B
Fall Time 0.5V Step 3.4 5.6 5.7 ns max B
Settling Time to 0.1% 1V Step 46 73 88 ns max B
Harmonic Distortion V
O
= 1V
PP
, f = 5MHz
2nd-Harmonic R
L
= 150 Ω– 60 – 56 – 54 dBc max B
R
L
≥500 Ω– 65 – 59 – 57 dBc max B
3rd-Harmonic R
L
= 150 Ω– 68 – 59 – 58 dBc max B
R
L
≥500 Ω– 76 – 65 – 64 dBc max B
Input Voltage Noise f > 1MHz 9.2 10.3 10.8 nV/ √Hz max B
Input Current Noise f > 1MHz 3.5 4.6 5.1 pA/ √Hz max B
DC PERFORMANCE
(4)
Open-Loop Voltage Gain 72 66 65 dB min A
Input Offset Voltage ± 1.5 ± 7.5 ± 8.7 mV max A
Average Offset Voltage Drift ± 27 µV/ °C max B
Input Bias Current V
CM
= 1.0V +5 +10 +12 µA max A
Input Bias Current Drift ± 44 nA/ °C max B
Input Offset Current V
CM
= 1.0V ± 0.2 ± 1.1 ± 1.3 µA max A
Input Offset Current Drift ± 5 nA/ °C max B
INPUT
Least Positive Input Voltage
(5)
– 0.45 – 0.4 – 0.27 V max A
Most Positive Input Voltage
(5)
1.2 1.1 1.0 V min A
Common-Mode Rejection Ratio (CMRR) Input-Referred 80 74 72 dB min A
Input Impedance
Differential-Mode 10 || 2.1 k Ω|| pF typ C
Common-Mode 400 || 1.2 k Ω|| pF typ C
OUTPUT
Least Positive Output Voltage G = +5, R
L
= 1k Ωto 1.5V 0.08 0.11 0.125 V max A
G = +5, R
L
= 150 Ωto 1.5V 0.17 0.39 0.40 V max A
Most Positive Output Voltage G = +5, R
L
= 1k Ωto 1.5V 2.91 2.88 2.85 V min A
G = +5, R
L
= 150 Ωto 1.5V 2.82 2.74 2.70 V min A
Current Output, Sourcing and Sinking ± 30 ± 20 ± 18 mA min A
Short-Circuit Output Current Output Shorted to Either Supply ± 45 mA typ C
Closed-Loop Output Impedance See Figure 73 , f < 100kHz 0.06 Ωtyp C
(1) Test levels: (A) 100% tested at +25 °C. Over temperature limits set by characterization and simulation. (B) Limits set by characterizationand simulation. (C) Typical value only for information.(2) Junction temperature = ambient for +25 °C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +5 °C at high temperature limit for overtemperature specifications.(4) Current considered positive out of pin.(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): OPA4830
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= +3V (continued)Boldface limits are tested at +25 °C.At T
A
= +25 °C, G = +2, and R
L
= 150 Ωto V
S
/3, unless otherwise noted.
OPA4830IPW
TYP MIN/MAX OVER TEMPERATURE
0°C to MIN/PARAMETER CONDITIONS +25 °C +25 °C
(2)
+70 °C
(3)
UNITS MAX TEST LEVEL
(1)
POWER SUPPLY
Minimum Operating Voltage +2.8 V min B
Maximum Operating Voltage +11 +11 V max A
Maximum Quiescent Current V
S
= +3V, All Channels 15 16.4 17.6 mA max A
Minimum Quiescent Current V
S
= +3V, All Channels 15 13.2 12.4 mA min A
Power-Supply Rejection Ratio (PSRR) Input-Referred 64 60 58 dB min A
THERMAL CHARACTERISTICS
Specification: IPW – 40 to +85 °C typ C
Thermal Resistance, θ
JA
PW TSSOP-14 95 °C/W typ C
8Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
TYPICAL CHARACTERISTICS: V
S
= ± 5V
6
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
NormalizedGain(dB)
1 10 100 600
V =0.2V
O PP
R =150W
L
G=+1
R =0W
V/V
F
G=+2V/V
G=+5V/V
G=+10V/V
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
NormalizedGain(dB)
1 10 100 400
V =0.2VO PP
R =150LW
G= 2-
G= 10-
G= 1-
G= 5-
9
6
3
0
-3
-6
-9
-12
Frequency(MHz)
Gain(dB)
10 100 400
G=+2V/V
R =150W
L
V =2V
O PP
V =0.5V
O PP
V =4V
O PP
V =1V
O PP
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
Gain(dB)
10 100 400
G= 1V/V-
R =150W
L
V =2V
O PP
V =1V
O PP
V =0.5V
O PP
V =4V
O PP
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
Time(10ns/div)
Small-SignalOutputVoltage(V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
Large-SignalOutputVoltage(V)
Large-Signal ±1V
RightScale
Small-Signal 100mV±
LeftScale
G= 1V/V-
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
Time(10ns/div)
Small-SignalOutputVoltage(V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
Large-SignalOutputVoltage(V)
Large-Signal 1V±
RightScale
Small-Signal 100mV±
LeftScale
G=+2V/V
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ω, and R
L
= 150 Ωto GND, unless otherwise noted (see Figure 74 ).
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Figure 2. Figure 3.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Figure 4. Figure 5.
NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE
Figure 6. Figure 7.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): OPA4830
-50
-55
-60
-65
-70
-75
-80
-85
Resistance( )W
HarmonicDistortion(dBc)
100 1k
G=+2V/V
V =2V
O PP
f=5MHz 3rd-Harmonic
2nd-Harmonic
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
SupplyVoltage(V)
HarmonicDistortion(dBc)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 6.05.5
G=+2V/V
VO PP
=2V
RW
L=500
2nd-Harmonic
3rd-Harmonic
InputLimitedforV =0V
CM
-55
-60
-65
-70
-75
-80
-85
-90
-95
HarmonicDistortion(dBc)
OutputVoltage(V )PP
0.1 1 10
2nd-Harmonic
3rd-Harmonic
G=+2V/V
RL=500W
f=5MHz
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
Frequency(MHz)
HarmonicDistortion(dBc)
0.1 1 10
3rd-Harmonic
R =150W
L
2nd-Harmonic
R =150W
L
2nd-Harmonic
R =500W
L
3rd-Harmonic
R =500W
L
G=+2V/V
V =2V
O PP
83
82
81
80
79
78
77
AmbientTemperature( C)°
OutputCurrent(mA)
13
12
11
10
9
8
7
SupplyCurrent(mA)
-50 -25 0 25 50 75 100 125
OutputCurrent(sourcing)
OutputCurrent(sinking)
QuiescentCurrent(total,bothamplifiers)
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ω, and R
L
= 150 Ωto GND, unless otherwise noted (see Figure 74 ).
HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs SUPPLY VOLTAGE
Figure 8. Figure 9.
HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY
Figure 10. Figure 11.
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Figure 12. Figure 13.
10 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
120
110
100
90
80
70
60
50
40
30
20
10
CapacitiveLoad(pF)
R ( )
W
S
1 10 100 1k
0.1dBPeakingTargeted
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
Resistance( )W
OutputVoltage(V)
10 100 1k
G=+5V/V
V = 5V±
S
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
I (mA)
O
V (V)
O
-160 -120 -80 -40 0 40 80 120 160
1WInternal PowerLimit,OneChannelOnly
Output
CurrentLimit
Output
CurrentLimit
1WInternal
PowerLimit
R =500
LW
R =100
LW
R =50
LW
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ω, and R
L
= 150 Ωto GND, unless otherwise noted (see Figure 74 ).
FREQUENCY RESPONSE vs CAPACITIVE LOAD RECOMMENDED R
S
vs CAPACITIVE LOAD
Figure 14. Figure 15.
OUTPUT SWING vs LOAD RESISTANCE OUTPUT VOLTAGE AND CURRENT LIMITATIONS
Figure 16. Figure 17.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): OPA4830
TYPICAL CHARACTERISTICS: V
S
= ± 5V, Differential Configuration
RL
500W
604W
604W
20W
20W
RG
RG
VO
VI
G =
D
604W
RG
+5V
-5V
1/4
OPA4830
1/4
OPA4830
3
0
-3
-6
-9
-12
-15
Frequency(MHz)
1 10 100 200
NormalizedGain(dB)
G =1
D
G =2
D
G =5
D
G =10
D
V =200mV
O PP
R =500
LW
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
Resistance( )W
100 150 200 250 300 350 400 450 500
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
V =4V
O PP
f=5MHz
-40
-50
-60
-70
-80
-90
-100
-110
Frequency(MHz)
0.1 1 10 100
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
V =4V
O PP
R =500
LW
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
OutputVoltageSwing(V )
PP
1 10
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
R =500W
L
f=5MHz
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
At T
A
= +25 °C, R
F
= 604 Ω(as shown in Figure 18 ), and R
L
= 500 Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
Figure 18. Figure 19.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Figure 20. Figure 21.
DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Figure 22. Figure 23.
12 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
TYPICAL CHARACTERISTICS: V
S
= +5V
6
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
NormalizedGain(dB)
1 10 100 500
V =0.2V
O PP
R =150W
L
G=+1
R =0W
F
G=+2V/V
G=+5V/V
G=+10V/V
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
NormalizedGain(dB)
1 10 100 300
V =0.2V
O PP
R =150W
L
G= 2-
G= 10-
G= 1-
G= 5-
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
Gain(dB)
10 100 300
G= 1V/V-
R =150W
L
V =2V
O PP
V =1V
O PP
V =0.5V
O PP
9
6
3
0
-3
-6
-9
-12
Frequency(MHz)
Gain(dB)
10 100 400
VO=0.5VPP
VO PP
=2V
VO PP
=1V
G=+2V/V
RW
L=150
Time(10ns/div)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
Small-SignalOutputVoltage(V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Large-SignalOutputVoltage(V)
Large-Signal1.5Vto3.5V
RightScale
Small-Signal2.4Vto2.6V
LeftScale
G=+2V/V
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
Time(10ns/div)
Small-SignalOutputVoltage(V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Large-SignalOutputVoltage(V)
Large-Signal1.5Vto3.5V
RightScale
Small-Signal2.4Vto2.6V
LeftScale
G= 1V/V-
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ωto V
S
/2, and input V
CM
= 2.5V, unless otherwise noted (see Figure 72 ).
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Figure 24. Figure 25.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Figure 26. Figure 27.
NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE
Figure 28. Figure 29.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): OPA4830
-55
-60
-65
-70
-75
-80
-85
-90
LoadResistance( )W
HarmonicDistortion(dBc)
100 1k
G=+2V/V
V =2VOPP
f=5MHz
3rd-Harmonic
2nd-Harmonic
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
Frequency(MHz)
HarmonicDistortion(dBc)
0.1 1 10
3rd-Harmonic
R =150W
L
2nd-Harmonic
R =150W
L
2nd-Harmonic
R =500W
L
3rd-Harmonic
R =500W
L
G=+2V/V
V =2V
O PP
-55
-60
-65
-70
-75
-80
-85
-90
Gain(V/V)
HarmonicDistortion(dBc)
1 10
R =500W
L
V =2V
O PP
f=5MHz
3rd-Harmonic
2nd-Harmonic
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
OutputVoltageSwing(V )
PP
HarmonicDistortion(dBc)
0.1 1 10
2nd-Harmonic
3rd-Harmonic
G=+2V/V
R =500W
L
f=5MHz
InputLimited
-50
-55
-60
-65
-70
-75
-80
Gain(V/V)
HarmonicDistortion(dBc)
1 10
R =500W
L
V =2V
O PP
f=5MHz
3rd-Harmonic
2nd-Harmonic
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
Single-ToneLoadPower(dBm)
3rd-OrderSpuriousLevel(dBc)
10MHz
5MHz
20MHz
750W
1/4
OPA4830
PI
PO
50W
500W
750W
-26 -23 -20 -17 -14 -11 -8-5-2
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V (continued)At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ωto V
S
/2, and input V
CM
= 2.5V, unless otherwise noted (see Figure 72 ).
HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY
Figure 30. Figure 31.
HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs NONINVERTING GAIN
Figure 32. Figure 33.
HARMONIC DISTORTION vs INVERTING GAIN TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
Figure 34. Figure 35.
14 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
100
10
1
0.1
0.01
Frequency(Hz)
1k 10k 100k 1M 10M 100M
OutputImpedance( )W
100
10
1
Frequency(Hz)
10 100 1k 10k 100k 1M 10M
VoltageNoise(nV/ )ÖHz
CurrentNoise(pA/ )ÖHz
VoltageNoise
(9.2nV/ )
ÖHz
CurrentNoise
(3.5pA/ )ÖHz
130
120
110
100
90
80
70
60
50
40
30
20
10
CapacitiveLoad(pF)
R ( )
W
S
1 10 100 1k
0.1dBPeakingTargeted
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
AmbientTemperature(10 C/div)°
-50 0 50 110
VoltageRange(V)
MostPositiveOutputVoltage
MostPositiveInputVoltage
LeastPositiveOutputVoltage
LeastPositiveInputVoltage
R =150W
L
80
70
60
50
40
30
20
10
0
-10
-20
Frequency(Hz)
Open-LoopGain(dB)
Open-LoopPhase(dB)
100 1k 10k 100k 1M 10M 100M 1G
20log(A )
OL
Ð(A )
OL
0
20
40
60
80
100
120
140
160
180
200
-
-
-
-
-
-
-
-
-
-
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: V
S
= +5V (continued)At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ωto V
S
/2, and input V
CM
= 2.5V, unless otherwise noted (see Figure 72 ).
INPUT VOLTAGE AND CURRENT NOISE DENSITY CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
Figure 36. Figure 37.
RECOMMENDED R
S
vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD
Figure 38. Figure 39.
OPEN-LOOP GAIN AND PHASE VOLTAGE RANGES vs TEMPERATURE
Figure 40. Figure 41.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): OPA4830
4
3
2
1
0
-1
-2
-3
-4
AmbientTemperature( C)°
InputOffsetVoltage(mV)
8
6
4
2
0
-2
-4
-6
-8
InputBiasandOffsetCurrent( A)m
-50 -25 0 25 50 75 100 125
InputBiasCurrent(I )
B
10 InputOffsetCurrent(I )´OS
InputOffsetVoltage(V )
OS
100
95
90
85
80
75
70
65
60
AmbientTemperature( C)°
OutputCurrent(mA)
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
SupplyCurrent(mA)
-50 -25 0 25 50 75 100 125
OutputCurrent,Sinking
QuiescentCurrent
OutputCurrent,Sourcing
90
80
70
60
50
40
30
20
10
0
Frequency(Hz)
Common-ModeRejectionRatio(dB)
Power-SupplyRejectionRatio(dB)
1k 10k 100k 1M 10M 100M
CMRR
PSRR
-30
-40
-50
-60
-70
-80
-90
Frequency(MHz)
Crosstalk(dB)
1 10 100
Input-Referred
AllHostileCrosstalk
1V Output,3Channels
PP
Channel-to-ChannelCrosstalk
1V Output,1Channel
PP
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V (continued)At T
A
= +25 °C, G = +2V/V, R
F
= 750 Ωto V
S
/2, and input V
CM
= 2.5V, unless otherwise noted (see Figure 72 ).
TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
Figure 42. Figure 43.
CMRR AND PSRR vs FREQUENCY OUTPUT SWING vs LOAD RESISTANCE
Figure 44. Figure 45.
CROSSTALK vs FREQUENCY
Figure 46.
16 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
TYPICAL CHARACTERISTICS: V
S
= +5V, Differential Configuration
RL
604W
604W
RG
VO
VI
G =
D
604W
RG
+5V
1.2kW
1.2kW0.1 Fm
1/4
OPA4830
1/4
OPA4830
RG
2.5V
2.5V
3
0
-3
-6
-9
-12
-15
Frequency(MHz)
1 10 100 200
NormalizedGain(dB)
G =1
D
G =2
D
G =5
D
G =10
D
V =200mV
O PP
R =500
LW
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
Resistance( )W
100 150 200 250 300 350 400 450 500
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
VO PP
=4V
f=5MHz
-30
-40
-50
-60
-70
-80
-90
-100
-110
Frequency(MHz)
1 10 100
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
VO PP
=4V
RW
L=500
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
OutputVoltageSwing(V )
PP
1 10
HarmonicDistrtion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
R =500W
L
f=5MHz
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
At T
A
= +25 °C, R
F
= 604 Ω, and R
L
= 500 Ωdifferential (as shown in Figure 47 ), unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
Figure 47. Figure 48.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Figure 49. Figure 50.
DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Figure 51. Figure 52.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): OPA4830
TYPICAL CHARACTERISTICS: V
S
= +3V
6
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
NormalizedGain(dB)
1 10 100 400
R =150W
L
V =0.2V
O PP
G=+1V/V
R =0W
F
G=+2V/V
G=+5V/V
G=+10V/V
6
3
0
-3
-6
-9
-12
-15
-18
NormalizedGain(dB)
Frequency(MHz)
1 10 100 300
G= 10-
G= 5-
G= 2-
G= 1-
R =150W
L
V =0.2V
O PP
9
6
3
0
-3
-6
-9
-12
Frequency(MHz)
Gain(dB)
10 100 300
G=+2V/V
R =150W
LV =1.5V
O PP
V =1V
O PP
V =0.5V
O PP
3
0
-3
-6
-9
-12
-15
-18
Frequency(MHz)
Gain(dB)
10 100 300
G= 1V/V-
R =150W
L
V =1V
O PP
V =0.5V
O PP
V =1.5V
O PP
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
Time(10ns/div)
Small-SignalOutputVoltage(V)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
Large-SignalOutputVoltage(V)
Large-Signal0.5Vto1.5V
RightScale
Small-Signal
0.95Vto1.05V
LeftScale
G=+2V/V
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
Time(10ns/div)
Small-SignalOutputVoltage(V)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
Large-SignalOutputVoltage(V)
Large-Signal0.5Vto1.5V
RightScale
Small-Signal0.95Vto1.05V
LeftScale
G= 1V/V-
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
At T
A
= +25 °C, G = +2V/V, and R
L
= 150 Ωto V
S
/3, unless otherwise noted (see Figure 73 ).
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
Figure 53. Figure 54.
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
Figure 55. Figure 56.
NONINVERTING PULSE RESPONSE INVERTING PULSE RESPONSE
Figure 57. Figure 58.
18 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
-50
-55
-60
-65
-70
-75
-80
-85
Resistance( )W
HarmonicDistortion(dBc)
100 1k
G=+2V/V
V =1V
f=5MHz
O PP
3rd-Harmonic
2nd-Harmonic
OutputVoltageSwing(V )
PP
0.1 1 10
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
NormalizedGain(dB)
2nd-Harmonic
3rd-Harmonic
G=+2V/V
R =500
f=5MHz
W
L
InputLimited
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
Frequency(MHz)
HarmonicDistortion(dBc)
0.1 1 10
2nd-Harmonic
R =150
LW
2nd-Harmonic
R =500
LW
3rd-Harmonic
R =150
LW
3rd-Harmonic
R =500
LW
G=+2V/V
V =1V
O PP
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
Single-ToneLoadPower(dBm)
3rd-OrderSpuriousLevel(dBc)
10MHz
5MHz
20MHz
-26 -23 -20 -17 -14 -11 -8
750W
1/4
OPA4830
PI
PO
50W
500W
750W
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
TYPICAL CHARACTERISTICS: V
S
= +3V (continued)At T
A
= +25 °C, G = +2V/V, and R
L
= 150 Ωto V
S
/3, unless otherwise noted (see Figure 73 ).
HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs OUTPUT VOLTAGE
Figure 59. Figure 60.
HARMONIC DISTORTION vs FREQUENCY TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
Figure 61. Figure 62.
RECOMMENDED R
S
vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD
Figure 63. Figure 64.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): OPA4830
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
LoadResistance( )W
OutputVoltage(V)
10 100 1k
G=+5V/V
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +3V (continued)At T
A
= +25 °C, G = +2V/V, and R
L
= 150 Ωto V
S
/3, unless otherwise noted (see Figure 73 ).
OUTPUT SWING vs LOAD RESISTANCE
Figure 65.
20 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
TYPICAL CHARACTERISTICS: V
S
= +3V, Differential Configuration
RL
604W
604W
RD
VO
VI
G =
D604W
RG
+3V
2kW
1kW0.1 Fm
1/4
OPA4830
1/4
OPA4830
RD
1V
1V
3
0
-3
-6
-9
-12
-15
Frequency(MHz)
1 10 100 200
NormalizedGain(dB)
G =1
D
G =2
D
G =5
D
G =10
D
V =200mV
O PP
R =500
LW
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
Resistance( )W
100 150 200 250 300 350 400 450 500
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
V =4V
f=5MHz
O PP
-35
-45
-55
-65
-75
-85
-95
-105
-115
Frequency(MHz)
0.1 1 10 100
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
O PP
L
V =2V
R =500W
-75
-80
-85
-90
-95
-100
OutputVoltageSwing(V )
PP
0.50 0.75 1.00 1.25 1.50 1.75 2.00
HarmonicDistortion(dBc)
3rd-Harmonic
2nd-Harmonic
G =2
D
L
R =500
f=5MHz
W
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
At T
A
= +25 °C, R
F
= 604 Ω, and R
L
= 500 Ωdifferential (as shown in Figure 66 ), unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
Figure 66. Figure 67.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
Figure 68. Figure 69.
DIFFERENTIAL DISTORTION vs FREQUENCY DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
Figure 70. Figure 71.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): OPA4830
APPLICATION INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
1/4
OPA4830
V =+3V
S
VOUT
53.6W
VIN
2.26kW
1.13kW
RL
150W
+VS
3
6.8 Fm
+
0.1 Fm
0.1 Fm
RF
750W
RG
750W
+1V
+V /3
S
1/4
OPA4830
V =+5V
S
VOUT
53.6W
VIN
1.50kW
+V /2
S
1.50kW
RL
150W
+VS
2
6.8 Fm
+
0.1 Fm
0.1 Fm
RF
750W
RG
750W
2.5V
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
Figure 73 shows the ac-coupled, gain of +2V/Vconfiguration used for the +3V ElectricalOPERATION
Characteristics and Typical Characteristics . For testThe OPA4830 is a unity-gain stable, very high-speed
purposes, the input impedance is set to 50 Ωwith avoltage-feedback op amp designed for single-supply
resistor to ground. Voltage swings reported in theoperation (+3V to +10V). The input stage supports
Electrical Characteristics are taken directly at theinput voltages below ground and to within 1.7V of the
input and output pins. For the circuit of Figure 73 , thepositive supply. The complementary common-emitter
total effective load on the output at high frequenciesoutput stage provides an output swing to within 25mV
is 150 Ω|| 1500 Ω. The 1.13k Ωand 2.26k Ωresistorsof ground and the positive supply. The OPA4830 is
at the noninverting input provide the common-modecompensated to provide stable operation with a wide
bias voltage. The parallel combination equals the dcrange of resistive loads.
resistance at the inverting input (R
F
), reducing the dcoutput offset as a result of input bias current.Figure 72 shows the ac-coupled, gain of +2V/Vconfiguration used for the +5V ElectricalCharacteristics and Typical Characteristics . For testpurposes, the input impedance is set to 50 Ωwith aresistor to ground. Voltage swings reported in theElectrical Characteristics are taken directly at theinput and output pins. For the circuit of Figure 72 , thetotal effective load on the output at high frequenciesis 150 Ω|| 1500 Ω. The 1.5k Ωresistors at thenoninverting input provide the common-mode biasvoltage. This parallel combination equals the dcresistance at the inverting input (R
F
), reducing the dcoutput offset because of input bias current.
Figure 73. AC-Coupled, G = +2V/V, +3VSingle-Supply Specification and Test Circuit
Figure 72. AC-Coupled, G = +2V/V, +5VSingle-Supply Specification and Test Circuit
22 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
DC LEVEL-SHIFTING
NG=G+V /V
R =R /G
R =R /(NG G)
R =R /(NG 1)
OUT S
1 4
2
3
4
4
-
-
(1)
NG=1+R /R
V =(G)V +(NG G)V
4 3
OUT IN S
-
(2)
1/4
OPA4830
+VS
VOUT
VIN
R3
R2
R1
R4
1/4
OPA4830
+5V
-5V
VO
50W
VIN
RF
750W
348W
50 SourceW
150W
RG
750W
6.8 Fm
+
6.8 Fm
+0.1 Fm
0.1 Fm
0.01 Fm
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
Figure 74 illustrates the dc-coupled, gain of +2V/V,dual power-supply circuit configuration used as the
Figure 75 shows a DC-coupled noninverting amplifierbasis of the ± 5V Electrical Characteristics and Typical
that level-shifts the input up to accommodate theCharacteristics . For test purposes, the input
desired output voltage range. Given the desiredimpedance is set to 50 Ωwith a resistor to ground and
signal gain (G), and the amount V
OUT
needs to bethe output impedance is set to 150 Ωwith a series
shifted up ( ΔV
OUT
) when V
IN
is at the center of itsoutput resistor. Voltage swings reported in the
range, Equation 1 and Equation 2 give the resistorspecifications are taken directly at the input and
values that produce the desired performance.output pins. For the circuit of Figure 74 , the total
Assume that R
4
is between 200 Ωand 1.5k Ω.effective load is 150 Ω1.5k Ω. Two optionalcomponents are included in Figure 74 . An additionalresistor (348 Ω) is included in series with thenoninverting input. Combined with the 25 Ωdc sourceresistance looking back towards the signal generator,this gives an input bias current cancelling resistancethat matches the 375 Ωsource resistance seen at the
where:inverting input (see the DC Accuracy and OffsetControl section). In addition to the usual power-supplydecoupling capacitors to ground, a 0.01 µF capacitoris included between the two power-supply pins. In
Make sure that V
IN
and V
OUT
stay within the specifiedpractical printed circuit board layouts, this optional
input and output voltage ranges.capacitor typically improves the 2nd-harmonicdistortion performance by 3dB to 6dB.
Figure 75. DC Level-Shifting
The circuit on the front page is a good example ofthis type of application. It was designed to take V
INbetween 0V and 0.5V and produce V
OUT
between 1VFigure 74. DC-Coupled, G = +2V/V, Bipolar Supply
and 2V when using a +3V supply. This output meansSpecification and Test Circuit
G = 2.00, and ΔV
OUT
= 1.50V – G ×0.25V = 1.00V.Plugging these values into Equation 1 and Equation 2(with R
4
= 750 Ω) gives: NG = 2.33, R
1
= 375 Ω, R
2
=2.25k Ω, and R
3
= 563 Ω. The resistors were changedto the nearest standard values for the front pagecircuit .
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): OPA4830
1/4
OPA4830
325W528W
78.7W
650W
+5V
845W
1.87kW
VO
22 Fm
47 Fm75W
VideoDAC
75 LoadW
AC-COUPLED OUTPUT VIDEO LINE DRIVER
3
0
-3
-6
-9
-12
-15
-18
-21
Frequency(Hz)
NormalizedGain(dB)
1 10 102103104105106107108109
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
Figure 76. Video Line Driver with SAG Correction
output with a gain of approximately – 20dB, so goodsupply decoupling is recommended on thepower-supply pin. Figure 77 shows the frequencyLow-power and low-cost video line drivers often
response for the circuit of Figure 76 . This plot showsbuffer digital-to-analog converter (DAC) outputs with
the 8Hz low-frequency high-pass pole and a high-enda gain of 2V/V into a doubly-terminated line. Those
cutoff at approximately 100MHz.interfaces typically require a dc blocking capacitor.For a simple solution, that interface often has used avery large value blocking capacitor (220 µF) to limittilt, or SAG, across the frames. One approach tocreating a very low high-pass pole location usingmuch lower capacitor values is shown in Figure 76 .This circuit gives a voltage gain of 2 at the output pinwith a high-pass pole at 8Hz. Given the 150 Ωload, asimple blocking capacitor approach would require a133 µF value. The two much lower valued capacitorsgive this same low-pass pole using this simple SAGcorrection circuit of Figure 76 .
The input is shifted slightly positive in Figure 76 usingthe voltage divider from the positive supply. Thisconfiguration gives about a 200mV input dc offsetthat shows up at the output pin as a 400mV dc offsetwhen the DAC output is at zero current during the
Figure 77. Video Line Driver Response to Matchedsync tip portion of the video signal. This offset acts to
Loadhold the output in its linear operating region. Thiscircuit then passes on any power-supply noise to the
24 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
NONINVERTING AMPLIFIER WITH REDUCED
SINGLE-SUPPLY ACTIVE FILTER
1/4
OPA4830 VOUT
+5V
VIN
RG
RT
RF
RC
RF
RG
G =1+
1
(3)
RC
G =1+
2
RT+RF
G1
(4)
NG=G G´
1 2
(5)
1/4
OPA4830
1.5kW
1.87kW
500W
+5V
1.87kW
4VI
VI
150pF
0.1 Fm
1MHz,2nd-Order
ButterworthFilter
100pF
432W137W
0.1 Fm
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
circuit gives a noise gain of 2V/V, so the response isPEAKING similar to the characteristics plots with G = +2V/V.Decreasing R
C
to 20.0 Ωincreases the noise gain toFigure 78 shows a noninverting amplifier that reduces
3V/V, which typically gives a flat frequency response,peaking at low gains. The resistor RC compensates
but with less bandwidth.the OPA4830 to have higher noise gain (NG), whichreduces the ac response peaking (typically 5dB at G The circuit in Figure 72 can be redesigned to have= +1V/V without RC) without changing the dc gain. less peaking by increasing the noise gain to 3. ThisV
IN
needs to be a low-impedance source, such as an increase is accomplished by adding R
C
= 2.55k Ωop amp. The resistor values are low in order to across the op amp inputs.reduce noise. Using both R
T
and R
F
helps minimizethe impact of parasitic impedances.
The OPA4830, while operating on a single +3V or+5V supply, lends itself well to high-frequency activefilter designs. Again, the key additional requirement isto establish the dc operating point of the signal nearthe supply midpoint for highest dynamic range.Figure 79 shows an example design of a 1MHzlow-pass Butterworth filter using the Sallen-Keytopology.
Both the input signal and the gain setting resistor areac-coupled using 0.1 µF blocking capacitors (actuallygiving bandpass response with the low-frequencypole set to 32kHz for the component values shown).Figure 78. Compensated Noninverting Amplifier
As discussed for Figure 72 , this configuration allowsthe midpoint bias formed by the two 1.87k ΩresistorsThe noise gain can be calculated as shown in
to appear at both the input and output pins. TheEquation 3 ,Equation 4 , and Equation 5 :
midband signal gain is set to +4 (12dB) in this case.The capacitor to ground on the noninverting input isintentionally set larger to dominate input parasiticterms. At a gain of +4, the OPA4830 on a singlesupply shows 30MHz small- and large-signalbandwidth. The resistor values have been slightlyadjusted to account for this limited bandwidth in theamplifier stage. Tests of this circuit show a precise1MHz, – 3dB point with a maximally-flat passband(above the 32kHz ac-coupling corner), and aA unity-gain buffer can be designed by selecting R
T
=
maximum stop band attenuation of 36dB at theR
F
= 20.0 Ωand R
C
= 40.2 Ω(do not use R
G
). This
amplifier – 3dB bandwidth of 30MHz.
Figure 79. Single-Supply, High-Frequency Active Filter
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): OPA4830
DIFFERENTIAL INTERFACE APPLICATIONS
VO
VI
=A =1+2 ´
D
RF
RG
(6)
RF
750W
RF
750W
RG
RG
1/4
OPA4830
+VCC
-VCC
VCM
VCM
VO
1/4
OPA4830
VI
RF
750W
RF
750W
1/4
OPA4830
+VCC
-VCC
RGVO
1/4
OPA4830
VI
VO
VI
=-RF
RG
(7)
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
Various combinations of single-supply or ac-coupledgains can also be delivered using the basic circuit ofDual and quad op amps are particularly suitable to
Figure 80 . Common-mode bias voltages on the twodifferential input to differential output applications.
noninverting inputs pass on to the output with a gainTypically, these op amps fall into either ADC input
of 1V/V because an equal dc voltage at eachinterface or line driver applications. Two basic
inverting node creates no current through R
G
, givingapproaches to differential I/O are noninverting or
that voltage a common-mode gain of 1 to the output.inverting configurations. Because the output isdifferential, the signal polarity is somewhat Figure 81 shows a differential I/O stage configured asmeaningless — the noninverting and inverting an inverting amplifier. In this case, the gain resistorsterminology applies here to where the input is brought (R
G
) become the input resistance for the source. Thisinto the OPA4830. Each has its advantages and configuration provides a better noise performancedisadvantages. Figure 80 shows a basic starting point than the noninverting configuration, but does limit thefor noninverting differential I/O applications. flexibility in setting the input impedance separatelyfrom the gain.This approach provides for a source terminationimpedance that is independent of the signal gain. Forinstance, simple differential filters may be included inthe signal path right up to the noninverting inputswithout interacting with the amplifier gain. Thedifferential signal gain for the circuit of Figure 80 isshown in Equation 6 :
Figure 80 shows the recommended value of 750 Ω.However, the gain may be adjusted using just the R
Gresistor.
Figure 81. Inverting Differential I/O Amplifier
The two noninverting inputs provide an easycommon-mode control input. This control isparticularly useful if the source is ac-coupled througheither blocking caps or a transformer. In either case,the common-mode input voltages on the twononinverting inputs again have a gain of 1 to theoutput pins, giving an easy common-mode control forsingle-supply operation. The input resistors may beadjusted to the desired gain but also change the inputimpedance as well. The differential gain for this circuitis shown in Equation 7 :
Figure 80. Noninverting Differential I/O Amplifier
26 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
DC-COUPLED SINGLE-TO-DIFFERENTIAL
402W
250W
402W
1/4
OPA4830
+5V
-5V
VCM
1.5V
1/4
OPA4830
1/4
OPA4830
50W750W750W402W
1/4
OPA4830
+V =V +V (1+)
OUT CM I
402W
RG
-V =V -V (1+)
OUT CM I
402W
RG
750W
750W
0.1 Fm
RI
200W
RG
VCM
2
VI
200W
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
common-mode voltage, V
CM
, is cut in half and appliedCONVERSION to the noninverting input of the second stage. Thesignal path in this stage sees a gain of – 1V/V whileThe previous differential output circuits were set up to
this (1/2 ×V
CM
) voltage sees a gain of +2V/V. Thereceive a differential input as well as provide a
output of this second stage is then the originaldifferential output. Figure 82 illustrates one way to
common-mode voltage plus the inverted signal fromprovide a single-to-differential conversion, with dc
the output of the first stage. The 2nd stage outputcoupling, and independent output common-mode
appears directly at the output of the noninverting finalcontrol using a quad op amp.
stage. The inverting node of the inverting outputstage is also biased to the common-mode voltage,The circuit of Figure 82 provides several useful
equal to the common-mode voltage appearing at thefeatures for isolating the input signal from the final
output of the second stage, creating no current flowoutputs. Using the first amplifier as a simple
and placing the desired V
CM
at the output of thisnoninverting stage gives an independent adjustment
stage as well.on R
I
(to set the source loading) while the gain canbe easily adjusting in this stage using the R
G
resistor.The next stage allows a separate outputcommon-mode level to be set up. The desired output
Figure 82. Wideband, DC-Coupled, Single-to-Differential Conversion
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): OPA4830
1/4
OPA4830
+5V
-5V
1/4
OPA4830
294W77W
100pF
294W77W
100pF
250W
250W
VO
VI
1/4
OPA4830
1/4
OPA4830
121W161W
100pF
500W
100pF
G =2, =2w p 10MHz,Q=0.54
D O
G =2, =2w p 10MHz,Q=1.31
D O
121W161W
100pF
250W
250W
V =4V/V/V
O I
f =10MHz
-3dB
P =225mW
D
500W
100pF
100pF
100pF
LOW-POWER, DIFFERENTIAL I/O,
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
Figure 83. Low-Power, Differential I/O, 4th-Order Butterworth Active Filter
4th-ORDER ACTIVE FILTERThe OPA4830 can give a very capable gain block foractive filters. The quad design lends itself very well todifferential active filters. Where the filter topology islooking for a simple gain function to implement thefilter, the noninverting configuration is preferred toisolate the filter elements from the gain elements inthe design. See Figure 83 for an example of a10MHz, 4th-order Butterworth, low-pass Sallen-Keyfilter. The design places the higher Q stage first toallow the lower Q 2nd stage to roll off the peakednoise of the first stage. The resistor values have beenadjusted slightly to account for the amplifier groupdelay.
Figure 84. Differential 4th-Order, 10MHzWhile this circuit is bipolar, using ± 5V supplies, it can
Butterworth Filtereasily be adapted to single-supply operation. Thisconfiguration adds two real zeroes in the response,transforming this circuit into a bandpass. Thefrequency response for the filter of Figure 83 isillustrated in Figure 84 .
28 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
DUAL-CHANNEL, DIFFERENTIAL ADC
VIDEO LINE DRIVING
+5V
1/4
OPA4830
1/4
OPA4830
800W
800W
RS
RS
16.7dB
NoiseFigure
Gain=8V/V
18dB
200W
200W
1kW
1kW
0.1 Fm
VCM
CL
500W
500W
VCM
DualADC
1of2
Channels
1:2
50W
Source
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
signal at the transformer input. The two pull-downDRIVER resistors do show a signal path ground and should beconnected at the same physical point to ground, inWhere a low-noise, single-supply, interface to a
order to eliminate imbalanced ground return currentsdifferential input +5V ADC is required, the circuit of
from degrading 2nd-harmonic distortion.Figure 85 can provide a high dynamic range, mediumgain interface for dual high-performance ADCs. Thecircuit of Figure 85 uses two amplifiers in thedifferential inverting configuration. The common-mode
Most video distribution systems are designed withvoltage is set on the noninverting inputs to the supply
75 Ωseries resistors to drive a matched 75 Ωcable. Inmidscale. In this example, the input signal is coupled
order to deliver a net gain of 1 to the 75 Ωmatchedin through a 1:2 transformer. This design provides
load, the amplifier is typically set up for a voltage gainboth signal gain, single to differential conversion, and
of +2V/V, compensating for the 6dB attenuation of thea reduction in noise figure. To show a 50 Ωinput
voltage divider formed by the series and shunt 75 Ωimpedance at the input to the transformer, two 200 Ω
resistors at either end of the cable.resistors are required on the transformer secondary.
The circuit of Figure 72 applies to this requirement ifThese two resistors are also the amplifier gain
all references to 50 Ωresistors are replaced by 75 Ωelements. Because the same dc voltage appears on
values. Often, the amplifier gain is further increasedboth inverting nodes in the circuit of Figure 85 , no dc
to 2.2, which recovers the additional dc loss of acurrent will flow through the transformer, giving a dc
typical long cable run. This change would require thegain of 1 to the output for this common-mode voltage,
gain resistor (R
G
) in Figure 72 to be reduced fromV
CM
.
750 Ωto 625 Ω. In either case, both the gain flatnessThe circuit of Figure 85 is particularly suitable for a
and the differential gain/phase performance of themoderate resolution dual ADC used as I/Q samplers.
OPA4830 provide exceptional results in videoThe optional 500 Ωresistors to ground on each
distribution applications. Differential gain and phaseamplifier output can be added to improve the 2nd-
measure the change in overall small-signal gain andand 3rd-harmonic distortion by >15dB if higher
phase for the color sub-carrier frequency (3.58MHz indynamic range is required.
NTSC systems) versus changes in the large-signaloutput level (which represents luminance informationThe 5mA added output stage current significantly
in a composite video signal). The OPA4830, with theimproves linearity if that is required. The measured
typical 150 Ωload of a single matched video cable,2nd-harmonic distortion is consistently lower than the
shows less than 0.07%/0.17 °differential gain/phase3rd-harmonics for this balanced differential design. It
errors over the standard luminance range for ais particularly helpful for this low-power design if there
positive video (negative sync) signal. Similarare no grounds in the signal path after the low-level
performance would be observed for multiple videosignals (see Figure 86 ).
Figure 85. Single-Supply Differential ADC Driver (1 of 2 channels)
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): OPA4830
1/4
OPA4830 VOUT
750W625W
Video
Input
75W
75W
75 TransmissionLineW
VOUT
75W
75W
VOUT
75W
75W
75W
Highoutputcurrentdrivecapabilityallowsthree
back-terminated75 transmissionlinestobesimultaneouslydriven.W
4-CHANNEL DAC TRANSIMPEDANCE
1/4
OPA4830
High-Speed
DAC
V =I R
O D F
RF
CF
GBP GainBandwidth®
Product(Hz)fortheOPA4830.
CD
ID
ID
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
Figure 86. Video Distribution Amplifier
AMPLIFIER
High-frequency Digital-to-Analog Converters (DACs)require a low-distortion output amplifier to retain theSFDR performance into real-world loads. Figure 87illustrates a single-ended output driveimplementation. In this circuit, only one side of thecomplementary output drive signal is used. Thediagram shows the signal output current connectedinto the virtual ground-summing junction of theOPA4830, which is set up as a transimpedance stageor I-V converter. The unused current output of theDAC is connected to ground. If the DAC requires itsoutputs to be terminated to a compliance voltageother than ground for operation, then the appropriatevoltage level may be applied to the noninverting inputof the OPA4830.
Figure 87. Wideband, Low-Distortion DACTransimpedance Amplifier
30 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
GBP
4 R CpF D
=
1
2 R CpF F
GBP
2 R CpF D
=
f-3dB
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
MACROMODELS AND APPLICATIONS
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
The dc gain for this circuit is equal to R
F
. At highfrequencies, the DAC output capacitance (C
D
)produces a zero in the noise gain for the OPA4830that may cause peaking in the closed-loop frequencyresponse. C
F
is added across R
F
to compensate for
Because the OPA4830 is a unity-gain stable,this noise-gain peaking. To achieve a flat
voltage-feedback op amp, a wide range of resistortransimpedance frequency response, this pole in the
values may be used for the feedback and gain settingfeedback network should be set to:
resistors. The primary limits on these values are setby dynamic range (noise and distortion) and parasiticcapacitance considerations. For a noninvertingunity-gain follower application, the feedbackwhich gives a corner frequency f
– 3dB
of connection should be made with a direct short.approximately:
Below 200 Ω, the feedback network presentsadditional output loading that can degrade theharmonic distortion performance of the OPA4830.Above 1k Ω, the typical parasitic capacitance(approximately 0.2pF) across the feedback resistormay cause unintentional band limiting in the amplifierresponse.
A good rule of thumb is to target the parallelA printed circuit board (PCB) is available to assist in
combination of R
F
and R
G
(see Figure 74 ) to be lessthe initial evaluation of circuit performance using the
than about 400 Ω. The combined impedance R
F
|| R
GOPA4830. The fixture is offered free of charge as
interacts with the inverting input capacitance, placingunpopulated PCB, delivered with a user ’ s guide. The
an additional pole in the feedback network, and thussummary information for this fixture is shown in
a zero in the forward response. Assuming a 2pF totalTable 2 .
parasitic on the inverting node, holding R
F
|| R
G
<400 Ωkeeps this pole above 200MHz. By itself, thisTable 2. Demonstration Fixture
constraint implies that the feedback resistor R
F
canincrease to several k Ωat high gains. This increase isLITERATUREPRODUCT PACKAGE ORDERING NUMBER NUMBER
acceptable as long as the pole formed by R
F
and anyOPA4830IPW TSSOP-14 DEM-OPA-TSSOP-4A SBOU017
parasitic capacitance appearing in parallel is kept outof the frequency range of interest.The demonstration fixture can be requested at the
In the inverting configuration, an additional designTexas Instruments web site (www.ti.com ) through the
consideration must be noted. R
G
becomes the inputOPA4830 product folder.
resistor and therefore the load impedance to thedriving source. If impedance matching is desired, R
Gmay be set equal to the required termination value.SUPPORT
However, at low inverting gains, the resultingComputer simulation of circuit performance using
feedback resistor value can present a significant loadSPICE is often a quick way to analyze the
to the amplifier output. For example, an inverting gainperformance of the OPA4830 and its circuit designs.
of 2 with a 50 Ωinput matching resistor (= R
G
) wouldThis approach is particularly true for video and RF
require a 100 Ωfeedback resistor, which wouldamplifier circuits where parasitic capacitance and
contribute to output loading in parallel with theinductance can play a major role on circuit
external load. In such a case, it would be preferableperformance. A SPICE model for the OPA4830 is
to increase both the R
F
and R
G
values, and thenavailable through the TI web page (www.ti.com ). Note
achieve the input matching impedance with a thirdthat this model is the OPA830 model applied to the
resistor to ground (see Figure 88 ). The total inputOPA4830 quad version. The applications department
impedance becomes the parallel combination of R
Gis also available for design assistance. These models
and the additional shunt resistor.predict typical small-signal ac, transient steps, dcperformance, and noise under a wide variety ofoperating conditions. The models include the noiseterms found in the electrical specifications of the datasheet. This model does not attempt to distinguishbetween the package types in their small-signal acperformance.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): OPA4830
BANDWIDTH VS GAIN:
1/4
OPA4830
50 SourceWRF
750W
RG
374W
2RT
1.5kW
RM
57.6W
+5V
2RT
1.5kW
150W
0.1 Fm6.8 Fm
+
0.1 Fm
0.1 Fm
+VS
2
INVERTING AMPLIFIER OPERATION
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
benefits. It also allows the input to be biased at V
S
/2NONINVERTING OPERATION without any headroom issues. The output voltage canbe independently moved to be within the outputVoltage-feedback op amps exhibit decreasing
voltage range with coupling capacitors, or biasclosed-loop bandwidth as the signal gain is
adjustment resistors.increased. In theory, this relationship is described bythe gain bandwidth product (GBP) shown in theElectrical Characteristics . Ideally, dividing GBP by thenoninverting signal gain (also called the noise gain, orNG) predicts the closed-loop bandwidth. In practice,this calculation only holds true when the phasemargin approaches 90 °, as it does in high-gainconfigurations. At low gains (increased feedbackfactors), most amplifiers exhibit a more complexresponse with lower phase margin. The OPA4830 iscompensated to give a slightly peaked response in anoninverting gain of 2V/V (see Figure 74 ). Thiscompensation results in a typical gain of +2V/Vbandwidth of 110MHz, far exceeding that predictedby dividing the 110MHz GBP by 2V/V. Increasing thegain causes the phase margin to approach 90 °andthe bandwidth to more closely approach the predictedvalue of (GBP/NG). At a gain of +10V/V, the 11MHzbandwidth illustrated in the Electrical Characteristics
Figure 88. AC-Coupled, G = – 2V/V Example Circuitagrees with that predicted using the simple formulaand the typical GBP of 110MHz.
In the inverting configuration, three key designFrequency response in a gain of +2V/V may be
considerations must be noted. The first considerationmodified to achieve exceptional flatness simply by
is that the gain resistor (R
G
) becomes part of theincreasing the noise gain to 3V/V. One way to do this,
signal channel input impedance. If input impedancewithout affecting the +2V/V signal gain, is to add a
matching is desired (which is beneficial whenever the2.55k Ωresistor across the two inputs (see Figure 78 ).
signal is coupled through a cable, twisted pair, longA similar technique may be used to reduce peaking in
PCB trace, or other transmission line conductor), R
Gunity-gain (voltage follower) applications. For
may be set equal to the required termination valueexample, by using a 750 Ωfeedback resistor along
and R
F
adjusted to give the desired gain. Thiswith a 750 Ωresistor across the two op amp inputs,
approach is the simplest and results in optimumthe voltage follower response is similar to the gain of
bandwidth and noise performance.+2V/V response of Figure 73 . Further reducing thevalue of the resistor across the op amp inputs further
However, at low inverting gains, the resultingdampens the frequency response because of
feedback resistor value can present a significant loadincreased noise gain. The OPA4830 exhibits minimal
to the amplifier output. For an inverting gain of 2,bandwidth reduction going to single-supply (+5V)
setting R
G
to 50 Ωfor input matching eliminates theoperation as compared with ± 5V. This minimal
need for R
M
but requires a 100 Ωfeedback resistor.reduction is because the internal bias control circuitry
This configuration has the interesting advantage ofretains nearly constant quiescent current as the total
the noise gain becoming equal to 2 for a 50 Ωsourcesupply voltage between the supply pins changes.
impedance — the same as the noninverting circuitsconsidered above. The amplifier output now sees the100 Ωfeedback resistor in parallel with the externalload. In general, the feedback resistor should beAll of the familiar op amp application circuits are
limited to the 200 Ωto 1.5k Ωrange. In this case, it isavailable with the OPA4830 to the designer. See
preferable to increase both the R
F
and R
G
values, asFigure 88 for a typical inverting configuration where
shown in Figure 88 , and then achieve the inputthe I/O impedances and signal gain from Figure 72
matching impedance with a third resistor (R
M
) toare retained in an inverting circuit configuration.
ground. The total input impedance becomes theInverting operation is one of the more common
parallel combination of R
G
and R
M
.requirements and offers several performance
32 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
DRIVING CAPACITIVE LOADS
OUTPUT CURRENT AND VOLTAGES
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
The second major consideration, touched on in the To maintain maximum output stage linearity, noprevious paragraph, is that the signal source output short-circuit protection is provided. Thisimpedance becomes part of the noise gain equation absence of protection is not normally a problem,and thus influences the bandwidth. For the example because most applications include a series matchingin Figure 88 , the R
M
value combines in parallel with resistor at the output that limits the internal powerthe external 50 Ωsource impedance (at high dissipation if the output side of this resistor is shortedfrequencies), yielding an effective driving impedance to ground. However, shorting the output pin directly toof 50 Ω|| 57.6 Ω= 26.8 Ω. This impedance is added in the adjacent positive power-supply pin (8-pinseries with R
G
for calculating the noise gain. The packages), in most cases, destroys the amplifier. Ifresulting noise gain is 2.87 for Figure 88 , as opposed additional short-circuit protection is required, considerto only 2 if R
M
could be eliminated as discussed a small series resistor in the power-supply leads. Thisabove. The bandwidth is therefore lower for the gain resistor reduces the available output voltage swingof – 2 circuit of Figure 88 (NG = +2.87) than for the under heavy output loads.gain of +2 circuit of Figure 72 .
The third important consideration in inverting amplifierdesign is setting the bias current cancellation
One of the most demanding and yet very commonresistors on the noninverting input (a parallel
load conditions for an op amp is capacitive loading.combination of R
T
= 750 Ω). If this resistor is set equal
Often, the capacitive load is the input of anto the total dc resistance looking out of the inverting
ADC — including additional external capacitance thatnode, the output dc error (as a result of the input bias
may be recommended to improve ADC linearity. Acurrents) is reduced to (input offset current) times R
F
.
high-speed, high open-loop gain amplifier such as theWith the dc blocking capacitor in series with R
G
, the
OPA4830 can be very susceptible to decreaseddc source impedance looking out of the inverting
stability and closed-loop response peaking when amode is simply R
F
= 750 Ωfor Figure 88 . To reduce
capacitive load is placed directly on the output pin.the additional high-frequency noise introduced by this
When the primary considerations are frequencyresistor and power-supply feed-through, R
T
is
response flatness, pulse response fidelity, and/orbypassed with a capacitor.
distortion, the simplest and most effective solution isto isolate the capacitive load from the feedback loopby inserting a series isolation resistor between theamplifier output and the capacitive load.The OPA4830 provides outstanding output voltagecapability. For the +5V supply, under no-load The Typical Characteristics show the recommendedconditions at +25 °C, the output voltage typically R
S
versus capacitive load and the resulting frequencyswings closer than 90mV to either supply rail. response at the load. Parasitic capacitive loadsgreater than 2pF can begin to degrade theThe minimum specified output voltage and current
performance of the OPA4830. Long PCB traces,specifications over temperature are set by worst-case
unmatched cables, and connections to multiplesimulations at the cold temperature extreme. Only at
devices can easily exceed this value. Alwayscold startup does the output current and voltage
consider this effect carefully, and add thedecrease to the numbers shown in the specification
recommended series resistor as close as possible totables. As the output transistors deliver power, the
the output pin (see the Board Layout Guidelinesjunction temperatures increase, decreasing the V
BE
s
section).(increasing the available output voltage swing), andincreasing the current gains (increasing the available The criterion for setting this R
S
resistor is a maximumoutput current). In steady-state operation, the bandwidth, flat frequency response at the load. For aavailable output voltage and current is always greater gain of +2, the frequency response at the output pinthan that shown in the over-temperature is already slightly peaked without the capacitive load,specifications, because the output stage junction requiring relatively high values of R
S
to flatten thetemperatures are higher than the minimum specified response at the load. Increasing the noise gain alsooperating ambient temperature. reduces the peaking (see Figure 78 ).
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): OPA4830
DISTORTION PERFORMANCE
4kT
RG
RG
RF
RS
1/4
OPA4830
IBI
EO
IBN
4kT=1.6E 20J-
at290 K°
ERS
ENI
4kTRS
4kTRF
NOISE PERFORMANCE
E =
O(E +(I R ) +4kTR )NG +(I R ) +4kTR NG
NI BN S BI FS F
2 2 2 2
E =
NE +(I R ) +4kTR +
NI BN S S
2 2 I R
BI F
NG
2
+4kTRF
NG
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
The OPA4830 provides good distortion performanceinto a 150 Ωload. Relative to alternative solutions, itprovides exceptional performance into lighter loadsand/or operating on a single +3V supply. Generally,until the fundamental signal reaches very highfrequency or power levels, the 2nd-harmonicdominates the distortion with a negligible3rd-harmonic component. Focusing then on the2nd-harmonic, increasing the load impedanceimproves distortion directly. Remember that the totalload includes the feedback network; in thenoninverting configuration (see Figure 74 ) this is sumof R
F
+ R
G
, while in the inverting configuration, onlyR
F
needs to be included in parallel with the actual
Figure 89. Noise Analysis Modelload. Running differential suppresses the2nd-harmonic, as shown in the Differential Typical
The total output spot noise voltage can be computedCharacteristics .
as the square root of the sum of all squared outputnoise voltage contributors. Equation 8 shows thegeneral form for the output noise voltage using theHigh slew rate, unity-gain stable, voltage-feedback op
terms shown in Figure 89 :amps usually achieve their slew rate at the expenseof a higher input noise voltage. The 9.2nV/ √Hz inputvoltage noise for the OPA4830 however, is much
(8)lower than comparable amplifiers. The input-referredvoltage noise and the two input-referred current noiseterms (2.8pA/ √Hz) combine to give low output noise
Dividing this expression by the noise gain [ NG = (1 +under a wide variety of operating conditions.
R
F
/R
G
) ] gives the equivalent input-referred spot noiseFigure 89 shows the op amp noise analysis model
voltage at the noninverting input; this result is shownwith all the noise terms included. In this model, all
in Equation 9 :noise terms are taken to be noise voltage or currentdensity terms in either nV/ √Hz or pA/ √Hz.
(9)
Evaluating these two equations for the circuit andcomponent values shown in Figure 72 gives a totaloutput spot noise voltage of 19.3nV/ √Hz and a totalequivalent input spot noise voltage of 9.65nV/ √Hz.This value is including the noise added by theresistors. This total input-referred spot noise voltageis not much higher than the 9.2nV/ √Hz specificationfor the op amp voltage noise alone.
34 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
DC ACCURACY AND OFFSET CONTROL THERMAL ANALYSIS
(NG=noninvertingsignalgainatdc)
(NG V ) (R I )
= (2 8mV) (375 1.1 A)
= 16.41mV
± ´
W m
OS(MAX) F OS(MAX)
+ ´
± ´ ´ ´
±
(10)
P =5V 19mA+4 5 /(4 (150 ||750 ))=295mWW
D´ ´ ´ W
2
MaximumT =+85 C+(0.295W 95 C/W)=+113 C° ´ °
J°
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
The balanced input stage of a wideband Maximum desired junction temperature sets thevoltage-feedback op amp allows good output dc maximum allowed internal power dissipation, asaccuracy in a wide variety of applications. The described below. In no case should the maximumpower-supply current trim for the OPA4830 gives junction temperature be allowed to exceed +150 °C.even tighter control than comparable products.
Operating junction temperature (T
J
) is given by T
A
+Although the high-speed input stage does require
P
D
× θ
JA
. The total internal power dissipation (P
D
) isrelatively high input bias current (typically 5 µA out of
the sum of quiescent power (P
DQ
) and additionaleach input terminal), the close matching between
power dissipated in the output stage (P
DL
) to deliverthem may be used to reduce the output dc error
load power. Quiescent power is simply the specifiedcaused by this current. This reduction is achieved by
no-load supply current times the total supply voltagematching the dc source resistances appearing at the
across the part. P
DL
depends on the required outputtwo inputs. Evaluating the configuration of Figure 74
signal and load; though, for resistive loads connected(which has matched dc input resistances), using
to mid-supply (V
S
/2), P
DL
is at a maximum when theworst-case +25 °C input offset voltage and current
output is fixed at a voltage equal to V
S
/4 or 3V
S
/4.specifications, gives a worst-case output offset
Under this condition, P
DL
= V
S
2
/(16 ×R
L
), where R
Lvoltage equal to Equation 10 :
includes feedback network loading.
Note that it is the power in the output stage, and notinto the load, that determines internal powerdissipation.
As a worst-case example, compute the maximum T
Jusing an OPA4830 (TSSOP-14 package) in the circuitof Figure 72 operating at the maximum specifiedA fine-scale output offset null, or dc operating point
ambient temperature of +85 °C and driving a 150 Ωadjustment, is often required. Numerous techniques
load at mid-supply.are available for introducing dc offset control into anop amp circuit. Most of these techniques are basedon adding a dc current through the feedback resistor.In selecting an offset trim method, one keyconsideration is the impact on the desired signal pathfrequency response. If the signal path is intended to
Although this value is still well below the specifiedbe noninverting, the offset control is best applied as
maximum junction temperature, system reliabilityan inverting summing signal to avoid interaction with
considerations may require lower ensured junctionthe signal source. If the signal path is intended to be
temperatures. The highest possible internalinverting, applying the offset control to the
dissipation occurs if the load requires current to benoninverting input may be considered. Bring the dc
forced into the output at high output voltages oroffsetting current into the inverting input node through
sourced from the output at low output voltages. Thisresistor values that are much larger than the signal
puts a high current through a large internal voltagepath resistors. This configuration ensures that the
drop in the output transistors.adjustment circuit has minimal effect on the loop gainand therefore the frequency response.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): OPA4830
BOARD LAYOUT GUIDELINES
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
shunt with the resistor. For resistor values > 1.5k Ω,this parasitic capacitance can add a pole and/or zeroAchieving optimum performance with a
below 500MHz that can effect circuit operation. Keephigh-frequency amplifier like the OPA4830 requires
resistor values as low as possible consistent withcareful attention to board layout parasitics and
load driving considerations. The 750 Ωfeedback usedexternal component types. Recommendations that
in the Typical Characteristics is a good starting pointoptimize performance include:
for design.a) Minimize parasitic capacitance to any ac ground
d) Connections to other wideband devices on thefor all of the signal I/O pins. Parasitic capacitance on
board may be made with short direct traces orthe output and inverting input pins can cause
through onboard transmission lines. For shortinstability: on the noninverting input, it can react with
connections, consider the trace and the input to thethe source impedance to cause unintentional
next device as a lumped capacitive load. Relativelybandlimiting. To reduce unwanted capacitance, a
wide traces (50mils to 100mils) should be used,window around the signal I/O pins should be opened
preferably with ground and power planes opened upin all of the ground and power planes around those
around them. Estimate the total capacitive load andpins. Otherwise, ground and power planes should be
set R
S
from the typical characteristic curveunbroken elsewhere on the board.
Recommended R
S
vs Capacitive Load (Figure 15 ,Figure 38 , or Figure 63 ). Low parasitic capacitiveb) Minimize the distance ( < 0.25 ” ) from the
loads (< 5pF) may not need an R
S
because thepower-supply pins to high-frequency 0.1 µF
OPA4830 is nominally compensated to operate with adecoupling capacitors. At the device pins, the ground
2pF parasitic load. Higher parasitic capacitive loadsand power-plane layout should not be in close
without an R
S
are allowed as the signal gainproximity to the signal I/O pins. Avoid narrow power
increases (increasing the unloaded phase margin). Ifand ground traces to minimize inductance between
a long trace is required, and the 6dB signal lossthe pins and the decoupling capacitors. Each
intrinsic to a doubly-terminated transmission line ispower-supply connection should always be
acceptable, implement a matched impedancedecoupled with one of these capacitors. An optional
transmission line using microstrip or striplinesupply decoupling capacitor (0.1 µF) across the two
techniques (consult an ECL design handbook forpower supplies (for bipolar operation) improves
microstrip and stripline layout techniques). A 50 Ω2nd-harmonic distortion performance. Larger (2.2 µF
environment is normally not necessary onboard, andto 6.8 µF) decoupling capacitors, effective at lower
in fact, a higher impedance environment improvesfrequency, should also be used on the main supply
distortion as shown in the distortion versus load plots.pins. These may be placed somewhat farther from
With a characteristic board trace impedance definedthe device and may be shared among several
(based on board material and trace dimensions), adevices in the same area of the PCB.
matching series resistor into the trace from the outputc) Careful selection and placement of external
of the OPA4830 is used as well as a terminatingcomponents preserve the high-frequency
shunt resistor at the input of the destination device.performance. Resistors should be a very low
Remember also that the terminating impedance is thereactance type. Surface-mount resistors work best
parallel combination of the shunt resistor and theand allow a tighter overall layout. Metal film or carbon
input impedance of the destination device; this totalcomposition axially-leaded resistors can also provide
effective impedance should be set to match the tracegood high-frequency performance. Again, keep the
impedance. If the 6dB attenuation of aleads and PCB traces as short as possible. Never
doubly-terminated transmission line is unacceptable,use wire-wound type resistors in a high-frequency
a long trace can be series-terminated at the sourceapplication. Because the output pin and inverting
end only. Treat the trace as a capacitive load in thisinput pin are the most sensitive to parasitic
case and set the series resistor value as shown in thecapacitance, always position the feedback and series
typical characteristic curve Recommended R
S
vsoutput resistor, if any, as close as possible to the
Capacitive Load (Figure 15 ,Figure 38 , or Figure 63 ).output pin. Other network components, such as
This configuration does not preserve signal integritynoninverting input termination resistors, should also
as well as a doubly-terminated line. If the inputbe placed close to the package. Where double-side
impedance of the destination device is low, there willcomponent mounting is allowed, place the feedback
be some signal attenuation due to the voltage dividerresistor directly under the package on the other side
formed by the series output into the terminatingof the board between the output and inverting input
impedance.pins. Even with a low parasitic capacitance shuntingthe external resistors, excessively high resistor valuescan create significant time constants that candegrade performance. Good axial metal film orsurface-mount resistors have approximately 0.2pF in
36 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
External
Pin
+VCC
-VCC
Internal
Circuitry
INPUT AND ESD PROTECTION
OPA4830
www.ti.com
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
e) Socketing a high-speed part is notrecommended. The additional lead length andpin-to-pin capacitance introduced by the socket cancreate an extremely troublesome parasitic networkwhich can make it almost impossible to achieve asmooth, stable frequency response. Best results areobtained by soldering the OPA4830 directly onto theboard.
Figure 90. Internal ESD Protection
The OPA4830 is built using a very high-speed,
These diodes provide moderate protection to inputcomplementary bipolar process. The internal junction
overdrive voltages above the supplies as well. Thebreakdown voltages are relatively low for these very
protection diodes can typically support 30mAsmall geometry devices. These breakdowns are
continuous current. Where higher currents arereflected in the Absolute Maximum Ratings table. All
possible (that is, in systems with ± 15V supply partsdevice pins are protected with internal ESD protection
driving into the OPA4830), current-limiting seriesdiodes to the power supplies, as shown in Figure 90 .
resistors should be added into the two inputs. Keepthese resistor values as low as possible, becausehigh values degrade both noise performance andfrequency response.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): OPA4830
OPA4830
SBOS350A – DECEMBER 2006 – REVISED MAY 2008 ....................................................................................................................................................
www.ti.com
Revision History
Changes from Original (December 2006) to Revision A ................................................................................................ Page
•Changed rating for storage temperature range in Absolute Maximum Ratings table from – 40 °C to +125 °C to – 65 °Cto +125 °C............................................................................................................................................................................... 2
38 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA4830
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
OPA4830IPW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4830IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4830IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
OPA4830IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 19-May-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA4830IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA4830IPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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