October 2008 Rev 12 1/55
1
M25P20
2 Mbit, low voltage, Serial Flash memory
with 75 MHz SPI bus interface
Feature summar y
2 Mbit of Flash Memory
Page Program (up to 256 Bytes) in 0.8 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (2 Mbit) in 3 s (typical)
2.3 to 3.6 V Single Supply Voltage
SPI Bus Compatible Serial Interface
75 MHz Clock Rate (maximum)
Deep Power-down Mode 1 μA (typical)
Hardware Write Protection: protected area
size defined by two non-volatile bits (BP0,
BP1)
Electronic Signatures
– JEDEC Standard two-Byte Signature
(2012h)
– Unique ID code (UID) with 16 bytes read-
only, available upon customer request
– RES Instruction, One-Byte, Signature
(11h), for backward compatibility
Packages
– ECOPACK® (RoHS compliant)
SO8 (MN)
150 mils width
VFQFPN8 (MP)
(MLP8 6 x 5 mm)
QFN8L (MS)
MLP8 6 x 5 mm
www.Numonyx.com
Contents M25P20
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Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.3 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . .11
4.4 Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . .11
4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M25P20 Contents
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6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 25
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 31
7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
List of tables M25P20
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List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. DC Characteristics (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. DC Characteristics (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Instruction Times, process technology T9HX (Device Grade 6). . . . . . . . . . . . . . . . . . . . . 38
Table 16. Instruction Times, process technology T7Y, Device Grade 6. . . . . . . . . . . . . . . . . . . . . . . 39
Table 17. Instruction Times (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. AC Characteristics (25MHz Operation, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. AC Characteristics (40MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. AC Characteristics (50MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. AC characteristics, grade 6 (T9HX technology), 75 MHz operation, VCC min = 2.7 V . . . 44
Table 23. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 24. QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data. . . 49
Table 25. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Dual Flat Package No lead,
6x5mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 26. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
M25P20 List of figures
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List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO and MLP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Disable (WRDI) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . 20
Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . 21
Figure 11. Write Status Register (WRSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 24
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Sector Erase (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Release from Deep Power-down (RES) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1. . . . . . . . . . . . . . . . . 46
Figure 24. Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25. Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . . . 48
Figure 27. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 × 5 mm, package outline . . . . . . . . . 49
Figure 28. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Dual Flat Package No lead,
6x5mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Summary description M25P20
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1 Summary description
The M25P20 is a 2 Mbit (256K x 8) Serial Flash Memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The M25P20 features high
performance instructions allowing clock frequency operation up to 75 MHz(1)
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144
bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an
Numonyx trademark. ECOPACK specifications are available at: www.Numonyx.com.
Important: This datas heet deta i l s t he f unctionalit y of t he M 25P20 devices, based on the previo us T7 Y
process or based on the current T9HX pro cess (avai l able si nce Aug u s t 2008). T he new
device in T9HX is completely backward compatibl e with the old one in T7Y and it additionaly
features:
- extended Vcc range (2.3-3.6V)
- improved max frequency (Fast Read) to 75 MHz in the standard Vcc range 2.7-3.6 V
- ma x f requency (Fas t Read) of 40 MHz in the exte nded Vc c range 2. 3-2.7V
- UI D/CFD protection f eature
Figure 1. Logic Diagram
1. 75 MHz operation is available only on the VCC range 2.7 V - 3.6 V and for process technology T9HX devices,
identified by process identification digit "4" in the device marking and process letter "B" in the part number.
AI04080
S
VCC
M25P20
HOLD
VSS
W
Q
C
D
M25P20 Summary description
7/55
Figure 2. SO and MLP8 Connections
1. There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally, to VSS,
and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
Tab le 1. Sign al Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
SChip Select
WWrite Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
1
AI04081B
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P20
Signal description M25P20
8/55
2 Signal description
2.1 Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6 Write Prot ect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP1 and
BP0 bits of the Status Register).
M25P20 SPI modes
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3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Fig ur e 3. Bus Maste r an d m emory devices on th e SPI Bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the tSHCH requirement is met).
AI12836
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
R
(2)
R
(2)
R
(2)
V
C
C
V
CC
V
CC
V
CC
V
S
S
V
SS
V
SS
V
SS
R
(2)
SPI modes M25P20
10/55
Figure 4. SPI modes support ed
AI01438
B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
M25P20 Op er ati n g fe atu r es
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4 Operating features
4.1 Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is
one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This
is followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Page Pr ogram ( PP),
Ins t ruction Times, process techno l ogy T9HX (Device Grade 6) and Table 17: In st ruction
Times (Dev i ce Grade 3)).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling During a W rite, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP
, tSE, or tBE). The
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
4.4 Active Power, Standby Power and Deep Power-Down Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active
Power mode until all internal cycles have completed (Program, Erase, Write Status
Register). The device then goes in to the Standby Power mode. The device consumption
drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
Ope rating features M25P20
12/55
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
4.5 Status Register
The Status Register contains a number of status and control bits, as shown in Table 6, that
can be read or set (as appropriate) by specific instructions. For a detailed description of the
Status Register bits, see Se ct i on 6 .4: Rea d Status Regis ter (RD SR).
4.6 Protection Modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P20 features the following data protection mechanisms:
Power On Reset and an internal timer (tPUW) can provide protection against
inadvertant changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal, in co-operation with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertant Write, Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
M25P20 Op er ati n g fe atu r es
13/55
4.7 Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Tab le 2. Protected Area Sizes
Status Register
Content Memory Content
BP1 Bit BP0 Bit Protected Area Unprotected Area
0 0 none All sectors(1)(four sectors: 0, 1, 2 and 3)
1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.
0 1 Upper quarter (Sector 3) Lower three-quarters (three sectors: 0 to
2)
1 0 Upper half (two sectors: 2 and 3) Lower half (Sectors 0 and 1)
1 1 All sectors (four sectors: 0, 1, 2 and 3) none
Ope rating features M25P20
14/55
Figure 5. Hold Condition Activa tion
AI02029
D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
M25P20 Mem ory orga niza tion
15/55
5 Memory organization
The memory is organized as:
262,144 bytes (8 bits each)
4 sectors (512 Kbits, 65536 bytes each)
1024 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Figure 6. Block Diagram
Tab l e 3. Memory Org anizat ion
Sector Address Range
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
AI04079
HOLD
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
10000h
20000h
30000h
3FFFFh
000FFh
Size of the
read-only
memory area
Instructions M25P20
16/55
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-
down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
M25P20 Instructions
17/55
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7. Write Enable (WREN) Instructi on Sequen ce
Tab le 4. Instruction S et
Instruction Description On e- b y t e I nstr uct i on
Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID(1)
1. The Read Identification (RDID) instruction is available only in products with Process Technology code X
and 4 (see Application Note AN1995).
Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher
Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES
Release from Deep Power-
down, and Read Electronic
Signature 1010 1011 ABh
0 3 1 to ∞
Release from Deep Power-
down 0 0 0
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
Instructions M25P20
18/55
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Fig u re 8. Write Disable (WRDI) In structi o n Sequence
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
M25P20 Instructions
19/55
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction allows to read the device identification data:
Manufacturer identification (1 byte)
Device identification (2 bytes)
A Unique ID code (UID) (17 bytes, of which 16 available upon customer request).(2)
The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx.
The device identification is assigned by the device manufacturer, and indicates the memory
type in the first byte (20h), and the memory capacity of the device in the second byte (12h).
The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes
of the optional Customized Factory Data (CFD) content.
The CFD bytes are read-only and can be programmed with customers data upon their
demand. If the customers do not make requests, the devices are shipped with all the CFD
bytes programmed to zero (00h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress. The device is first selected
by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted
in. After this, the 24-bit device identification, stored in the memory, the 8-bit CFD length
followed by 16 bytes of CFD content will be shifted out on Serial Data output (Q). Each bit is
shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. Once in
the Stand-by Power mode, the device waits to be selected, so that it can receive, decode
and execute instructions.
2. The UID feature is available only for process technology T9HX devices, identified by with process identification
digit "4" in the device marking and process letter "B" in the part number.
Table 5. Read Identification (RDID ) dat a-out sequence
Manufa cturer iden tification Device id en tification UID
Memory type Memory capacity CFD length CFD content
20h 20h 12h 10h 16 bytes
Instructions M25P20
20/55
Figure 9. Read Identificatio n (RDID) Instruction Seque nce and Data-Out Sequence
6.4 Re ad Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 10.
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
C
D
S
21 3456789101112131415
Instruction
0
AI06809b
Q
Manufacturer Identification
High Impedance
MSB
15 1413 3210
Device Identification
MSB
16 17 18 28 29 30 31
Table 6. Status Regi ster Format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
M25P20 Instructions
21/55
6.4.3 BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1,
BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected
against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1,
BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are
0.
6.4.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Fig ur e 10. Read Status R eg ister (RD SR ) Instru ction Sequence and Data-Out
Sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
Instructions M25P20
22/55
6.5 Write Status Registe r (WRS R)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the
user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode
(HPM) is entered.
Figure 11. Write Status Register (W RSR) Instruction Sequenc e
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25P20 Instructions
23/55
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Table 7. Protection Modes
W
Signal SRWD
Bit Mode Write Protection of the
Sta tus Register
Memory Content
Protected Area(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
Unprotected
Area(1)
10
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP1 and BP0 bits can be
changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP1 and BP0 bits cannot
be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
Instructions M25P20
24/55
6.6 Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Fig u re 12. Re ad Data Bytes (READ ) instructi on sequence and data-out sequence
1. Address bits A23 to A18 are Don’t Care.
C
D
AI03748
D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
M25P20 Instructions
25/55
6.7 Re ad Data Byte s at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_REA D) Instruc tion Seque nce
and Data-Out Sequen ce
1. Address bits A23 to A18 are Don’t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
Instructions M25P20
26/55
6.8 Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Instruction Times,
process tech nology T9 HX ( D e v i ce Grade 6) and Tabl e 17: Ins tr uction Times (Dev i ce Grade
3)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see Table 3 and Table 2) is not executed.
M25P20 Instructions
27/55
Figure 14. Page Prog ram (PP ) Inst ruct ion S equence
1. Address bits A23 to A18 are Don’t Care.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
Instructions M25P20
28/55
6.9 Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP1, BP0) bits (see Table 3 and Table 2) is not executed.
Figu r e 15. Sect o r Erase (S E) In struction Seq u ence
1. Address bits A23 to A18 are Don’t Care.
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
M25P20 Instructions
29/55
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0.
The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 16. B ulk Erase (BE) Instruction Sequence
C
D
AI03752D
S
21 345670
Instruction
Instructions M25P20
30/55
6.11 Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode
(if there is no internal cycle currently in progress). But this mode is not the Deep Power-
down mode. The Deep Power-down mode can only be entered by executing the Deep
Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2,
as specified in Table 13).
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction and
the Read Identification (RDID) instruction also allow the Electronic Signature of the device
to be output on Serial Data Output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Standby mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Powe r-down (DP) Instruction Sequence
C
D
AI03753D
S
21 345670t
DP
Deep Power-down Mode
Stand-by Mode
Instruction
M25P20 Instructions
31/55
6.12 Release from Deep Power-down and Read Electronic
Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of the Deep Power-down mode.
The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic
Signature, whose value for the M25P20 is 11h.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-down and Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep
Power-down mode has not been entered.
Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while
an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge
of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out
on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock
(C).
The instruction sequence is shown in Figure 18.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the Electronic Signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)
must remain High for at least tRES2(max), as specified in Table 19. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Instructions M25P20
32/55
Figure 18. Release from Deep Power-down and Read Electronic Sign atu re (RES ) Instruction
Sequenc e and Data-Out Sequence
1. The value of the 8-bit Electronic Signature, for the M25P20, is 11h.
Figure 19. Release from Deep Power-down (RES) Instruction Sequence
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time
(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S)
must remain High for at least tRES1(max), as specified in Table 19. Once in the Standby
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
tRES2
C
D
AI04078B
S
21 345670t
RES1
Stand-by Mode
Deep Power-down Mode
QHigh Impedance
Instruction
M25P20 Pow er- up and Power-down
33/55
7 Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
VCC(min) at Power-up, and then for a further delay of tVSL
VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper
Power-up and Power-down.
To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the later of:
tPUW after VCC passed the VWI threshold
tVSL after VCC passed the VCC(min) level
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
The device is in the Standby mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 0.1μF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
Power-up and Power-down M 25P20
34/55
Figure 20. Powe r-up Timing
Table 8. Power-Up Timing and V WI Thre shold
Symbol Parameter Min. Max. Unit
tVSL(1)
1. These parameters are characterized only.
VCC(min) to S low 10 μs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI(1) Write Inhibit Voltage (Device grade 6) 1 2.1 V
Write Inhibit Voltage (Device grade 3) 1 2.1 V
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M25P20 Initial d eli v ery s tate
35/55
8 Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9 Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Tab le 9. Absolute maximum ratin g s
Symbol Parameter Min. Max. Unit
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.
°C
VIO Input and output voltage (with respect to Ground)(2)
2. The minimum voltage may reach the value of -2 V for no more than 20 ns during transitions; The maximum
voltage may reach the value of VCC+2 V for no more than 20 ns during transitions..
–0.6 VCC +
0.6 V
VCC Supply voltage –0.6 4.0 V
VESD Electrostatic Discharge voltage (Human Body model)(3)
3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
–2000 2000 V
DC and AC parameters M25P20
36/55
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
The operation at Vcc = 2.3 V is available only for process technology T9HX devices, identified by with process
identification digit "4" in the device marking and process letter "B" in the part number, for the other devices the
minimum Supply Voltage is 2.7 V
.
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 20MHz.
Table 10. Operating Conditions
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.3(1)
1. The operation at Vcc = 2.3 V is available only for process technology T9HX devices, identified by process
identification digit "4" in the device marking and process letter "B" in the part number; for the other devices,
the minimum Supply Voltage is 2.7 V.
3.6 V
TA
Ambient Operating Temperature (Device Grade 6) –40 85
°C
Ambient Operating Temperature (Device Grade 3) –40 125
Table 11. Data Retention and Endur ance
Parameter Condition Min. Max. Unit
Erase/Program
Cycles
Device Grade 6 100,000 cycles per
sector
Device Grade 3 10,000
Data Retention at 55°C 20 years
Tab le 12. Capacitance
Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
M2 5P20 DC and AC p ar amet ers
37/55
Table 13. DC Characteristics (Device Grade 6)
Symbol Parameter T est Condition (in addition to
those in Table 10)Min. Max. Unit
ILI Input Leakage Current ± 2 μA
ILO Output Leakage Current ± 2 μA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 μA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 5μA
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at
40MHz and 75 MHz, Q = open 8mA
C = 0.1VCC / 0.9.VCC at
20MHz, Q = open 4mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 15 mA
ICC7 Operating Current (BE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 μAV
CC–0.2 V
DC and AC parameters M25P20
38/55
2. This is preliminary data
, Pro
Table 14. DC Characteristics (Device Grade 3)
Symbol Parameter Tes t Condition (in addition t o
those in Table 10)Min.(1) Max.(1) Unit
ILI Input Leakage Current ± 2 μA
ILO Output Leakage Current ± 2 μA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 μA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 50 μA
ICC3 Operating Current (READ)
C=0.1V
CC / 0.9.VCC at 25MHz,
Q = open 8mA
C=0.1V
CC / 0.9.VCC at 20MHz,
Q = open 4mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 15 mA
ICC7 Operating Current (BE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 μAVCC–
0.2 V
Table 15. Instruction Times, process technology T9HX (1) (Device Grade 6)
1. Technology T9HX devices are identified by process identification digit "4" in the device marking and
process letter "B" in the part number.
Tes t conditions specified in Table 10 and Table 18
Symbol Alt. Parameter Min. Typ. Max. Unit
tWWrite Status Register Cycle Time 1.3 15 ms
tPP(2)
2. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are
obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤
256)
Page Program Cycle Time (256 Bytes) 0.8
5ms
Page Program Cycle Time (n Bytes) int(n/8) ×
0.025
tSE Sector Erase Cycle Time 0.6 3 s
tBE Bulk Erase Cycle Time 2.5 6 s
M2 5P20 DC and AC p ar amet ers
39/55
,
1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 16. Instruction Times, process technology T7Y, Device Grade 6(1)
1. Technology T7Y devices are identified by process identification digit "X" in the device marking.
Tes t conditions specified in Table 10 and Table 18
Symbol Alt. Parameter Min. Typ. Max. Unit
tWWrite Status Register Cycle Time 5 15 ms
tPP(2)
2. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are
obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤
256)
Page Program Cycle Time (256 Bytes) 1.4
5ms
Page Program Cycle Time (n Bytes) 0.4+n×
1/256
tSE Sector Erase Cycle Time 0.8 3 s
tBE Bulk Erase Cycle Time 2.5 6 s
Tab l e 17. I ns truction T i mes (D evice Grade 3)
Test conditions specified in Table 10 and Table 18
Symbol Alt. Parameter Min. Typ(1) (2)
1. At 85°C
2. Preliminary data.
Max(2) Unit
tWWrite Status Register Cycle Time 8 15 ms
tPP(3)
3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are
obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤
256)
Page Program Cycle Time (256 Bytes) 1.5
5ms
Page Program Cycle Time (n Bytes) 0.4+
n*1.1/256
tSE Sector Erase Cycle Time 1 3 s
tBE Bulk Erase Cycle Time 2.8 6 s
Table 18. AC Measurement Conditions
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
DC and AC parameters M25P20
40/55
Figure 21. AC Measurement I/O Waveform
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Outpu
t
Timing Reference Level
s
Input Levels
0.5VCC
M2 5P20 DC and AC p ar amet ers
41/55
Tab le 19. AC Ch aracteristi cs (25M Hz Oper ation, Device Grade 6 o r 3)
Test conditions specified in Table 10 and Table 18
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock Frequency for the following
instructions: FAST_READ, PP, SE, BE,
DP, RES, WREN, WRDI, RDSR, WRSR
D.C. 25 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH(1)
1. tCH + tCL must be greater than or equal to 1/ fC
tCLH Clock High Time 18 ns
tCL(1) tCLL Clock Low Time 18 ns
tCLCH(2)
2. Value guaranteed by characterization, not 100% tested in production.
Clock Rise Time(3) (peak to peak)
3. Expressed as a slew-rate.
0.1 V/ns
tCHCL(2) Clock Fall Time(3) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 10 ns
tCHSL S Not Active Hold Time (relative to C) 10 ns
tDVCH tDSU Data In Setup Time 5 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 10 ns
tSHCH S Not Active Setup Time (relative to C) 10 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ(2) tDIS Output Disable Time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 10 ns
tCHHH HOLD Hold Time (relative to C) 10 ns
tHHCH HOLD Setup Time (relative to C) 10 ns
tCHHL HOLD Hold Time (relative to C) 10 ns
tHHQX(2) tLZ HOLD to Output Low-Z 15 ns
tHLQZ(2) tHZ HOLD to Output High-Z 20 ns
tWHSL(4)
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Write Protect Setup Time 20 ns
tSHWL(4) Write Protect Hold Time 100 ns
tDP(2) S High to Deep Power-down Mode 3 μs
tRES1(2) S High to Standby Mode without
Electronic Signature Read 3 or 30(5)
5. It is 30μs in devices produced with the “X” process technology (grade 3 devices are only produced using
the “X” process technology). Details of how to find the process letter on the device marking are given in the
Application note AN1995.
μs
tRES2(2) S High to Standby Mode with Electronic
Signature Read 1.8 or 30(5) μs
DC and AC parameters M25P20
42/55
Tab le 20. AC Ch aracteristi cs (40M Hz Oper ation, Device Grade 6)(1)
1. 40MHz is the maximum frequency for T9HX device operation in the extended Vcc range 2.3 V to 2.7 V.
40MHz available for products marked since week 20 of 2004, only(2)
Test conditions specified in Table 10 and Table 18
2. Details of how to find the date of marking are given in Application Note, AN1995.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock Frequency for the following
instructions: FAST_READ, PP, SE, BE,
DP, RES, WREN, WRDI, RDSR, WRSR
D.C. 40 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH (3)
3. tCH + tCL must be greater than or equal to 1/ fC
tCLH Clock High Time 11 ns
tCL(3) tCLL Clock Low Time 11 ns
tCLCH(4)
4. Value guaranteed by characterization, not 100% tested in production.
Clock Rise Time(5) (peak to peak)
5. Expressed as a slew-rate.
0.1 V/ns
tCHCL(4) Clock Fall Time(5) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ(4) tDIS Output Disable Time 9 ns
tCLQV tVClock Low to Output Valid 9 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX(4) tLZ HOLD to Output Low-Z 9 ns
tHLQZ(4) tHZ HOLD to Output High-Z 9 ns
tWHSL(6)
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Write Protect Setup Time 20 ns
tSHWL(6) Write Protect Hold Time 100 ns
tDP(4) S High to Deep Power-down Mode 3 μs
tRES1(4) S High to Standby Mode without
Electronic Signature Read 3 or 30(7) μs
tRES2(4) S High to Standby Mode with Electronic
Signature Read 1.8 or 30(7) μs
M2 5P20 DC and AC p ar amet ers
43/55
7. It is 30μs in devices produced with the “X” process technology. Details of how to find the process letter on
the device marking are given in the Application note AN1995.
Tab le 21. AC Ch aracteristi cs (50M Hz Oper ation, Device Grade 6)(1)
1. 50 MHz operation is available only on the VCC range 2.7 V to 3.6 V; the maximum frequency in the
extended Vcc range 2.3 V to 2.7 V is 40 MHz.
50MHz available only in products with Process Technology code X(2) and 4
Test conditions specified in Table 10 and Table 18
2. Details of how to find the date of marking are given in Application Note, AN1995.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfC
Clock Frequency for the following
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, RDID, WRDI, RDSR, WRSR
D.C. 50 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH(3) tCLH Clock High Time 9 ns
tCL(3) tCLL Clock Low Time 9 ns
tCLCH(4) Clock Rise Time(5) (peak to peak) 0.1 V/ns
tCHCL(4) Clock Fall Time(5) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ(4) tDIS Output Disable Time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX(4) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(4) tHZ HOLD to Output High-Z 8 ns
tWHSL(6) Write Protect Setup Time 20 ns
tSHWL(6) Write Protect Hold Time 100 ns
tDP(4) S High to Deep Power-down Mode 3 μs
tRES1(4) S High to Standby Power mode without
Electronic Signature Read 30 μs
tRES2(4) S High to Standby Power mode with
Electronic Signature Read 30 μs
DC and AC parameters M25P20
44/55
3. tCH + tCL must be greater than or equal to 1/ fC
4. Value guaranteed by characterization, not 100% tested in production.
5. Expressed as a slew-rate.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
T able 22. AC characteristics, grade 6 (T9HX technology), 75 MHz operation, VCC min
= 2. 7 V
Applies only to products made with T9HX technology, identified with process digit ‘4’(1) and
process letter “B” in the part number(2)
Test conditions specified in Table 10 and Table 18
Symbol Alt. Parameter Min Typ(3) Max Unit
fCfC
Clock frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, RDID, RDSR, WRSR
D.C. 75 MHz
fRClock frequency for READ instructions D.C. 33 MHz
tCH(4) tCLH Clock High time 6 ns
tCL(3) tCLL Clock Low time 6 ns
tCLCH(5) Clock Rise time(6) (peak to peak) 0.1 V/ns
tCHCL(5) Clock Fall time(6) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup time (relative to C) 5 ns
tCHSL S Not Active Hold time (relative to C) 5 ns
tDVCH tDSU Data In Setup time 2 ns
tCHDX tDH Data In Hold time 5 ns
tCHSH S Active Hold time (relative to C) 5 ns
tSHCH S Not Active Setup time (relative to C) 5 ns
tSHSL tCSH S Deselect time 100 ns
tSHQZ(5) tDIS Output Disable time 8 ns
tCLQV tVClock Low to Output Valid under 30 pF/10 pF 8/6 ns
tCLQX tHO Output Hold time 0 ns
tHLCH HOLD Setup time (relative to C) 5 ns
tCHHH HOLD Hold time (relative to C) 5 ns
tHHCH HOLD Setup time (relative to C) 5 ns
tCHHL HOLD Hold time (relative to C) 5 ns
tHHQX(5) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(5) tHZ HOLD to Output High-Z 8 ns
tWHSL(7) Write Protect Setup time 20 ns
tSHWL(7) Write Protect Hold time 100 ns
tDP(5) S High to Deep Power-down mode 3 μs
M2 5P20 DC and AC p ar amet ers
45/55
Figure 22. S erial Input Timing
tRES1(5) S High to Standby mode without Read Elec-
tronic Signature 30 μs
tRES2(5) S High to Standby mode with Read Electronic
Signature 30 μs
1. Details of how to find the technology process in the marking are given in AN1995, see also Section 12:
Part numbering.
2. 75 MHz operation is available only on the VCC range 2.7 V to 3.6 V; the maximum frequency in the
extended Vcc range 2.3 V to 2.7 V is 40 MHz.
3. Typical values given for TA = 25 °C.
4. tCH + tCL must be greater than or equal to 1/ fC.
5. Value guaranteed by characterization, not 100% tested in production.
6. Expressed as a slew-rate.
7. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’.
T able 22. AC characteristics, grade 6 (T9HX technology), 75 MHz operation, VCC min
= 2.7 V (continued)
Applies only to products made with T9HX technology, identified with process digit ‘4’(1) and
process letter “B” in the part number(2)
Test conditions specified in Table 10 and Table 18
Symbol Alt. Parameter Min Typ(3) Max Unit
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
DC and AC parameters M25P20
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Figure 23. Wri te Protec t Setu p and Hold Timing during WRSR when SRWD=1
Figure 24. Hold Timing
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
M2 5P20 DC and AC p ar amet ers
47/55
Figure 25. Output Timing
C
Q
AI01449
e
S
LSB OUT
DADDR.
LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
Package mechanical M25P20
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11 Package mechanical
Figure 26. SO8 narrow – 8 lead Pla stic Small Outli ne, 150 mils body width, Package
Outline
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1.
Table 23 . SO8 narrow – 8 lead Pla stic Small Outli ne, 150 mil s body width,
package mechanical dat a
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.009
ccc 0.10 0.004
D 4.90 4.80 5.00 0.193 0.189 0.197
E 6.00 5.80 6.20 0.236 0.228 0.244
E1 3.90 3.80 4.00 0.154 0.150 0.157
e 1.27 – – 0.050 – –
h 0.25 0.50 0.010 0.020
k0°8°0°8°
L 0.40 1.27 0.016 0.050
L1 1.04 0.041
SO-A
E1
8
ccc
be
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M25P20 Package mechan ical
49/55
Fig ur e 27. QFN8L (MLP8 ) 8-lead, d u al flat packa ge n o lead, 6 × 5 mm, packag e
outline
1. Drawing is not to scale.
Tab le 24. QFN 8L (MLP8 ) 8-lead du al fla t pack age no lea d , 6 x 5 mm packag e
mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 0.90 0.80 1.00 0.035 0.031 0.039
A1 0.02 0.00 0.05 0.001 0.000 0.002
A3 0.20 0.008
b 0.40 0.35 0.48 0.016 0.014 0.019
D 6.00 0.236
D2 3.00 2.80 3.20 0.118 0.110 0.126
E 5.00 0.197
E2 3.00 2.80 3.20 0.118 0.110 0.126
e 1.27 0.050
L 0.60 0.50 0.75 0.024 0.020 0.030
0.08
D2
L
b
5X_ME
E2
e
E
D
AA3 A1 E2/2
0PIN 1 ID OPTION
Package mechanical M25P20
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Fig ur e 28. VFQF P N8 (MLP 8) 8-le ad Ver y thin Fin e Pitch D u al F lat Pack ag e No lead,
6x5mm, Pac kage Out li n e
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Tab le 25. VFQF PN8 (ML P8) 8- lead Very thin Fin e P itch Du al F lat Pack ag e No lead,
6x5mm, Pac kage Mechani cal Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.20 0.1575 0.1496 0.1654
e 1.27 0.0500
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
θ12° 12°
D
E
VFQFPN-01
A2
A
A3
A1
E1
D1
eE2
D2
L
b
θ
M25P20 Part number ing
51/55
12 Part numbering
Table 26. Ordering Inform at io n Scheme
Example: M25P20 – V MN 6 T P B
Device Type
M25P = Serial Flash Memory for Code Storage
Device Function
20 = 2 Mbit (256K x 8)
Secu rity featu res(1)
1. Secure options are available upon customer request.
– = no extra security
S = CFD programmed with UID
Operating Voltage
V = VCC = 2.3 to 3.6V
Package
MN = SO8 (150 mil width)
MS = QFN8L (MLP8)(2), 6 x 5 mm
2. Exposed pad of 3 x 3 mm.
MP = VFQFPN8 6x5mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3(3)= Device tested with High Reliability Certified Flow(4).
Automotive temperature range (–40 to 125 °C)
3. Device grade 3 available in SO8 ECOPACK® (RoHS compliant) package.
4. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive
environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.
Please ask your nearest Numonyx sales office for a copy.
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHS compliant)
Process(5)
/X = T7Y
B = T9HX
Part numbering M25P20
52/55
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
The category of Second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
5. The process letter (/X) is specified in the ordering information of Grade 3 devices only.
For Grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on the
device package (marking) and on the shipment box. Please contact your nearest Numonyx Sales Office.
For more information on how to identify products by the Process Identification Letter, please refer to
AN1995: Serial Flash Memory Device Marking.
M25P20 Revision history
53/55
13 Revision history
Table 27. Document revision history
Date Revision Changes
12-Apr-2001 1.0 Document written
25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory
11-Sep-2001 1.2
Changes to text: Signal Description/Chip Select; Hold Condition/1st para;
Protection modes; Release from Power-down and Read Electronic
Signature (RES); Power-up
Repositioning of several tables and illustrations without changing their
contents
Power-up timing illustration; SO8W package removed
Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL
16-Jan-2002 1.3
FAST_READ instruction added. Document revised with new timings, VWI,
ICC3 and clock slew rate. Descriptions of Polling, Hold Condition, Page
Programming, Release for Deep Power-down made more precise. Value
of tW(max) modified.
16-May-2002 1.4
Clarification of descriptions of entering Standby Power mode from Deep
Power-down mode, and of terminating an instruction sequence or data-
out sequence.
12-Sep-2002 1.5 VFQFPN8 package (MLP8) added. Document promoted to full datasheet.
13-Dec-2002 1.6
Typical Page Program time improved. Write Protect setup and hold times
specified, for applications that switch Write Protect to exit the Hardware
Protection mode immediately before a WRSR, and to enter the Hardware
Protection mode again immediately after.
24-Nov-2003 2.0
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
40MHz AC Characteristics table included as well as 25MHz. ICC3(max),
tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8
package
26-Apr-2004 3.0 Automotive range added. Soldering temperature information clarified for
RoHS compliant devices. Device Grade clarified
05-Aug-2004 4.0 Device Grade information clarified. Data-retention measurement
temperature corrected. Details of how to find the date of marking added.
21-Dec-2004 5.0
2 Notes removed from Table 26: Ordering Info rmation Sc heme. Small
text changes. End timing line of tSHQZ modified in Figu r e 25: Ou tp ut
Timing.
01-Aug-2005 6.0
Updated Page Program (PP) instructions in Page Programming, Page
Program (PP), Instruc tion Times, proces s technology T 9H X (Dev i ce
Grade 6) and Instruction Times (Device Grade 3).
Revision h istor y M25P20
54/55
01-Dec-2005 7.0
50MHz operation added (see Table 21: AC Characteristics (50MHz
Oper ation , Device Gra de 6)). All packages are ECOPACK®. Blank option
removed from under Pla ting Tech nology in Table 26: Ordering
Inf orm ation S chem e. MLP package renamed as VFQFPN, silhouette and
package mechanical drawing updated (see package silhouette on page 1
and Figure 28: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Dual Flat
Pac kage No l ead , 6x 5 mm, Pa ck age Out lin e. Note added to <Blue>Figure
26. and Figure 28 Read Id enti fi ca tio n (RD ID ) instruction added.
22-Dec-2005 8.0 tRES1 and tRES2 modified in Table 21: AC Characteristics (50MHz
Operati on, Device Gr ade 6). Titles of Figure 28 and Table 25 corrected.
14-Apr-2006 9
The data contained in Table 11, Table 17 and Table 19 is no longer
preliminary data.
Fig ure 3: Bu s Master and memory de vices on th e SPI Bus modified and
Note 2 added.
40MHz frequency condition modified for ICC3 in Table 14: DC
Char acteristics (Device Grade 3).
Table 17: Instruction Times (Device Grade 3) shows preliminary data.
Device Grade distinction removed, Condition changed for the Data
Retention parameter in Table 11: Data Ret ention and Endurance.
VWI parameter for Device Grade 3 added to Table 8: Power-Up Timing
and VWI Thre shold .
SO8 package specifications updated (see Figure 26 and Table 23).
/X Process added to Table 26: Ordering Informati on Scheme.
05-Jun-2006 10
tRES1 and tRES2 parameter timings changed for devices produced with
the “X” process technology in Table 19 and Table 20.
SO8 Narrow package specifications updated (see Figure 26 and
Table 23).
10-Dec-2008 11 Applied Numonyx branding.
12-Oct-2008 12
Changed frequency up to 75MHz (only in the standard Vcc range).
Added new package.
Added UID/CFD protection.
Extended Vcc range to 2.3 V.
Table 27. Document revision history ( cont inu ed)
Date Revision Changes
M25P20
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