512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Features DDR SDRAM UDIMM MT16VDDT6464A - 512MB MT16VDDT12864A - 1GB MT16VDDT25664A - 2GB For component data sheets, refer to Micron's Web site: www.micron.com Features Figure 1: * 184-pin, unbuffered dual in-line memory module (UDIMM) * Fast data transfer rates: PC-2100, PC-2700, or PC-3200 * 512MB (64 Meg x 64), 1GB (128 Meg x 64), or 2GB (256 Meg x 64) * VDD = VDDQ = +2.5V (-40B: VDD = VDDQ = +2.6V) * VDDSPD = +2.3V to +3.6V * 2.5V I/O (SSTL_2-compatible) * Internal, pipelined double data rate (DDR) 2n-prefetch architecture * Bidirectional data strobe (DQS) transmitted/ received with data--that is, source-synchronous data capture * Differential clock inputs (CK and CK#) * Multiple internal device banks for concurrent operation * Dual rank * Selectable burst lengths (BL): 2, 4, or 8 * Auto precharge option * Auto refresh and self refresh modes: 7.8125s maximum average periodic refresh interval * Serial presence-detect (SPD) with EEPROM * Selectable CAS latency (CL) for maximum compatibility * Gold edge contacts Table 1: 184-Pin UDIMM (MO-206 R/C B) PCB height: 31.75mm (1.25in) Options * Marking Operating temperature1 - Commercial (0C TA +70C) - Industrial (-40C TA +85C) * Package - 200-pin DIMM (standard) - 200-pin DIMM (Pb-free) * Memory clock, speed, CAS latency - 5.0ns (200 MHz), 400 MT/s, CL = 3 - 6.0ns (167 MHz), 333 MT/s, CL = 2.5 - 7.5ns (133 MHz), 266 MT/s, CL = 22 - 7.5ns (133 MHz), 266 MT/s, CL = 22 - 7.5ns (133 MHz), 266 MT/s, CL = 2.52 None I G Y -40B -335 -262 -26A -265 1. Contact Micron for industrial temperature module offerings. 2. Not recommended for new designs. Key Timing Parameters Data Rate (MT/s) tRCD tRP tRC CL = 2 (ns) (ns) (ns) 266 15 15 55 333 266 18 18 60 Speed Grade Industry Nomenclature CL = 3 CL = 2.5 -40B PC3200 400 333 -335 PC2700 - -262 PC2100 - 266 266 15 15 60 -26A PC2100 - 266 266 20 20 65 -265 PC2100 - 266 200 20 20 65 Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN Notes 1 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Features Table 2: Addressing Parameter Refresh count 512MB 1GB 2GB 8K 8K 8K Row address 8K (A0-A12) 8K (A0-A12) 16K (A0-A13) Device bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) Column address 1K (A0-A9) 2K (A0-A9, A11) 2K (A0-A9, A11) Module rank address 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) Table 3: Part Numbers and Timing Parameters - 512MB Modules Base device: MT46V32M8,1 256Mb DDR SDRAM Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT16VDDT6464AG-40B__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDT6464AY-40B__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDT6464AG-335__ 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 Part Number2 MT16VDDT6464AY-335__ 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDT6464AG-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT6464AG-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDT6464AG-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT6464AY-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Table 4: Part Numbers and Timing Parameters - 1GB Modules Base device: MT46V64M8,1 512Mb DDR SDRAM Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT16VDDT12864AG-40B__ 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDT12864AY-40B__ 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 Part Number2 MT16VDDT12864AG-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDT12864AY-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDT12864AG-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDT12864AG-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDT12864AY-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 1. The data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16VDDT6464AY-40BG4. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Features Table 5: Part Numbers and Timing Parameters - 2GB Modules Base device: MT46V128M8,1 1Gb DDR SDRAM Module Density Part Number2 Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT16VDDT25664AG-335__ 2GB 256 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDT25664AY-335__ 2GB 256 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDT25664AG-265__ 2GB 256 Meg x 64 2.71 GB/s 7.5ns/333 MT/s 2.5-3-3 MT16VDDT25664AY-265__ 2GB 256 Meg x 64 2.71 GB/s 7.5ns/333 MT/s 2.5-3-3 Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 1. The data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16VDDT6464AY-40BG4. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 6: Pin Assignments 184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1# VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 NC NC VDD Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 NC A0 NC VSS NC BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS CK2# CK2 VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin Symbol Pin Symbol Pin Symbol Pin Symbol 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 162 163 164 165 166 1671 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 DQ47 NC VDDQ DQ52 DQ53 NC/A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ NC DQ20 A12 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 NC NC VDDQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS NC A10 NC VDDQ NC VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDDQ S0# S1# DM5 VSS DQ46 1. Pin 167 is NC for 512MB and 1GB or A13 for 2GB. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Table 7: Pin Descriptions Symbol Type Description A0-A13 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. A0-A12 (512MB and1GB) and A0-A13 (2GB). BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. CK0, CK0#, CK1, CK1#, CK2, CK2# Input Clock: CK and CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE enables (registered HIGH) and CKE disables (registered LOW) the internal clock, input buffers, and output drivers. DM0-DM7 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although the DM pins are input-only, the DM loading is designed to match that of the DQ and DQS pins. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. S0#, S1# Input Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. SA0-SA2 Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data transfer to and from the module. DQ0-DQ63 I/O Data input/output: Data bus. DQS0-DQS7 I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data. SDA I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. VDD/VDDQ Supply Power supply: +2.5V 0.2V (-40B: +2.6V 0.1V). VDDSPD Supply SPD EEPROM power supply: +2.3V to +3.6V. VREF Supply SSTL_2 reference voltage (VDD/2). VSS Supply Ground. NC - PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN No connect: These pins are not connected on the module. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0 DQS4 DM0 DM4 DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ DQ U18 DQ DQ DQ DQ DQS1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ U5 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ U6 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ U7 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DQS5 DM1 DM5 DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U17 DQ DQ DQ DQ DQS2 DQS6 DM2 DM6 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ DQS3 DQS7 DM3 DM7 DM CS# DQS DQ DQ DQ U4 DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0, BA1 DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ BA0, BA1: DDR SDRAM A0-A13 A0-A13: DDR SDRAM RAS# RAS#: DDR SDRAM CAS# CAS#: DDR SDRAM WE# WE#: DDR SDRAM CKE1 CKE0: DDR SDRAM U1, U3, U6, U8, U11, U13, U14, U16 CKE0 CKE1: DDR SDRAM U2, U4, U5, U7, U10, U12, U15, U17 VDDSPD SPD/EEPROM VDDQ DDR SDRAM VDD PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN DDR SDRAM VREF DDR SDRAM VSS DDR SDRAM 6 CK0 CK0# U4, U5, U14, U15 CK1 CK1# U1-U3, U16-U18 CK2 CK2# U6-U8, U11-U13 U19 SCL SPD/EEPROM WP A0 A1 SDA A2 VSS SA0 SA1 SA2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM General Description General Description The MT16VDDT6464A, MT16VDDT12864A, and MT16VDDT25664A are high-speed, CMOS dynamic random access 512MB, 1GB, and 2GB memory modules organized in a x64 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation These DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 8 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 8: Symbol Absolute Maximum Ratings Parameter Min Max Units VDD/VDDQ VDD/VDDQ supply voltage relative to VSS -1.0 +3.6 V VIN, VOUT Voltage on any pin relative to VSS -0.5 +3.2 V Input leakage current; Any input 0V VIN VDD; Address inputs, VREF input 0V VIN 1.35V (All other pins not under RAS#, CAS#, WE#, BA test = 0V) S#, CKE -32 +32 A II 16 16 CK0, CK0# -8 +8 CK1, CK1#, CK2, CK2# -12 +12 DM -4 +4 -10 +10 IOZ Output leakage current; 0V VOUT VDDQ; DQ are disabled DQ, DQS TA DRAM ambient operating temperature1 Commercial Industrial Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN A 0 +70 C -40 +85 C 1. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron's Web site. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 9. Table 9: Module and Component Speed Grades DDR components may exceed the listed module speed grades Module Speed Grade Component Speed Grade -40B -5B -335 -6 -262 -75E -26A -75Z -265 -75 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications IDD Specifications Table 10: IDD Specifications and Conditions - 512MB (Die Revision K) Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Symbol -40B -335 Units Operating one bank active-precharge current: RC = RC (MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles 1 IDD0 832 752 mA Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); t CK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 992 952 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P2 64 64 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 800 800 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 560 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 960 880 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,472 1,132 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 1,472 1,312 mA IDD52 2,560 2,560 mA IDD5A2 96 96 mA t t t tREFC Auto refresh current tREFC t = tRFC (MIN) = 7.8125s Self refresh current: CKE 0.2V IDD62 64 64 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD71 2,352 2,192 mA Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 11: IDD Specifications and Conditions - 512MB (All Other Die Revisions) Values are for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet -40B -335 -262 -26A/ -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1 1,112 1,032 1,032 992 mA Operating one bank active-read-precharge current: BL = 2; RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 1,392 1,392 1,312 1,192 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P2 64 64 64 64 mA Idle standby current: CS# = HIGH; All device banks idle; = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 960 800 720 720 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 640 480 400 400/ 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 1,120 960 800 800 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,632 1,432 1,232 1,232 mA Operating burst write current: BL = 2; Continuous burst writes; IDD4W1 One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle 1,592 1,432 1,232 1,232 mA IDD52 4,160 4,080 3,760 3,760/ 3,920 mA IDD5A2 96 96 96 96 mA Self refresh current: CKE 0.2V IDD62 64 64 64 64 mA Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD71 3,792 3,312 2,832 2,832/ 2,952 mA Parameter/Condition Symbol t t t t tCK Auto refresh current Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN tREFC = tRFC (MIN) tREFC = 7.8125s 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 12: IDD Specifications and Conditions - 1GB Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet -40B -335 -262 -26A/ -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1 1,280 1,080 1,080 960 mA Operating one bank active-read-precharge current: BL = 2; RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 1,520 1,320 1,320 1,200 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P2 80 80 80 80 mA Idle standby current: CS# = HIGH; All device banks idle; = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 880 720 720 640 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 720 560 560 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 960 800 800 720 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,560 1,360 1,360 1,200 mA Operating burst write current: BL = 2; Continuous burst writes; IDD4W1 One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle 1,600 1,440 1,280 1,120 mA IDD52 5,520 4,640 4,640 4,480 mA IDD5A2 IDD62 176 160 160 160 mA 80 80 80 80 mA IDD71 3,640 3,280 3,240 2,840 mA Parameter/Condition Symbol t t t t tCK tREFC Auto refresh current tREFC = tRFC (MIN) = 7.8125s Self refresh current: CKE 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 13: IDD Specifications and Conditions - 2GB Values are for the MT46V128M8 DDR SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet Parameter/Condition Symbol -335 -265 Units Operating one bank active-precharge current: RC = RC (MIN); CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1 1,360 1,240 mA Operating one bank active-read-precharge current: BL = 2; RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 1,640 1,520 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P2 160 160 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DM, and DQS IDD2F2 1,040 960 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 560 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 800 720 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,840 1,680 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 1,920 1,760 mA IDD52 5,440 5,280 mA IDD5A2 IDD62 160 160 mA 144 144 mA IDD71 4,280 3,960 mA t t t t tRC tREFC Auto refresh current tREFC = tRFC (MIN) = 7.8125s Self refresh current: CKE 0.2V Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect Table 14: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Symbol Min Max Units VDDSPD 2.3 3.6 V Input high voltage: Logic 1; All inputs VIH Input low voltage: Logic 0; All inputs VIL VDDSPD x 0.7 VDDSPD + 0.5 -1.0 VDDSPD x 0.3 Output low voltage: IOUT = 3mA V V VOL - 0.4 V Input leakage current: VIN = GND to VDD ILI - 10 A Output leakage current: VOUT = GND to VDD ILO - 10 A Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB - 30 A Power supply current: SCL clock frequency = 100 kHz ICC - 2.0 mA Table 15: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 s 1 Time the bus must be free before a new transition can start tBUF 1.3 - s Data-out hold time tDH 200 - ns SDA fall time tF - 300 ns 2 SDA rise time tR - 300 ns 2 tHD:DAT 0 - s Start condition hold time tH:STA 0.6 - s Clock HIGH period tHIGH 0.6 - s tI - 50 ns tLOW 1.3 - s fSCL - 400 kHz Data-in setup time tSU:DAT 100 - ns Start condition setup time tSU:STA 0.6 - s Stop condition setup time tSU:STO 0.6 - s tWRC - 10 ms Data-in hold time Noise suppression time constant at SCL, SDA inputs Clock LOW period SCL clock frequency WRITE cycle time Notes: 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/SPD. PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved 512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM Module Dimensions Module Dimensions Figure 3: 184-Pin DDR UDIMM 4.0 (0.157) MAX Front view 133.50 (5.256) 133.20 (5.244) 2.0 (0.079) R (4X) U1 U2 U3 U4 U5 U6 U7 U8 31.9 (1.256) 31.6 (1.244) 17.78 (0.7) TYP 2.5 (0.098) D (2X) 2.3 (0.091) TYP 0.9 (0.035) R Pin 1 1.27 (0.05) TYP 2.2 (0.87) TYP 1.37 (0.054) 1.17 (0.046) Pin 92 6.35 (0.25) TYP 1.02 (0.04) TYP 120.65 (4.75) TYP Back view U10 U11 U12 U13 U14 U15 U16 U17 U18 10.0 (0.394) TYP Pin 93 Pin 184 49.53 (1.95) TYP 64.77 (2.55) TYP 3.8 (0.15) TYP 73.3 (2.89) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80739fa5/Source:09005aef807397e5 DD16C64_128_256x64A.fm - Rev. E 8/08 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.