DC1872A - Linear Technology - Datasheet.Directory

LTM4637

4637fc

For more information www.linear.com/LTM4637

Typical applicaTion

DescripTion

20A DC/DC µModule

Step-Down Regulator

The LT M

4637 is a complete 20A output high efficiency

switch mode step-down DC/DC µModule (micromodule)

regulator. Included in the package are the switching control-

ler, power FETs, inductor and compensation components.

Operating over an input voltage range from 4.5V to 20V,

the LTM4637 supports an output voltage range of 0.6V

to 5.5V, set by a single external resistor. Only a few input

and output capacitors are needed.

Current mode operation allows precision current sharing

of up to four LTM4637 regulators to obtain up to 80A

output. High switching frequency and a current mode

architecture enable a very fast transient response to line

and load changes without sacrificing stability. The device

supports frequency synchronization, multiphase/current

sharing, Burst Mode operation and output voltage tracking

for supply rail sequencing. A diode-connected PNP transis-

tor is available for use as an internal temperature monitor.

The LTM4637 is offered in 15mm × 15mm × 4.32mm LGA

and 15mm × 15mm × 4.92mm packages. The LTM4637

is available with SnPb (BGA) or RoHS compliant terminal

finish. The LTM4637 is pin compatible with the LTM4627,

a 15A DC/DC µModule regulator.

L, LT , LT C , LT M , PolyPhase, Burst Mode, µModule, Linear Technology, the Linear logo are

registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643.

12VIN, 1.2VOUT, 20A DC/DC µModule

Regulator

FeaTures

applicaTions

n Complete 20A Switch Mode Power Supply

n 4.5V to 20V Input Voltage Range

n 0.6V to 5.5V Output Voltage Range

n ±1.5% Total DC Output Voltage Error

(–40°C to 125°C)

n Differential Remote Sense Amplifier for Precision

Regulation for (VOUT ≤ 3.3V)

n Current Mode Control/Fast Transient Response

n Parallel Current Sharing (Up to 80A)

n Frequency Synchronization

n Selectable Pulse-Skipping or Burst Mode

Operation

n Soft-Start/Voltage Tracking

n Up to 88% Efficiency (12VIN, 1.8VOUT)

n Overcurrent Foldback Protection

n Output Overvoltage Protection

n Internal Temperature Monitor

n Overtemperature Protection

n 15mm × 15mm × 4.32mm LGA and

15mm × 15mm × 4.92mm BGA Packages

n SnPb (BGA) or RoHS Compliant (LGA and BGA) Finish

n Telecom Servers and Networking Equipment

n Industrial Equipment

n Medical Systems

n High Ambient Temperature Systems

12VIN Efficiency vs Load Current

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

10k

RFB**

60.4k

22µF

16V

×4

0.1µF

100µF*

6.3V

×2

470µF

6.3V

×2

VOUT

1.2V

20A

330pF

INTVCC

2.2µF

EXTVCC

* SEE TABLE 5

** SEE TABLE 1

4637 TA01a

VIN

12V

SGND GND

OUTPUT CURRENT (A)

EFFICIENCY (%)

100

210 14

4637 TA01b

818 20

4612 16

1.2VOUT

250kHz

CCM

LTM4637

4637fc

For more information www.linear.com/LTM4637

pin conFiguraTion

absoluTe MaxiMuM raTings

VIN ............................................................. –0.3V to 22V

VOUT ............................................................. –0.3V to 6V

INTVCC, VOUT_LCL, PGOOD, EXTVCC ............ –0.3V to 6V

MODE_PLLIN, fSET, TRACK/SS,

VOSNS–, VOSNS+, DIFF_OUT ...................–0.3V to INTVCC

VFB, COMP (Note 7) ................................. –0.3V to 2.7V

RUN (Note 5) ............................................... –0.3V to 5V

(Note 1)

LGA PACKAGE

133-LEAD (15mm × 15mm × 4.32mm)

VIN

1 2 3 4 5 6 7 8 109 11 12

INTVCC

fSET

COMPTRACK/SS

MODE_PLLIN

INTVCC

TOP VIEW

SGND

VOUT

VIN

GND

EXTVCC

VFB

PGOOD

TEMP

RUN

VOSNS+

DIFF_OUT

VOUT_LCL

VOSNS–

BGA PACKAGE

133-LEAD (15mm × 15mm × 4.92mm)

VIN

1 2 3 4 5 6 7 8 109 11 12

INTVCC

fSET

COMPTRACK/SS

MODE_PLLIN

INTVCC

TOP VIEW

SGND

VOUT

VIN

GND

EXTVCC

VFB

PGOOD

TEMP

RUN

VOSNS+

DIFF_OUT

VOUT_LCL

VOSNS–

TJ(MAX) = 125°C, θJA = 9.5°C/W, θJCbottom = 4°C/W, θJCtop = 6.7°C/W, θJB = 4.5°C/W

θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 2.9g

θ VALUES DETERMINED PER JESD51-12

TJ(MAX) = 125°C, θJA = 10.4°C/W, θJCbottom = 4.6°C/W, θJCtop = 6.7°C/W, θJB = 5.3°C/W

θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 3.1g

θ VALUES DETERMINED PER JESD51-12

TEMP ........................................................ –0.3V to 0.8V

INTVCC Peak Output Current (Note 6) ..................100mA

Internal Operating Temperature Range

(Note 2) .................................................. –40°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

Reflow (Peak Body) Temperature .......................... 245°C

orDer inForMaTion

PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE

TYPE

MSL

RATING

TEMPERATURE RANGE

(Note 2)

DEVICE FINISH CODE

LTM4637EV#PBF Au (RoHS) LTM4637V e4 LGA 4 –40°C to 125°C

LTM4637IV#PBF Au (RoHS) LTM4637V e4 LGA 4 –40°C to 125°C

LTM4637EY#PBF SAC305 (RoHS) LTM4637Y e1 BGA 4 –40°C to 125°C

LTM4637IY#PBF SAC305 (RoHS) LTM4637Y e1 BGA 4 –40°C to 125°C

LTM4637IY SnPb (63/37) LTM4637Y e0 BGA 4 –40°C to 125°C

Consult Marketing for parts specified with wider operating temperature

ranges. *Device temperature grade is indicated by a label on the shipping

container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Terminal Finish Part Marking:

www.linear.com/leadfree

• Recommended LGA and BGA PCB Assembly and Manufacturing

Procedures:

www.linear.com/umodule/pcbassembly

• LGA and BGA Package and T

ray Drawings:

www.linear.com/packaging

LTM4637

4637fc

For more information www.linear.com/LTM4637

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal

operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 22.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Input DC Voltage l4.5 20 V

VOUT Range VOUT Range l0.6 5.5 V

VOUT(DC) Output Voltage, Total

Variation with Line and Load

CIN = 22µF × 3

COUT = 100µF Ceramic, 470µF POSCAP

RFB = 40.2k, MODE_PLLIN = GND

VIN = 5V to 20V, IOUT = 0A to 20A (Note 4)

l1.477 1.50 1.523 V

Input Specifications

VRUN RUN Pin On Threshold VRUN Rising 1.1 1.25 1.4 V

VRUNHYS RUN Pin On Hysteresis 130 mV

IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A

VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A

VIN = 12V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A

Shutdown, RUN = 0, VIN = 12V

µA

IS(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 20A

VIN = 12V, VOUT = 1.5V, IOUT = 20A

6.8

2.87

Output Specifications

IOUT(DC) Output Continuous Current

Range

VIN = 12V, VOUT = 1.5V (Note 4) 0 20 A

∆VOUT (Line)

VOUT

Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 20V

IOUT = 0A

l0.02 0.06 %/V

∆VOUT (Load)

VOUT

Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 20A, VIN = 12V (Note 4) l0.2 0.45 %

VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, 470µF POSCAP

VIN = 12V, VOUT = 1.5V

30 mVP-P

∆VOUT(START) Turn-On Overshoot COUT = 100µF Ceramic, 470µF POSCAP,

VOUT = 1.5V, IOUT = 0A, VIN = 12V

15 mV

tSTART Turn-On Time COUT = 100µF Ceramic, 470µF POSCAP,

No Load, TRACK/SS = 0.001µF, VIN = 12V

0.6 ms

∆VOUTLS Peak Deviation for Dynamic

Load

Load: 0% to 50% to 0% of Full Load

COUT = 100µF × 2 Ceramic, 470µF × 3 POSCAP,

VIN = 12V, VOUT = 1.5V

50 mV

tSETTLE Settling Time for Dynamic

Load Step

Load: 0% to 50% to 0% of Full Load, VIN = 5V,

COUT = 100µF × 2 Ceramic, 470µF × 3 POSCAP

50 µs

IOUTPK Output Current Limit VIN = 12V, VOUT = 1.5V

VIN = 5V, VOUT = 1.5V

Control Section

VFB Voltage at VFB Pin IOUT = 0A, VOUT = 1.5V l0.594 0.60 0.606 V

IFB Current at VFB Pin (Note 7) –12 –25 nA

VOVL Feedback Overvoltage

Lockout

l0.65 0.67 0.69 V

ITRACK/SS Track Pin Soft-Start Pull-Up

Current

TRACK/SS = 0V 1.0 1.2 1.4 µA

tON(MIN) Minimum On-Time (Note 3) 100 ns

RFBHI Resistor Between VOUT_LCL

and VFB Pins

60.05 60.40 60.75 kΩ

Remote Sense Amplifier

VOSNS+,

VOSNS– CM RANGE

Common Mode Input Range VIN = 12V, Run > 1.4V 0 3.6 V

VDIFF_OUT(MAX) Maximum DIFF_OUT

Voltage

IDIFF_OUT = 300µA INTVCC – 1.4 V

LTM4637

4637fc

For more information www.linear.com/LTM4637

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage VOSNS+ = VDIFF_OUT = 1.5V, IDIFF_OUT = 100µA 2 mV

AVDifferential Gain (Note 7) 1 V/V

SR Slew Rate (Note 6) 2 V/µs

GBP Gain Bandwidth Product (Note 6) 3 MHz

CMRR Common Mode Rejection (Note 7) 60 dB

IDIFF_OUT DIFF_OUT Current Sourcing 2 mA

PSRR Power Supply Rejection

Ratio

5V < VIN < 20V (Note 7) 100 dB

RIN Input Resistance VOSNS+ to GND 80 kΩ

PGOOD Output

VPGOOD PGOOD Trip Level VFB With Respect to Set Output

VFB Ramping Negative

VFB Ramping Positive

–10

VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V

INTVCC Linear Regulator

VINTVCC Internal VCC Voltage 6V < VIN < 20V 4.8 5 5.2 V

VINTVCC Load Reg INTVCC Load Regulation ICC = 0 to 50mA 0.5 %

VEXTVCC External VCC Switchover EXTVCC Ramping Positive l4.5 4.7 V

VLDO Ext EXTVCC Voltage Drop ICC = 25mA, VEXTVCC = 5V 50 100 mV

Oscillator and Phase-Locked Loop

fSYNC Frequency Sync Capture

Range

MODE_PLLIN Clock Duty Cycle = 50% 250 800 kHz

fNOM Nominal Frequency VfSET = 1.2V 450 500 550 kHz

fLOW Lowest Frequency VfSET = 0V 210 250 290 kHz

fHIGH Highest Frequency VfSET ≥ 2.4V 700 770 850 kHz

IFREQ Frequency Set Current 9 10 11 µA

RMODE_PLLIN MODE_PLLIN Input

Resistance

250 kΩ

VIH_MODE_PLLIN Clock Input Level High 2.0 V

VIL_MODE_PLLIN Clock Input Level Low 0.8 V

Temperature Diode

VTEMP TEMP Diode Voltage ITEMP = 100µA 0.6 V

TC VTEMP Temperature Coefficient l–2.0 mV/°C

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal

operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 22.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4637 is tested under pulsed load conditions such that

TJ ≈ TA. The LTM4637E is guaranteed to meet performance specifications

over the 0°C to 125°C internal operating temperature range. Specifications

over the –40°C to 125°C internal operating temperature range are assured

by design, characterization and correlation with statistical process

controls. The LTM4637I is guaranteed to meet specifications over the

full –40°C to 125°C internal operating temperature range. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board

layout, the rated package thermal resistance and other environmental

factors.

Note 3: The minimum on-time condition is specified for a peak-to-peak

inductor ripple current of ~40% of IMAX Load. (See the Applications

Information section)

Note 4: See output current derating curves for different VIN, VOUT and TA.

Note 5: Limit current into the RUN pin to less than 2mA.

Note 6: Guaranteed by design.

Note 7: 100% tested at wafer level.

LTM4637

4637fc

For more information www.linear.com/LTM4637

Typical perForMance characTerisTics

Burst Mode Efficiency

vs Load Current

Pulse-Skipping Mode Efficiency

vs Load Current 1V Transient Response

1.2V Transient Response 1.5V Transient Response 1.8V Transient Response

Efficiency vs Load Current

with 5VIN

Efficiency vs Load Current with

8VIN (Limit 5V Output to 15A)

Efficiency vs Load Current with

12VIN (Limit 5V Output to 15A)

LOAD CURRENT (A)

EFFICIENCY (%)

100

210 14

4637 G01

818 20

4612 16

1VOUT, 250kHz, CCM

1.2VOUT, 250kHz, CCM

1.5VOUT, 350kHz, CCM

1.8VOUT, 350kHz, CCM

2.5VOUT, 450kHz, CCM

3.3VOUT, 600kHz, CCM

LOAD CURRENT (A)

EFFICIENCY (%)

100

210 14

4637 G02

818 20

4612 16

1VOUT, 250kHz, CCM

1.2VOUT, 250kHz, CCM

1.5VOUT, 350kHz, CCM

1.8VOUT, 350kHz, CCM

2.5VOUT, 450kHz, CCM

3.3VOUT, 600kHz, CCM

5VOUT, 600kHz, CCM

LOAD CURRENT (A)

EFFICIENCY (%)

100

210 14

4637 G03

818 20

4612 16

1VOUT, 250kHz, CCM

1.2VOUT, 250kHz, CCM

1.5VOUT, 350kHz, CCM

1.8VOUT, 350kHz, CCM

2.5VOUT, 450kHz, CCM

3.3VOUT, 600kHz, CCM

5VOUT, 600kHz, CCM

LOAD CURRENT (A)

EFFICIENCY (%)

0.5 1 1.5 2

4637 G04

2.5 3

5VIN, 1.8VOUT, 350kHz

8VIN, 1.8VOUT, 350kHz

12VIN, 1.8VOUT, 350kHz

LOAD CURRENT (A)

EFFICIENCY (%)

0.5 1 1.5 2

4637 G05

2.5 3

5VIN, 1.8VOUT, 350k

8VIN, 1.8VOUT, 350k

12VIN, 1.8VOUT, 350k

OUTPUT

TRANSIENT

50mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 1V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G06

OUTPUT

TRANSIENT

50mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 1.2V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G07

OUTPUT

TRANSIENT

50mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 1.5V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G08

OUTPUT

TRANSIENT

50mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 1.8V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G09

LTM4637

4637fc

For more information www.linear.com/LTM4637

Typical perForMance characTerisTics

2.5V Transient Response

Turn-On No Load

Short-Circuit Protection No Load

3.3V Transient Response

Turn-On 20A Load

Short-Circuit Protection with 20A

Load

5V Transient Response

OUTPUT

TRANSIENT

50mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 2.5V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G10

OUTPUT

TRANSIENT

50mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 3.3V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G11

OUTPUT

TRANSIENT

100mV/DIV

200µs/DIV

LOAD STEP

5A/DIV

200µs/DIVVIN = 12V

VOUT = 5V

IOUT = 0A TO 10A, CFF = 330pF

OUTPUT CAPACITORS:

3 × 470µF POSCAP CAPACITORS

2 × 100µF CERAMIC CAPACITORS

4637 G12

VIN

2V/DIV

20ms/DIV

VOUT

200mV/DIV

20ms/DIV

12V to 1.5V AT 0A LOAD

TRACK/SS = 0.1µF

4637 G13

VIN

2V/DIV

20ms/DIV

VOUT

200mV/DIV

20ms/DIV

12V to 1.5V AT 20A LOAD

TRACK/SS = 0.1µF

4637 G14

VOUT

500mV/DIV

200µs/DIV

INPUT

CURRENT

200mA/DIV

200µs/DIV

12V to 1.5V AT 0A LOAD

TRACK/SS = 0.1µF

4637 G15

VOUT

500mV/DIV

200µs/DIV

INPUT

CURRENT

1A/DIV

200µs/DIV

12V to 1.5V AT 20A LOAD

TRACK/SS = 0.1µF

4637 G16

LTM4637

4637fc

For more information www.linear.com/LTM4637

pin FuncTions

VIN (A1-A6, B1-B6, C1-C6): Power Input Pins. Apply

input voltage between these and GND pins. Recommend

placing input decoupling capacitance directly between

VIN and GND pins.

VOUT (J1-J10, K1-K11, L1-L11, M1-M11): Power Output

Pins. Apply output load between these and GND pins. Rec-

ommend placing output decoupling capacitance between

these pins and GND pins. Review Table 5.

GND (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9,

H1-H9): Power Ground Pins for Both Input and Output.

PGOOD (F11, G12): Output Voltage Power Good Indica-

tor. Open-drain logic output is pulled to ground when the

output voltage exceeds a ±10% regulation window. Both

pins are tied together internally.

SGND (G11, H11, H12): Signal Ground Pin. Return

ground path for all analog and low power circuitry. Tie a

single connection to the output capacitor GND. See layout

guidelines in Figure 21.

TEMP (D10): Temperature Monitor. See Applications

Information section.

MODE_PLLIN (A8): Forced Continuous Mode, Burst Mode

Operation, or Pulse-Skipping Mode Selection Pin and

External Synchronization Input to Phase Detector Pin.

Connect this pin to INTVCC to enable pulse-skipping mode.

Connect to ground to enable forced continuous mode.

Floating this pin will enable Burst Mode operation. A clock

on this pin will enable synchronization with forced continu-

ous operation. See the Applications Information section.

fSET (B12): A resistor can be applied from this pin to

ground to set the operating frequency, or a DC voltage

can be applied to set the frequency. See the Applications

Information section.

TRACK/SS (A9): Output Voltage Tracking Pin and Soft-

Start Inputs. The pin has a 1.2µA pull-up current source. A

capacitor from this pin to ground will set a soft-start ramp

rate. In tracking, the regulator output can be tracked to a

different voltage. See the Applications Information section.

VFB (F12): The Negative Input of the Error Amplifier.

Internally, this pin is connected to VOUT_LCL with a

60.4k precision resistor. Different output voltages can

be programmed with an additional resistor between VFB

and ground pins. In PolyPhase

operation, tying the

VFB pins together allows for parallel operation. See the

Applications Information section.

COMP (A11): Current Control Threshold and Error Amplifier

Compensation Point. The current comparator threshold

increases with this control voltage. Tie all COMP pins

together for parallel operation. The device is internally

compensated.

RUN: (A10) Run Control Pin. A voltage above 1.4V will turn

on the module. A 5.1V Zener diode to ground is internal

to the module for limiting the voltage on the RUN pin to

5V, and allowing a pull-up resistor to VIN for enabling the

device. Limit current into the RUN pin to ≤ 2mA.

INTVCC: (A7, D9) Internal 5V LDO for Driving the Control

Circuitry and the Power MOSFET Drivers. Both pins are

internally connected. The 5V LDO has a 100mA current

limit. INTVCC is controlled and enabled when RUN is

activated high.

EXTVCC (E12): External power input to an internal control

switch allows an external source greater than 4.7V, but less

than 6V to supply IC power and bypass the internal INTVCC

LDO. EXTVCC must be less than VIN at all times during

power-on and power-off sequences. See the Applications

Information section. 5V output application can connect the

5V output to this pin to improve efficiency. The 5V output

is connected to EXTVCC in the 5V derating curves.

VOUT_LCL: (L12) This pin connects to VOUT through a 1M

resistor, and to VFB with a 60.4k resistor. The remote sense

amplifier output DIFF_OUT is connected to VOUT_LCL, and

drives the 60.4k top feedback resistor in remote sensing

applications. When the remote sense amplifier is used,

DIFF_OUT effectively eliminates the 1MΩ from VOUT to

VOUT_LCL. When the remote sense amplifier is not used,

then connect VOUT_LCL to VOUT directly.

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

LTM4637

4637fc

For more information www.linear.com/LTM4637

blocK DiagraM

Figure 1. Simplified LTM4637 Block Diagram

POWER

CONTROL

VOUT

VIN

5.1V

60.4k

fSET

RUN

VFB

SGND

COMP

VOUT_LCL

MODE_PLLIN

TRACK/SS

RfSET

50k

RFB

90.9k

C SOFT-START

4637 F01

0.6µH

VOUT VOUT

20A

VIN VIN

4.5V TO 20V

INTERNAL

COMP

2.2Ω

SGND

INTERNAL

LOOP

FILTER

INTVCC

2.2µF

250k

DIFF_OUT

VOSNS+

VOSNS–

GND

PGOOD

INTVCC

EXTVCC

> 1.4V = ON

< 1.1V = OFF

MAX = 5V

–

1.5µF

10µF

CIN

COUT

TEMP

PNP

10k

400mV

499k

PTC

INTVCC

DIFF

AMP

–

OTP

~135°C

pin FuncTions

VOSNS+: (J12) (+) Input to the Remote Sense Amplifier.

This pin connects to the output remote sense point. The

remote sense amplifier can be used for VOUT ≤ 3.3V. Con-

nect to ground when not used.

VOSNS–: (M12) (–) Input to the Remote Sense Amplifier.

This pin connects to the ground remote sense point. The

remote sense amplifier can be used for VOUT ≤ 3.3V. Con-

nect to ground when not used.

DIFF_OUT: (K12) Output of the Remote Sense Amplifier.

This pin connects to the VOUT_LCL pin for remote sense

applications. Otherwise float when not used. The remote

sense amplifier can be used for VOUT ≤ 3.3V.

MTP1, MTP2, MTP3, MTP4, MTP5, MTP6, MTP7,

(A12, B11, C10, C11, C12, D11, D12): Extra mounting

pads used for increased solder integrity strength. Leave

floating.

LTM4637

4637fc

For more information www.linear.com/LTM4637

Decoupling reQuireMenTs

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CIN External Input Capacitor Requirement

(VIN = 4.5V to 20V, VOUT = 1.5V)

IOUT = 20A, 4× 22µF Ceramic X7R Capacitors

(See Table 5)

88 µF

COUT External Output Capacitor Requirement

(VIN = 4.5V to 20V, VOUT = 1.5V)

IOUT = 20A (See Table 5) 400 µF

TA = 25°C. Use Figure 1 configuration.

Power Module Description

The LTM4637 is a high performance single output stand-

alone nonisolated switching mode DC/DC power supply.

It can provide a 20A output with few external input and

output capacitors. This module provides precisely regu-

lated output voltages programmable via external resistors

from 0.6VDC to 5.5VDC over a 4.5V to 20V input range.

The typical application schematic is shown in Figure 22.

The LTM4637 has an integrated constant-frequency cur-

rent mode regulator, power MOSFETs, 0.6µH inductor,

and other supporting discrete components. The switching

frequency range is from 250kHz to 770kHz, and the typical

operating frequency is shown in Table 5 for each VOUT. For

switching noise-sensitive applications, it can be externally

synchronized from 250kHz to 800kHz, subject to minimum

on-time limitations. A single resistor is used to program

the frequency. See the Applications Information section.

With current mode control and internal feedback loop

compensation, the LTM4637 module has sufficient stabil-

ity margins and good transient performance with a wide

range of output capacitors, even with all ceramic output

capacitors.

Current mode control provides cycle-by-cycle fast current

limit in an overcurrent condition. An internal overvoltage

monitor protects the output voltage in the event of an

overvoltage >10%. The top MOSFET is turned off and the

bottom MOSFET is turned on until the output is cleared.

Overtemperature protection will turn off the regulator’s

RUN pin at ~130°C to 137°C. See Applications Information.

operaTion

Pulling the RUN pin below 1.1V forces the regulator into a

shutdown state. The TRACK/SS pin is used for program-

ming the output voltage ramp and voltage tracking during

start-up. See the Application Information section.

The LTM4637 is internally compensated to be stable over

all operating conditions. Table 5 provides a guideline for

input and output capacitances for several operating condi-

tions. L

TpowerCAD™ is available for transient and stability

analysis. The VFB pin is used to program the output voltage

with a single external resistor to ground.

A remote sense amplifier is provided for accurately sensing

output voltages ≤3.3V at the load point.

Multiphase operation can be easily employed with the

synchronization inputs using an external clock source.

See application examples.

High efficiency at light loads can be accomplished with

selectable Burst Mode operation using the MODE_PLLIN

pin. These light load features will accommodate battery

operation. Efficiency graphs are provided for light load op-

eration in the Typical Performance Characteristics section.

A TEMP pin is provided to allow the internal device tem-

perature to be monitored using an onboard diode connected

PNP transistor. This diode connected PNP transistor is

grounded in the module and can be used as a general

temperature monitor using a device that is designed to

monitor the single-ended connection.

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The typical LTM4637 application circuit is shown in

Figure 22. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 5 for specific external capacitor

requirements for particular applications.

VIN to VOUT Step-Down Ratios

There are restrictions in the VIN to VOUT step-down ratio

that can be achieved for a given input voltage. The duty

cycle is 94% typical at 500kHz operation. The VIN to VOUT

minimum dropout is a function of load current and operation

at very low input voltage and high duty cycle applications.

At very low duty cycles the minimum 100ns on-time must

be maintained. See the Frequency Adjustment section and

temperature derating curves.

Output Voltage Programming

The PWM controller has an internal 0.6V ±1% reference

voltage. As shown in the Block Diagram, a 60.4k internal

feedback resistor connects the VOUT_LCL and VFB pins

together. When the remote sense amplifier is used, then

DIFF_OUT is connected to the VOUT_LCL pin. If the remote

sense amplifier is not used, then VOUT_LCL connects to

VOUT. The output voltage will default to 0.6V with no feed-

back resistor. Adding a resistor RFB from VFB to ground

programs the output voltage:

OUT =0.6V •

60.4k +R

RFB

Table 1. VFB Resistor Table vs Various Output Voltages

VOUT (V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0

RFB (k) Open 90.9 60.4 40.2 30.1 19.1 13.3 8.25

For parallel operation of N LTM4637s, the following

equation can be used to solve for RFB:

RFB=

60.4k /N

OUT

0.6V

–1

Tie the VFB pins together for each parallel output. The

COMP pins must be tied together also.

Input Capacitors

The LTM4637 module should be connected to a low AC-

impedance DC source. Additional input capacitors are

needed for the RMS input ripple current rating. The ICIN(RMS)

equation which follows can be used to calculate the input

capacitor requirement. Typically 22µF X7R ceramics are a

good choice with RMS ripple current ratings of ~ 2A each.

A 47µF to 100µF surface mount aluminum electrolytic bulk

capacitor can be used for more input bulk capacitance.

This bulk input capacitor is only needed if the input source

impedance is compromised by long inductive leads, traces

or not enough source capacitance. If low impedance power

planes are used, then this bulk capacitor is not needed.

For a buck converter, the switching duty cycle can be

estimated as:

OUT

VIN

Without considering the inductor ripple current, for each

output the RMS current of the input capacitor can be

estimated as:

ICIN(RMS)=

OUT(MAX)

η%•D•(1–D)

where η% is the estimated efficiency of the power mod-

ule. The bulk capacitor can be a switcher-rated aluminum

electrolytic capacitor or a Polymer capacitor.

Output Capacitors

The LTM4637 is designed for low output voltage ripple

noise. The bulk output capacitors defined as COUT are

chosen with low enough effective series resistance (ESR)

to meet the output voltage ripple and transient require-

ments. COUT can be a low ESR tantalum capacitor, low

ESR Polymer capacitor or ceramic capacitors. The typical

output capacitance range is from 200µF to 800µF. Additional

output filtering may be required by the system designer

if further reduction of output ripple or dynamic transient

spikes is required. Table 5 shows a matrix of different output

voltages and output capacitors to minimize the voltage

droop and overshoot during a 10A/µs transient. The table

optimizes total equivalent ESR and total bulk capacitance

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to optimize the transient performance. Stability criteria

are considered in the Table 5 matrix, and LTpowerCAD is

available for stability analysis. Multiphase operation will

reduce effective output ripple as a function of the number of

phases. Application Note 77 discusses this noise reduction

versus output ripple current cancellation, but the output

capacitance should be considered carefully as a function

of stability and transient response. LTpowerCAD can be

used to calculate the output ripple reduction as the number

of implemented phases increases by N times.

Burst Mode Operation

The LTM4637 is capable of Burst Mode operation in which

the power MOSFETs operate intermittently based on load

demand, thus saving quiescent current. For applications

where maximizing the efficiency at very light loads is a

high priority, Burst Mode operation should be applied. To

enable Burst Mode operation, simply float the MODE_PLLIN

pin. During Burst Mode operation, the peak current of the

inductor is set to approximately 30% of the maximum peak

current value in normal operation even though the voltage

at the COMP pin indicates a lower value. The voltage at the

COMP pin drops when the inductor’s average current is

greater than the load requirement. As the COMP voltage

drops below 0.5V, the burst comparator trips, causing

the internal sleep line to go high and turn off both power

MOSFETs.

In sleep mode, the internal circuitry is partially turned

off, reducing the quiescent current. The load current is

now being supplied from the output capacitors. When the

output voltage drops, causing COMP to rise, the internal

sleep line goes low, and the LTM4637 resumes normal

operation. The next oscillator cycle will turn on the top

power MOSFET and the switching cycle repeats.

Pulse-Skipping Mode Operation

In applications where low output ripple and high efficiency

at intermediate currents are desired, pulse-skipping

mode should be used. Pulse-skipping operation allows

the LTM4637 to skip cycles at low output loads, thus

increasing efficiency by reducing switching loss. Tying

the MODE_PLLIN pin to INTVCC enables pulse-skipping

operation. With pulse-skipping mode at light load, the

internal current comparator may remain tripped for several

cycles, thus skipping operation cycles. This mode has

lower ripple than Burst Mode operation and maintains a

higher frequency operation than Burst Mode operation.

Forced Continuous Operation

In applications where fixed frequency operation is more

critical than low current efficiency, and where the lowest

output ripple is desired, forced continuous operation

should be used. Forced continuous operation can be

enabled by tying the MODE_PLLIN pin to ground. In this

mode, inductor current is allowed to reverse during low

output loads, the COMP voltage is in control of the current

comparator threshold throughout, and the top MOSFET

always turns on with each oscillator pulse. During start-up,

forced continuous mode is disabled and inductor current

is prevented from reversing until the LTM4637’s output

voltage is in regulation.

Multiphase Operation

For applications that demand more than 20A of load

current, multiple LTM4637 devices can be paralleled to

provide more output current without increasing input

and output ripple voltage. The MODE_PLLIN pin allows

the LTM4637 to be synchronized to an external clock and

the internal phase-locked loop allows the LTM4637 to

lock onto input clock phase as well. The fSET resistor is

selected for normal frequency, then the incoming clock

can synchronize the device over the specified range. See

Figure 24 for a synchronizing example circuit.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output ca-

pacitors. The RMS input ripple current is reduced by, and

the effective ripple frequency is multiplied by, the number

of phases used (assuming that the input voltage is greater

than the number of phases used times the output voltage).

The output ripple amplitude is also reduced by the number

of phases used. See Application Note 77.

The LTM4637 device is an inherently current mode con-

trolled device, so parallel modules will have good current

sharing. This will balance the thermals in the design. Tie

the COMP and VFB pins of each LTM4637 together to

share the current evenly. Figure 24 shows a schematic of

the parallel design.

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Input RMS Ripple Current Cancellation

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current can-

cellation mathematical derivations are presented, and a

graph is displayed representing the RMS ripple current

reduction as a function of the number of interleaved phases

(see Figure 2).

PLL, Frequency Adjustment and Synchronization

The LTM4637 switching frequency is set by a resistor (RfSET)

from the fSET pin to signal ground. A 10µA current (IFREQ)

flowing out of the fSET pin through RfSET develops a volt-

age on fSET. RfSET can be calculated as:

RfSET =FREQ

500kHz / V +0.2V









1

10µA

The relationship of fSET voltage to switching frequency is

shown in Figure 3. For low output voltages from 0.6V to

1.2V, 250kHz operation is an optimal frequency for the

best power conversion efficiency while maintaining the

applicaTions inForMaTion

Figure 3. Relationship Between Switching

Frequency and Voltage at the fSET Pin

Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)

0.75 0.8

4637 F02

0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9

DUTY CYCLE (VOUT/VIN)

DC LOAD CURRENT

RMS INPUT RIPPLE CURRENT

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

1 PHASE

2 PHASE

3 PHASE

4 PHASE

6 PHASE

fSET PIN VOLTAGE (V)

SWITCHING FREQUENCY (kHz)

0.5 1 1.5 2

4637 F03

2.5

100

300

400

500

900

800

700

200

600

inductor current to about 30% to 40% of maximum load

current. For output voltages from 1.5V to 1.8V, 350kHz is

optimal. For output voltages from 2.5V to 5V, 500kHz is

optimal. See efficiency graphs for optimal frequency set

point. Limit 5V output to 15A.

The LTM4637 can be synchronized from 250kHz to

800kHz with an input clock that has a high level above

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2V and a low level below 0.8V. See the Typical Applica-

tions section for synchronization examples. The LTM4637

minimum on-time is limited to approximately 100ns.

Guardband the on-time to 110ns. The on-time can be

calculated as:

tON(MIN)=1

FREQ •VOUT

VIN











Output Voltage Tracking

Output voltage tracking can be programmed externally

using the TRACK/SS pin. The output can be tracked up

and down with another regulator. The master regulator’s

output is divided down with an external resistor divider

that is the same as the slave regulator’s feedback divider

to implement coincident tracking. The LTM4637 uses an

accurate 60.4k resistor internally for the top feedback

resistor. Figure 4 shows an example of coincident tracking.

VOUT(SLAVE) =1+60.4k

RTA









•VTRACK

VTRACK is the track ramp applied to the slave’s track pin.

VTRACK has a control range of 0V to 0.6V, or the internal

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

output, then the slave will coincident track with the master

until it reaches its final value. The master will continue

to its final value from the slave’s regulation point (see

Figure 5). Voltage tracking is disabled when VTRACK is

more than 0.6V. RTA in Figure 4 will be equal to RFB for

coincident tracking.

The TRACK/SS pin of the master can be controlled by an

external ramp or the soft-start function of that regulator can

be used to develop that master ramp. The LTM4637 can

be used as a master by setting the ramp rate on its track

pin using a soft-start capacitor. A 1.2µA current source

is used to charge the soft-start capacitor. The following

equation can be used:

tSOFT-START =0.6V •CSS

1.2µA











Ratiometric tracking can be achieved by a few simple

calculations and the slew rate value applied to the master’s

TRACK/SS pin. As mentioned above, the TRACK/SS pin

has a control range from 0V to 0.6V. The master’s

TRACK/SS pin slew rate is directly equal to the master’s

output slew rate in volts/time. The equation:

•60.4k =RTB

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in volts/time. When coincident

tracking is desired, then MR and SR are equal, thus RTB

is equal to 60.4k. RTA is derived from equation:

RTA =

0.6V

VFB

60.4k +VFB

–VTRACK

where VFB is the feedback voltage reference of the regula-

tor, and VTRACK is 0.6V. Since RTB is equal to the 60.4k

top feedback resistor of the slave regulator in equal slew

rate or coincident tracking, then RTA is equal to RFB with

VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in

Figure 4.

In ratiometric tracking, a different slew rate maybe desired

for the slave regulator. RTB can be solved for when SR

is slower than MR. Make sure that the slave supply slew

rate is chosen to be fast enough so that the slave output

voltage will reach its final value before the master output.

For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB

= 75k. Solve for RTA to equal 51.1k.

For applications that do not require tracking or sequenc-

ing, simply tie the TRACK/SS pin to INTVCC to let RUN

control the turn on/off. When the RUN pin is below

its threshold or the VIN undervoltage lockout, then

TRACK/SS is pulled low.

Overcurrent and Overvoltage Protection

The LTM4637 has overcurrent protection (OCP) in a

short circuit. The internal current comparator threshold

folds back during a short to reduce the output current. An

overvoltage condition (OVP) above 10% of the regulated

output voltage will force the top MOSFET off and the bottom

MOSFET on until the condition is cleared. Foldback current

limiting is disabled during soft-start or tracking start-up.

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Figure 5. Output Voltage Coincident Tracking Characteristics

4637A F05

TIME

SLAVE OUTPUT

MASTER OUTPUT

OUTPUT

VOLTAGE

Figure 4. Dual Outputs (1.5V and 1.2V) with Tracking

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

10k

RFB1

40.2k

75k

330pF

2.2µF

CSS

SOFT-START

CAPACITOR VOUT2

1.5V

20A

470µF

6.3V

×2

C11

100µF

6.3V

×2

CIN1

22µF

16V

×4INTVCC

EXTVCC

VIN

4.5V TO 16V

SGND GND

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

10k

RFB

60.4k

50k

330pF

VOUT1

1.2V

20A

470µF

6.3V

×2

100µF

6.3V

×2

INTVCC

EXTVCC

4637 F04

SGND GND

RTB

60.4k

RTA

60.4k

MASTER RAMP

OR OUTPUT

VIN

4.5V TO 16V CIN2

22µF

16V

×4

2.2µF

Temperature Monitoring

A diode connected PNP transistor is used for the TEMP

monitor function by monitoring its voltage over tempera-

ture. The temperature dependence of this diode voltage

can be understood in the equation:

VD=nVTln ID











where VT is the thermal voltage (kT/q), and n, the ideality

factor, is 1 for the diode connected PNP transistor be-

ing used in the LTM4637. IS is expressed by the typical

empirical equation:

IS=I0exp –VG0











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where I0 is a process and geometry dependent current, (I0

is typically around 20k orders of magnitude larger than IS

at room temperature) and VG0 is the band gap voltage of

1.2V extrapolated to absolute zero or –273°C.

If we take the IS equation and substitute into the VD equa-

tion, then we get:

VD=VG0 –kT









ln I0









, VT=kT

The expression shows that the diode voltage decreases

(linearly if I0 were constant) with increasing temperature

and constant diode current. Figure 6 shows a plot of VD

vs Temperature over the operating temperature range of

the LTM4637.

If we take this equation and differentiate it with respect to

temperature T, then:

=–

– V

This dVD/dT term is the temperature coefficient equal to

about –2mV/K or –2mV/°C. The equation is simplified for

the first order derivation.

Solving for T, T = –(VG0 – VD)/(dVD/dT) provides the

temperature.

1st Example: Figure 6 for 27°C, or 300K the diode

voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/

–2.0 mV/K)

2nd Example: Figure 6 for 75°C, or 350K the diode

voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/

–2.0mV/K)

Converting the Kelvin scale to Celsius is simply taking the

Kelvin temp and subtracting 273 from it.

A typical forward voltage is given in the electrical charac-

teristics section of the data sheet, and Figure 6 is the plot

of this forward voltage. Measure this forward voltage at

applicaTions inForMaTion

27°C to establish a reference point. Then using the above

expression while measuring the forward voltage over

temperature will provide a general temperature monitor.

Connect a resistor between TEMP and VIN to set the cur-

rent to 100µA. See Figure 22 for an example.

Figure 6. Diode Voltage VD vs Temperature T(°C)

TEMPERATURE (°C)

–50 –25

0.3

DIODE VOLTAGE (V)

0.5

0.8

050 75

0.4

0.7

0.6

25 100

4637 F06

125

ID = 100µA

Overtemperature Protection

The internal overtemperature protection monitors the

internal temperature of the module and shuts off the

regulator at ~130°C to 137°C. Once the regulator cools

down the regulator will restart.

Run Enable

The RUN pin is used to enable the power module or se-

quence the power module. The threshold is 1.25V, and

the pin has an internal 5.1V Zener to protect the pin. The

RUN pin can be used as an undervoltage lockout (UVLO)

function by connecting a resistor divider from the input

supply to the RUN pin:

VUVLO = ((R1+R2)/R2) • 1.25V

See Figure 1, Simplified Block Diagram.

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INTVCC Regulator

The LTM4637 has an internal low dropout regulator from

VIN called INTVCC. This regulator output has a 2.2µF

ceramic capacitor internal. An additional 2.2µF ceramic

capacitor is needed on this pin to ground. This regulator

powers the internal controller and MOSFET drivers. The

gate driver current is ~20mA for 750kHz operation. The

regulator loss can be calculated as:

(VIN – 5V) • 20mA = PLOSS

EXTVCC external voltage source ≥ 4.7V can be applied to

this pin to eliminate the internal INTVCC LDO power loss and

increase regulator efficiency. A 5V supply can be applied

to run the internal circuitry and power MOSFET driver. If

unused, leave pin floating. EXTVCC must be less than VIN

at all times during power-on and power-off sequences.

Stability Compensation

The LTM4637 has already been internally compensated

for all output voltages. Table 5 is provided for most ap-

plication requirements. LTpowerCAD is available for other

control loop optimization.

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those

param-

eters defined by JESD51-12 and are intended for use with

finite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation performed on a

µModule package mounted to a hardware test board.

The motivation for providing these thermal coefficients

in found in JESD51-12 (“Guidelines for Reporting and

Using Electronic Package Thermal Information”).

Many designers may opt to use laboratory equipment

and a test vehicle such as the demo board to predict the

µModule regulator’s thermal performance in their appli-

cation at various electrical and environmental operating

conditions to compliment any FEA activities. Without FEA

software, the thermal resistances reported in the Pin Con-

figuration section are, in and of themselves, not relevant to

providing guidance of thermal performance; instead, the

derating curves provided in this data sheet can be used

in a manner that yields insight and guidance pertaining to

one’s application-usage, and can be adapted to correlate

thermal performance to one’s own application.

The Pin Configuration section gives four thermal coeffi-

cients explicitly defined in JESD51-12; these coefficients

are quoted or paraphrased below:

1 θJA, the thermal resistance from junction to ambient, is

the natural convection junction-to-ambient air thermal

resistance measured in a one cubic foot sealed enclo-

sure. This environment is sometimes referred to as

“still air” although natural convection causes the air to

move. This value is determined with the part mounted

to a 95mm × 76mm PCB with four layers.

2 θJCbottom, the thermal resistance from junction to the

bottom of the product case, is determined with all of

the component power dissipation flowing through the

bottom of the package. In the typical µModule regulator,

the bulk of the heat flows out the bottom of the pack-

age, but there is always heat flow out into the ambient

environment. As a result, this thermal resistance value

may be useful for comparing packages but the test

conditions don’t generally match the user’s application.

3 θJCtop, the thermal resistance from junction to top of

the product case, is determined with nearly all of the

component power dissipation flowing through the top of

the package. As the electrical connections of the typical

µModule regulator are on the bottom of the package, it

is rare for an application to operate such that most of

the heat flows from the junction to the top of the part.

As in the case of θJCbottom, this value may be useful

for comparing packages but the test conditions don’t

generally match the user’s application.

4 θJB, the thermal resistance from junction to the printed

circuit board, is the junction-to-board thermal resistance

where almost all of the heat flows through the bottom

of the µModule package and into the board, and is really

the sum of the θJCbottom and the thermal resistance of

the bottom of the part through the solder joints and a

portion of the board. The board temperature is measured

a specified distance from the package.

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A graphical representation of the aforementioned ther-

mal resistances is given in Figure 7; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package.

As a practical matter, it should be clear to the reader that

no individual or sub-group of the four thermal resistance

parameters defined by JESD51-12 or provided in the Pin

Configuration section replicates or conveys normal op-

erating conditions of a µModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally con-

duct exclusively through the top or exclusively through

bottom of the µModule package—as the standard defines

for θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4637, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

complication without sacrificing modeling simplicity—but

also not ignoring practical realities—an approach has been

taken using FEA software modeling along with laboratory

testing in a controlled-environment chamber to reason-

ably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4637 and the specified PCB with all of the correct

material coefficients along with accurate power loss source

definitions; (2) this model simulates a software-defined

JEDEC environment consistent with JESD51-12 to predict

power loss heat flow and temperature readings at different

interfaces that enable the calculation of the JEDEC-defined

thermal resistance values; (3) the model and FEA software

is used to evaluate the LTM4637 with heat sink and airflow;

(4) having solved for and analyzed these thermal resis-

tance values and simulated various operating conditions

in the software model, a thorough laboratory evaluation

replicates the simulated conditions with thermocouples

within a controlled-environment chamber while operat-

ing the device at the same power loss as that which was

simulated. The outcome of this process and due diligence

yields the set of derating curves shown in this data sheet.

The 1V, 2.5V and 5V power loss curves in Figures 8 to 10

can be used in coordination with the load current derating

curves in Figures 11 to 20 for calculating an approximate

θJA thermal resistance for the LTM4637 with various

heat sinking and airflow conditions. The power loss

curves are taken at room temperature and are increased

with a multiplicative factor according to the junction

temperature, which is 1.4 for 120°C. The derating curves

are plotted with the output current starting at 20A and the

Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients

4637 F07

µMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION At

CASE (BOTTOM)-TO-BOARD

RESISTANCE

LTM4637

4637fc

For more information www.linear.com/LTM4637

Figure 8. 1VOUT Power Loss Figure 9. 2.5VOUT Power Loss

applicaTions inForMaTion

Figure 10. 5VOUT Power Loss

ambient temperature at ~40°C. The output voltages are

1V, 2.5V and 5V. These are chosen to include the lower,

middle and higher output voltage ranges for correlating

the thermal resistance. Thermal models are derived

from several temperature measurements in a controlled

temperature chamber along with thermal modeling

analysis. The junction temperatures are monitored while

ambient temperature is increased with and without airflow.

The power loss increase with ambient temperature change

is factored into the derating curves. The junctions are

maintained at ~120°C maximum while lowering output

current or power with increasing ambient temperature.

The decreased output current will decrease the internal

module loss as ambient temperature is increased.

The monitored junction temperature of 120°C minus

the ambient operating temperature specifies how much

module temperature rise can be allowed. As an example, in

Figure 13 the load current is derated to ~16A at ~80°C with

no air or heat sink and the power loss for the 12V to 1.0V at

16A output is about 4W. The 4W loss is calculated with the

~2.8W room temperature loss from the 12V to 1.0V power

loss curve at 16A, and the 1.4 multiplying factor at 120°C

junction. If the 80°C ambient temperature is subtracted

from the 120°C junction temperature, then the difference

of 40°C divided by 4W equals a 10°C/W θJA thermal

resistance. Table 2 specifies a 9.3°C/W value which is very

close. Table 2 provides equivalent thermal resistances for

1.0V, 2.5V and 5V outputs with and without airflow and

heat sinking. The derived thermal resistances in Tables 2

thru 4 for the various conditions can be multiplied by the

calculated power loss as a function of ambient temperature

to derive temperature rise above ambient, thus maximum

junction temperature. Room temperature power loss

can be derived from the efficiency curves in the Typical

Performance Characteristics section and adjusted with

the above ambient temperature multiplicative factors. The

printed circuit board is a 1.6mm thick four layer board with

two ounce copper for the two outer layers and one ounce

copper for the two inner layers. The PCB dimensions are

95mm × 76mm. The BGA heat sinks are listed in Table 6.

OUTPUT CURRENT (A)

POWER LOSS (W)

2.5

3.0

3.5

4637 F08

2.0

1.5

0510 15

1.0

0.5

4.5

4.0

5V TO 1V PLOSS

12V TO 1V PLOSS

OUTPUT CURRENT (A)

POWER LOSS (W)

2.5

3.0

3.5

4637 F09

2.0

1.5

0510 15

1.0

0.5

5.0

4.5

4.0

5V TO 2.5V PLOSS

12V TO 2.5V PLOSS

OUTPUT CURRENT (A)

4637 F10

5 10 20

POWER LOSS (W)

12V TO 5V PLOSS

8V TO 5V PLOSS

LTM4637

4637fc

For more information www.linear.com/LTM4637

Figure 11. 5VIN to 1.0VOUT No Heat Sink

Figure 14. 12VIN to 1.0VOUT with Heat Sink Figure 15. 5VIN to 2.5VOUT No Heat Sink

applicaTions inForMaTion

Figure 13. 12VIN to 1.0VOUT No Heat Sink

Figure 12. 5VIN to 1.0VOUT with Heat Sink

Figure 16. 5VIN to 2.5VOUT with Heat Sink

Figure 17. 12VIN to 2.5VOUT No Heat Sink Figure 18. 12VIN to 2.5VOUT with Heat Sink

TEMPERATURE (°C)

OUTPUT CURRENT (A)

60 80 90 130

4637 F11

50 70 100 110 120

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

70 90 110

4637 F13

50 60 80 100

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

70 90 110

4637 F14

50 60 80 100

200 LFM

200 LFM HEAT SINK

400 LFM HEAT SINK

TEMPERATURE (°C)

OUTPUT CURRENT (A)

70 90 130120

4637 F15

50 60 80 100 110

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

70 90 130120

4637 F16

50 60 80 100 110

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

70 90 120

4637 F17

50 60 80 100 110

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

70 90 120

4637 F18

50 60 80 100 110

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

60 80 90 130

4637 F12

50 70 100 110 120

100 LFM

200 LFM

400 LFM

LTM4637

4637fc

For more information www.linear.com/LTM4637

Table 2. 1V Output

DERATING

CURVE VIN

POWER LOSS

CURVE

AIRFLOW

(LFM)HEAT SINK

LGA

θJA (°C/W)

BGA

θJA (°C/W)

Figures 11, 13 5V, 12VFigure 8 0 None 9.3 10.4

Figures 11, 13 5V, 12VFigure 8 200 None 7.0 8.4

Figures 11, 13 5V, 12VFigure 8 400 None 6.0 7.4

Figures 12, 14 5V, 12VFigure 8 0 BGA Heat Sink 7.0 8.9

Figures 12, 14 5V, 12VFigure 8 200 BGA Heat Sink 6.0 6.9

Figures 12, 14 5V, 12VFigure 8 400 BGA Heat Sink 5.0 5.9

Table 3. 2.5V Output

DERATING

CURVE VIN

POWER LOSS

CURVE

AIRFLOW

(LFM)HEAT SINK

LGA

θJA (°C/W)

BGA

θJA (°C/W)

Figures 15, 17 5V, 12VFigure 9 0 None 9.5 10.4

Figures 15, 17 5V, 12VFigure 9 200 None 8.0 8.4

Figures 15, 17 5V, 12VFigure 9 400 None 7.0 7.4

Figures 16, 18 5V, 12VFigure 9 0 BGA Heat Sink 8.0 8.9

Figures 16, 18 5V, 12VFigure 9 200 BGA Heat Sink 6.5 6.9

Figures 16, 18 5V, 12VFigure 9 400 BGA Heat Sink 5.5 5.9

Table 4. 5V Output (5V Output Connected to EXTVCC Pin)

DERATING

CURVE VIN

POWER LOSS

CURVE

AIRFLOW

(LFM)HEAT SINK

LGA

θJA (°C/W)

BGA

θJA (°C/W)

Figures 19 12VFigure 10 0None 9.5 10.4

Figures 19 12VFigure 10 200 None 8.0 8.9

Figures 19 12VFigure 10 400 None 7.0 7.9

Figures 20 12VFigure 10 0BGA Heat Sink 8.0 8.9

Figures 20 12VFigure 10 200 BGA Heat Sink 6.5 7.4

Figures 20 12VFigure 10 400 BGA Heat Sink 5.5 6.4

applicaTions inForMaTion

Figure 19. 12VIN to 5VOUT No Heat Sink, EXTVCC = 5V

(Limit 5V Output to 15A)

Figure 20. 12VIN to 5VOUT with Heat Sink, EXTVCC = 5V

(Limit 5V Output to 15A)

TEMPERATURE (°C)

OUTPUT CURRENT (A)

100

4637 F19

030 40 50 50 70 80 90 110 120

0 LFM

200 LFM

400 LFM

TEMPERATURE (°C)

OUTPUT CURRENT (A)

100

4637 F20

030 40 50 50 70 80 90 110 120

0 LFM

200 LFM

400 LFM

LTM4637

4637fc

For more information www.linear.com/LTM4637

applicaTions inForMaTion

Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 22) 0A to 10A Load Step

COUT1 AND

COUT2 CERAMIC

VENDOR VALUE PART NUMBER

COUT1 AND

COUT2 BULK

VENDOR VALUE PART NUMBER

CIN

VENDOR VALUE PART NUMBER

TDK 100µF 6.3V C4532X5R0J107MZ Sanyo POSCAP 1000µF 2.5V 2R5TPD1000M5 Sanyo 56µF 25V 25SVP56M

Murata 100µF 6.3V GRM32ER60J107M Sanyo POSCAP 470µF 2.5V 2R5TPD470M5 TDK 22µF 16V C3216X651C226M

Sanyo POSCAP 470µF 6.3V 6TPD470M5 Murata 22µF 16V GRM31CR61C226KE15L

VOUT

(V)

CIN

(CERAMIC)

CIN

(BULK)†COUT2 (CERAMIC)

AND COUT1 (BULK)

CFF

(pF)

CCOMP

(pF)

VIN

(V)

DROOP

(mV)

PEAK-TO-PEAK

DEVIATION

(mV)

RECOVERY

TIME (µs)

LOAD

STEP

(A/µs)

RFB

(kΩ)

FREQ

(kHz)

122µF × 4 56µF 100µF × 2, 470µF × 3 330 150 5,12 65 123 30 10 90.6 250

1.2 22µF × 4 56µF 100µF × 2, 470µF × 3 330 150 5,12 65 123 30 10 60.4 250

1.5 22µF × 4 56µF 100µF × 2, 470µF × 3 330 150 5,12 65 120 50 10 40.2 350

1.8 22µF × 4 56µF 100µF × 2, 470µF × 3 330 150 5,12 65 120 60 10 30.1 350

2.5 22µF × 4 56µF 100µF × 2, 470µF × 3 330 150 5,12 65 130 70 10 19.1 450

3.3 22µF × 4 56µF 100µF × 2, 470µF × 3 330 150 5,12 75 150 75 10 13.3 600

522µF × 4 56µF 100µF × 2, 470µF × 3 330 150 7,12 100 195 80 10 8.25 600

122µF × 4 56µF 100µF × 2, 470µF × 3 330 None 5,12 50 100 30 10 90.6 250

1.2 22µF × 4 56µF 100µF × 2, 470µF × 3 330 None 5,12 50 100 30 10 60.4 250

1.5 22µF × 4 56µF 100µF × 2, 470µF × 3 330 None 5,12 50 100 50 10 40.2 350

1.8 22µF × 4 56µF 100µF × 2, 470µF × 3 330 None 5,12 65 110 60 10 30.1 350

2.5 22µF × 4 56µF 100µF × 2, 470µF × 3 330 None 5,12 65 120 70 10 19.1 450

3.3 22µF × 4 56µF 100µF × 2, 470µF × 3 330 None 5,12 70 130 75 10 13.3 600

522µF × 4 56µF 100µF × 2, 470µF × 3 330 None 7,12 85 165 80 10 8.25 600

122µF × 4 56µF 100µF × 2, 470µF × 2 330 None 5,12 75 150 30 10 90.6 250

1.2 22µF × 4 56µF 100µF × 2, 470µF × 2 330 None 5,12 75 150 30 10 60.4 250

1.5 22µF × 4 56µF 100µF × 2, 470µF × 2 330 None 5,12 70 140 50 10 40.2 350

1.8 22µF × 4 56µF 100µF × 2, 470µF × 2 330 None 5,12 65 130 60 10 30.1 350

2.5 22µF × 4 56µF 100µF × 2, 470µF × 2 330 None 5,12 65 130 70 10 19.1 450

3.3 22µF × 4 56µF 100µF × 2, 470µF × 2 330 None 5,12 70 140 75 10 13.3 600

522µF × 4 56µF 100µF × 2, 470µF × 2 330 None 7,12 100 190 80 10 8.25 600

122µF × 4 56µF 100µF × 4, 470µF × 1 47 None 5,12 95 190 30 10 90.6 250

1.2 22µF × 4 56µF 100µF × 4, 470µF × 1 47 None 5,12 95 190 30 10 60.4 250

1.5 22µF × 4 56µF 100µF × 4, 470µF × 1 47 None 5,12 90 180 50 10 40.2 350

1.8 22µF × 4 56µF 100µF × 4, 470µF × 1 47 None 5,12 95 190 60 10 30.1 350

2.5 22µF × 4 56µF 100µF × 4, 470µF × 1 47 None 5,12 100 200 70 10 19.1 450

3.3 22µF × 4 56µF 100µF × 4, 470µF × 1 47 None 5,12 125 250 75 10 13.3 600

522µF × 4 56µF 100µF × 4, 470µF × 1 47 None 7,12 155 310 80 10 8.25 600

122µF × 4 56µF 100µF × 5 47 None 5,12 100 200 35 10 90.6 250

1.2 22µF × 4 56µF 100µF × 5 47 None 5,12 100 200 35 10 60.4 250

1.5 22µF × 4 56µF 100µF × 5 47 None 5,12 100 200 35 10 40.2 350

1.8 22µF × 4 56µF 100µF × 5 47 None 5,12 112 225 35 10 30.1 350

2.5 22µF × 4 56µF 100µF × 5 47 None 5,12 125 250 40 10 19.1 450

3.3 22µF × 4 56µF 100µF × 5 47 None 5,12 170 340 40 10 13.3 600

522µF × 4 56µF 100µF × 5 47 None 7,12 225 450 60 10 8.25 600

†Bulk capacitance is optional if VIN has very low input impedance.

LTM4637

4637fc

For more information www.linear.com/LTM4637

applicaTions inForMaTion

Safety Considerations

The LTM4637 does not provide galvanic isolation from VIN

to VOUT. There is no internal fuse. If required, a slow blow

fuse with a rating twice the maximum input current needs

to be provided to protect each unit from catastrophic failure.

The fuse or circuit breaker should be selected to limit the

current to the regulator during overvoltage in case of an

internal top MOSFET fault. If the internal top MOSFET fails,

then turning it off will not resolve the overvoltage, thus

the internal bottom MOSFET will turn on indefinitely trying

to protect the load. Under this fault condition, the input

voltage will source very large currents to ground through

the failed internal top MOSFET and enabled internal bot-

tom MOSFET. This can cause excessive heat and board

damage depending on how much power the input voltage

can deliver to this system. A fuse or circuit breaker can be

used as a secondary fault protector in this situation. The

LTM4637 does support overvoltage protection, overcurrent

protection and overtemperature protection.

Layout Checklist/Example

The high integration of the LTM4637 makes the PCB

board layout very simple and easy. However, to optimize

its electrical and thermal performance, some layout

considerations are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output

capacitors next to the VIN, GND and VOUT pins to

minimize high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put vias directly on the pad, unless they are

capped or plated over.

• Place test points on signal pins for testing.

• Use a separated SGND ground copper area for

components connected to signal pins. Connect the

SGND to GND underneath the unit.

• For parallel modules, tie the COMP and VFB pins together.

Use an internal layer to closely connect these pins

together.

Figure 21 gives a good example of the recommended layout.

Table 6. Recommended Heat Sinks

HEAT SINK MANUFACTURER PART NUMBER WEBSITE

AAVID Thermalloy 375424B00034Gwww.aavidthermalloy.com

Cool Innovations 4-050503P to 4-050508Pwww.coolinnovations.com

LTM4637

4637fc

For more information www.linear.com/LTM4637

applicaTions inForMaTion

Figure 21. Recommended PCB Layout

(LGA Shown, for BGA Use Circle Pads)

GND

VIN

CONTROL

4637 F21

CONTROL

SIGNAL

GROUND

VOUT VOUT

COUT COUT

CIN CIN

Typical applicaTions

Figure 22. 4.5V to 20VIN, 1.5V at 20A Design

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

10k

RFB

40.2k

75k

VIN

CIN

22µF

25V

×4

CFF

330pF

2.2µF

0.1µF

470µF

6.3V

×2

100µF

6.3V

×2

VOUT

1.5V

20A

COUT1*COUT2*

INTVCC

EXTVCC

CONTINUOUS

MODE

*SEE TABLE 5

4627 F22

VIN

4.5V TO 20V

SGND GND

A/D

RT = VIN – 0.6V

100µA

LTM4637

4637fc

For more information www.linear.com/LTM4637

Figure 23. 3.3V at 40A, Two Parallel Outputs with 2-Phase Operation

Typical applicaTions

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

RFB1

6.65k

10k

VIN

5V TO 16V C10

22µF

25V

22µF

25V

200k

500kHz

C13

0.1µF

220µF

6.3V C11

100µF

6.3V

×2

22µF

25V

INTVCC

CLOCK SYNC 0 PHASE

CLOCK SYNC 180 PHASE

SGND GND

2.2µF

C14

1µF

EXTVCC

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

22µF

25V

22µF

25V

220µF

6.3V C6

100µF

6.3V

×2

22µF

25V

INTVCC

2.2µF

EXTVCC

4627 F23

SGND GND

V+

GND

SET

OUT1

OUT2

MOD

LTC6908-1

3.3V

40A

100k

330pF

INTVCC

LTM4637

4637fc

For more information www.linear.com/LTM4637

Typical applicaTions

Figure 24. 1.2V, 80A, Current Sharing with 4-Phase Operation

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

RFB2

15k

10k

C22

22µF

25V

200k

4-PHASE CLOCK

C28

0.1µF

470pF

2.2µF

VIN

5V TO 16V

VOUT

1.2V AT 80A

C21

470µF

6.3V

×2

C15

470µF

6.3V

×2

C18

100µF

6.3V

×2

470µF

6.3V

×2

C11

100µF

6.3V

×2

470µF

6.3V

×2

100µF

6.3V

×2

C24

100µF

6.3V

×2

C20

22µF

25V INTVCC

SGND GND

1µF

EXTVCC

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN INTVCC

INTVCC

SGND GND

EXTVCC

V+

DIV

OUT1

OUT2

SET

MOD

GND

OUT4

OUT3

LTC6902

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN INTVCC

SGND GND

EXTVCC

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN INTVCC

4637 F24

SGND GND

EXTVCC

50k

C18

22µF

25V

C14

22µF

25V

22µF

25V

22µF

25V

22µF

25V

22µF

25V

22µF

25V

22µF

25V

2.2µF

LTM4637

4637fc

For more information www.linear.com/LTM4637

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

A1 VIN B1 VIN C1 VIN D1 GND E1 GND F1 GND

A2 VIN B2 VIN C2 VIN D2 GND E2 GND F2 GND

A3 VIN B3 VIN C3 VIN D3 GND E3 GND F3 GND

A4 VIN B4 VIN C4 VIN D4 GND E4 GND F4 GND

A5 VIN B5 VIN C5 VIN D5 GND E5 GND F5 GND

A6 VIN B6 VIN C6 VIN D6 GND E6 GND F6 GND

A7 INTVCC B7 GND C7 GND D7 – E7 GND F7 GND

A8 MODE_PLLIN B8 – C8 – D8 GND E8 – F8 GND

A9 TRACK/SS B9 GND C9 GND D9 INTVCC E9 GND F9 GND

A10 RUN B10 – C10 MTP3 D10 TEMP E10 – F10 –

A11 COMP B11 MTP2 C11 MTP4 D11 MTP6 E11 – F11 PGOOD

A12 MTP1 B12 fSET C12 MTP5 D12 MTP7 E12 EXTVCC F12 VFB

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION

G1 GND H1 GND J1 VOUT K1 VOUT L1 VOUT M1 VOUT

G2 GND H2 GND J2 VOUT K2 VOUT L2 VOUT M2 VOUT

G3 GND H3 GND J3 VOUT K3 VOUT L3 VOUT M3 VOUT

G4 GND H4 GND J4 VOUT K4 VOUT L4 VOUT M4 VOUT

G5 GND H5 GND J5 VOUT K5 VOUT L5 VOUT M5 VOUT

G6 GND H6 GND J6 VOUT K6 VOUT L6 VOUT M6 VOUT

G7 GND H7 GND J7 VOUT K7 VOUT L7 VOUT M7 VOUT

G8 GND H8 GND J8 VOUT K8 VOUT L8 VOUT M8 VOUT

G9 GND H9 GND J9 VOUT K9 VOUT L9 VOUT M9 VOUT

G10 – H10 – J10 VOUT K10 VOUT L10 VOUT M10 VOUT

G11 SGND H11 SGND J11 – K11 VOUT L11 VOUT M11 VOUT

G12 PGOOD H12 SGND J12 VOSNS+ K12 DIFF_OUT L12 VOUT_LCL M12 VOSNS–

pacKage DescripTion

Pin Assignment Table (Arranged by Pin Number)

pacKage phoTo

PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY.

LTM4637

4637fc

For more information www.linear.com/LTM4637

pacKage DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

LAND DESIGNATION PER JESD MO-222, SPP-010

5. PRIMARY DATUM -Z- IS SEATING PLANE

6. THE TOTAL NUMBER OF PADS: 133

DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE

SYMBOL

aaa

bbb

eee

TOLERANCE

0.15

0.10

0.05

4.22 – 4.42

DETAIL B

SUBSTRATE

MOLD

CAP

0.27 – 0.37

3.95 – 4.05

bbb Z

BSC

8.42

BSC

3.29

BSC

PACKAGE TOP VIEW

BSC

3.54

BSC

2.18

BSC

PAD 1

CORNER

aaa Z

DETAIL A

13.97

BSC

1.27

BSC

13.97

BSC

0.12 – 0.28

L K J H G F E D C B

PACKAGE BOTTOM VIEW

C(0.30)

PAD 1

PADS

SEE NOTES M A

DETAIL A

0.630 ±0.025 SQ. 133x

SYXeee

SUGGESTED PCB LAYOUT

TOP VIEW

0.0000

0.6350

1.9050

3.1750

4.4450

5.7150

6.9850

5.7150

4.4450

3.1750

1.9050

0.6350

0.0000

6.9850

LGA 133 0811 REV Ø

LTMXXXXXX

µModule

TRAY PIN 1

BEVEL

PACKAGE IN TRAY LOADING ORIENTATION

COMPONENT

PIN “A1”

0.630

LGA Package

133-Lead (15mm × 15mm × 4.32mm)

(Reference LTC DWG # 05-08-1906 Rev Ø)

LTM4637

4637fc

For more information www.linear.com/LTM4637

pacKage DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

BALL DESIGNATION PER JESD MS-028 AND JEP95

DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE

PACKAGE TOP VIEW

PIN “A1”

CORNER

aaa Z

PACKAGE BOTTOM VIEW

PIN 1

SEE NOTES

SUGGESTED PCB LAYOUT

TOP VIEW

BGA 133 0213 REV Ø

LTMXXXXXX

µModule

TRAY PIN 1

BEVEL PACKAGE IN TRAY LOADING ORIENTATION

COMPONENT

PIN “A1”

DETAIL A

0.0000

DETAIL A

Øb (133 PLACES)

DETAIL B

SUBSTRATE

0.27 – 0.37

3.95 – 4.05

// bbb Z

ccc Z

DETAIL B

PACKAGE SIDE VIEW

MOLD

CAP

MX YZddd

MZeee

0.630 ±0.025 Ø 133x SYMBOL

aaa

bbb

ccc

ddd

eee

MIN

4.72

0.50

4.22

0.60

NOM

4.92

0.60

4.32

0.75

0.63

15.0

1.27

13.97

MAX

5.12

0.70

4.42

0.90

0.66

0.15

0.10

0.20

0.30

0.15

NOTES

DIMENSIONS

TOTAL NUMBER OF BALLS: 133

BGA Package

133-Lead (15mm × 15mm × 4.92mm)

(Reference LTC DWG # 05-08-1940 Rev Ø)

0.6350

1.9050

3.1750

4.4450

5.7150

6.9850

5.7150

4.4450

3.1750

1.9050

0.6350

6.9850

FGHM L JK E ABCD

5. PRIMARY DATUM -Z- IS SEATING PLANE

6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE

LAYOUT CAREFULLY

SEE NOTES

8.42

BSC

3.29

BSC

3.54

BSC

2.18

BSC

LTM4637

4637fc

For more information www.linear.com/LTM4637

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 07/13 Added instruction to TEMP pin usage

Updated all graphs

19, 20

B 10/13 Added BGA package 1, 2, 28

C 02/14 Added SnPb BGA package option 1, 2

LTM4637

4637fc

For more information www.linear.com/LTM4637

 LINEAR TECHNOLOGY CORPORATION 2013

LT 0214 REV C • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM4637

relaTeD parTs

Design resources

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTM4609 Buck-Boost DC/DC µModule Family All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm × 15mm × 2.82mm

LTM4612 Ultralow Noise High VOUT DC/DC µModule Regulator 5A, 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 2.82mm Package

LTM4627 15A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, LGA and BGA Packages

LTM4620 Dual 13A, Single 26A DC/DC µModule Regulator Up to 100A with Four in Parallel, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V

COMP

TRACK/SS

RUN

fSET

MODE_PLLIN

TEMP

PGOOD

VOUT

VOUT_LCL

DIFF_OUT

VOSNS+

VOSNS–

VFB

LTM4637

VIN

10k

RFB

30.1k

75k

CIN

22µF

25V

×4C7

0.1µF C4

100µF

6.3V

X5R

×2

470µF

VOUT

1.8V

20A

INTVCC

EXTVCC

CONTINUOUS MODE

4627 TA02

SGND GND

47pF

1.8V at 20A Design

SUBJECT DESCRIPTION

µModule Design and Manufacturing Resources Design:

• Selector Guides

• Demo Boards and Gerber Files

• Free Simulation Tools

Manufacturing:

• Quick Start Guide

• PCB Design, Assembly and Manufacturing Guidelines

• Package and Board Level Reliability

µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.

2. Search using the Quick Power Search parametric table.

TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products.

Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that

offer essential functions, including power supply monitoring, supervision, margining and sequencing,

and feature EEPROM for storing user configurations and fault logging.