ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 12-Bit Octal-Channel ADC Family Up to 65MSPS Check for Samples: ADS5281, ADS5282 LCLKN 12x ADCLK PLL ADCLKP 1x ADCLK ADCLKN PowerDown Channels 2 to 7 OUT8P OUT8N Drive Current ADC Control PD SCLK SDATA CS RESET OUT1N Test Patterns Output Format Digital Gain (0dB to 12dB) REFT REFB VCM ISET Serializer Registers Reference INT/EXT Digital OUT1P 1/4 12-Bit ADC Serializer 1/4 1/4 IN8P IN8N Digital 1/4 12-Bit ADC 1/4 IN1P IN1N 1/4 Medical Imaging Wireless Base-Station Infrastructure Test and Measurement Instrumentation LCLKP 6x ADCLK Clock Buffer APPLICATIONS * * * LVDD (1.8V) The ADS528x is a family of high-performance, lowpower, octal channel analog-to-digital converters (ADCs). Available in either a 9mm x 9mm QFN package or an HTQFP-80 package, with serialized low-voltage differential signaling (LVDS) outputs and a wide variety of programmable features, the ADS528x is highly customizable for a diversity of applications and offers an unprecedented level of system integration. An application note, XAPP774 (available at www.xilinx.com), describes how to interface the serial LVDS outputs of TI's ADCs to Xilinx(R) field-programmable gate arrays (FPGAs). The ADS528x family is specified over the industrial temperature range of -40C to +85C. AVDD (3.3V) * Speed and Resolution Grades: - ADS5281: 12-bit, 50MSPS - ADS5282: 12-bit, 65MSPS * Power Dissipation: - 48mW/Channel at 30MSPS - 55mW/Channel at 40MSPS - 64mW/Channel at 50MSPS - 77mW/Channel at 65MSPS * 70dBFS SNR at 10MHz IF * Analog Input Full-Scale Range: 2VPP * Low-Frequency Noise Suppression Mode * 6dB Overload Recovery In One Clock * External and Internal (Trimmed) Reference * 3.3V Analog Supply, 1.8V Digital Supply * Single-Ended or Differential Clock: - Clock Duty Cycle Correction Circuit (DCC) * Programmable Digital Gain: 0dB to 12dB * Serialized DDR LVDS Output * Programmable LVDS Current Drive, Internal Termination * Test Patterns for Enabling Output Capture * Straight Offset Binary or Two's Complement Output * Package Options: - 9mm x 9mm QFN-64 - HTQFP-80 PowerPADTM Compatible with ADS527x Family 234 (AVSS) CLKN DESCRIPTION (ADCLK) CLKP FEATURES 1 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. Xilinx is a registered trademark of Xilinx, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. RELATED PRODUCTS MODEL RESOLUTION (BITS) SAMPLE RATE (MSPS) CHANNELS ADS5281 12 50 8 ADS5282 12 65 8 ADS5287 10 65 8 ADS5270 12 40 8 ADS5271 12 50 8 ADS5272 12 65 8 ADS5273 12 70 8 ADS5242 12 65 4 Table 1. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR HTQFP-80 (PowerPAD) PFP QFN-64 RGC ADS5281 ADS5282 (1) (2) (3) SPECIFIED TEMPERATURE RANGE (2) PACKAGE MARKING ORDERING NUMBER ADS5281I -40C to +85C QFN-64 RGC AZ5281 -40C to +85C AZ5282 TRANSPORT MEDIA, QUANTITY (3) ADS5281IPFP Tray ADS5281PFPR Tape and Reel ADS5281IRGCT Tape and Reel ADS5281IRGCR Tape and Reel ADS5282IRGCT Tape and Reel ADS5282IRGCR Tape and Reel For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. These devices meet the following planned eco-friendly classification: Green (RoHS and No Sb/Br): Texas Instruments defines Green to mean Pb-free (RoHS compatible) and free of bromine (Br)- and antimony (Sb)-based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. These devices have a Cu NiPdAu lead/ball finish. Refer to the Package Option Addendum at the end of this document for specific transport media and quantity information. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS528x UNIT Supply voltage range, AVDD -0.3 to +3.9 V Supply voltage range, LVDD -0.3 to +2.2 V Voltage between AVSS and LVSS -0.3 to +0.3 V External voltage applied to REFT pin -0.3 to +3 V External voltage applied to REFB pin -0.3 to +2 V Voltage applied to analog input pins -0.3 to minimum [3.6, (AVDD + 0.3)] V Voltage applied to digital input pins -0.3 to minimum [3.9, (AVDD + 0.3)] V Peak solder temperature +260 C Junction temperature +125 C -65 to +150 C Storage temperature range (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS (1) ADS528x PARAMETER MIN TYP MAX UNIT V SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES AVDD Analog supply voltage 3.0 3.3 3.6 LVDD Digital supply voltage 1.7 1.8 1.9 Differential input voltage range Input common-mode voltage V 2 VPP VCM 0.05 V REFT External reference mode 2.5 V REFB External reference mode 0.5 V CLOCK INPUTS ADCLK input sample rate 1/ tC 10 50, 65 MSPS Input clock amplitude differential (VCLKP-VCLKN) peak-to-peak Sine wave, ac-coupled 3.0 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Input clock CMOS, single-ended (VCLKP) VIL 0.6 VIH 2.2 Input clock duty cycle V V 50 % DIGITAL OUTPUTS ADCLKP and ADCLKN outputs (LVDS) 10 1x (sample rate) 50, 65 MHz LCLKP and LCLKN outputs (LVDS) 60 6x (sample rate) 300, 390 MHz CLOAD Maximum external capacitance from each pin to LVSS RLOAD Differential load resistance between the LVDS output pairs TA Operating free-air temperature (1) 5 pF 100 -40 +85 C All conditions are common to the ADS528x family. INITIALIZATION REGISTERS After the device has been powered up, the following registers must be written to (in the exact order listed below) through the serial interface as part of an initialization sequence. (1) ADDRESS (hex) DATA (hex) 03 0002 (1) 01 0010 Initialization Register 3 (1) C7 8001 Initialization Register 4 (1) DE 01C0 Initialization Register 1 (1) Initialization Register 2 (1) It is no longer necessary to write these initialization registers. However, customers who have already included them in their software can continue to use them. Programming these registers does not affect device performance. If the analog input is ac-coupled, the following registers must be written to in the order listed below. ADDRESS (hex) DATA (hex) Initialization Register 1 01 0010 Initialization Register 5 E2 00C0 To disable the PLL configuration switching (especially useful in systems where a system-level timing calibration is done once after power-up), the following registers must be written to in the order listed below. Also, see section PLL Operation Across Sampling Frequency. ADDRESS (hex) For 10 Fs 25 (1) For 15 Fs = 45 (1) (1) DATA (hex) E3 0060 E3 00A0 where Fs = sampling clock frequency Copyright (c) 2006-2012, Texas Instruments Incorporated 3 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com DIGITAL CHARACTERISTICS DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. At CLOAD = 5pF (1), IOUT = 3.5mA (2), RLOAD = 100 (2), and no internal termination, unless otherwise noted. ADS528x PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 1.4 V Low-level input voltage 0.3 V High-level input current 33 A Low-level input current -33 A 3 pF High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 350 mV Common-mode voltage of OUTP and OUTN 1200 mV Output capacitance inside the device, from either output to ground 2 pF Input capacitance LVDS OUTPUTS VOS output offset voltage Output capacitance (1) (2) 4 CLOAD is the effective external single-ended load capacitance between each output pin and ground. IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS (1) Typical values at +25C. Minimum and maximum values are measured across the specified temperature range of TMIN = -40C to TMAX = +85C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, -1dBFS differential analog input, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. ADS528x PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE VOLTAGES VREFB Reference bottom 0.5 VREFT Reference top 2.5 VCM V V VREFT - VREFB 1.95 2.0 2.05 Common-mode voltage (internal) 1.425 1.5 1.575 VCM output current 2 V V mA EXTERNAL REFERENCE VOLTAGES VREFB Reference bottom 0.4 0.5 0.6 V VREFT Reference top 2.4 2.5 2.6 V VREFT - VREFB 1.9 2.0 2.1 V ANALOG INPUT Differential input voltage range 2.0 Differential input capacitance Analog input bandwidth VPP 3 pF 520 MHz Analog input common-mode range DC-coupled input VCM 0.05 V Analog input common-mode current Per input pin per MSPS of sampling speed 2.5 A/MHz per pin Recovery from 6dB overload to within 1% accuracy 1 Clock cycle Standard deviation seen on a periodic first data within full-scale range in a 6dB overloaded sine wave 1 LSB Voltage overload recovery time Voltage overload recovery repeatability DC ACCURACY Offset error -1.25 Offset error temperature coefficient (2) DC PSRR 0.2 +1.25 %FS 5 ppm/C Channel gain error Excludes error in internal reference -0.8 %FS Channel gain error temperature coefficient Excludes temperature coefficient of internal reference 10 ppm/C Internal reference error temperature coefficient (3) 15 ppm/C DC power-supply rejection ratio (4) 1.5 mV/V POWER-DOWN MODES Power in complete power-down mode Power in partial power-down mode 45 mW 135 mW 88 mW 5MHz full-scale signal applied to seven channels, measurement taken on channel with no input signal -90 dBc f1 = 9.5MHz at -7dBFs f2 = 10.2MHz at -7dBFs -92 dBFS Clock at 65MSPS Power with no clock DYNAMIC PERFORMANCE Crosstalk Two-tone, third-order intermodulation distortion (1) (2) (3) (4) All characteristics are common for the ADS528x family. The offset temperature coefficient in ppm/C is defined as (O1 - O2) x 106/(T1 - T2)/4096, where O1 and O2 are the offset codes in LSB at the two extreme temperatures, T1 and T2. The internal reference temperature coefficient is defined as (REF1 - REF2) x 106/(T1 - T2)/2, where REF1 and REF2 are the internal reference voltages (VREFT - VREFB) at the two extreme temperatures, T1 and T2. DC PSRR is defined as the ratio of the change in the ADC output (expressed in mV) to the change in supply voltage (in volts). Copyright (c) 2006-2012, Texas Instruments Incorporated 5 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (BY DEVICE) (1) Typical values at +25C. Minimum and maximum values are measured across the specified temperature range of TMIN = -40C to TMAX = +85C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, -1dBFS differential analog input, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. ADS5281 HTQFP-80 50MSPS PARAMETER TEST CONDITIONS MIN TYP ADS5281 QFN-64 50MSPS MAX MIN TYP ADS5282 QFN-64 65MSPS MAX MIN TYP MAX UNIT DC ACCURACY No missing codes Assured Assured Assured DNL Differential nonlinearity -0.75 0.25 +0.75 -0.75 0.25 +0.75 -0.9 0.3 +0.9 LSB INL Integral nonlinearity -1.5 0.7 +1.5 -1.5 0.7 +1.5 -1.7 0.7 +1.7 LSB 119 145 119 145 145 170 mA 76 95 76 95 89 102 mA 530 649.5 530 649.5 639 744.6 mW POWER SUPPLY--INTERNAL REFERENCE MODE IAVDD Analog supply current ILVDD Digital current Zero input to all channels Total power Incremental power saving Obtained on powering down one channel at a time 51 51 63 mW 113 113 138 mA 76 76 89 mA 510 510 616 mW Obtained on powering down one channel at a time 50 50 61 mW Current drawn by the eight ADCs from the external reference voltages; sourcing for REFT, sinking for REFB. 2.5 2.5 3.5 mA 85 dBc 80 dBc 85 dBc 82 dBc 85 dBc 80 dBc POWER SUPPLY--EXTERNAL REFERENCE MODE IAVDD Analog supply current ILVDD Digital current Zero input to all channels Total power Incremental power saving EXTERNAL REFERENCE LOADING Switching current DYNAMIC CHARACTERISTICS SFDR Spurious-free dynamic range fIN = 5MHz, single-ended clock 74 fIN = 30MHz, differential clock HD2 Magnitude of second harmonic fIN = 5MHz, single-ended clock HD3 Magnitude of third harmonic 74 THD Total harmonic distortion 74 SNR Signal-to-noise ratio 71 SINAD Signal-to-noise and distortion fIN = 30MHz, differential clock (1) 6 85 80 70 74 69.7 69.5 85 72 85 72 80 71 80 70 78 68.3 69.8 67.7 72 82 78 68.3 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 74 80 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 85 85 80 82 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 74 80 fIN = 30MHz, differential clock fIN = 5MHz, single-ended clock 85 70 78 68.3 69.8 67.7 69.7 69.5 80 67.3 70 dBFS 69.8 dBFS 69.7 dBFS 69.5 dBFS All characteristics are specific to each grade. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 PIN CONFIGURATIONS CS AVDD AVSS AVSS CLKN CLKP AVDD INT/EXT AVSS REFT REFB VCM 77 76 75 74 73 72 71 70 69 68 67 66 65 TP SDATA 78 NC SCLK 79 ISET AVSS 80 AVDD AVSS TQFP-80 TOP VIEW 64 63 62 61 AVDD 1 60 AVDD IN1P 2 59 IN8N IN1N 3 58 IN8P AVSS 4 57 AVSS IN2P 5 56 IN7N IN2N 6 55 IN7P AVDD 7 54 AVDD AVSS 8 53 AVSS IN3P 9 52 IN6N IN3N 10 51 IN6P ADS528x PD 16 45 RESET LVSS 17 44 LVSS LVSS 18 43 LVSS LCLKP 19 42 ADCLKN LCLKN 20 41 ADCLKP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 OUT8N LVSS OUT8P 46 OUT7P 15 OUT7N LVSS LVSS AVDD LVDD 47 OUT6N 14 OUT6P AVDD OUT5N IN5P OUT5P 48 OUT4N 13 OUT4P IN4N OUT3P IN5N OUT3N 49 LVSS 12 LVDD IN4P OUT2N AVSS OUT2P 50 OUT1N 11 OUT1P AVSS Table 2. PIN DESCRIPTIONS: TQFP-80 PIN NAME PIN NUMBER # OF PINS ADCLKN DESCRIPTION LVDS frame clock (1X)--negative output 42 1 ADCLKP LVDS frame clock (1X)--positive output 41 1 AVDD Analog power supply, 3.3V AVSS Analog ground 1, 7, 14, 47, 54, 60, 63, 70, 75 9 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 11 CLKN Negative differential clock Tie CLKN to 0V for a single-ended clock 72 1 CLKP Positive differential clock 71 1 Serial enable chip select--active low digital input 76 1 IN1N Negative differential input signal, channel 1 3 1 IN1P Positive differential input signal, channel 1 2 1 IN2N Negative differential input signal, channel 2 6 1 CS Copyright (c) 2006-2012, Texas Instruments Incorporated 7 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com Table 2. PIN DESCRIPTIONS: TQFP-80 (continued) PIN NAME PIN NUMBER # OF PINS IN2P Positive differential input signal, channel 2 5 1 IN3N Negative differential input signal, channel 3 10 1 IN3P Positive differential input signal, channel 3 9 1 IN4N Negative differential input signal, channel 4 13 1 IN4P Positive differential input signal, channel 4 12 1 IN5N Negative differential input signal, channel 5 49 1 IN5P Positive differential input signal, channel 5 48 1 IN6N Negative differential input signal, channel 6 52 1 IN6P Positive differential input signal, channel 6 51 1 IN7N Negative differential input signal, channel 7 56 1 IN7P Positive differential input signal, channel 7 55 1 IN8N Negative differential input signal, channel 8 59 1 IN8P Positive differential input signal, channel 8 58 1 Internal/external reference mode select input 69 1 INT/EXT ISET Bias pin--56.2k to ground 64 1 LCLKN LVDS bit clock (6X)--negative output 20 1 LCLKP LVDS bit clock (6X)--positive output 19 1 LVDD Digital and I/O power supply, 1.8V LVSS Digital ground 25, 35 2 15, 17, 18, 26, 36, 43, 44, 46 8 No connection (or connect to ground) 62 1 OUT1N LVDS channel 1--negative output 22 1 NC OUT1P LVDS channel 1--positive output 21 1 OUT2N LVDS channel 2--negative output 24 1 OUT2P LVDS channel 2--positive output 23 1 OUT3N LVDS channel 3--negative output 28 1 OUT3P LVDS channel 3--positive output 27 1 OUT4N LVDS channel 4--negative output 30 1 OUT4P LVDS channel 4--positive output 29 1 OUT5N LVDS channel 5--negative output 32 1 OUT5P LVDS channel 5--positive output 31 1 OUT6N LVDS channel 6--negative output 34 1 OUT6P LVDS channel 6--positive output 33 1 OUT7N LVDS channel 7--negative output 38 1 OUT7P LVDS channel 7--positive output 37 1 OUT8N LVDS channel 8--negative output 40 1 OUT8P LVDS channel 8--positive output 39 1 Power-down input 16 1 REFB Negative reference input/output 66 1 REFT Positive reference input/output 67 1 Active low RESET input 45 1 SCLK Serial clock input 78 1 SDATA PD RESET 8 DESCRIPTION Serial data input 77 1 TP Test pin, do not use 61 1 VCM Common-mode output pin, 1.5V output 65 1 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 CLKP AVDD INT/EXT REFT 59 58 57 56 55 54 AVDD CLKN 60 AVDD AVDD 61 ISET CS 62 TP SDATA 63 VCM SCLK 64 REFB RESET QFN-64 PowerPAD TOP VIEW 53 52 51 50 49 IN1P 1 48 IN8N IN1N 2 47 IN8P AVSS 3 46 AVSS IN2P 4 45 IN7N IN2N 5 44 IN7P AVSS 6 43 AVSS IN3P 7 42 IN6N IN3N 8 41 IN6P AVSS 9 40 AVSS IN4P 10 39 IN5N IN4N 11 38 IN5P LVSS 12 37 AVSS PD 13 36 LVSS LVSS 14 35 LVDD OUT1P 15 34 OUT8N OUT1N 16 33 OUT8P 22 23 24 25 26 27 28 29 30 OUT4N ADCLKP ADCLKN LCLKP LCLKN OUT5P OUT5N OUT6P OUT6N 31 32 OUT7N 21 OUT7P 20 OUT4P OUT2N 19 OUT3N 18 OUT3P 17 OUT2P ADS528X Table 3. PIN DESCRIPTIONS: QFN-64 PIN NAME DESCRIPTION ADCLKN LVDS frame clock (1X)--negative output ADCLKP LVDS frame clock (1X)--positive output PIN NUMBER # OF PINS 24 1 23 1 49, 50, 57, 60 4 3, 6, 9, 37, 40, 43, 46 7 CLKN Negative differential clock input Tie CLKN to 0V for a single-ended clock 59 1 CLKP Positive differential clock input 58 1 Serial enable chip select--active low digital input 61 1 IN1N Negative differential input signal, channel 1 2 1 IN1P Positive differential input signal, channel 1 1 1 IN2N Negative differential input signal, channel 2 5 1 IN2P Positive differential input signal, channel 2 4 1 IN3N Negative differential input signal, channel 3 8 1 IN3P Positive differential input signal, channel 3 7 1 IN4N Negative differential input signal, channel 4 11 1 IN4P Positive differential input signal, channel 4 10 1 IN5N Negative differential input signal, channel 5 39 1 AVDD Analog power supply, 3.3V AVSS Analog ground CS Copyright (c) 2006-2012, Texas Instruments Incorporated 9 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com Table 3. PIN DESCRIPTIONS: QFN-64 (continued) PIN NAME PIN NUMBER # OF PINS IN5P Positive differential input signal, channel 5 38 1 IN6N Negative differential input signal, channel 6 42 1 IN6P Positive differential input signal, channel 6 41 1 IN7N Negative differential input signal, channel 7 45 1 IN7P Positive differential input signal, channel 7 44 1 IN8N Negative differential input signal, channel 8 48 1 IN8P Positive differential input signal, channel 8 47 1 Internal/external reference mode select input 56 1 Bias pin--56.2k to ground 51 1 LCLKN LVDS bit clock (6X)--negative output 26 1 LCLKP LVDS bit clock (6X)--positive output 25 1 LVDD Digital and I/O power supply, 1.8V LVSS Digital ground INT/EXT ISET 35 1 12, 14, 36 3 OUT1N LVDS channel 1--negative output 16 1 OUT1P LVDS channel 1--positive output 15 1 OUT2N LVDS channel 2--negative output 18 1 OUT2P LVDS channel 2--positive output 17 1 OUT3N LVDS channel 3--negative output 20 1 OUT3P LVDS channel 3--positive output 19 1 OUT4N LVDS channel 4--negative output 22 1 OUT4P LVDS channel 4--positive output 21 1 OUT5N LVDS channel 5--negative output 28 1 OUT5P LVDS channel 5--positive output 27 1 OUT6N LVDS channel 6--negative output 30 1 OUT6P LVDS channel 6--positive output 29 1 OUT7N LVDS channel 7--negative output 32 1 OUT7P LVDS channel 7--positive output 31 1 OUT8N LVDS channel 8--negative output 34 1 OUT8P LVDS channel 8--positive output 33 1 Power-down input 13 1 REFB Negative reference input/output 54 1 REFT Positive reference input/output 55 1 Active low RESET input 64 1 SCLK Serial clock input 63 1 SDATA PD RESET 10 DESCRIPTION Serial data input 62 1 TP Test pin, do not use 52 1 VCM Common-mode output pin, 1.5V output 53 1 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 LVDD (1.8V) AVDD (3.3V) (AVSS) CLKN (ADCLK) CLKP FUNCTIONAL BLOCK DIAGRAM LCLKP 6x ADCLK Clock Buffer LCLKN 12x ADCLK PLL ADCLKP 1x ADCLK ADCLKN IN6P IN6N IN7P IN7N IN8P Digital 12-Bit ADC Digital 12-Bit ADC Digital 12-Bit ADC Digital 12-Bit ADC Digital 12-Bit ADC Digital Digital Gain (0dB-12dB) IN8N 12-Bit ADC REFT REFB VCM ISET INT/EXT Copyright (c) 2006-2012, Texas Instruments Incorporated OUT2N OUT3P Serializer OUT3N OUT4P Serializer OUT4N OUT5P Serializer OUT5N OUT6P Serializer OUT6N OUT7P Serializer OUT7N OUT8P Serializer OUT8N Registers Reference OUT2P Serializer Drive Current IN5P IN5N Digital OUT1N PowerDown ADC Control PD IN4P IN4N 12-Bit ADC OUT1P Serializer Test Patterns IN3P IN3N Digital Output Format IN2P IN2N 12-Bit ADC SCLK SDATA CS RESET IN1P IN1N 11 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com LVDS TIMING DIAGRAM Sample n Analog Input Sample n + 12 tD(A) Sample n + 13 Clock Input tSAMPLE 12 clocks latency LCLKN 6X ADCLK LCLKP OUTP SERIAL DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 OUTN ADCLKN 1X ADCLK ADCLKP tPROP DEFINITION OF SETUP AND HOLD TIMES LCLKN LCLKP OUTN OUTP tH1 tSU1 tH2 tSU2 tSU = min(tSU1, tSU2) tH = min(tH1, tH2) TIMING CHARACTERISTICS (1) (2) ADS528x PARAMETER tA TEST CONDITIONS Aperture delay Aperture delay variation tJ Wake-up time Channel-to-channel within the same device (3) 12 MAX UNIT 4.5 ns 20 ps 400 fs Time to valid data after coming out of COMPLETE POWER-DOWN mode 50 s Time to valid data after coming out of PARTIAL POWER-DOWN mode (with clock continuing to run during power-down) 2 s Time to valid data after stopping and restarting the input clock 40 s 12 Clock cycles Data latency (1) (2) TYP 1.5 Aperture jitter tWAKE MIN Timing characteristics are common to the ADS528x family. Timing parameters are ensured by design and characterization; not production tested. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 LVDS OUTPUT TIMING CHARACTERISTICS (1) (2) Typical values are at +25C, minimum and maximum values are measured across the specified temperature range of TMIN = -40C to TMAX = +85C, sampling frequency = as specified, CLOAD = 5pF (3), IOUT = 3.5mA, RLOAD = 100 (4), and no internal termination, unless otherwise noted. ADS528x 40MSPS PARAMETER tSU Data setup time (6) 50MSPS 65MSPS TEST CONDITIONS (5) MIN Data valid (7) to zero-crossing of LCLKP 0.67 0.47 0.27 ns Zero-crossing of LCLKP to data becoming invalid (7) 0.85 0.65 0.4 ns TYP MAX MIN TYP MAX MIN TYP MAX tH Data hold time (6) tPROP Clock propagation delay Input clock (ADCLK) rising edge cross-over to output clock (ADCLKP) rising edge cross-over 10 14 16.6 10 12.5 14.1 9.7 11.5 14 LVDS bit clock duty cycle Duty cycle of differential clock, (LCLKP - LCLKN) 45.5 50 53 45 50 53.5 41 50 57 UNIT ns Bit clock cycle-to-cycle jitter 250 250 250 ps, pp Frame clock cycle-to-cycle jitter 150 150 150 ps, pp tRISE, tFALL Data rise time, data fall time Rise time is from -100mV to +100mV Fall time is from +100mV to -100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time Rise time is from -100mV to +100mV Fall time is from +100mV to -100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns (1) (2) (3) (4) (5) (6) (7) All characteristics are at the maximum rated speed for each speed grade. Timing parameters are ensured by design and characterization; not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100 characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margin. Data valid refers to a logic high of +100mV and a logic low of -100mV. LVDS OUTPUT TIMING CHARACTERISTICS (1) (2) Typical values are at +25C, minimum and maximum values are measured across the specified temperature range of TMIN = -40C to TMAX = +85C, sampling frequency = as specified, CLOAD = 5pF (3), IOUT = 3.5mA, RLOAD = 100 (4), and no internal termination, unless otherwise noted. ADS528x 30MSPS PARAMETER tSU Data setup time (6) 20MSPS 10MSPS TEST CONDITIONS (5) MIN Data valid (7) to zero-crossing of LCLKP 0.8 1.5 3.7 ns Zero-crossing of LCLKP to data becoming invalid (7) 1.2 1.9 3.9 ns TYP MAX MIN TYP MAX MIN TYP MAX tH Data hold time (6) tPROP Clock propagation delay Input clock (ADCLK) rising edge cross-over to output clock (ADCLKP) rising edge cross-over 9.5 13.5 17.3 9.5 14.5 17.3 10 14.7 17.1 LVDS bit clock duty cycle Duty cycle of differential clock, (LCLKP - LCLKN) 46.5 50 52 48 50 51 49 50 51 UNIT ns Bit clock cycle-to-cycle jitter 250 250 750 ps, pp Frame clock cycle-to-cycle jitter 150 150 500 ps, pp tRISE, tFALL Data rise time, data fall time Rise time is from -100mV to +100mV Fall time is from +100mV to -100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns tCLKRISE, tCLKFALL Output clock rise time, output clock fall time Rise time is from -100mV to +100mV Fall time is from +100mV to -100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns (1) (2) (3) (4) (5) (6) (7) All characteristics are at the speeds other than the maximum rated speed for each speed grade. Timing parameters are ensured by design and characterization; not production tested. CLOAD is the effective external single-ended load capacitance between each output pin and ground. IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair. Measurements are done with a transmission line of 100 characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margin. Data valid refers to a logic high of +100mV and a logic low of -100mV. Copyright (c) 2006-2012, Texas Instruments Incorporated 13 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com LVDS OUTPUT TIMING CHARACTERISTICS PARAMETER (1) TIMINGS WHEN USING REGISTER 0xE3 (2) At 40 MSPS TEST CONDITIONS MIN Data setup time Data valid (3) to zero-crossing of LCLKp 0.60 Data hold time Zero-crossing of LCLKP to data becoming invalid (3) 0.92 Clock propagation delay Input clock (ADCLK) rising edge cross-over to output clock (ADCLK) rising edge crossover (1) (2) (3) TYP MAX 12 14.6 8 Only the setup time, hold time and clock propagation delay parameters are affected. Rest of the parameters are same as given in previous two tables. Only timing specifications for 40MSPS are affected when using register 0xE3 (as specified in the recommended operating table section). The timing specifications for other clock frequencies are same as given in previous two tables. Data valid refers to logic high of +100mV and logic low of -100mV. RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING t1 AVDD (3V to 3.6V) AVDD t2 LVDD LVDD (1.7V to 1.9V) t3 t4 t7 High-Level RESET (1.4V to 3.6V) t5 RESET t6 CS Device Ready for High-Level CS (1.4V to 3.6V) Serial Register Write Start of Clock (2) Device Ready for Data Conversion ADCLK t8 10s < t1 < 50ms, 10s < t2 < 50ms, -10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100s. (1) The AVDD and LVDD power on sequence does not matter as long as -10ms < t3 < 10ms. Similar considerations apply while shutting down the device. (2) Write initialization registers listed in the Initialization Registers table. 14 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 POWER-DOWN TIMING 1ms tWAKE PD Device Fully Powers Down Device Fully Powers Up Power-up time shown is based on 1F bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up completely from power-down mode. The ADS528x has two power-down modes: complete power-down mode and partial power-down mode. The device can be configured in partial power-down mode through a register setting. tWAKE < 50s for complete power-down mode. tWAKE < 2s for partial power-down mode (provided the clock is not shut off during power-down). Copyright (c) 2006-2012, Texas Instruments Incorporated 15 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com SERIAL INTERFACE The ADS528x has a set of internal registers that can be accessed through the serial interface formed by pins CS (chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the following actions occur: * Serial shift of bits into the device is enabled * SDATA (serial data) is latched at every rising edge of SCLK * SDATA is loaded into the register at every 24th SCLK rising edge If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16 bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds (a few hertz) and also with a non-50% SCLK duty cycle. Register Initialization After power-up, the internal registers must be initialized to the respective default values. Initialization can be done in one of two ways: 1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or 2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the internal registers to the respective default values and then self-resets the RST bit low. In this case, the RESET pin stays high (inactive). After all registers have been initialized to their default values through a RESET operation, the registers detailed in the Initialization Registers table must be written into. This process must be done after every hardware or software RESET operation in order to reconfigure the device for the best mode of operation. SERIAL INTERFACE TIMING Start Sequence End Sequence CS t6 t1 t7 t2 Data latched on rising edge of SCLK SCLK t3 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDATA t4 t5 ADS528x 16 PARAMETER DESCRIPTION MIN t1 SCLK period 50 TYP MAX UNIT ns t2 SCLK high time 20 ns t3 SCLK low time 20 ns t4 Data setup time 5 ns t5 Data hold time 5 ns t6 CS fall to SCLK rise 8 ns t7 Time between last SCLK rising edge to CS rising edge 8 ns Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 SERIAL REGISTER MAP Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 X X X X X X X (2) (3) (4) D0 NAME X RST Self-clearing software RESET. Inactive PDN_CH<8:1> Channel-specific ADC powerdown mode. Inactive PDN_PARTIAL Partial power-down mode (fast recovery from power-down). Inactive PDN_COMPLETE Register mode for complete power-down (slower recovery). X X DESCRIPTION DEFAULT 0F X X X 11 X X X X X X PDN_PIN_CFG Complete power-down ILVDS_LCLK<2:0> LVDS current drive programmability for LCLKN and LCLKP pins. 3.5mA drive LVDS current drive programmability for ADCLKN and ADCLKP pins. 3.5mA drive ILVDS_DAT<2:0> LVDS current drive programmability for OUTN and OUTP pins. 3.5mA drive EN_LVDS_TERM Enables internal termination for LVDS buffers. Termination disabled TERM_LCLK<2:0> Programmable termination for LCLKN and LCLKP buffers. Termination disabled TERM_FRAME <2:0> Programmable termination for ADCLKN and ADCLKP buffers. Termination disabled TERM_DAT<2:0> Programmable termination for OUTN and OUTP buffers. Termination disabled ILVDS_FRAME <2:0> X X X 1 X X X 12 1 X 1 X X X X X Inactive Configures the PD pin for partial power-down mode. 14 X X X X X X X X LFNS_CH<8:1> Channel-specific, low-frequency noise suppression mode enable. Inactive 24 X X X X X X X X INVERT_CH<8:1> Swaps the polarity of the analog input pins electrically. INP is positive input X 0 0 EN_RAMP Enables a repeating full-scale ramp pattern on the outputs. Inactive 0 X 0 DUALCUSTOM_ PAT Enables the mode wherein the output toggles between two defined codes. Inactive 0 0 X SINGLE_CUSTOM _PAT Enables the mode wherein the output is a constant specified code. Inactive BITS_CUSTOM1 <11:10> 2MSBs for a single custom pattern (and for the first code of the dual custom pattern). <11> is the MSB. Inactive BITS_CUSTOM2 <11:10> 2MSBs for the second code of the dual custom pattern. Inactive Inactive 25 X X X X 26 X X X X X X X X X X BITS_CUSTOM1 <9:0> 10 lower bits for the single custom pattern (and for the first code of the dual custom pattern). <0> is the LSB. 27 X X X X X X X X X X BITS_CUSTOM2 <9:0> 10 lower bits for the second code of the dual custom pattern. Inactive GAIN_CH1<3:0> Programmable gain channel 1. 0dB gain GAIN_CH2<3:0> Programmable gain channel 2. 0dB gain GAIN_CH3<3:0> Programmable gain channel 3. 0dB gain X X X X X X X X 2A X X X X X X X X GAIN_CH4<3:0> Programmable gain channel 4. 0dB gain X X X X GAIN_CH5<3:0> Programmable gain channel 5. 0dB gain GAIN_CH6<3:0> Programmable gain channel 6. 0dB gain GAIN_CH7<3:0> Programmable gain channel 7. 0dB gain GAIN_CH8<3:0> Programmable gain channel 8. 0dB gain X X X X 2B X X X X X (1) (2) (3) (4) X X X The unused bits in each register (identified as blank table cells) must be programmed as '0'. X = Register bit referenced by the corresponding name and description (default is 0). Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed. Multiple functions in a register should be programmed in a single write operation. Copyright (c) 2006-2012, Texas Instruments Incorporated 17 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 1 1 D0 NAME X DIFF_CLK X EN_DCC (3) (4) (continued) DESCRIPTION Differential clock mode. Enables the duty-cycle correction circuit. X 1 X X Singleended clock Disabled EXT_REF_VCM Drives the external reference mode through the VCM pin. External reference drives REFT and REFB PHASE_DDR<1:0> Controls the phase of LCLK output relative to data. 90 degrees 42 1 DEFAULT 0 X PAT_DESKEW Enables deskew pattern mode. Inactive X 0 PAT_SYNC Enables sync pattern mode. Inactive BTC_MODE Binary two's complement format for ADC output. MSB_FIRST Serialized ADC output comes out MSB-first. 45 46 1 1 1 1 1 1 X EN_SDR 1 1 FALL_SDR 1 X X X Straight offset binary LSB-first output Enables SDR output mode (LCLK becomes a 12x input clock). DDR output mode Controls whether the LCLK rising or falling edge comes in the middle of the data window when operating in SDR output mode. Rising edge of LCLK in middle of data window SUMMARY OF FEATURES FEATURES POWER IMPACT (relative to default) AT fS = 65MSPS DEFAULT SELECTION Internal or external reference (driven on the REFT and REFB pins) N/A Pin External reference driven on the VCM pin Off Register 42 Approximately 9mW less power on AVDD Duty cycle correction circuit Off Register 42 Approximately 7mW more power on AVDD Low-frequency noise suppression Off Register 14 With zero input to the ADC, low-frequency noise suppression causes digital switching at fS/2, thereby increasing LVDD power by approximately 7mW/channel Single-ended or differential clock Single-ended Register 42 Differential clock mode uses approximately 7mW more power on AVDD Off Pin and register 0F 0dB Registers 2A and 2B No difference Straight offset Register 46 No difference Off Register 24 No difference ANALOG FEATURES Power-down mode Internal reference mode uses approximately 23mW more power on AVDD Refer to the Power-Down Modes section in the Electrical Characteristics table DIGITAL FEATURES Programmable digital gain (0dB to 12dB) Straight offset or BTC output Swap polarity of analog input pins LVDS OUTPUT PHYSICAL LAYER LVDS internal termination LVDS current programmability Off Register 12 Approximately 7mW more power on AVDD 3.5mA Register 11 As per LVDS clock and data buffer current setting LSB-first Register 46 No difference DDR Register 46 SDR mode uses approximately 2mW more power on LVDD (at fS = 30MSPS) Refer to Figure 1 Register 42 No difference LVDS OUTPUT TIMING LSB- or MSB-first output DDR or SDR output LCLK phase relative to data output 18 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 DESCRIPTION OF SERIAL REGISTERS SOFTWARE RESET ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 D0 NAME X RST Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears to '0'. POWER-DOWN MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X PDN_CH<8:1> X PDN_PARTIAL 0F 0 X PDN_COMPLETE X 0 PDN_PIN_CFG Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for the ADC channel <N>. In addition to channel-specific power-down, the ADS528x also has two global power-down modes--partial power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip; recovery from this mode is much quicker, provided that the clock has been running for at least 50s before exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and involves a much longer recovery time. In addition to programming the device for either of these two power-down modes (through either the PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin is high, the device enters partial power-down mode. LVDS DRIVE PROGRAMMABILITY ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 11 D7 D6 X X X X D5 X D4 X D3 D2 D1 D0 NAME X X X ILVDS_LCLK<2:0> ILVDS_FRAME<2:0> ILVDS_DAT<2:0> The LVDS drive strength of the bit clock (LCLKP or LCLKN) and the frame clock (ADCLKP or ADCLKN) can be individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTN can also be programmed to the same value. Copyright (c) 2006-2012, Texas Instruments Incorporated 19 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 5 shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame clock and data drive strengths). Table 5. Bit Clock Drive Strength (1) (1) ILVDS_LCLK<2> ILVDS_LCLK<1> ILVDS_LCLK<0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKN 0 0 0 3.5mA (default) 0 0 1 2.5mA 0 1 0 1.5mA 0 1 1 0.5mA 1 0 0 7.5mA 1 0 1 6.5mA 1 1 0 5.5mA 1 1 1 4.5mA Current settings lower than 1.5mA are not recommended. LVDS INTERNAL TERMINATION PROGRAMMABILITY ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X EN_LVDS_TERM 1 X X X TERM_LCLK<2:0> 12 1 X 1 X X X X TERM_FRAME<2:0> X TERM_DAT<2:0> The LVDS buffers have high-impedance current sources driving the outputs. When driving traces whose characteristic impedance is not perfectly matched with the termination impedance on the receiver side, there may be reflections back to the LVDS output pins of the ADS528x that cause degraded signal integrity. By enabling an internal termination (between the positive and negative outputs) for the LVDS buffers, the signal integrity can be significantly improved in such scenarios. To set the internal termination mode, the EN_LVDS_TERM bit should be set to '1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table 6 shows an example of how the internal termination of the LVDS buffer driving the bit clock is programmed (the method is similar for the frame clock and data buffers). These termination values are only typical values and can vary by up to 20% across temperature and from device to device. Table 6. Bit Clock Internal Termination 20 TERM_LCLK<2> TERM_LCLK<1> TERM_LCLK<0> INTERNAL TERMINATION BETWEEN LCLKP AND LCLKN IN 0 0 0 None 0 0 1 260 0 1 0 150 0 1 1 94 1 0 0 125 1 0 1 80 1 1 0 66 1 1 1 55 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 LOW-FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 14 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X LFNS_CH<8:1> The low-frequency noise suppression mode is specifically useful in applications where good noise performance is desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of the ADS528x to approximately fS/2, thereby moving the noise floor around dc to a much lower value. LFNS_CH<8:1> enables this mode individually for each channel. ANALOG INPUT INVERT ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 24 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X X X X X INVERT_CH<8:1> Normally, the INP pin represents the positive analog input pin, and INN represents the complementary negative input. Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be swapped. INN now represents the positive input, and INP the negative input. LVDS TEST PATTERNS ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 25 D6 D5 D4 X 0 0 D3 D2 D1 0 X 0 DUALCUSTOM_PAT 0 0 X SINGLE_CUSTOM_PAT X X X X X X X X X X X 27 X X X X X X X X X X NAME EN_RAMP X 26 D0 X X BITS_CUSTOM1<11:10> BITS_CUSTOM2<11:10> BITS_CUSTOM1<9:0> BITS_CUSTOM2<9:0> 0 X PAT_DESKEW X 0 PAT_SYNC 45 The ADS528x can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the fullscale code, it returns back to zero code and ramps again. The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and programming the desired code in BITS_CUSTOM1<11:0>. In this mode, BITS_CUSTOM1<11:0> take the place of the 12-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as normal ADC data are. The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT to '1'. The two codes are represented by the contents of BITS_CUSTOM1<11:0> and BITS_CUSTOM2<11:0>. In addition to custom patterns, the device may also be made to output two preset patterns: 1. Deskew patten: Set using PAT_DESKEW, this mode replaces the 12-bit ADC output D<11:0> with the 010101010101 word. 2. Sync pattern: Set using PAT_SYNC, the normal ADC word is replaced by a fixed 111111000000 word. Note that only one of the above patterns should be active at any given instant. Copyright (c) 2006-2012, Texas Instruments Incorporated 21 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com PROGRAMMABLE GAIN ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 X D6 X D5 D4 X D3 D2 D1 D0 NAME X X X X GAIN_CH1<3:0> X GAIN_CH2<3:0> 2A X X X X X X X X X X X X GAIN_CH3<3:0> GAIN_CH4<3:0> GAIN_CH5<3:0> X X X X GAIN_CH6<3:0> 2B X X X X GAIN_CH7<3:0> X X X X GAIN_CH8<3:0> In applications where the full-scale swing of the analog input signal is much less than the 2VPP range supported by the ADS528x, a programmable gain can be set to achieve the full-scale output code even with a lower analog input swing. The programmable gain not only fills the output code range of the ADC, but also enhances the SNR of the device by utilizing quantization information from some extra internal bits. The programmable gain for each channel can be individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain setting is coded in binary from 0dB to 12dB, as shown in Table 7. Table 7. Gain Setting for Channel 1 22 GAIN_CH1<3> GAIN_CH1<2> GAIN_CH1<1> GAIN_CH1<0> CHANNEL 1 GAIN SETTING 0 0 0 0 0dB 0 0 0 1 1dB 0 0 1 0 2dB 0 0 1 1 3dB 0 1 0 0 4dB 0 1 0 1 5dB 0 1 1 0 6dB 0 1 1 1 7dB 1 0 0 0 8dB 1 0 0 1 9dB 1 0 1 0 10dB 1 0 1 1 11dB 1 1 0 0 12dB 1 1 0 1 Do not use 1 1 1 0 Do not use 1 1 1 1 Do not use Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 CLOCK, REFERENCE, AND DATA OUTPUT MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 1 1 X D1 D0 NAME X DIFF_CLK EN_DCC 42 1 X 1 X 1 1 1 1 EXT_REF_VCM X PHASE_DDR<1:0> X X BTC_MODE MSB_FIRST 46 1 1 X 1 X EN_SDR 1 1 FALL_SDR INPUT CLOCK The ADS528x is configured by default to operate with a single-ended input clock--CLKP is driven by a CMOS clock and CLKN is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a differential input clock on CLKP and CLKN. Operating with a low-jitter differential clock usually gives better SNR performance, especially at input frequencies greater than 30MHz. In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'. EXTERNAL REFERENCE The ADS528x can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode, the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The advantage of using the external reference mode is that multiple ADS528x units can be made to operate with the same external reference, thereby improving parameters such as gain matching across devices. However, in applications that do not have an available high drive, differential external reference, the ADS528x can still be driven with a single external reference voltage on the VCM pin. When EXT_REF_VCM is set as '1' (and the INT/EXT pin is set to '0'), the VCM pin is configured as an input pin, and the voltages on REFT and REFB are generated as shown in Equation 1 and Equation 2. VCM VREFT = 1.5V + 1.5V (1) VCM VREFB = 1.5V 1.5V (2) Copyright (c) 2006-2012, Texas Instruments Incorporated 23 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com BIT CLOCK PROGRAMMABILITY The output interface of the ADS528x is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. This default phase is shown in Figure 1. ADCLKP LCLKP OUTP Figure 1. Default Phase of LCLK The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2. PHASE_DDR<1:0> = '00' PHASE_DDR<1:0> = '10' ADCLKP ADCLKP LCLKP LCLKP OUTP OUTP PHASE_DDR<1:0> = '01' PHASE_DDR<1:0> = '11' ADCLKP ADCLKP LCLKP LCLKP OUTP OUTP Figure 2. Phase Programmability Modes for LCLK 24 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two manners shown in Figure 3. As can be seen in Figure 3, only the LCLK rising (or falling) edge is used to capture the output data in SDR mode. EN_SDR = '1', FALL_SDR = '0' ADCLKP LCLKP OUTP EN_SDR = '1', FALL_SDR = '1' ADCLKP LCLKP OUTP Figure 3. SDR Interface Modes The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high. DATA OUTPUT FORMAT MODES The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the MSB, and the output becomes binary two's complement mode. Also by default, the first bit of the frame (following the rising edge of ADCLKP) is the LSB of the ADC output. Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit following the ADCLKP rising edge. Copyright (c) 2006-2012, Texas Instruments Incorporated 25 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, -1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. SPECTRAL PERFORMANCE (fS = 40MHz, fIN = 10MHz) SPECTRAL PERFORMANCE (fS = 40MHz, fIN = 25MHz) 0 0 SFDR = 85.3dBc SNR = 70.8dBFS SINAD = 70.7dBFS THD = 89.3dBc -20 -40 Amplitude (dB) Amplitude (dB) -40 SFDR = 82.8dBc SNR = 70.2dBFS SINAD = 70dBFS THD = 82.3dBc -20 -60 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 2 4 6 8 10 12 14 16 18 20 0 2 4 Input Frequency (MHz) 10 12 14 Figure 4. Figure 5. SPECTRAL PERFORMANCE (fS = 50MHz, fIN = 10MHz) SPECTRAL PERFORMANCE (fS = 50MHz, fIN = 25MHz) 16 18 20 0 SFDR = 88.4dBc SNR = 70.9dBFS SINAD = 70.8dBFS THD = 87.5dBc SFDR = 85.6dBc SNR = 70.5dBFS SINAD = 70.4dBFS THD = 83.9dBc -20 -40 Amplitude (dB) -40 Amplitude (dB) 8 Input Frequency (MHz) 0 -20 -60 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 15 Input Frequency (MHz) Figure 6. 26 6 20 25 0 5 10 15 20 25 Input Frequency (MHz) Figure 7. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, -1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. SPECTRAL PERFORMANCE (fS = 65MHz, fIN = 10MHz) SPECTRAL PERFORMANCE (fS = 65MHz, fIN = 25MHz) 0 0 SFDR = 90.9dBc SNR = 70.8dBFS SINAD = 70.7dBFS THD = 90.4dBc -20 -40 Amplitude (dB) Amplitude (dB) -40 -60 -80 -100 -120 SFDR = 87.4dBc SNR = 70.4dBFS SNR (0MHz to 1MHz) = 81.9dBFS SINAD = 70.3dBFS THD = 86.4dBc -20 -60 -80 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 15 20 25 0 30 33 5 Figure 8. 15 20 25 30 33 Figure 9. SPECTRAL PERFORMANCE, LOW-FREQUENCY NOISE SUPPRESSION MODE ENABLED (fS = 65MHz, fIN = 25MHz) DYNAMIC PERFORMANCE vs INPUT FREQUENCY 92 0 -40 -60 Dynamic Performance (SNR, SFDR) SFDR = 86.2dBc SNR = 70.5dBFS SNR (0MHz to 1MHz) = 86.1dBFS SINAD = 70.4dBFS THD = 85.4dBc -20 Amplitude (dB) 10 Input Frequency (MHz) Input Frequency (MHz) -80 -100 -120 -140 -160 SFDR (dBc) 87 82 fS = 40MHz 77 72 SNR (dBFS) 67 -180 0 5 10 15 20 Input Frequency (MHz) Figure 10. Copyright (c) 2006-2012, Texas Instruments Incorporated 25 30 33 5 10 15 20 25 30 Input Frequency (MHz) Figure 11. 27 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, -1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. DYNAMIC PERFORMANCE vs INPUT FREQUENCY DYNAMIC PERFORMANCE vs INPUT FREQUENCY 97 Dynamic Performance (SNR, SFDR) Dynamic Performance (SNR, SFDR) 92 SFDR (dBc) 87 82 fS = 50MHz 77 72 SNR (dBFS) SFDR (dBc) 92 87 82 fS = 65MHz 77 72 SNR (dBFS) 67 67 10 5 15 20 25 30 5 10 Input Frequency (MHz) 15 Figure 12. DYNAMIC PERFORMANCE vs DIGITAL GAIN DYNAMIC PERFORMANCE vs AVDD Dynamic Performance (SNR, SFDR) Dynamic Performance (SNR, SFDR) 30 95 90 SFDR (dBc) 85 fS = 65MHz fIN = 10MHz 80 75 70 SNR (dBFS) 65 60 SFDR (dBc) 90 85 fS = 65MHz fIN = 10MHz 80 75 SNR (dBFS) 70 65 60 0 2 4 6 8 10 12 3.0 3.1 3.2 Digital Gain (dB) 3.3 3.4 3.5 3.6 AVDD (V) Figure 14. Figure 15. DYNAMIC PERFORMANCE vs INPUT AMPLITUDE DYNAMIC PERFORMANCE vs CLOCK AMPLITUDE 94 Dynamic Performance (SNR, SFDR) 95 Dynamic Performance (SNR, SFDR) 25 Figure 13. 95 85 75 SNR (dBFS) 65 55 SFDR (dBc) 45 35 fS = 65MHz fIN = 10MHz 25 SFDR (dBc) 89 84 fS = 65MHz fIN = 10MHz 79 74 SNR (dBFS) 69 -60 -50 -40 -30 -20 Input Amplitude (dBFS) Figure 16. 28 20 Input Frequency (MHz) -10 0 0.6 1.1 1.6 2.1 2.3 Clock Amplitude (VPP Differential) Figure 17. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, -1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. DYNAMIC PERFORMANCE vs ANALOG INPUT COMMONMODE VOLTAGE DYNAMIC PERFORMANCE vs EXTERNAL REFERENCE DIFFERENTIAL VOLTAGE 94 Dynamic Performance (SNR, SFDR) Dynamic Performance (SNR, SFDR) 94 SFDR (dBc) 89 84 fS = 65MHz fIN = 10MHz 79 74 SNR (dBFS) 69 1.30 SFDR (dBc) 89 84 External reference common-mode voltage maintained at 1.5V. 79 74 SNR (dBFS) 69 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.6 1.70 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 External Reference Differential Voltage, REFT - REFB (V) Analog Input Common-Mode Voltage (V) Figure 18. Figure 19. DYNAMIC PERFORMANCE vs EXTERNAL REFERENCE COMMON-MODE VOLTAGE DYNAMIC PERFORMANCE vs EXTERNAL REFERENCE FORCED THROUGH VCM 94 94 SFDR (dBc) 89 fS = 65MHz fIN = 10MHz 84 External reference differential voltage maintained at 2V. 79 74 SNR (dBFS) 69 1.35 1.40 1.45 1.50 1.55 1.60 1.65 Dynamic Performance (SNR, SFDR) Dynamic Performance (SNR, SFDR) fS = 65MHz fIN = 10MHz SFDR (dBc) 89 84 fS = 65MHz fIN = 10MHz 79 74 SNR (dBFS) 69 1.35 1.40 1.45 1.50 1.55 External Reference Common-Mode Voltage, (REFT + REFB)/2 (V) Voltage on VCM (V) Figure 20. Figure 21. Copyright (c) 2006-2012, Texas Instruments Incorporated 1.60 1.65 29 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, -1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC DISABLED DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC ENABLED 95 Dynamic Performance (SNR, SFDR) Dynamic Performance (SNR, SFDR) 95 90 SFDR (dBc) 85 80 fS = 65MHz fIN = 10MHz 75 70 SNR (dBFS) 65 60 90 SFDR (dBc) 85 fS = 65MHz fIN = 10MHz 80 75 70 SNR (dBFS) 65 60 40 35 45 50 55 60 65 30 20 40 Figure 22. 70 60 80 Figure 23. HISTOGRAM OF OUTPUT CODE FOR ZERO INPUT INTERMODULATION DISTORTION 60 10 fS = 65MHz f1 = 10MHz (-7dBFS) f2 = 16.1MHz (-7dBFS) IMD = -97dBFS fS = 65MSPS 51.92% -10 47.43% 50 -30 40 Amplitude (dB) Occurrence (%) 50 Clock Duty Cycle (%) Clock Duty Cycle (%) 30 20 -50 -70 -90 -110 10 0% 0.37% 0.28% -130 0% 0 -150 2049 2050 2051 2052 2053 0 2054 2 4 Figure 24. 10 12 14 16 20 18 DIFFERENTIAL NONLINEARITY 0.35 fS = 50MSPS fIN = 5MHz 0.4 8 Figure 25. INTEGRAL NONLINEARITY 0.5 6 Input Frequency (MHz) Code Bin (LSB) fS = 50MSPS fIN = 5MHz 0.25 0.3 0.15 DNL (LSB) INL (LSB) 0.2 0.1 0 -0.1 -0.2 0.05 -0.05 -0.15 -0.3 -0.25 -0.4 -0.5 -0.35 0 512 1024 1536 2048 2560 Code (LSB) Figure 26. 30 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096 Code (LSB) Figure 27. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TA = +25C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50% clock duty cycle, input frequency = 10MHz, -1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2k, and LVDS buffer current setting = 3.5mA, unless otherwise noted. INTEGRAL NONLINEARITY 0.75 DIFFERENTIAL NONLINEARITY 0.35 fS = 65MSPS fIN = 5MHz 0.55 0.15 DNL (LSB) 0.35 INL (LSB) fS = 65MSPS, fIN = 5MHz 0.25 0.15 -0.05 0.05 -0.05 -0.25 -0.15 -0.45 -0.25 -0.65 -0.35 0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 Code (LSB) Figure 28. 2560 3072 3584 4096 Figure 29. AVDD AND LVDD POWER-SUPPLY CURRENTS vs CLOCK FREQUENCY OVERLOAD RECOVERY AT 50MSPS 170 0.70 Zero Input on All Channels Internal Reference Mode fS = 50MSPS fIN = 5MHz 0.68 Standard Deviation (in LSB) 150 IAVDD IAVDD, ILVDD (mA) 2048 Code (LSB) 130 110 90 ILVDD 70 50 Standard Deviation of 2nd Point After Overload 0.66 0.64 0.62 0.60 0.58 0.56 0.54 Standard Deviation of 1st Point After Overload 0.52 30 0.50 5 15 25 35 55 45 65 75 0 1 Clock Frequency (MSPS) 3 2 5 4 6 Overload Signal Amplitude (dBFS) Figure 30. Figure 31. OVERLOAD RECOVERY AT 65MSPS Standard Deviation (LSB) 0.64 16384 tS (Group 1) fS = 65MSPS fIN = 5MHz 0.62 Standard Deviation of 1st Point After Overload First point after overload (Set 1) Second point after overload (Set 1) +FS Set 1, Point 1 (of 16) 0.60 Set 1, Point 2 (of 16) tS 0.58 Overload Amplitude 0.56 -FS Second point after overload (Set 2) 0.54 First point after overload (Set 2) Standard Deviation of 2nd Point After Overload 0.52 0 1 2 3 4 5 6 NOTES: Input sine wave phase is repetitive over 16384 clock cycles. 16 such repetitive groups (of 16384 clock cycles) are captured-a total of 262,144 points. Standard deviation of every set of first and second points after overload are analyzed over the 16 groups. Worst case of all such standard deviations are plotted in the graphs. Overload Signal Amplitude (dBFS) Figure 32. Copyright (c) 2006-2012, Texas Instruments Incorporated Figure 33. Overload Recovery 31 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The ADS528x devices are a family of 8-channel, high-speed, CMOS ADCs. The 12 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the ADS528x operate from a single clock (ADCLK). The sampling clocks for each of the eight channels are generated from the input clock using a carefully matched clock buffer tree. The 12x clock required for the serializer is generated internally from ADCLK using a phase-locked loop (PLL). A 6x and a 1x clock are also output in LVDS format, along with the data, to enable easy data capture. The ADS528x operates from internally-generated reference voltages that are trimmed to improve to a high level of accuracy. Trimmed references improve the gain matching across devices, and provide the option to operate the devices without having to externally drive and route reference lines. The nominal values of REFT and REFB are 2.5V and 0.5V, respectively. The references are internally scaled down differentially by a factor of 2. This scaling results in a differential input of -1V to correspond to the zero code of the ADC, and a differential input of +1V to correspond to the full-scale code (4095 LSB). VCM (the common-mode voltage of REFT and REFB) is also made available externally through a pin, and is nominally 1.5V. The ADC employs a pipelined converter architecture that consists of a combination of multi-bit and singlebit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12bit level. 32 The ADC output goes to a serializer that operates from a 12x clock generated by the PLL. The 12 data bits from each channel are serialized and sent LSB first. In addition to serializing the data, the serializer also generates a 1x clock and a 6x clock. These clocks are generated in the same way the serialized data are generated, so these clocks maintain perfect synchronization with the data. The data and clock outputs of the serializer are buffered externally using LVDS buffers. Using LVDS buffers to transmit data externally has multiple advantages, such as a reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the analog circuit inside the ADS528x. The ADS528x operates from two sets of supplies and grounds. The analog supply and ground set is identified as AVDD and AVSS, while the digital set is identified by LVDD and LVSS. ANALOG INPUT The analog input consists of a switched-capacitor based, differential sample-and-hold architecture. This differential topology results in very good ac performance even for high input frequencies at high sampling rates. The INN and INP pins must be externally biased around a common-mode voltage of 1.5V, available on VCM. For a full-scale differential input, each input pin (INN and INP) must swing symmetrically between VCM + 0.5V and VCM - 0.5V, resulting in a 2VPP differential input swing. The maximum input peak-to-peak differential swing is determined to be the difference between the internal reference voltages REFT (2.5V nominal) and REFB (0.5V nominal). Figure 34 illustrates the model of the input driving circuit. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 5nH to 9nH (TQFP-80) 2nH to 3nH (QFN-64) IN OUT INP 1.5pF to 2.5pF 5W to 10W 15W to 25W 1W IN 1.5pF to 2.4pF 15W to 30W OUT IN 1000W to 1440W OUT OUT OUTP 0.2pF to 0.3pF IN OUTN 1000W to 1440W 16W to 32W 5W to 10W 15W to 25W IN 5nH to 9nH (TQFP-80) 2nH to 3nH (QFN-64) OUT 1.5pF to 2.4pF 15W to 30W IN OUT INN 1.5pF to 2.5pF Switches that are ON in SAMPLE phase. 1W Switches that are ON in HOLD phase. IN OUT Figure 34. Analog Input Circuit Model Input Common-Mode Current The input stage of all eight ADCs together sinks a common-mode current on the order of 2mA at 50MSPS. Equation 3 describes the dependency of the common-mode current and the sampling frequency. (2mA) fS 50MSPS ADS528x INP 1.2kW (3) If the driving stage is dc-coupled to the inputs, then Equation 3 can be used to determine its commonmode drive capability and impedance. The inputs can also be ac-coupled to the INN and INP pins. In that case, the input common-mode is set by two internal 1.2k resistors connecting the input pins to VCM. This architecture is shown in Figure 35. When the inputs are ac-coupled, there is a drop in the voltages at INP and INN relative to VCM. This can be computed from Equation 3. At 50MSPS, for example, the drop at each of the 16 input pins is 150mV, which is not optimal for ADC operation. Initialization Registers 1 and 5, described in the Initialization Registers table, can be used to partially reduce the effect of this input common-mode drop Copyright (c) 2006-2012, Texas Instruments Incorporated during ac-coupling by increasing VCM by roughly 75mV. When operating above 50MSPS, it is recommended that additional parallel resistors be added externally to restore the input common-mode to at least 1.4V, if the inputs are to be ac-coupled. Input Circuitry 1.2kW INN Internal Voltage Reference VCM CM Buffer Dashed area denotes one of eight channels. Figure 35. Common-Mode Biasing of Input Pins 33 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com Driving Circuit At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps to minimize this mismatch, and good performance is obtained for high-frequency input signals. An additional termination resistor pair is required between the two transformers, as shown in Figure 37. The center point of this termination is connected to ground to improve the balance between the positive and negative sides. The values of the terminations between the transformers and on the secondary side must be chosen to achieve an overall 50 (in the case of 50 source impedance). For optimum performance, the analog inputs must be driven differentially. This approach improves the common-mode noise immunity and even-order harmonic rejection. Input configurations using RF transformers suitable for low and high input frequencies are shown in Figure 36 and Figure 37, respectively. The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated by 50 resistor on the secondary side. Placing the termination on the secondary side helps to shield the kicks caused by the input sampling capacitors from the RF transformer leakage inductances. The termination is accomplished by two 25 resistors, connected in series, with the center point connected to the 1.5V common-mode. The 4.7 resistor in series with each input pin is required to damp the ringing caused by the device package parasitics. 4.7W 0.1mF INP 1:1 25W 0.1mF 25W 4.7W INN VCM Figure 36. Drive Circuit at Low Input Frequencies 1:2 2:1 INP 0.1mF 200W 200W 0.1mF 50W 50W INN VCM Figure 37. Drive Circuit at High Input Frequencies 34 Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 CLOCK INPUT The eight channels on the device operate from a single ADCLK input. To ensure that the aperture delay and jitter are the same for all channels, a clock tree network is used to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point to the sampling circuit. This architecture ensures that the performance and timing for all channels are identical. The use of the clock tree for matching introduces an aperture delay that is defined as the delay between the rising edge of ADCLK and the actual instant of sampling. The aperture delays for all the channels are matched to the best possible extent. A mismatch of 20ps (3) could exist between the aperture instants of the eight ADCs within the same chip. However, the aperture delays of ADCs across two different chips can be several hundred picoseconds apart. The ADS528x can be made to operate either in CMOS single-ended clock mode (default is DIFF_CLK = 0) or differential clock mode (SINE, LVPECL, or LVDS). When operating in the singleended clock mode, CLKN must be forced to 0VDC, and the single-ended CMOS applied on the CLKP pin. This operation is shown in Figure 38. CMOS Single-Ended Clock CLKP VCM VCM 5kW 5kW CLKP CLKN Figure 39. Internal Clock Buffer 0.1mF CLKP Differential Sine-Wave, PECL, or LVDS Clock Input 0.1mF CLKN Figure 40. Differential Clock Driving Circuit (DIFF_CLK = 1) 0.1mF 0V CLKN CMOS Clock Input CLKP 0.1mF Figure 38. Single-Ended Clock Driving Circuit (DIFF_CLK = 0) When configured to operate in the differential clock mode (register bit DIFF_CLK = 1) the ADS528x clock inputs can be driven differentially (SINE, LVPECL, or LVDS) with little or no difference in performance between them, or with a single-ended (LVCMOS). The common-mode voltage of the clock inputs is set to VCM using internal 5k resistors, as shown in Figure 39. This method allows using transformercoupled drive circuits for a sine wave clock or accoupling for LVPECL and LVDS clock sources, as shown in Figure 40. When operating in the differential clock mode, the single-ended CMOS clock can be accoupled to the CLKP input, with CLKN (pin 11) connected to ground with a 0.1F capacitor, as shown in Figure 41. Copyright (c) 2006-2012, Texas Instruments Incorporated CLKN Figure 41. Single-Ended Clock Driving Circuit When DIFF_CLK = 1 For best performance, the clock inputs must be driven differentially in order to reduce susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock source can help reduce the effect of jitter. If the duty cycle deviates from 50% by more than 2% or 3%, it is recommended to enable the DCC through register bit EN_DCC. 35 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 www.ti.com PLL OPERATION ACROSS SAMPLING FREQUENCY The ADS528X uses a PLL for generating the high speed bit clock (LCLK), the frame clock (ADCLK) & internal clocks for the serializer operation. To enable operation across the entire frequency range, the PLL is automatically configured to one of four states, depending on the sampling clock frequency range. The frequency range detection is automatic and each time the sampling frequency crosses a threshold, the PLL changes its configuration to a new state. To prevent unwanted toggling of PLL state around a threshold, the circuit has an inbuilt hysteresis. The ADS528x has three thresholds - taking into account the hysteresis range of each threshold, variation across devices and temperature, the thresholds can span the sampling clock frequency range from 10MHz to 45MHz. Threshold 1 Threshold 2 Threshold 3 Step 2: Disable the PLL automatic switch and set the PLL configuration depending on the clock frequency SAMPLE CLOCK FREQUENCY RANGE (MSPS) REGISTER SETTING (Hex) Min Max Address Data 10 25 E3 0060 15 45 E3 00A0 With the above settings applied for the respective frequency ranges, the part will continue to operate as per the stated datasheet specifications for all timing parameters at all specified frequencies, EXCEPT for the timing specifications at 40MSPS. At 40MSPS, the affected parameters are - Data setup time, Data hold time and Clock propagation delay (refer to LVDS Timing ). 2. For sampling clock frequency 45MSPS As there are no PLL thresholds beyond 45MHz, no change in PLL configuration can occur as the temperature in the system stabilizes. The ADS528x can be used in the system without using the above software fix. INPUT OVER-VOLTAGE RECOVERY 45 MHz 10 MHz 65 MHz Sampling Frequency Figure 42. Variation of Thresholds Across Sampling Frequency Based on actual system clock frequency, there are two scenarios: 1. For sampling clock frequency < 45MSPS After system power up, depending on the frequency of operation and the frequency threshold for the given device, the frequency range detection circuit may change state once. In some applications where a timing calibration might be done at the system level once after power up, this subsequent change of the PLL state might be undesirable as it can cause a loss of alignment in the received data. A software fix for eliminating this one-time change of PLL state exists using the serial register interface: - Disable the automatic switch of the PLL configuration based on frequency detected. - In addition to disabling the switching, it is also required to set the PLL to the correct configuration, depending on the sample clock frequency used in the system. The following sequence of register writes must be followed: Step 1: Write Address = 0x01, Data = 0x0010 36 The differential peak-to-peak full-scale range supported by the ADS528x is nominally 2.0V. The ADS528x is specially designed to handle an overvoltage condition where the differential peak-to-peak voltage can be up to twice the ADC full-scale range. If the input common-mode is not considerably off from VCM during overload (less than 300mV around the nominal value of 1.5V), recovery from an overvoltage pulse input of twice the amplitude of a fullscale pulse is expected to be within one clock cycle when the input switches from overload to zero signal. REFERENCE CIRCUIT The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels. A typical system would have about 12 octal ADCs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the ADCs to be the same. Matching references within the eight channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures that the reference voltages are well-matched across different chips. All bias currents required for the internal operation of the device are set using an external resistor to ground at the ISET pin. Using a 56.2k resistor on ISET generates an internal reference current of 20A. This current is mirrored internally to generate the bias current for the internal blocks. Using a larger external Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 resistor at ISET reduces the reference bias current and thereby scales down the device operating power. However, it is recommended that the external resistor be within 10% of the specified value of 56.2k so that the internal bias margins for the various blocks are proper. The device also supports the use of external reference voltages. There are two methods to force the references externally. The first method involves pulling INT/EXT low and forcing externally REFT and REFB to 2.5V and 0.5V nominally, respectively. In this mode, the internal reference buffer goes to a 3-state output. The external reference driving circuit should be designed to provide the required switching current for the eight ADCs inside the chip. It should be noted that in this mode, VCM and ISET continue to be generated from the internal bandgap voltage, as in the internal reference mode. It is therefore important to ensure that the common-mode voltage of the externally-forced reference voltages matches to within 50mV of VCM. Buffering the internal bandgap voltage also generates the common-mode voltage VCM, which is set to the midlevel of REFT and REFB, and is accessible on a pin (pin 65 in TQFP-80 package, pin 53 in QFN-64 package). It is meant as a reference voltage to derive the input common-mode if the input is directly coupled. It can also be used to derive the reference common-mode voltage in the external reference mode. The suggested decoupling for the reference pins is shown in Figure 43. The second method of forcing the reference voltages externally can be accessed by pulling INT/EXT low, and programming the serial interface to drive the external reference mode through the VCM pin (register bit called EXT_REF_VCM). In this mode, VCM becomes configured as an input pin that can be driven from external circuitry. The internal reference buffers driving REFT and REFB are active in this mode. Forcing 1.5V on the VCM pin in the mode results in REFT and REFB coming to 2.5V and 0.5V, respectively. In general, the voltages on REFT and REFB in this mode are given by Equation 4 and Equation 5, respectively: VCM VREFT = 1.5V + 1.5V (4) VCM VREFB = 1.5V 1.5V (5) ADS528x ISET REFT REFB 0W to 2W 0.1mF 56.2kW 0W to 2W 2.2mF 2.2mF 0.1mF Figure 43. Suggested Decoupling on the Reference Pins The state of the reference voltage internal buffers during various combinations of the PD, INT/EXT, and EXT_REF_VCM register bits is described in Table 8. Table 8. State of Reference Voltages for Various Combinations of PD, INT/EXT, and EXT_REF_VCM REGISTER BIT (1) INTERNAL BUFFER STATE PD 0 0 1 1 0 0 1 1 INT/EXT 0 1 0 1 0 1 0 1 EXT_REF_VCM 0 0 0 0 1 1 1 1 REFT buffer 3-state 2.5V 3-state 2.5V (1) 1.5V + VCM/1.5V Do not use 2.5V (1) Do not use REFB buffer 3-state 0.5V 3-state 0.5V (1) 1.5V - VCM/1.5V Do not use 0.5V (1) Do not use VCM pin 1.5V 1.5V 1.5V 1.5V Force Do not use Force Do not use Weakly forced with reduced strength. NOISE COUPLING ISSUES High-speed mixed signals are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffers. Maximum care is taken to isolate these noise sources from the sensitive analog blocks. As a starting point, the analog and digital domains of the device are clearly demarcated. AVDD and AVSS are used to denote the supplies for the analog Copyright (c) 2006-2012, Texas Instruments Incorporated sections, while LVDD and LVSS are used to denote the digital supplies. Care is taken to ensure that there is minimal interaction between the supply sets within the device. The extent of noise coupled and transmitted from the digital to the analog sections depends on: 1. The effective inductances of each of the supply and ground sets. 2. The isolation between the digital and analog supply and ground sets. 37 ADS5281 ADS5282 SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 Smaller effective inductance of the supply and ground pins leads to better noise suppression. For this reason, multiple pins are used to drive each supply and ground. It is also critical to ensure that the impedances of the supply and ground lines on the board are kept to the minimum possible values. Use of ground planes in the printed circuit board (PCB) as well as large decoupling capacitors between the supply and ground lines are necessary to obtain the best possible SNR performance from the device. 38 www.ti.com It is recommended that the isolation be maintained on the board by using separate supplies to drive AVDD and LVDD, as well as separate ground planes for AVSS and LVSS. The use of LVDS buffers reduces the injected noise considerably, compared to CMOS buffers. The current in the LVDS buffer is independent of the direction of switching. Also, the low output swing as well as the differential nature of the LVDS buffer results in low-noise coupling. Copyright (c) 2006-2012, Texas Instruments Incorporated ADS5281 ADS5282 www.ti.com SBAS397I - DECEMBER 2006 - REVISED JUNE 2012 REVISION HISTORY Changes from Revision G (March 2008) to Revision H Page * Changed second table and conditions in the Initialization Registers section ....................................................................... 3 * Changed In Input Common-Mode Current section, changed initialization register 5 to initialization registers 1 and 5 to reflect change in Initialization Registers table ................................................................................................................ 33 Changes from Revision F (March 2008) to Revision G Page * Deleted note (3) of Ordering Information table to indicate device status is now Production Data for all parts .................... 2 * Added new note (3) of Ordering Information table to indicate the quantity of transport media is available in the Package Option Addendum .................................................................................................................................................. 2 * Added note (1) to Initialization Registers section to indicate it is no longer necessary to program initialization registers 1 to 4 ...................................................................................................................................................................... 3 * Changed maximum specifications for ADS5282 column in the Power Supply--Internal Reference Mode section of Electrical Characteristics (By Device) table .......................................................................................................................... 6 * Changed minimum specification for ADS5282 column in the f = 10 MHz row of the SNR section of Electrical Characteristics (By Device) table .......................................................................................................................................... 6 Changes from Revision H (March 2008) to Revision I Page * Added table in the INITIALIZATION REGISTERS section ................................................................................................... 3 * Added table in the LVDS OUTPUT TIMING CHARACTERISTICS section ....................................................................... 14 * Added PLL OPERATION ACROSS SAMPLING FREQUENCY section ............................................................................ 36 Copyright (c) 2006-2012, Texas Instruments Incorporated 39 PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS5281IPFP ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IPFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IPFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IPFPRG4 ACTIVE HTQFP PFP 80 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IRGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5281IRGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5282IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5282IRGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5282IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS5282IRGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 18-Jan-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS5281IPFPR HTQFP PFP 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 Q2 ADS5281IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS5281IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS5282IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 ADS5282IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS5281IPFPR HTQFP PFP 80 1000 367.0 367.0 45.0 ADS5281IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS5281IRGCT VQFN RGC 64 250 336.6 336.6 28.6 ADS5282IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 ADS5282IRGCT VQFN RGC 64 250 336.6 336.6 28.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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