AMC7812SPAPR - Texas Instruments - Datasheet.Directory

ADC-REF-IN/CMP

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

D1+

D2+

D1-

D2-

ALARM

DAV

RESET

CNVT

SCLK/SCL

SPI/I2C

DGND

IOVDD

DVDD

SDI/SDA

CS/A0

SDO/A1

REF-DAC

REF-OUT

AGND4

Local

Temperature

Sensor

Remote

Temperature

Sensor

Driver

Out-of-Range

Alarms

Control

Logic

SerialInterfaceRegisterandControl

(SPI/I C)

DACsClearLogic

Control/Limits/Status

Registers

Trigger

Reference

(2.5V)

AMC7812

ADC DAC-0

DAC-11

LOAD-DAC

DAC0-OUT

DAC1-OUT

DAC2-OUT

DAC3-OUT

DAC4-OUT

DAC5-OUT

DAC6-OUT

DAC7-OUT

DAC8-OUT

DAC9-OUT

DAC10-OUT

DAC11-OUT

DAC-CLR-0

DAC-CLR-1

AGND3

AGND2

AGND1

AVDD2

AVDD1

AVCC

Single-Ended/

Differential

Single-Ended

GPIO-5

GPIO-4

GPIO-7

GPIO-6

GPIOController

GPIO-3

GPIO-0

TEMP/GPIO

GPIO

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

12-Bit ANALOG MONITORING AND CONTROL SOLUTION

with Multichannel ADC, DACs, and Temperature Sensors

Check for Samples: AMC7812

1FEATURES DESCRIPTION

The AMC7812 is a complete analog monitoring and

2345• 12, 12-Bit DACs with Programmable Outputs: control solution that includes a 16-channel, 12-bit

◇◇ 0V to 5V analog-to-digital converter (ADC), twelve 12-bit

◇◇ 0V to 12.5V digital-to-analog converters (DACs), eight GPIOs, and

• DAC Shutdown to User-Defined Level two remote/one local temperature sensor channels.

• 12-Bit, 500kSPS ADC with 16 Inputs: The AMC7812 has an internal reference of +2.5V that

◇◇ 16 Single-Ended or can configure the DAC output voltage to a range of

◇◇ Two Differential + 12 Single-Ended either 0V to +5V or 0V to +12.5V. An external

• Two Remote Temperature Sensors: reference can be used as well. Typical power

dissipation is 95mW. The AMC7812 is ideal for

◇◇ –40°C to +150°C, ±2°C Accuracy multichannel applications where board space, size,

• One Internal Temperature Sensor: and low power are critical.

◇◇ –40°C to +125°C, ±2.5°C Accuracy The AMC7812 is available in either a 64-lead QFN or

• Input Out-of-Range Alarms HTQFP-64 PowerPAD™ package and is fully

• 2.5V Internal Reference specified over the –40°C to +105°C temperature

• Eight General-Purpose Input/Outputs range.

• Configurable I2C™-Compatible/ SPI™ Interface For applications that require a different channel

with 5V/3V Logic count, additional features, or converter resolutions,

Texas Instruments offers a complete family of analog

• Power-Down Mode monitor and control (AMC) products. Visit

• Wide Temperature Range: http://www.ti.com/amc for more information.

◇◇ –40°C to +105°C

• Small Packages: 9mm x 9mm QFN-64, and

10mm x 10mm HTQFP-64

APPLICATIONS

• RF Power Amplifier Control in Base Stations

• Test and Measurement

• Industrial Control

• General Analog Monitoring and Control

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc.

3I2C is a trademark of NXP Semiconductors.

4MICROWIRE is a trademark of National Semiconductor.

5All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION(1)

MAXIMUM MAXIMUM

RELATIVE DIFFERENTIAL SPECIFIED

ACCURACY NONLINEARITY PACKAGE- PACKAGE TEMPERATURE PACKAGE

PRODUCT (LSB) (LSB) LEAD DESIGNATOR RANGE MARKING

QFN-64 RGC –40°C to +105°C AMC7812

AMC7812 ±1 ±1 HTQFP-64 PAP –40°C to +105°C AMC7812

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range, unless otherwise noted. AMC7812 UNIT

AVDD to GND –0.3 to +6 V

DVDD to GND –0.3 to +6 V

IOVDD to GND –0.3 to +6 V

AVCC to GND –0.3 to +18 V

DVDD to DGND –0.3 to +6 V

Analog input voltage to GND –0.3 to AVDD + 0.3 V

ALARM, GPIO-0, GPIO-1, GPIO-2, GPIO-3, SCLK/SCL, and SDI/SDA to GND –0.3 to +6 V

D1+/GPIO-4, D1–/GPIO-5, D2+/GPIO-6, D2–/GPIO-7 to GND –0.3 to AVDD + 0.3 V

Digital input voltage to DGND –0.3 to IOVDD + 0.3 V

SDO and DAV to GND –0.3 to IOVDD + 0.3 V

Operating temperature range –40 to +105 °C

Storage temperature range –40 to +150 °C

Junction temperature range (TJmax) +150 °C

Human body model (HBM) 2.5 kV

ESD ratings Charged device model (CDM) 1.0 kV

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

THERMAL INFORMATION AMC7812

THERMAL METRIC(1) RGC (QFN) PAP (HTQFP) UNITS

64 PINS 64 PINS

θJA Junction-to-ambient thermal resistance 24.1 33.7

θJCtop Junction-to-case (top) thermal resistance 8.1 9.5

θJB Junction-to-board thermal resistance 3.2 9.0 °C/W

ψJT Junction-to-top characterization parameter 0.1 0.3

ψJB Junction-to-board characterization parameter 3.3 8.9

θJCbot Junction-to-case (bottom) thermal resistance 0.6 0.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

ELECTRICAL CHARACTERISTICS

At TA= –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal

2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC PERFORMANCE

DAC DC ACCURACY

Resolution 12 Bits

Measured by line passing through codes 020h

INL Relative accuracy ±1 LSB

and FFFh

12-bit monotonic, Measured by line passing

DNL Differential nonlinearity ±0.3 ±1 LSB

through codes 020h and FFFh

TA= +25°C, DAC output = 5.0V ±10 mV

TUE Total unadjusted error TA= +25°C, DAC output = 12.5V ±30 mV

TA= +25°C, DAC output = 0V to +5V, ±2 mV

code 020h

Offset error TA= +25°C, DAC output = 0V to +12.5V, ±5 mV

code 020h

Offset error temperature coefficient ±1 ppm/°C

External reference, output = 0V to +5V ±0.025 ±0.15 %FSR

Gain error External reference, output = 0V to +12.5V -0.15 ±0.3 %FSR

Gain temperature coefficient ±2 ppm/°C

DAC OUTPUT CHARACTERISTICS

VREF = 2.5V, gain = 2 0 5 V

Output voltage range(1) VREF = 2.5V, gain = 5 0 12.5 V

DAC output = 0V to +5V, code 400h to C00h, to

Output voltage settling time(2) ½ LSB, from CS rising edge, 3 µs

RL= 2kΩ, CL= 200pF

Slew rate(2) 1.5 V/µs

Short-circuit current(2) Full-scale current shorted to ground 30 mA

Source within 200mV of supply +10 mA

Load current Sink within 300mV of supply -10 mA

Capacitive load stability(2) RL=∞10 nF

DC output impedance(2) Code 800h 0.3 Ω

Power-on overshoot AVCC 0 to 5V, 2ms ramp 5 mV

Digital-to-analog glitch energy Code changes from 7FFh to 800h, 800h to 7FFh 0.15 nV-s

Digital feedthrough Device is not accessed 0.15 nV-s

TA= +25°C, at 1kHz, code 800h, gain = 2, 81 nV/√Hz

excludes reference

Output noise f = 0.1Hz to 10Hz, excludes reference 8 µVPP

DAC REFERENCE INPUT

Reference voltage input range REF-DAC pin 1 2.6 V

Input current(2) VREF = 2.5V 170 µA

INTERNAL REFERENCE

Output voltage TA= +25°C, REF-OUT pin 2.495 2.5 2.505 V

Output impedance 0.4 Ω

Reference temperature coefficient 10 25 ppm/°C

Output current (sourcing/sinking) ±5 mA

TA= +25°C, f = 1kHz 260 nV/√Hz

Output voltage noise f = 0.1Hz to 10Hz 13 µVPP

(1) The output voltage must not be greater than AVCC. See the DAC Output section for more details.

(2) Sampled during initial release to ensure compliance; not subject to production testing.

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ELECTRICAL CHARACTERISTICS (continued)

At TA= –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal

2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC PERFORMANCE

ADC DC ACCURACY (for AVDD = 5V)

Resolution 12 Bits

INL Integral nonlinearity ±0.5 ±1 LSB

DNL Differential nonlinearity ±0.5 ±1 LSB

Single-Ended Mode

Offset error ±1 ±3 LSB

Offset error match ±0.4 LSB

Gain error External reference ±1 ±5 LSB

Gain error match ±0.4 LSB

Differential Mode

External reference, 0V to (2 · VREF) mode, VCM =±2 ±5 LSB

2.5V

Gain error External reference, 0V to VREF mode, ±1 ±5 LSB

VCM = 1.25V

Gain error match ±0.5 LSB

0V to (2 · VREF) mode, VCM = 2.5V ±1 ±3 LSB

Zero code error External reference, 0V to VREF mode, ±1 ±3 LSB

VCM = 1.25V

Zero code error match ±0.5 LSB

Common mode rejection DC, 0V to (2 · VREF) mode 67 dB

SAMPLING DYNAMICS

External single analog channel, auto mode 500 kSPS

Conversion rate External single analog channel, direct mode 167 kSPS

Conversion time(3) External single analog channel 2 µs

Autocycle update rate(3) All 16 single-ended inputs enabled 32 µs

SPI clock 12MHz or greater, single analog

Throughput rate 500 kSPS

channel

ANALOG INPUT(4)

Single-ended, 0V to VREF mode 0 VREF V

Single-ended, 0V to (2 · VREF) mode 0 2 · VREF V

Full-scale input voltage VIN+ – VIN-, fully-differential, 0V to VREF mode –VREF +VREF V

VIN+ – VIN-, fully-differential, 0V to (2 · VREF)–2 · VREF 2 · VREF V

mode

Absolute input voltage GND - 0.2 AVDD + 0.2 V

Input capacitance(3) 40 pF

DC input leakage current Unselected ADC input ±10 µA

ADC REFERENCE INPUT

Reference input voltage range 1.2 AVDD V

Input current VREF = 2.5V 145 µA

INTERNAL ADC REFERENCE BUFFER

Offset TA= +25°C ±5 mV

(3) Sampled during initial release to ensure compliance; not subject to production testing.

(4) VIN+ or VIN– must remain within GND - 0.2V and AVDD + 0.2V. See Analog Inputs section.

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

ELECTRICAL CHARACTERISTICS (continued)

At TA= –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal

2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL TEMPERATURE SENSOR

Operating range –40 +125 °C

AVDD = 5V, TA= –40°C to +125°C ±1.25 ±2.5 °C

Accuracy AVDD = 5V, TA= 0°C to +100°C ±1.5 °C

Resolution Per LSB 0.125 °C

Conversion rate External temperature sensors are disabled 15 ms

EXTERNAL TEMPERATURE SENSOR (Using 2N3906 external transistor)

Operating range Limited by external diode –40 +150 °C

AVDD = 5V, TA= 0°C to +100°C, ±1.5 °C

TD= –40°C to +150°C

Accuracy(5)(6) AVDD = 5V, TA= –40°C to +100°C, ±2 °C

TD= –40°C to +150°C

Resolution Per LSB 0.125 °C

With resistance cancellation 72 93 100 ms

(RC bit = '1')

Conversion rate per sensor Without resistance cancellation 33 44 47 ms

(RC bit = '0')

DIGITAL LOGIC: GPIO(7)(8) and ALARM

IOVDD = +5V 2.1 0.3 + IOVDD V

VIH Input high voltage IOVDD = +3.3V 2.1 0.3 + IOVDD V

IOVDD = +5V –0.3 0.8 V

VIL Input low voltage IOVDD = +3.3V –0.3 0.8 V

IOVDD = +5V, sinking 5mA 0.4 V

VOL Output low voltage IOVDD = +3.3V, sinking 2mA 0.4 V

High-impedance leakage 5 µA

High-impedance output capacitance 10 pF

DIGITAL LOGIC: All Except SCL, SDA, ALARM, and GPIO

IOVDD = +5V 2.1 0.3 + IOVDD V

VIH Input high voltage IOVDD = +3.3V 2.1 0.3 + IOVDD V

IOVDD = +5V –0.3 0.8 V

VIL Input low voltage IOVDD = +3.3V –0.3 0.8 V

Input current ±1 µA

Input capacitance 5 pF

IOVDD = +5V, sourcing 3mA 4.8 V

VOH Output high voltage IOVDD = +3.3V, sourcing 3mA 2.9 V

IOVDD = +5V, sinking 3mA 0.4 V

VOL Output low voltage IOVDD = +3.3V, sinking 3mA 0.4 V

High-impedance leakage ±5 µA

High-impedance output capacitance 10 pF

(5) TDis the external diode temperature.

(6) Auto conversion mode disabled

(7) For pins GPIO0-3, the external pull up resistor must be connected to a voltage less than or equal to 5.5V.

(8) For pins GPIO4-7, the external pull up resistor must be connected to a voltage less than or equal to AVDD.

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ELECTRICAL CHARACTERISTICS (continued)

At TA= –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AVCC = +15V, AGND = DGND = 0V, IOVDD = 2.7V to 5.5V, internal

2.5V reference, and the DAC output span = 0V to 5V, unless otherwise noted. AMC7812

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL LOGIC: SDA, SCL (I2C-Compatible Interface)

IOVDD = +5V 2.1 0.3 + IOVDD V

VIH Input high voltage IOVDD = +3.3V 2.1 0.3 + IOVDD V

IOVDD = +5V –0.3 0.8 V

VIL Input low voltage IOVDD = +3.3V –0.3 0.8 V

Input current ±5 µA

Input capacitance 5 pF

IOVDD = +5V, sinking 3mA 0 0.4 V

VOL Output low voltage IOVDD = +3.3V, sinking 3mA 0 0.4 V

High-impedance leakage ±5 µA

High-impedance output capacitance 10 pF

TIMING REQUIREMENTS

From AVDD , DVDD ≥2.7V and AVCC ≥4.5V to

Power-on delay 100 250 µs

normal operation

Power-down recovery time from CS rising edge 70 µs

Reset delay Delay to normal operation from any reset 100 250 µs

Convert pulse width 20 ns

Reset pulse width 20 ns

POWER-SUPPLY REQUIREMENTS

AVDD AVDD must be ≥(VREF + 1.2V) +2.7 +5.5 V

AVDD and DVDD combined, 7.9 12.5 mA

normal operation, no DAC load

AIDD AVDD and DVDD combined, 1.6 mA

all blocks in power down

AVCC +4.5 +18 V

IVCC AVCC, no load, DACs at code 800h 6.5 mA

Normal operation(9), AVDD = DVDD = 5V, AVCC =

Power dissipation 95 120 mW

15V

DVDD +2.7 +5.5 V

IOVDD +2.7 +5.5 V

TEMPERATURE RANGE

Specified performance –40 +105 °C

(9) No DAC load, all DACs at 800h and both ADCs at the fastest auto conversion rate

Product Folder Link(s): AMC7812

ADC-REF-IN/CMP

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

D1+

D2+

D1-

D2-

ALARM

DAV

RESET

CNVT

SCLK/SCL

SPI/I2C

DGND

IOVDD

DVDD

SDI/SDA

CS/A0

SDO/A1

REF-DAC

REF-OUT

AGND4

Local

Temperature

Sensor

Remote

Temperature

Sensor

Driver

Out-of-Range

Alarms

Control

Logic

SerialInterfaceRegisterandControl

(SPI/I C)

DACsClearLogic

Control/Limits/Status

Registers

Trigger

Reference

(2.5V)

AMC7812

ADC DAC-0

DAC-11

LOAD-DAC

DAC0-OUT

DAC1-OUT

DAC2-OUT

DAC3-OUT

DAC4-OUT

DAC5-OUT

DAC6-OUT

DAC7-OUT

DAC8-OUT

DAC9-OUT

DAC10-OUT

DAC11-OUT

DAC-CLR-0

DAC-CLR-1

AGND3

AGND2

AGND1

AVDD2

AVDD1

AVCC

Single-Ended/

Differential

Single-Ended

GPIO-5

GPIO-4

GPIO-7

GPIO-6

GPIOController

GPIO-3

GPIO-0

TEMP/GPIO

GPIO

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

FUNCTIONAL BLOCK DIAGRAM

Product Folder Link(s): AMC7812

AMC7812

RESET

DAV

CNVT

SDI/SDA

SCLK/SCL

DGND

IOV

/A0

SDO/A1

SPI/I2C

GPIO-0

GPIO-1

GPIO-2

GPIO-3

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

DAC-CLR-0

DAC5-OUT

DAC4-OUT

DAC3-OUT

AGND4

AGND3

DAC2-OUT

DAC1-OUT

DAC0-OUT

D2 /GPIO-6

D2+/GPIO-7

D1 /GPIO-4

D1+/GPIO-5

ADC-REF-IN/CMP

ADC-GND

CC2

DGND2

DAC11-OUT

DAC10-OUT

DAC9-OUT

REF-DAC

REF-OUT

AGND2

AGND1

DAC8-OUT

DAC7-OUT

DAC6-OUT

DAC-CLR-1

ALARM

CC1

DD2

DD1

AMC7812

RESET

DAV

CNVT

SDI/SDA

SCLK/SCL

DGND

IOV

/A0

SDO/A1

SPI/I2C

GPIO-0

GPIO-1

GPIO-2

GPIO-3

CH15

CH14

CH13

CH12

CH11

CH10

CH9

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

DAC-CLR-0

DAC5-OUT

DAC4-OUT

DAC3-OUT

AGND4

AGND3

DAC2-OUT

DAC1-OUT

DAC0-OUT

D2-/GPIO-6

D2+/GPIO-7

D1-/GPIO-4

D1+/GPIO-5

ADC-REF-IN/CMP

ADC-GND

CC2

DGND2

DAC11-OUT

DAC10-OUT

DAC9-OUT

REF-DAC

REF-OUT

AGND2

AGND1

DAC8-OUT

DAC7-OUT

DAC6-OUT

DAC-CLR-1

ALARM

CC1

DD2

DD1

AMC7812

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PIN CONFIGURATION

RGC PACKAGE

QFN-64

(TOP VIEW)

PAP PACKAGE

HTQFP-64

(TOP VIEW)

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PIN DESCRIPTIONS

PIN (QFN / HTQFP) DESCRIPTION

NO. NAME

1 RESET Reset input, active low. Logic low on this pin causes the device to perform a hardware reset.

Data available indicator, active low output. In direct mode, the DAV pin goes low (active) when the conversion

2 DAV ends. In auto mode, a 1µs pulse (active low) appears on this pin when a conversion cycle finishes (see the

Primary ADC Operation and Registers sections for details). DAV stays high when deactivated.

3 CNVT External conversion trigger, active low. The falling edge starts the sampling and conversion of the ADC.

Serial interface data. SDI for the serial peripheral interface (SPI) when the SPI/I2C pin is high. SDA for I2C

4 SDI/SDA when the SPI/I2C pin is low.

Serial clock input of the main serial interface. SPI clock when the SPI/I2C pin is high; I2C clock when the

5 SCLK/SCL SPI/I2C pin is low.

6 DGND Digital ground

7 IOVDD Interface power supply

8 DVDD Digital power supply (+3V to +5V). Must be the same value as AVDD.

Chip select signal for SPI when the SPI/I2C pin is high. Slave address selection A0 for I2C when the SPI/I2C

9 CS/A0 pin is low.

10 SDO/A1 SDO for SPI when the SPI/I2C pin is high. Slave address selection A1 for I2C when the SPI/I2C pin is low.

11 A2 Slave address selection A2 for I2C when the SPI/I2C pin is low.

Interface selection pin. Digital input. When this pin is tied to IOVDD, the SPI is enabled and the I2C interface is

12 SPI/I2C disabled. When this pin is tied to ground, the SPI is disabled and the I2C interface is enabled.

13 GPIO-0

14 GPIO-1 General-purpose digital input/output. This pin is a bidirectional open-drain, digital input/output, and requires an

external pull-up resistor. See the General Purpose Input/Output Pins section for more details.

15 GPIO-2

16 GPIO-3 DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter

a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.

17 DAC-CLR-0 However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC

Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,

regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.

18 DAC5-OUT

19 DAC4-OUT Output of DAC channels 3, 4, and 5

20 DAC3-OUT

21 AGND4 Analog ground

22 AGND3 Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, DAC5-OUT, must be

23 AVCC2 tied to AVCC1

24 DAC2-OUT

25 DAC1-OUT Output of DAC channels 0, 1, and 2

26 DAC0-OUT

27 D2–/GPIO-6 Remote sensor D2 negative input when D2 enabled; GPIO-6 when D2 disabled. Pull-up required for output.

28 D2+/GPIO-7 Remote sensor D2 positive input when D2 enabled; GPIO-7 when D2 disabled. Pull-up required for output.

29 D1–/GPIO4 Remote sensor D1 negative input when D1 enabled; GPIO-6 when D1 disabled. Pull-up required for output.

30 D1+/GPIO-5 Remote sensor D1 positive input when D1 enabled; GPIO-7 when D1 disabled. Pull-up required for output.

External ADC reference input when external VREF is used to drive ADC. Compensation capacitor connection

31 ADC-REF-IN/CMP (connect 4.7µF capacitor between this pin and AGND) when Internal VREF is used to drive ADC.

32 ADC-GND ADC ground. Must be connected to AGND.

33- Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be

CH0 to CH15

48 programmed as differential or single-ended.

49 AVDD1 Positive analog power supply

50 AVDD2

51 DAC6-OUT

52 DAC7-OUT Output of DAC channels 6, 7, and 8

53 DAC8-OUT

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PIN DESCRIPTIONS (continued)

PIN (QFN / HTQFP) DESCRIPTION

NO. NAME

54 AGND1 Analog ground

55 AGND2 Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, DAC11-OUT, must

56 AVCC1 be tied to AVCC2

57 REF-OUT Internal reference output

58 REF-DAC DAC reference Input

59 DAC9-OUT

60 DAC10-OUT Output of DAC channels 9, 10, and 11

61 DAC11-OUT Global alarm. Open drain output. External 10kΩpull-up resistor required. This pin goes low (active) when one

62 ALARM (or more) of the analog channels are out of range.

DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter

a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.

63 DAC-CLR-1 However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC

Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,

regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.

64 DGND2 Digital ground

Product Folder Link(s): AMC7812

tHD, STA

tSU, DAT

tHD, DAT

tSU, STA

tSU, STO

tHD,STA

tLOW

tHIGH

tRtF

tBUF

SDA

SCL

S Sr P S

S=STARTCondition

Sr=RepeatedSTARTCondition

P=STOPCondition

=ResistorPull-Up

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

I2C-COMPATIBLE TIMING DIAGRAMS

Figure 1. Timing for Standard and Fast Mode Devices on the I2C Bus

TIMING CHARACTERISTICS: SDA and SCL for Standard and Fast Modes(1)

At –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AGND = DGND = 0V, and IOVDD = 2.7V to 5.5V, unless otherwise noted.

STANDARD FAST

MODE MODE

PARAMETER MIN MAX MIN MAX UNIT

fSCL SCL clock frequency 0 100 0 400 kHz

tLOW Low period of the SCL clock 4.7 — 1.3 — ms

tHIGH High period of the SCL clock 4.0 — 0.6 — ms

tSU, STA Set-up time for a repeated start condition 4.7 — 0.6 — ms

Hold time (repeated) start condition. After this

tHD, STA 4..0 — 0.6 — ms

period, the first clock pulse is generated

tSU, DAT Data set-up time 250 — 100 — ns

tHD, DAT Data hold time: for I2C-bus devices 0 3.45 0 0.9 ms

tSU, STO Set-up time for stop condition 4.0 — 0.6 — ms

tRRise time of both SDA and SCL signals — 1000 20 + 0.1CB(2) 300 ns

tFFall time of both SDA and SCL signals — 300 20 + 0.1CB(2) 300 ns

tBUF Bus free time between a stop and start condition 4.7 — 1.3 — ms

CBCapacitive load for each bus line — 400 — 400 pF

tSP Pulse width of spike suppressed NA NA 0 50 ns

(1) All values refer to VIHmin and VILmax levels.

(2) CB= total capacitance of one bus line in pF.

Product Folder Link(s): AMC7812

SDA

tFDA

tRDA

tSU, STA tHD, STA

SCL

tHD, DAT

tSU, DAT

tRCL1

(1) tRCL1

(1)

tHIGH tLOW tLOW

tRCL

tFCL

tHIGH

tSU, STO

=CurrentSourcePull-Up

=ResistorPull-Up

Sr=RepeatedSTARTCondition

P=STOPCondition

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

www.ti.com

(1) First rising edge of the SCL signal after Sr and after each acknowledge bit.

Figure 2. Timing for High-Speed (Hs) Mode Devices on the I2C Bus

TIMING CHARACTERISTICS: SDA and SCL for Hs Mode(1)

At –40°C to +105°C, AVDD = 4.5V to 5.5V, DVDD = 2.7V to 5.5V, AGND = DGND = 0V, and IOVDD = 2.7V to 5.5V, unless

otherwise noted. CB= 10pF to 100pF CB= 400pF

PARAMETER MIN MAX MIN MAX UNIT

fSCL SCL clock frequency 0 3.4 0 1.7 MHz

tSU, STA Setup time for (repeated) start condition 160 — 160 — ns

tHD, STA Hold time (repeated) start condition 160 — 160 — ns

tLOW Low period of the SCL clock 160 — 320 — ns

tHIGH High period of the SCL clock 60 — 120 — ns

tSU, DAT Data setup time 10 — 10 — ns

tHD, DAT Data hold time 0 70 0 150 ns

tRCL Rise time of SCL signal 10 40 20 80 ns

Rise time of SCL signal after a repeated start condition

tRCL1 10 80 20 160 ns

and after an acknowledge bit

tFCL Fall time of SCL signal 10 40 20 80 ns

tRDA Rise time of SDA signal 10 80 20 160 ns

tFDA Fall time of SDA signal 10 80 20 160 ns

tSU, STO Set-up time for stop condition 160 — 160 — ns

CB(2) Capacitive load for SDA and SCL lines 10 100 — 400 pF

tSP Pulse width of spike suppressed 0 10 0 10 ns

(1) All values refer to VIHmin and VILmax levels.

(2) For bus line loads where CBis between 100pF and 400pF, the timing parameters must be linearly interpolated.

Product Folder Link(s): AMC7812

-- Don’tCare Bit23=MSB

Bit23

SCLK

SDI

Bit0

Bit1

t10

SDI

SCLK

SDO

Bit23 Bit22 Bit0

Bit1

ReadCommand AnyCommand

DataReadfromtheRegisterSelected

inthePreviousReadOperation

Bit23 Bit22 Bit0

Bit1

Bit0Bit23

tFtR

t5t6

Bit22

SDO

Bit23(A) Bit0(A)

SCLK

SDI Bit0(B)

Bit23(A) Bit0(A)

Bit23(B)

(CommandtoA) (CommandtoB)

tFtR

t1t7

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

SPI TIMING DIAGRAMS

Figure 3. SPI Single-Chip Write Operation

Figure 4. SPI Single-Chip Read Operation

Figure 5. Daisy-Chain Operation: Two Devices

Product Folder Link(s): AMC7812

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

www.ti.com

TIMING CHARACTERISTICS: SPI Bus(1)

At –40°C to +105°C, AVDD = DVDD = 4.5V to 5.5V, AGND = DGND = 0V, and IOVDD = 3.0V to 5.5V, unless otherwise noted.

LIMIT AT TMIN, TMAX

PARAMETER MIN MAX UNIT

fSCLK Clock frequency 50 MHz

t1SCLK cycle time 20 ns

t2SCLK high time 8 ns

t3SCLK low time 8 ns

t4CS falling edge to SCLK rising edge setup time 5 ns

t5Input data setup time 5 ns

t6Input data hold time 4 ns

t7SCLK falling edge to CS rising edge 10 ns

t8Minimum CS high time 30 ns

t9Output data valid time 15 ns

t10 CS rising to next SCLK rising edge 3 ns

(1) Specified by design; not production tested.

Product Folder Link(s): AMC7812

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = −40°C

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = −40°C

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +105°C

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +105°C

Gain = 2

VREF = 2.5V, Internal

AMC7812

www.ti.com

SBAS513C –JANUARY 2011–REVISED MARCH 2012

TYPICAL CHARACTERISTICS: DAC

At +25°C, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 6. Figure 7.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 8. Figure 9.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 10. Figure 11.

Product Folder Link(s): AMC7812

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +25°C

Gain = 5

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +25°C

Gain = 5

VREF = 2.5V, Internal

−40 −25 −10 5 20 35 50 65 80 95 110

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

DNL Max

DNL Min

TA (°C )

DNL (LSB)

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

−40 −25 −10 5 20 35 50 65 80 95 110

INL Max

INL Min

TA (°C )

INL (LSB)

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

−40 −25 −10 5 20 35 50 65 80 95 110

DNL Max

DNL Min

TA (°C )

DNL (LSB)

Gain = 5

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

−40 −25 −10 5 20 35 50 65 80 95 110

INL Max

INL Min

TA (°C )

INL (LSB)

Gain = 5

VREF = 2.5V, Internal

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

www.ti.com

TYPICAL CHARACTERISTICS: DAC (continued)

At +25°C, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 12. Figure 13.

DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE LINEARITY ERROR vs TEMPERATURE

Figure 14. Figure 15.

DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE LINEARITY ERROR vs TEMPERATURE

Figure 16. Figure 17.

Product Folder Link(s): AMC7812

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

Ch0

Ch1

Ch2

Ch3

Ch4

Ch5

Ch6

Ch7

Ch8

Ch9

Ch10

Ch11

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

Ch0

Ch1

Ch2

Ch3

Ch4

Ch5

Ch6

Ch7

Ch8

Ch9

Ch10

Ch11

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

TA=+25°C

Gain=2

10884Channels

-0.15

-0.13

-0.11

-0.09

-0.07

-0.05

-0.03

-0.01

0.01

0.03

0.05

0.07

0.09

0.11

0.13

0.15

GainError(%FSR)

Population(%)

TA=+25°C

Gain=5

10368Channels

-0.3

-0.26

-0.22

-0.18

-0.14

-0.1

-0.06

-0.02

0.02

0.06

0.1

0.14

0.18

0.22

0.26

0.3

GainError(%FSR)

Population(%)

−0.15

−0.1

−0.05

0.05

0.1

0.15

−40 −25 −10 5 20 35 50 65 80 95 110

TA (°C )

Gain Error (%FSR)

Gain = 2

VREF = 2.5V, Internal

−0.3

−0.2

−0.1

0.1

0.2

0.3

−40 −25 −10 5 20 35 50 65 80 95 110

TA (°C )

Gain Error (%FSR)

Gain = 5

VREF = 2.5V, Internal

AMC7812

www.ti.com

SBAS513C –JANUARY 2011–REVISED MARCH 2012

TYPICAL CHARACTERISTICS: DAC (continued)

At +25°C, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 18. Figure 19.

GAIN ERROR GAIN ERROR

Figure 20. Figure 21.

GAIN ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE

Figure 22. Figure 23.

Product Folder Link(s): AMC7812

−0.15

−0.1

−0.05

0.05

0.1

0.15

4.5 6 7.5 9 10.5 12 13.5 15 16.5 18

AVCC (V)

Gain Error (%FSR)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

−0.3

−0.2

−0.1

0.1

0.2

0.3

12 13 14 15 16 17 18

AVCC (V)

Gain Error (%FSR)

TA = +25°C

Gain = 5

VREF = 2.5V, Internal

TA=+25°C

Gain=2

VREF =2.5V,Internal

Code=020h

2220Channels

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.6

OffsetError(mV)

Population(%)

TA=+25°C

Gain=5

VREF =2.5V,Internal

Code=020h

10884Channels

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.2

1.4

1.6

OffsetError(mV)

Population(%)

−2

−1.5

−1

−0.5

0.5

1.5

−40 −25 −10 5 20 35 50 65 80 95 110

TA (°C )

Offset Error (mV)

Gain = 2

VREF = 2.5V, Internal

Code = 020h

−5

−4

−3

−2

−1

−40 −25 −10 5 20 35 50 65 80 95 110

TA (°C )

Offset Error (mV)

Gain = 5

VREF = 2.5V, Internal

Code = 020h

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

www.ti.com

TYPICAL CHARACTERISTICS: DAC (continued)

At +25°C, unless otherwise noted.

GAIN ERROR vs SUPPLY GAIN ERROR vs SUPPLY

Figure 24. Figure 25.

OFFSET VOLTAGE OFFSET VOLTAGE

Figure 26. Figure 27.

OFFSET VOLTAGE vs TEMPERATURE OFFSET VOLTAGE vs TEMPERATURE

Figure 28. Figure 29.

Product Folder Link(s): AMC7812

−3

−2

−1

4.5 6 7.5 9 10.5 12 13.5 15 16.5 18

AVCC (V)

Offset Error (mV)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

Code = 020h

−5

−3

−1

12 13 14 15 16 17 18

AVCC (V)

Offset Error (mV)

TA = +25°C

Gain = 5

VREF = 2.5V, Internal

Code = 020h

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

−40 −30 −20 −10 0 10 20 30 40

ILOAD (mA)

Voltage Output (V)

TA = +25°C

AVCC = 15V

Gain = 2

VREF = 2.5V, Internal

Code = 800h

4.7

4.75

4.8

4.85

4.9

4.95

0 2 4 6 8 10 12

ILOAD (mA)

Voltage Output (V)

FFFh

FF0h

FE0h

FC0h

F80h

TA = +25°C

AVCC = 5V

Gain = 2

VREF = 2.5V, Internal

100

150

200

250

300

350

−12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0

ILOAD (mA)

Voltage Output (mV)

080h

040h

020h

010h

000h

TA = +25°C

AVCC = 15V

Gain = 2

VREF = 2.5V, Internal

3.3

3.5

3.7

3.9

4.1

4.3

4.5

4.7

4.9

4.5 6 7.5 9 10.5 12 13.5 15 16.5 18

AVCC (V)

IVCC (mA)

TA = +25°C

Gain = 2

VREF = 2V, External

Code = 800h

AMC7812

www.ti.com

SBAS513C –JANUARY 2011–REVISED MARCH 2012

TYPICAL CHARACTERISTICS: DAC (continued)

At +25°C, unless otherwise noted.

OFFSET VOLTAGE vs SUPPLY VOLTAGE OFFSET VOLTAGE vs SUPPLY VOLTAGE

Figure 30. Figure 31.

OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs SOURCE CURRENT CAPABILITY

Figure 32. Figure 33.

OUTPUT VOLTAGE vs SINK CURRENT CAPABILITY DAC SUPPLY CURRENT vs DAC SUPPLY VOLTAGE

Figure 34. Figure 35.

Product Folder Link(s): AMC7812

3.4

3.7

4.4

4.7

5.1

5.4

5.8

6.1

6.5

0 512 1024 1536 2048 2560 3072 3584 4096

Code

IVCC (mA)

All DAC Channels

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

3.5

4.5

5.5

−40 −25 −10 5 20 35 50 65 80 95 110

TA (°C )

IVCC (mA)

Gain = 2

VREF = 2.5V, Internal

Code = 800h

200

400

600

800

1000

1200

1400

10 100 1k 10k 100k 1M

Frequency (Hz)

Noise (nV/ Hz)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

3.5

3.7

3.9

4.1

4.3

4.5

4.7

4.9

5.1

5.3

5.5

5.7

5.9

6.1

6.3

6.5

AICC (mA)

Population(%)

30Units

TA=+25°C

−3 0 3 6 9 12

−2

−1.5

−1

−0.5

0.5

1.5

Time (µs)

Small Signal (LSB)

Large Signal (V)

DAC Out SS

DAC Out LS

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

RL= 2KΩ, CL = 250pF

−20

−15

−10

−5

0 4 8 12 16 20

Time (s)

VNOISE (µV)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

Code = 800h

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

www.ti.com

TYPICAL CHARACTERISTICS: DAC (continued)

At +25°C, unless otherwise noted.

SUPPLY CURRENT vs DAC CODE SUPPLY CURRENT vs TEMPERATURE

Figure 36. Figure 37.

DAC SUPPLY CURRENT DAC NOISE VOLTAGE vs FREQUENCY

Figure 38. Figure 39.

DAC NOISE 0.1Hz to 10Hz SETTLING TIME RISING EDGE

Figure 40. Figure 41.

Product Folder Link(s): AMC7812

−3 0 3 6 9 12

−2

−1.5

−1

−0.5

0.5

1.5

Time (µs)

Small Signal (LSB)

Large Signal (V)

DAC Out SS

DAC Out LS

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

RL= 2KΩ, CL = 250pF

AMC7812

www.ti.com

SBAS513C –JANUARY 2011–REVISED MARCH 2012

TYPICAL CHARACTERISTICS: DAC (continued)

At +25°C, unless otherwise noted. SETTLING TIME FALLING EDGE

Figure 42.

Product Folder Link(s): AMC7812

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +25°C

0V to VREF Mode

VREF = 2.5V, Internal

Single−Ended Mode

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +25°C

0V to VREF Mode

VREF = 2.5V, Internal

Single−Ended Mode

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +25°C

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Single−Ended Mode

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +25°C

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Single−Ended Mode

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +25°C

0V to VREF Mode

VREF = 2.5V, Internal

Differential Mode

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +25°C

0V to VREF Mode

VREF = 2.5V, Internal

Differential Mode

AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

www.ti.com

TYPICAL CHARACTERISTICS: ADC

At +25°C, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 43. Figure 44.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 45. Figure 46.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 47. Figure 48.

Product Folder Link(s): AMC7812

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

DNL (LSB)

TA = +25°C

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Differential Mode

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

0 512 1024 1536 2048 2560 3072 3584 4096

Code

INL (LSB)

TA = +25°C

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Differential Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

DNL Max

DNL Min

TA (°C )

DNL (LSB)

0V to VREF Mode

VREF = 2.5V, Internal

Single−Ended Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

DNL Max

DNL Min

TA (°C )

DNL (LSB)

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Single−Ended Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

DNL Max

DNL Min

TA (°C )

DNL (LSB)

0V to VREF Mode

VREF = 2.5V, Internal

Differential Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

DNL Max

DNL Min

TA (°C )

DNL (LSB)

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Differential Mode

AMC7812

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TYPICAL CHARACTERISTICS: ADC (continued)

At +25°C, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR vs CODE LINEARITY ERROR vs CODE

Figure 49. Figure 50.

DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE

Figure 51. Figure 52.

DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE

Figure 53. Figure 54.

Product Folder Link(s): AMC7812

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

INL Max

INL Min

TA (°C )

INL (LSB)

0V to VREF Mode

VREF = 2.5V, Internal

Single−Ended Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

INL Max

INL Min

TA (°C )

INL (LSB)

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Single−Ended Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

INL Max

INL Min

TA (°C )

INL (LSB)

0V to VREF Mode

VREF = 2.5V, Internal

Differential Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−1

−0.8

−0.6

−0.4

−0.2

0.2

0.4

0.6

0.8

INL Max

INL Min

TA (°C )

INL (LSB)

0V to (2⋅VREF) Mode

VREF = 2.5V, Internal

Differential Mode

−3

−2.5

−2

−1.5

−1

−0.5

0.5

1.5

2.5

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

AVDD (V)

Gain Error (LSB)

0V to VREF Mode

0V to (2⋅VREF) Mode

TA = +25°C

VREF = 2.5V, Internal

Single−Ended Mode

−40 −25 −10 5 20 35 50 65 80 95 110 125

−3

−2.5

−2

−1.5

−1

−0.5

0.5

1.5

2.5

TA (°C )

Gain Error (LSB)

0V to VREF Mode

0V to (2⋅VREF) Mode VREF = 2.5V, Internal

Single−Ended Mode

AMC7812

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TYPICAL CHARACTERISTICS: ADC (continued)

At +25°C, unless otherwise noted.

LINEARITY ERROR vs TEMPERATURE LINEARITY ERROR vs TEMPERATURE

Figure 55. Figure 56.

LINEARITY ERROR vs TEMPERATURE LINEARITY ERROR vs TEMPERATURE

Figure 57. Figure 58.

GAIN ERROR vs SUPPLY GAIN ERROR vs TEMPERATURE

Figure 59. Figure 60.

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−40 −25 −10 5 20 35 50 65 80 95 110 125

−5

−4

−3

−2

−1

TA (dB)

Offset Error (LSB)

0V to VREF Mode

0V to (2⋅VREF) Mode VREF = 2.5V, Internal

Single−Ended Mode

480

482

484

486

488

490

492

494

496

498

500

502

504

506

508

510

512

514

516

518

520

ConversionFrequency(kHz)

Population(%)

972Units

460

470

480

490

500

510

520

530

540

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

AVDD (V)

Conversion Frequency (kHz)

TA = +25°C

−40 −25 −10 5 20 35 50 65 80 95 110 125

460

470

480

490

500

510

520

530

540

TA (°C )

Conversion Frequency (kHz)

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

AVDD (V)

AIDD (mA)

TA = +25°C

−40 −25 −10 5 20 35 50 65 80 95 110 125

TA (°C )

AIDD (mA)

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TYPICAL CHARACTERISTICS: ADC (continued)

At +25°C, unless otherwise noted.

OFFSET vs TEMPERATURE CONVERSION FREQUENCY

Figure 61. Figure 62.

CONVERSION FREQUENCY vs SUPPLY CONVERSION FREQUENCY vs TEMPERATURE

Figure 63. Figure 64.

SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs TEMPERATURE

Figure 65. Figure 66.

Product Folder Link(s): AMC7812

0 100 200 300 400 500

Frequency (kHz)

AIDD (mA)

Auto Convert Mode

Direct Mode With Nap

Direct Mode Without Nap

Single Channel

all DACs at code 800h

864Units

TA=+25°C

6.5

7.5

8.5

9.5

10.5

11.5

AI (mA)

DD )

Population(%)

AMC7812

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TYPICAL CHARACTERISTICS: ADC (continued)

At +25°C, unless otherwise noted.

SUPPLY CURRENT vs CONVERSION RATE COMBINED AVDD AND DVDD SUPPLY CURRENT

Figure 67. Figure 68.

Product Folder Link(s): AMC7812

−40 −25 −10 5 20 35 50 65 80 95 110 125

2.495

2.497

2.499

2.501

2.503

2.505

TA (°C )

Voltage Output (V)

10 Units

2.499

2.4995

2.5

2.5005

2.501

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

AVDD (V)

Voltage Output (V)

TA = +25°C

2.495

2.497

2.499

2.501

2.503

2.505

−10 −8 −6 −4 −2 0 2 4 6 8 10

ILOAD (mA)

Output Voltage (V)

TA = +25°C

-25

-20

-15

-10

-5

TemperatureDrift(ppm/°C )

Population(%)

30Units

TA=-40°Cto+105°C

200

400

600

800

1000

100 1k 10k 100k 1M

Frequency (Hz)

Noise (nV/ Hz)

TA = +25°C

Gain = 2

VREF = 2.5V, Internal

−20

−15

−10

−5

0 4 8 12 16 20

Time (s)

VNOISE (µV)

TA = +25°C

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TYPICAL CHARACTERISTICS: INTERNAL REFERENCE

At +25°C, unless otherwise noted.

OUTPUT VOLTAGE vs TEMPERATURE OUTPUT VOLTAGE vs SUPPLY

Figure 69. Figure 70.

OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE DRIFT

Figure 71. Figure 72.

INTERNAL REFERENCE NOISE vs FREQUENCY INTERNAL REFERENCE NOISE 0.1Hz to 10Hz

Figure 73. Figure 74.

Product Folder Link(s): AMC7812

−2.5

−2

−1.5

−1

−0.5

0.5

1.5

−40 −25 −10 5 20 35 50 65 80 95 110 125

TA(°C )

Local Temperature Error (°C )

10 Units

QFN Package

G001

−40 −25 −10 5 20 35 50 65 80 95 110 125

−2.5

−2

−1.5

−1

−0.5

0.5

1.5

2.5

TA(°C )

Remote Temperature Error (°C )

10 Units

QFN Package

Auto Conversion Mode Disabled

−2.5

−2

−1.5

−1

−0.5

0.5

1.5

2.5

−40 −25 −10 5 20 35 50 65 80 95 110 125

TA (°C)

Local Temperature Error (°C)

16 units

TQFP Package

G000

−2.5

−2.0

−1.5

−1.0

−0.5

0.0

0.5

1.0

1.5

2.0

2.5

−40 −25 −10 5 20 35 50 65 80 95 110 125

TA (°C)

Remote Temperature Error (°C)

16 units

TQFP Package

Auto Conversion Mode Disabled

G000

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Logic Input Voltage (V)

IOVDD (mA)

IOVDD = 2.7V

IOVDD = 5V

TA = +25°C

Digital Input = CS

AMC7812

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TYPICAL CHARACTERISTICS: TEMPERATURE SENSOR

At +25°C, unless otherwise noted.

LOCAL TEMPERATURE ERROR vs TEMPERATURE REMOTE TEMPERATURE ERROR vs TEMPERATURE

Figure 75. Figure 76.

LOCAL TEMPERATURE ERROR vs TEMPERATURE REMOTE TEMPERATURE ERROR vs TEMPERATURE

Figure 77. Figure 78.

TYPICAL CHARACTERISTICS: DIGITAL INPUTS

At +25°C, unless otherwise noted.

SUPPLY CURRENT vs INPUT VOLTAGE

Figure 79.

Product Folder Link(s): AMC7812

40W40pF

AVDD

50W

AVDD

50W

CH0

CH3

AVDD

50W

AVDD

50W

CH4

CH15

ADC-GND

50W40W40pF

DeviceinHoldMode

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

THEORY OF OPERATION

ADC OVERVIEW

The AMC7812 has two analog-to-digital converters (ADCs): a primary ADC and a secondary ADC. The primary

ADC features a 16-channel multiplexer, an on-chip track-and-hold, and a successive approximation register

(SAR) ADC based on a capacitive digital-to-analog converter (DAC). This ADC runs at 500kSPS and converts

the analog channel inputs, CH0 to CH15. The analog input range for the device can be selected as 0V to VREF or

0V to (2 · VREF). The analog input can be configured for either single-ended or differential signals. The AMC7812

has an on-chip 2.5V reference that can be disabled when an external reference is preferred. If the internal ADC

reference is to be used elsewhere in the system, the output must first be buffered. The various monitored and

uncommitted input signals are multiplexed into the ADC. The secondary ADC is a part of the temperature

sensing function that converts the analog temperature signals.

ANALOG INPUTS

The AMC7812 has 16 uncommitted analog inputs; 12 of these inputs (CH4 to CH15) are single-ended. The

inputs for CH0 to CH3 can be configured as four single-ended inputs or two fully-differential channels, depending

on the setup of the ADC Channel Registers, ADC Channel Register 0 and ADC Channel Register 1. See the

Registers section for details. Figure 80 shows the equivalent input circuit of the AMC7812. The (peak) input

current through the analog inputs depends on the sample rate, input voltage, and source impedance. The current

into the AMC7812 charges the internal capacitor array during the sample period. After this capacitance has been

fully charged, there is no further input current. The source of the analog input voltage must be able to charge the

input capacitance to a 12-bit settling level within the acquisition time. When the converter goes into hold mode,

the input impedance is greater than 1GΩ.

Figure 80. Equivalent Input Circuit

Product Folder Link(s): AMC7812

VDM

VCOMMON

V-

AMC7812

V +

(a)

V-

AMC7812

V +

(b)

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Single-Ended Analog Input

In applications where the signal source has high impedance, it is recommended to buffer the analog input before

applying it to the ADC. The analog input range can be programmed to be either 0V to VREF or 0V to (2 · VREF). In

2 · VREF mode, the input is effectively divided by two before the conversion takes place. Note that the voltage

with respect to GND on the ADC analog input pins cannot exceed AVDD.

Fully-Differential Input

When the AMC7812 is configured as a differential input, the differential signal is defined as VDM, as shown in

Figure 81(a). It is the equivalent of the difference between the signals of V1 and V2, as shown in Figure 81(b).

The common-mode input VCOMMON is equal to (V1 + V2)/2.

When the conversion occurs, only the differential mode voltage (VDM) is converted; the common mode voltage

(VCOMMON) is rejected. This process results in a virtually noise-free signal with a maximum amplitude of –VREF to

+VREF for VREF range, or (–2 · VREF) to (+2 · VREF) for (2 · VREF) range. The results are stored in straight binary or

twos complement format.

Figure 81. Fully-Differential Analog Input

PRIMARY ADC OPERATION

The following sections describe the operation of the primary ADC.

ADC Trigger Signals (see AMC Configuration Register 0)

The ADC can be triggered externally by the falling edge of the external trigger CNVT, or internally by writing to

the ICONV bit in AMC Configuration Register 0. The ADC Channel Registers specify which external analog

channel is converted.

When a new trigger activates, the ADC stops any existing conversion immediately and starts a new cycle. For

example, the ADC is programmed to sample channel 0 to channel 3 repeatedly (auto-mode). During the

conversion of channel 1, an external trigger is activated. The ADC stops the conversion of channel 1 immediately

and starts the conversion of channel 0 again, instead of proceeding to convert channel 2.

Conversion Mode

Two types of ADC conversions are available: direct mode and auto mode. The CMODE (conversion mode) bit of

the AMC Configuration 0 Register specifies the conversion mode.

In direct mode, each analog channel within the specified group is converted a single time. After the last channel

is converted, the ADC goes into an idle state and waits for a new trigger.

Auto mode is a continuous operation. In auto mode, each analog channel within the specified group is converted

sequentially and repeatedly.

The flow chart of the ADC conversion sequence in Figure 82 shows the conversion process.

Product Folder Link(s): AMC7812

Yes

Start

(Reset)

Waitfor

ADCTrigger

StopCurrent

Conversion

First

Conversion

New

TriggerOccurred

orCMODE

Changed?

Has

InputChannel

Rewritten?

Has

InputThreshold

Rewritten?

Isthisthe

Last

Conversion?

Convert

NextChannel

Direct

Mode?

Yes

AMC7812

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Figure 82. ADC Conversion Sequence

Product Folder Link(s): AMC7812

ToShift

ADC ADC-0

Data

ADC-0

Temporary

Out-of-Limit

Alarm

ADC-7

Data

ADC-7

Temporary

ADC-15

Data

ADC-15

Temporary

DAVFBit

PinDAV

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

Single-Ended/

Differential

Single-Ended

CONVERT

(ExternalTrigger)

ICONV

(Internal

Trigger)

Input

Range

Selection

AMC7812

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When any of following events occur, the current conversion cycle stops immediately:

• A new trigger is issued.

• The conversion mode changes.

• Either ADC channel register is rewritten.

• Any of the analog input threshold registers is rewritten.

When a new external or internal trigger activates, the ADC starts a new conversion cycle.

The internal trigger should not be issued at the same time the conversion mode is changed. If a '1' is

simultaneously written to the ICONV bit when changing the CMODE bit to '0' or '1', the current conversion stops

and immediately returns to the wait for ADC trigger state.

Double-Buffered ADC Data Registers

The host can access all sixteen, double-buffered ADC Data Registers, as shown in Figure 83. The conversion

result from the analog input with channel address n(where n = 0 to 15) is stored in the ADC-n-Data Register.

When the conversion of an individual channel is completed, the data are immediately transferred into the

corresponding ADC-ntemporary (TMPRY) register, the first stage of the data buffer. When the conversion of the

last channel completes, all data in the ADC-nTMPRY Registers are simultaneously transferred into the

corresponding ADC-n-Data Registers, the second stage of the data buffer. However, if a data transfer is in

progress between any ADC-n-Data Register and the AMC Shift Register, all ADC-n-Data Registers are not

updated until the data transfer is complete. The conversion result from channel address nis stored in the ADC-n-

Data Register. For example, the result from channel 0 is stored in the ADC-0-Data Register, and the result from

channel 3 is stored in the ADC-3-Data Register.

Figure 83. Double-Buffered ADC Structure

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ADC Data Format

For a single ended input, the conversion result is stored in straight binary format. For a differential input, the

results are stored in twos complement format.

SCLK Clock Noise Reduction

To avoid noise caused by the bus clock, it is recommended that no bus clock activity occurs for at least the

conversion process time immediately after the ADC conversion starts.

Programmable Conversion Rate

The maximum conversion rate is 500kSPS for a single channel in auto mode, as shown in Table 1. The

conversion rate is programmable through the CONV-RATE-[1:0] bits of AMC Configuration Register 1. When

more than one channel is selected, the conversion rate is divided by the number of channels selected in ADC

Channel Register 0 and ADC Channel Register 1. In auto mode, the CONV-RATE-[1:0] bits determine the actual

conversion rate. In direct mode, the CONV-RATE-[1:0] bits limit the maximum possible conversion rate. The

actual conversion rate in direct mode is determined by the rate of the conversion trigger. Note that when a trigger

is issued, there may be a delay of up to 4µs to internally synchronize and initiate the start of the sequential

channel conversion process. In both direct and auto modes, when the CONV-RATE-[1:0] bits are set to a value

other than the maximum rate ('00'), nap mode is activated between conversions. By activating nap mode, the

AIDD supply current is reduced, as shown in Figure 67.

Table 1. ADC Conversion Rate

tACQ tCONV NAP THROUGHPUT

CONV-RATE-1 CONV-RATE-0 (µs) (µs) ENABLED (Single-Channel Auto Mode)

0 0 0.375 1.625 No 500kSPS (default)

0 1 2.375 1.625 Yes 250kSPS

1 0 6.375 1.625 Yes 125kSPS

1 1 14.375 1.625 Yes 62.5kSPS

Handshaking with the Host (see AMC Configuration Register 0)

The DAV pin and the DAVF (data available flag) bit in AMC Configuration Register 0 provide handshaking with

the host. Pin and bit status depend on the conversion mode (direct or auto), as shown in Figure 84 and

Figure 85. In direct mode, after ADC-n-Data Registers of all of the selected channels are updated, the DAVF bit

in AMC Configuration Register 0 is set immediately to '1', and the DAV pin is active (low) to signify that new data

are available. Reading the ADC-n-Data Register or restarting via the external CNVT pin, the ADC clears the

DAVF bit to '0' and deactivates the DAV pin (high). If an internal convert start (ICONV bit) is used to start the new

ADC conversion, in order to reset the DAV status, an ADC-n-Data Register must be read after the current

conversion finishes before a new conversion can be started.

In auto-mode, after the ADC-n-Data Registers of the selected channels are updated, a pulse of 1µs (low)

appears on the DAV pin to signify that new data are available. However, the DAVF bit is always cleared to '0' in

auto-mode.

Product Folder Link(s): AMC7812

CNVT

DAV

FirstConversionof

theChannelsSpecifiedin

theADCChannelRegister

First

Trigger

b)ExternalTrigger,AutoMode:

1 sm

CNVT

DAV

SecondConversionof

theChannelsSpecifiedin

theADCChannelRegister

ThirdConversionof

theChannelsSpecifiedin

theADCChannelRegister

First

Trigger

Second

Trigger

Third

Trigger

FirstConversionof

theChannelsSpecifiedin

theADCChannelRegister

SecondConversionof

theChannelsSpecifiedin

theADCChannelRegister

ThirdConversionof

theChannelsSpecifiedin

theADCChannelRegister

a)ExternalTrigger,DirectMode:

SDI

DAV

SetICONV

bitto ‘1’

DATA

First

Internal

Trigger

ReadData

DATA

ReadData

SetICONV

bitto ‘1’

Second

Internal

Trigger

FirstConversionof

theChannelsSpecifiedin

theADCChannelRegister

SecondConversionof

theChannelsSpecifiedin

theADCChannelRegister

SDI

DAV

SetICONV

bitto ‘1’

Internal

Trigger

1 sm

FirstConversionof

theChannelsSpecifiedin

theADCChannelRegister

SecondConversion ThirdConversion

b)InternalTrigger,AutoMode:

a)InternalTrigger,DirectMode:

AMC7812

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Figure 85. ADC External Trigger

Figure 84. ADC Internal Trigger

Data Available Pin (DAV)

DAV is an output pin that indicates the completion of ADC conversions. The DAVF bit in AMC Configuration

been converted and the ADC has been stopped, the DAVF bit is set to '1' and the DAV pin is driven to logic low

(active). In ADC auto mode, each time the group of input channels have been sequentially converted, a 1µs

pulse (low) appears on the DAV pin.

Convert Pin (CNVT)

CNVT is the input pin for the external ADC trigger signal. ADC channel conversions begin on the falling edge of

the CNVT pulse. If a CNVT pulse occurs when the ADC is already converting, then the ADC continues

conversion of the current channel. After the completion of the current channel, the existing conversion cycle

finishes and a new conversion cycle starts. The selected channels specified in the ADC Channel Registers are

converted sequentially in order of enabled channels.

Analog Input Out-of-Range Detection (see the Analog Input Out-of-Range Alarm Section)

The analog inputs of CH0 to CH3 and the temperature inputs are implemented with out-of-range detection. When

any one of them is out of the preset range, the corresponding alarm flag in the Status Register is set. If any

inputs are out of range, the global out-of-range pin (ALARM) goes low. To avoid a false alarm, the device is

implemented with false-alarm protection. See the Alarm Operation section for more details.

Full-Scale Range of the Analog Input

The Gain bit of the ADC Gain Register determines the full-scale range of the analog input. Full-scale range is

VREF when ADGn= 0, or (2 · VREF) when ADGn= 1. If a channel pair is configured for differential operation, the

input ranges are either ±VREF or ±(2 · VREF). In (2 · VREF) mode, the input is effectively divided by two before the

conversion takes place. Each input must not exceed the supply value of AVDD + 0.2V or AGND - 0.2V. When the

REF-OUT pin is connected to the REF-ADC pin, the internal reference is used as the ADC reference. When an

external reference voltage is applied to the REF-ADC pin, the external reference is used as the ADC reference.

Product Folder Link(s): AMC7812

V V =-

BE_HIGH BE_LOW ln

hkT

()

HIGH

LOW

Diode

Temperature

Sensor

SW1

ILOW

SecondADC

andSignal

Processing

LPFandSignal

Conditioning

Local

Temperature

Registers

Mux

SW2

IHIGH

Remote

Temperature

Registers

LPFandSignal

Conditioning

Mux

SW1

ILOW

SW2

IHIGH

VBIAS

D+ SecondADC

andSignal

Processing

D-

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

SECONDARY ADC/TEMPERATURE SENSOR OPERATION

The AMC7812 contains one local and two remote temperature sensors. The temperature sensors continuously

monitor the three temperature inputs, and new readings are automatically available every cycle. The on-chip

integrated temperature sensor (shown in Figure 86) is used to measure the device temperature, and two remote

diode sensor inputs are used to measure the two external temperatures. All analog signals are converted by the

secondary ADC that runs in the background at a lower speed. The measurement relies on the characteristics of

a semiconductor junction operation at a fixed current level. The forward voltage of the diode (VBE) depends on

the current passing through it and the ambient temperature. The change in VBE when the diode operates at two

different currents (a low current of ILOW and a high current of IHIGH, is shown in Equation 1:

Where:

k is Boltzmann's constant.

q is the charge of the carrier.

T is the absolute temperature in Kelvins (K).

ηis the ideality of the transistor as sensor. (1)

Figure 86. Integrated Local Temperature Sensor

The remote sensing transistor can be a discrete small-signal type transistor or substrate transistor built within the

microprocessor. This architecture is shown in Figure 87. An internal voltage source biases the D– terminal above

ground to prevent the ground noise from interfering with the measurement. An external capacitor (up to 330pF)

may be placed between D+ and D– to further reduce noise interference.

Figure 87. Remote Temperature Sensor

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The AMC7812 has three temperature sensors: two remote (D1 and D2) and one on-chip (LT). If any sensor is

not used, it can be disabled by clearing the corresponding enable bit (bits D2EN, D1EN, and LTEN of the Temp

Configuration Register). When disabled, the sensors are not converted. The AMC7812 continuously monitors the

selected temperature sensors in the background, leaving the user free to perform conversions on the other

channels. When one monitor cycle finishes, a signal passes to the control logic to automatically initiate a new

conversion.

The analog sensing signal is preprocessed by a low-pass filter and signal conditioning circuitry, and then

digitized by the ADC. The resulting digital signal is further processed by the digital filter and processing unit. The

final result is stored in the LT-Temperature-Data Register, the D1-Temperature-Data Register, and the D2-

Temperature-Data Register, respectively. The format of the final result is in twos complement, as shown in

Table 2. Note that the device measures the temperature from –40°C to +150°C.

Table 2. Temperature Data Format

TEMPERATURE (°C) DIGITAL CODE

+255.875 011111111111

+150 010010110000

+100 001100100000

+50 000110010000

+25 000011001000

+1 000000001000

0 000000000000

–1 111111111000

–25 111100111000

–50 111001110000

–100 110011100000

–150 101101010000

–256 100000000000

Product Folder Link(s): AMC7812

1.008 300

300 N

-ADJUST

heff =

300 1.008´

eff

NADJUST =300 -

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Remote Sensing Diode

Errors in remote temperature sensor readings are typically the consequence of the ideality factor and current

excitation used by the AMC7812 versus the manufacturer-specified operating current for a given transistor. Some

manufacturers specify a low-level (ILOW) and high-level (IHIGH) current for the temperature-sensing substrate

transistors. The AMC7812 uses 6μA for ILOW and 120μA for IHIGH. The AMC7812 is designed to work with

discrete transistors, such as the 2N3904 and 2N3906. If an alternative transistor is used, the AMC7812 operates

as specified, as long as the following conditions are met:

1. Base-emitter voltage > 0.25V at 6μA, at the highest sensed temperature.

2. Base-emitter voltage < 0.95V at 120μA, at the lowest sensed temperature.

3. Base resistance < 100Ω.

4. Tight control of VBE characteristics indicated by small variations in hFE (that is, 50 to 150).

Ideality Factor

The ideality factor (η) is a measured characteristic of a remote temperature sensor diode as compared to an

ideal diode. The AMC7812 allows for different η-factor values, according to Table 3. The AMC7812 is trimmed for

a power-on reset (POR) value of η= 1.008. If ηis different, the η-Factor Correction Register can be used. The

value (NADJUST) written in this register must be in twos complement format, as shown in Table 3. This value is

used to adjust the effective η-factor according to Equation 2 and Equation 3.

Table 3. η-Factor Range (Single Byte)

NADJUST

BINARY HEX DECIMAL ηEFF

0111 1111 7F 127 1.747977

0000 1010 0A 10 1.042759

0000 1000 08 8 1.035616

0000 0110 06 6 1.028571

0000 0100 04 4 1.021622

0000 0010 02 2 1.014765

0000 0001 01 1 1.011371

0000 0000 00 0 1.008

1111 1111 FF –1 1.004651

1111 1110 FE –2 1.001325

1111 1100 FC –4 0.994737

1111 1010 FA –6 0.988235

1111 1000 F8 –8 0.981818

1111 0110 F6 –10 0.975484

1000 0000 80 –128 0.706542

(2)

Where:

ηEFF is the actual ideality of the transistor being used

NADJUST is the corrected ideality being used in the calculation (3)

Product Folder Link(s): AMC7812

AMC7812

2N3904

D+

D-

AMC7812

2N3906

D+

D-

(b)PNP(a)NPN

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Filtering

Figure 88 shows the connection of recommended (a) NPN or (b) PNP transistors. Remote junction temperature

sensors are usually implemented in a noisy environment. Noise is most often created by fast digital signals, and

it can corrupt measurements. The AMC7812 has a built-in 65kHz filter on the inputs of D+ and D-, to minimize

the effects of noise. However, a bypass capacitor placed differentially across the inputs of the remote

temperature sensor can make the application more robust against unwanted coupled signals. If filtering is

required, the capacitance between D+ and D– should be limited to 330pF or less for optimum measurement

performance. This capacitance includes any cable capacitance between the remote temperature sensor and the

AMC7812.

Figure 88. Remote Temperature Sensor Using Transistor

Series Resistance Cancellation

Parasitic resistance (seen in series with the remote diode) to the D+ and D– inputs to the AMC7812 is caused by

a variety of factors, including printed circuit board (PCB) trace resistance and trace length. This series resistance

appears as a temperature offset in the remote sensor temperature measurement, and causes more than 0.45°C

error per ohm. The AMC7812 implements a technology to automatically cancel out the effect of this series

resistance, giving a more accurate result without the need for user characterization of this resistance. With this

technology, the AMC7812 is able to reduce the effects of series resistance to typically less than 0.0075°C per

ohm. The resistance cancellation is disabled when the RC bit in Temperature Configuration Register is cleared

('0').

Reading Temperature Data

The temperature is always read as 12-bit data. When the conversion finishes, the temperature is sent to the

corresponding Temp-Data Register. However, if a data transfer is in progress between the Temp-Data Register

and the AMC Shift Register, the Temp-Data Register is frozen until the data transfer is complete.

Conversion Time

The conversion time depends on the type of sensor and configuration, as shown in Table 4.

Table 4. Conversion Times

MONITORING PROGRAMMABLE

TEMPERATURE SENSOR CYCLE TIME (ms) DELAY RANGE (s)

Local sensor is active, remote sensors are disabled or in power-down 15 0.48 to 3.84

One remote sensor is active and RC = '0', local sensor and one remote sensor are disabled 44 1.40 to 11.2

or in power-down

One remote sensor is active and RC = '1', local sensor and one remote sensor are disabled 93 2.97 to 23.8

or in power-down

One remote sensor and local sensor are active and RC = '0', one remote sensor is disabled 59 1.89 to 15.1

or in power-down

One remote sensor and local sensor are active and RC = '1', one remote sensor is disabled 108 3.45 to 27.65

or in power-down

Two remote sensors are active and RC = '0', local sensor is disabled or in power-down 88 2.81 to 22.5

Two remote sensors are active and RC = '1', local sensor is disabled or in power-down 186 5.95 to 47.6

All sensors are active and RC = '0' 103 3.92 to 26.38

All sensors are active and RC = '1' 201 6.43 to 51.45

Product Folder Link(s): AMC7812

CH0

CH1

CH14

CH15

ADC

REF-DAC

REF-OUT

DAC-0 DAC0-OUT

Reference

(2.5V)

ADC-REF-IN/CMP

ControlLogic: Bit

ADC-REF-INT= ‘0’

ControlLogic:

BitPREF= ‘0’

Ext.

Ref.

Ext.

Ref.

CH0

CH1

CH14

CH15

ADC

REF-DAC

REF-OUT

DAC-0 DAC0-OUT

Reference

(2.5V)

ADC-REF-IN/CMP

ControlLogic: Bit

ADC-REF-INT= ‘1’

ControlLogic:

BitPREF= ‘1’

C>470nF

(Minimize

Inductance

toPin)

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REFERENCE OPERATION

The following sections describe the operation of the internal and external references.

Internal Reference

The AMC7812 includes a 2.5V internal reference. The internal reference is externally available at the REF-OUT

pin. A 100pF to 10nF capacitor is recommended between the reference output and GND for noise filtering. The

internal reference is a bipolar transistor-based, precision bandgap voltage reference. The output current is limited

by design to approximately 100mA.

The internal reference drives all temperature sensors. When connecting the REF-OUT pin to the REF-DAC pin,

the internal reference works as the DAC reference.

The ADC-REF-IN/CMP pin has a dual function. When an external reference is connected to this pin, the external

reference is used as the ADC reference. When a compensation capacitor ( 4.7µF, typical) is connected between

this pin and AGND, the internal reference is used as the ADC reference. When using an external reference to

drive the ADC, the ADC-REF-INT bit in AMC Configuration Register 0 must be cleared ('0') to turn off the ADC

reference buffer. When using the internal reference to drive the ADC, the ADC-REF-INT bit in AMC Configuration

External Reference

Figure 89 shows how the external reference is used as the DAC reference when applied on the DAC-REF pin,

and as the ADC reference when applied on the ADC-REF pin. Figure 90 shows the use of the internal reference.

Figure 89. Use of the External Reference Figure 90. Use of the Internal Reference

Product Folder Link(s): AMC7812

12-Bit

Resistor

String VOUT

DAC

Latch

DAC

Data

DACLoad(1)

GainLogic

GainBits

Gain

ToOutput

Amplifier

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DAC OPERATION

The AMC7812 contains 12 DACs that provide digital control with 12 bits of resolution using an internal or

external reference. The DAC core is a 12-bit string DAC and output buffer. The DAC drives the output buffer to

provide an output voltage. Refer to the DAC Configuration Register for details. Figure 91 shows a function block

diagram of the DAC architecture. The DAC Latch stores the code that determines the output voltage from the

DAC string. The code is transferred from the DAC-n-Data Register to the DAC Latch when the internal DAC-

Load signal is generated.

(1) Internal DAC load is generated by writing '1' to ILDAC bit in synchronous mode. In asynchronous mode, the DAC

latch is transparent.

Figure 91. DAC Block Diagram

Resistor String

The resistor string structure is shown in Figure 92. It consists of a string of resistors, each of value R. The code

loaded to the DAC Latch determines at which node on the string the voltage is tapped off to be fed into the

output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier.

This architecture is inherently monotonic, voltage out, and low glitch. It is also linear because all the resistors are

of equal value.

Figure 92. Resistor String

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DAC Output

The output range is programmable from 0 to (2 · VREF) or from 0 to (5 · VREF), depending on the gain bits in the

DAC Gain Register. The maximum output is AVCC. The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, giving an output range of 0V to AVCC. The source and sink capabilities of the output

amplifier can be seen in the Typical Characteristics. The slew rate is 1.5V/μs with a typical ¼ to ¾ scale settling

time of 3μs with the output unloaded.

Double-Buffered DAC Data Registers

There are 12 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC Data

DAC-nLatch. When the DAC-nLatch is updated, the output of DAC-nchanges to the newly set value. When the

host reads the register memory map location labeled DAC-nData, the value held in the DAC-nLatch is returned

(not the value held in the input DAC-n-Data Register).

Full-Scale Output Range

The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain

of the DAC output buffer (VREF · Gain). The gain bits of the DAC Gain Register set the output range of the

individual DAC-n. The full-scale output range of each DAC is limited by the analog power supply. The maximum

output from the DAC must not be greater than AVCC, and the minimum output must not be less than AGND.

DAC Output After Power-On Reset

After power on, the DAC output buffer is in power-down mode. The output buffer is in a Hi-Z state and the DAC-

Out output pin connects to the analog ground through an internal 10kΩresistor. After power on or hardware

reset, all DAC-n-Data Registers, all DAC-nLatches, and the DAC output are set to default values (000h).

Load DAC Latch

See Figure 91 for the structure of the DAC register and DAC latch. The contents of the DAC-nLatch determine

the output level of the DAC-npin. After writing to the DAC-n-Data Register, the DAC Latch can be loaded in the

following ways:

• In asynchronous mode (SLDAC-nbit = '0'), the data are loaded into the DAC-nLatch immediately after the

write operation.

• In synchronous mode (SLDAC-nbit = '1'), the DAC latch updates when the synchronous DAC loading signal

occurs. Setting the ILDAC bit in AMC Configuration Register 0 generates the loading signal.

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Synchronous Load, Asynchronous Load, and Output Updating

The SLDA-n(synchronous load) bit of the DAC Configuration Register determines the DAC updating mode, as

shown in Table 5. When SLDA-nis cleared to '0', asynchronous mode is active, the DAC Latch updates

immediately after writing to the DAC-n-Data Register, and the output of DAC-nchanges accordingly.

Table 5. DAC-nOutput Update Summary for Manual Mode Update

SLDA-nBIT WRITING TO ILDAC BIT OPERATION

Update DAC-nindividually. The DAC-nLatch and DAC-noutput are immediately

0 Don't care updated after writing to the DAC-n-Data Register.

Simultaneously update all DACs by internal trigger. Writing '1' to the ILDAC bit

1 1 generates an internal load DAC trigger signal that updates the DAC-nLatches and

DAC-noutputs with the contents of the corresponding DAC-n-Data Register.

When the SLDA-nbit is set to '1', synchronous mode is selected. The value of the DAC-n-Data Register is

transferred to the DAC-nLatch only after an active DAC synchronous loading signal (ILDAC) occurs, which

immediately updates the DAC-noutput. Under synchronous loading operation, writing data into a DAC-n-Data

until the synchronous load signal occurs.

The DAC synchronous load is triggered by writing '1' to the ILDAC bit in AMC Configuration Register 0. When

this DAC synchronous load signal occurs, all DACs with the SLDA-nbit set to '1' are simultaneously updated with

the value of the corresponding DAC-n-Data Register. By setting the SLDA-n bit properly, several DACs can be

updated at the same time. For example, to update DAC0 and DAC1 synchronously, set bits SLDA-0 and SLDA-1

to '1' first, and then write the proper values into the DAC-0 and DAC-1-Data Registers, respectively. After this

presetting, set the ILDAC bit = '1' to simultaneously load DAC0 and DAC1. The outputs of DAC0 and DAC1

change at the same time.

The AMC7812 updates the DAC Latch only if it has been accessed since the last time ILDAC was issued,

thereby eliminating any unnecessary glitch. Any DAC channels that have not been accessed are not reloaded

again. When the DAC Latch is updated, the corresponding output changes to the new level immediately.

NOTE

When DACs are cleared by an external DAC-CLR-n or by the internal CLR bit, the DAC

Latch is loaded with the predefined value of the DAC-n-CLR-Setting Register and the

output is set to the corresponding level immediately, regardless of the SLDA-nbit value.

However, the DAC Data Register does not change.

Product Folder Link(s): AMC7812

DAC

Latch DAC

CLR-nBitinHW-DAC-CLR- Registern

ACLR- Bitn

AlarmSource

DAC

CLR-Setting

CLR-nBitinSW-DAC-CLR- Registern

DAC-CLR-nPin

DAC

DataRegister

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Clear DACs

DAC-ncan be cleared using hardware or software as shown in Figure 93. When DAC-ngoes to a clear state, it

is immediately loaded with predefined code in the DAC-n-CLR-Setting Register, and the output is set to the

corresponding level to shut down the external LDMOS device. However, the DAC-DATA-nRegister does not

change. When the DAC goes back to normal operation, DAC-nis immediately loaded with the previous data from

the DAC-DATA-nRegister and the output of DAC-n-Out is set back to the previous level to restore LDMOS to the

status before shutdown, regardless of the SLDAC-nbit status.

Figure 93. Clearing DAC-n

The AMC7812 is implemented with two external control lines, the DAC-CLR-0 and DAC-CLR-1 pins, to clear the

DACs. When either pin goes low, the corresponding user-selected DACs are in a cleared state. The HW_DAC-

CLR-0 Register determines which DAC is cleared when the DAC-CLR-0 pin is low. The register contains 12 clear

bits (CLR-n), one per DAC. If the CLR-nbit = '1', DAC-nis in a cleared state when the DAC-CLR-0 pin is low.

However, if the CLR-nbit = '0', DAC-ndoes not change when the pin is low. Likewise, the HW-DAC-CLR-1

Writing directly to the SW_DAC_CLR Register puts the selected DACs in a cleared state. DACs can also be

forced into a clear state by alarm events. The AUTO-DAC-CLR-SOURCE Register specifies which alarm events

force the DACs into a clear state, and the AUTO-DAC-CLR-EN Register defines which DACs are forced into a

clear state. Refer to the AUTO-DAC-CLR-SOURCE and AUTO-DAC-CLR-EN Registers for further details.

DAC Output Thermal Protection

A significant amount of power can be dissipated in the DAC outputs. The AMC7812 is implemented with a

thermal protection circuit that sets the THERM-ALR bit in the Status Register if the die temperature exceeds

+150°C. The THERM-ALR bit can be used in combination with THERM-ALR-CLR (bit 2 in the AUTO-DAC-CLR-

SOURCE Register) and ACLR-n(bits[14:3] in the AUTO-DAC-CLR-EN Register) to set the DAC output to a

predefined code when this condition occurs. Note that this feature is disabled when the local temperature sensor

powers down.

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CH0-ALR

THERM-ALR

Alarm

Status

Bits

GALRBit

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Alarm Operation

The AMC7812 continuously monitors all analog inputs and temperatures in normal operation. When any input is

out of the specified range, an alarm triggers. When an alarm state occurs, the corresponding individual alarm bit

in the Status Register is set ('1'). Global alarm bit GALR in AMC Configuration Register 0 is the OR of individual

alarms, see Figure 94. When the ALARM-LATCH-DIS bit in the Alarm Control Register is cleared ('0'), the alarm

is latched. The global alarm bit (GALR) maintains '1' until the corresponding error condition[s] subside and the

alarm status is read. The alarm bits are referred to as being latched because they remain set until read by

software. This design ensures that out-of-limit events cannot be missed if the software is polling the device

periodically. All bits are cleared when reading the Status Register, and all bits are reasserted if the out-of limit

condition still exists on the next monitoring cycle, unless otherwise noted.

Figure 94. Global Alarm Bit

When the ALARM-LATCH-DIS bit in the Alarm Control Register is set ('1'), the alarm bit is not latched. The alarm

bit in the Status Register goes to '0' when the error condition subsides, regardless of whether the bit is read or

not. When GALR = '1', the ALARM pin goes low. When the GALR bit = '0', the ALARM is high (inactive).

Product Folder Link(s): AMC7812

CH -ALRBitn

thAnalogInput

( =0to3)

High-Threshold-

(upperbound)

Low-Threshold-

(lowerbound)

TemperatureData

(D1,D2,LT)

High-Threshold

(upperbound)

Low-Threshold

(lowerbound)

Low-ALRBit

High-ALRBit

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Analog Input Out-of-Range Alarm

The AMC7812 provides out-of-range detection for four individual analog inputs (CH0, CH1, CH2, and CH3) as

shown in Figure 95. When the measurement is out-of-range, the corresponding alarm bit in the Status Register is

set to '1' to flag the out-of-range condition. The value in the High-Threshold Register defines the upper bound

threshold of the nth analog input, while the value in Low-Threshold defines the lower bound. These two bounds

specify a window for the out-of-range detection.

Figure 95. CHnOut-of-Range Alarm

The AMC7812 also has high-limit or low-limit detection for the temperature sensors (D1, D2, and LT), as shown

in Figure 96. To implement single, upper-bound threshold detection for analog input CHn, the host processor can

set the upper-bound threshold to the desired value and the lower-bound threshold to the default value. For lower-

bound threshold detection, the host processor can set the lower-bound threshold to the desired value and the

upper-bound threshold to the default value. Note that the value of the High-Threshold Register must not be less

than the value of the Low-Threshold Register; otherwise, ALR-nis always set to '1' and the alarm indicator is

always active. Each temperature sensor has two alarm bits: High-ALR (high-limit alarm) and Low-ALR (low-limit

alarm).

Figure 96. Temperature Out-of-Range Alarm

Product Folder Link(s): AMC7812

AMC7812

CH0-ALRBit

EALR-CH0Bit

D2-FAIL-ALRBit

EALR-D2-FAILBit

THERM-ALRBit

EN-ALARMBit

ALARM

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ALARM pin

The ALARM pin is a global alarm indicator. ALARM is an open-drain pin, as Figure 97 illustrates; an external

pull-up resistor is required. When the pin is activated, it goes low. When the pin is inactive, it is in Hi-Z status.

The ALARM pin works as an interrupt to the host so that it may query the Status Register to determine the alarm

source. Any alarm event (including analog inputs, temperatures, diode status, and device thermal condition)

activates the pin if the alarm is not masked (the corresponding EALR bit in the Alarm Control Register = '1').

When the alarm pin is masked (EN-ALARM bit = '0'), the occurrence of the event sets the corresponding status

bit in Status Register to '1', but does not activate the ALARM pin.

Figure 97. ALARM Pin

When the ALARM-LATCH-DIS bit in the Alarm Control Register is cleared ('0'), the alarm is latched. Reading the

Status Register clears the alarm status bit. Whenever an alarm status bit is set, indicating an alarm condition, it

remains set until the event that caused it is resolved and the Status Register is read. The alarm bit can only be

cleared by reading the Status Register after the event is resolved, or by hardware reset, software reset, or

power-on reset (POR). All bits are cleared when reading the Status Register, and all bits are reasserted if the

out-of limit condition still exists after the next conversion cycle, unless otherwise noted. When the ALARM-

LATCH-DIS bit in the Alarm Control Register is set ('1'), the ALARM pin is not latched. The alarm bit clears to '0'

when the error condition subsides, regardless of whether the bit is read or not.

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HighThreshold

LowThreshold

Hysteresis

Input

Hysteresis

OverHighAlarm BelowLowAlarm

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Hysteresis

The AMC7812 continuously monitors the analog input channels and temperatures. If any of the alarms are out of

range and the alarm is enabled, its alarm bit is set ('1'). However, the alarm condition is cleared only when the

conversion result returns to a value of at least hys below the value of High Threshold Register, or hys above the

value of Low Threshold Register. The Hysteresis Registers store the value for each analog input (CH0, CH1,

CH2, and CH3) and temperature (D1, D2, and LT). hys is the value of hysteresis that is programmable: 0 LSB to

127 LSB for analog input, and 0°C to +31°C for temperatures. For the THERM-ALR bit, the hysteresis is fixed at

8°C. The hysteresis behavior is shown in Figure 98.

Figure 98. Hysteresis

False Alarm Protection

As noted previously, the AMC7812 continuously monitors all analog inputs and temperatures in normal operation.

When any input is out of the specified range in Nconsecutive conversions, the corresponding alarm bit is set

('1'). If the input returns to the normal range before Nconsecutive times, the alarm bit remains clear ('0'). This

design avoids false alarms.

The number Nis programmable by the CH-FALR-CT-[2:0] bits in AMC Configuration Register 1 for analog input

CH-n as shown in Table 6, or by the TEMP-FALR-CT-[1:0] bits for temperature monitors as shown in Table 7.

Table 6. Consecutive Sample Number for False Alarm Protection for CH-n

NCONSECUTIVE SAMPLES

CH-FALR-CT-2 CH-FALR-CT-1 CH-FALR-CT-0 BEFORE ALARM IS SET

0 0 0 1

0 0 1 4

0 1 0 8

0 1 1 16 (default)

1 0 0 32

1 0 1 64

1 1 0 128

1 1 1 256

Table 7. Consecutive Sample Number for False Alarm Protection for Temperature Channels

TEMP-FALR-CT-1 TEMP-FALR-CT-0 NCONSECUTIVE SAMPLES BEFORE ALARM IS SET

0 0 1

0 1 2

1 0 4 (default)

1 1 8

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GPIO-n

ENABLE

GPIO-nBit

(whenwriting)

V+

GPIO-nBit

(whenreading)

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GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0 to GPIO-7)

The AMC7812 has eight GPIO pins. The GPIO-0, -1, -2 and -3 pins are dedicated to general, bidirectional, digital

I/O signals. GPIO-4, GPIO-5, GPIO-6 and GPIO-7 are dual-function pins and can be programmed as either

bidirectional digital I/O pins or remote temperature sensors D1 and D2. When D1 or D2 is disabled, the pins work

as a GPIO. These pins can receive an input or produce an output. When the GPIO-npin acts as an output, it has

an open-drain, and the status is determined by the corresponding GPIO-nbit of the GPIO Register. The output

state is high impedance when the GPIO-nbit is set to '1', and is logic low when the GPIO-nbit is cleared ('0').

Note that a 10kΩpullup resistor is required when using the GPIO-npin as an output, see Figure 99. The dual

function GPIO-4, -5, -6 and -7 pins should not be tied to a pullup voltage that exceeds the AVDD supply. The

dedicated GPIO-0, -1, -2 and -3 pins are only restricted by the absolute maximum voltage. To use the GPIO-n

pin as an input, the corresponding GPIO-nbits in the GPIO Register must be set to '1'. When the GPIO-npin

acts as input, the digital value on the pin is acquired by reading the corresponding GPIO-nbit. After a power-on

reset or any forced hardware or software reset, all GPIO-nbits are set to '1', and the GPIO-npin goes to a high-

impedance state.

Figure 99. GPIO Pins

HARDWARE RESET

Pulling the RESET pin low performs a hardware reset. When the RESET pin is low, the device enters a reset

state, all registers are set to the default values (including the Power-Down Register); therefore, all function blocks

(except the internal temperature sensor) are in power-down mode. On the rising edge of RESET, the device

returns to the normal operating mode. After returning, all registers remain set to the default value until a new

value is written. Note that after reset, it is important to properly write to the power-down register in order to

activate the device. Hardware reset should only be issued when DVDD has reached the minimum specification of

2.7V or above.

SOFTWARE RESET

Software reset returns all register settings to their default and can be performed by writing to the Software Reset

case of SPI communications, only writing the specific value of 6600h to this register resets the device. See the

Registers section for details. During reset, all communication is blocked. After issuing the reset, the user should

wait at least 30µs before attempting to resume communication.

POWER-ON RESET (POR)

When powered on, the internal POR circuit invokes a power-on reset, which performs the equivalent function of

the RESET pin. To ensure a POR, DVDD must start from a level below 750mV.

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POWER SUPPLY SEQUENCE

The preferred (not required) order for applying power is IOVDD, DVDD/AVDD and then AVCC. All registers

initialize to the default values after these supplies have been established. Communication with the AMC7812 will

be valid after a 250µS maximum power-on reset delay. The default state of all analog blocks is off as determined

by the power-down register (6Bh). Before writing to this register, a hardware reset should be issued to ensure

specified operation of the AMC7812. Communication to the AMC7812 will be valid after a maximum 250µS reset

delay from the rising edge of RESET.

If DVDD falls below 2.7V, the minimum supply value of DVDD, either a hardware or power-on reset should be

issued before proper operation can be resumed.

To avoid activating the ESD protection diodes of the AMC7812, GPIO-4, GPIO-5, GPIO-6 and GPIO-7 inputs

should not be applied before the AVDD is established. Also, if using the external reference configuration of the

ADC, ADC-REF-IN/CMP should not be applied before AVDD.

PRIMARY COMMUNICATION INTERFACE

The AMC7812 communicates with the system controller through the primary communication interface, which can

be configured as either an I2C-compatible two-wire bus or an SPI bus. When the SPI/I2C pin is tied to ground,

the I2C interface is enabled, and the SPI is disabled. When the SPI/I2C pin is tied to IOVDD, the I2C interface is

disabled, and SPI is enabled.

I2C-Compatible Interface

This device uses a two-wire serial interface compatible with the I2C-bus specification, version 2.1. The bus

consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and

SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins SDA

and SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is

responsible for generating the SCL signal and device addresses. The master also generates specific conditions

that indicate the start and stop of data transfers. A slave device receives and/or transmits data on the bus under

control of the master device. The AMC7812 works as a slave and supports the following data transfer modes, as

defined in the I2C-bus specification: standard mode (100kbps), fast mode (400kbps), and high-speed mode

(3.4Mbps). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are

referred to as F/S mode in this document. The protocol for high-speed mode is different from the F/S mode, and

is referred to as Hs mode. The AMC7812 supports 7-bit addressing. However 10-bit addressing and general call

addressing are not supported. The slave address of the AMC7812 is determined by the status of pins A0, A1,

and A2, as shown in Table 8.

Table 8. Slave Addresses

A0 A1 A2 SLAVE ADDRESS

GND GND GND 1100001

GND GND IOVDD 1100010

GND IOVDD GND 1100100

GND IOVDD IOVDD 1100101

IOVDD GND GND 0101100

IOVDD GND IOVDD 0101101

IOVDD IOVDD GND 0101110

IOVDD IOVDD IOVDD 0101111

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F/S-Mode Protocol

• The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 2. All I2C-compatible devices must

recognize a start condition.

• The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 2). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave

device with a matching address generates an acknowledge (see Figure 2) by pulling the SDA line low during

the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master recognizes that

communication link with a slave has been established.

• The master generates further SCL cycles to either transmit data to the slave (R/W bit = '1') or receive data

from the slave (R/W bit = '0'). In either case, the receiver must acknowledge the data sent by the transmitter.

Therefore, an acknowledge signal can either be generated by the master or by the slave, depending on which

one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can

continue as long as necessary.

• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-

to-high while the SCL line is high (see Figure 2). This action releases the bus and stops the communication

link with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt

of a stop condition, all devices recognize that the bus is released and wait for a start condition followed by a

matching address.

Hs-Mode Protocol

• When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

• The master generates a start condition followed by a valid serial byte containing Hs master code 00001xxx.

This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the

Hs master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps

operation.

• The master then generates a repeated start condition (a repeated start condition has the same timing as the

start condition). After this repeated start condition, the protocol is the same as for F/S mode, except that

transmission speeds up to 3.4 Mbps are allowed. A stop condition ends Hs mode and switches all the internal

settings of the slave devices to support F/S mode. Note that instead of using a stop condition, repeated start

conditions should be used to secure the bus in Hs mode.

Address Pointer

The Address Pointer Register of AMC7812 is an 8-bit register. Each register has an address and when it is

accessed, the address pointer points to it. All registers in the AMC7812 are 16-bit, consisting of a high byte

(D15:D8) and a low byte (D7:D0). The high byte is always accessed first, and the low byte accessed second.

When the register is accessed, the entire register is frozen until the operation on the low byte is complete. During

write operation, the new content does not take effect until the low byte is written. In read operation, the whole

The address pointer does not change after the current register is accessed. To change the pointer, the master

issues a slave address byte with the R/W bit low, followed by the Pointer Register byte; no additional data are

required.

AMC7812 Communication Protocol for I2C

The AMC7812 uses the following I2C protocols.

Writing a Single Word of Data to a 16-Bit Register (Figure 100)

1. The master device asserts a start condition.

2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a

write operation.

3. The AMC7812 asserts an acknowledge signal on SDA.

4. The master sends a register address.

5. The AMC7812 asserts an acknowledge signal on SDA.

Product Folder Link(s): AMC7812

SAMC7812

SlaveAddress 0ARegisterPointer

(RegisterAddress) AHighByteto

AMC7812Register A A P

FromMastertoSlave A=Acknowledge

N=NotAcknowledge

S=STARTCondition

P=StopCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

LowByteto

AMC7812Register

AMC7812

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

6. The master sends a data byte of the high byte of the register (D15:D8).

7. The AMC7812 asserts an acknowledge signal on SDA.

8. The master sends a data byte of the low byte of the register (D7:D0).

9. The AMC7812 asserts an acknowledge signal on SDA.

10. The master asserts a stop condition to end the transaction.

Figure 100. Write Single Byte

Product Folder Link(s): AMC7812

FromMastertoSlave A=Acknowledge

N=NotAcknowledge

S=STARTCondition

P=StopCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

(2ndRegisterAddress) AHighByteofDatato

2ndRegister ALowByteofDatato

2ndRegister A

SAMC7812

SlaveAddress 0ARegisterPointer

(1stRegisterAddress) AHighByteofDatato

1stRegister A A

LowByteofDatato

1stRegister

(LastRegisterAddress) AHighByteofDatato

LastRegister ALowByteofDatato

LastRegister AP

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Writing Multiple Words to Different Registers (Figure 101)

A complete word must be written to a register (high byte and low byte) for proper operation.

1. The master device asserts a start condition.

2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a

write operation.

3. The AMC7812 asserts an acknowledge signal on SDA.

4. The master sends the first register address.

5. The AMC7812 asserts an acknowledge signal on SDA.

6. The master sends the high byte of the data word to the first register.

7. The AMC7812 asserts an acknowledge signal on SDA.

8. The master sends the low byte of the data word to the first register.

9. The AMC7812 asserts an acknowledge signal on SDA.

10. The master sends a second register address.

11. The AMC7812 asserts an acknowledge signal on SDA.

12. The master then sends the high byte of the data word to the second register.

13. The AMC7812 asserts an acknowledge on SDA.

14. The master sends the low byte of the data word to the second register.

15. The AMC7812 asserts an acknowledge signal on SDA.

16. The master and the AMC7812 repeat steps 4 to 15 until the last data are transferred.

17. The master then asserts a stop condition to end the transaction.

Figure 101. Write to Multiple 16-Bit Registers

Product Folder Link(s): AMC7812

SAMC7812

SlaveAddress 0ARegisterPointer

(RegisterAddress) ASr AMC7812

SlaveAddress 1

FromMastertoSlave A=Acknowledge

N=NotAcknowledge

S=STARTCondition

P=StopCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

AFromHighByteof

AMC7812Register AFromLowByteof

AMC7812Register NP

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Reading a Single Word from Any Register (Figure 102)

1. The master device asserts a start condition.

2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a

write operation.

3. The AMC7812 asserts an acknowledge signal on SDA.

4. The master sends a register address.

5. The AMC7812 asserts an acknowledge signal on SDA.

6. The master device asserts a restart condition.

7. The master then sends the 7-bit AMC7812 slave address followed by a '1' for the direction bit, indicating a

read operation.

8. The AMC7812 asserts an acknowledge signal on SDA.

9. The AMC7812 then sends the high byte of the register (D15:D8).

10. The master asserts an acknowledge signal on SDA.

11. The AMC7812 sends the low byte of the register (D7:D0).

12. The master asserts a not acknowledge signal on SDA.

13. The master then asserts a stop condition to end the transaction.

Figure 102. Read a Single Word

Product Folder Link(s): AMC7812

SAMC7812

SlaveAddress 0ARegisterPointer

(RegisterAddress) ASr AMC7812

SlaveAddress 1

AHighByteofRegister;

1stReading ALowByteofRegister;

1stReading A

FromMastertoSlave A=Acknowledge

N=NotAcknowledge

S=STARTCondition

P=StopCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

HighByteofRegister;

LastReading ALowByteofRegister;

LastReading NP

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Reading the Same Register Multiple Times (Figure 103 and Figure 104)

1. The master device asserts a start condition.

2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a

write operation.

3. The AMC7812 asserts an acknowledge signal on SDA.

4. The master sends a register address.

5. The AMC7812 asserts an acknowledge signal on SDA.

6. The master device asserts a restart condition.

7. The master then sends the 7-bit AMC7812 slave address followed by a '1' for the direction bit, indicating a

read operation.

8. The AMC7812 asserts an acknowledge signal on SDA.

9. The AMC7812 then sends the high byte of the register (D15:D8).

10. The master asserts an acknowledge signal on SDA.

11. The AMC7812 sends the low byte of the register (D7:D0).

12. The master asserts an acknowledge signal on SDA.

13. The AMC7812 and the master repeat steps 9 to 12 until the low byte of last reading is transferred.

14. After receiving the low byte of the last register, the master asserts a not acknowledge signal on SDA.

15. The master then asserts a stop condition to end the transaction.

Figure 103. Read Multiple Words

Product Folder Link(s): AMC7812

SAMC7812

SlaveAddress 0ARegisterPointer

(1stRegisterAddress) ASr AMC7812

SlaveAddress 1

AHighByteof

1stRegister ALowByteof

1stRegister N

FromMastertoSlave A=Acknowledge

N=NotAcknowledge

S=STARTCondition

P=StopCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

HighByteoftheLast

SAMC7812

SlaveAddress 0ARegisterPointer

(2ndRegisterAddress) ASr AMC7812

SlaveAddress 1

AHighByteof

2ndRegister ALowByteof

2ndRegister NP

SAMC7812

SlaveAddress 0ARegisterPointer

(LastRegisterAddress) ASr AMC7812

SlaveAddress 1

AMC7812

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Figure 104. Read Multiple Registers Using the Reading Single Word from Any Register Method

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Serial Peripheral Interface (SPI)

The AMC7812 can be controlled over a versatile 3-wire serial interface that operates at clock rates of up to

50MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. The SPI communication

command consists of a read/write bit, seven register address bits, and 16 data bits (as shown in Table 9), for a

total of 24 bits. The timing for this operation is shown in the SPI timing diagrams (Figure 3,Figure 4, and

Figure 5).

SPI Shift Register

The SPI shift register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control

of the serial clock input, SCLK. The falling edge of CS starts the communication cycle. The data are latched into

the SPI shift register on the falling edge of SCLK, while CS is low. When CS is high, the SCLK and SDI signals

are blocked out and the SDO line is in a high-impedance state. The contents of the SPI shift register are loaded

into the device internal register on the rising edge of CS (with delay). During the transfer, the command is

decoded and the new data are transferred into the proper registers.

The serial interface works with both a continuous and non-continuous serial clock. A continuous SCLK source

can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock

containing the exact number of clock cycles must be used and CS must be taken high after the final clock to

latch the data.

AMC7812 Communications Command for SPI

The AMC7812 is entirely controlled by registers. Reading from and writing to these registers is accomplished by

issuing a 24-bit operation word shown in Table 9.

Table 9. 24-Bit Word Structure for Read/Write Operation

OPERATION I/O BIT 23 (MSB) BIT22:BIT16 BIT15:BIT0

SDI 0 (R/W) Addr6:Addr0 Data to be written

Write Undefined or data depending on the

SDO Data is undefined Data is undefined previous frame

SDI 1 (R/W) Addr6:Addr0 don't care

Read frame 1 Undefined or data depending on the

SDO Data is undefined Data is undefined previous frame

SDI 1 (R/W) Addr6:Addr0 don't care

Read frame 2 SDO Data is undefined Data is undefined Data for address specified in frame 1

Bit 23 R/W. Indicates a read from or a write to the addressed register.

Bit = '0' sets the write operation and the data are written to the specified register.

Bit = '1' sets the read operation where bits [addr6:addr0] select the register to be read. The remaining bits are don't care.

The data read from the selected register appear on SDO pin in the next SPI cycle.

Bits[22:16] Addr6:Addr0. Register address; specifies which register is accessed.

Bits[15:0] DATA. 16-bit data bits.

In write operation, these bits are written to bits[15:0] of the register with the address of [Addr6:Addr0].

In read operation, these bits are determined by previous operation. If previous operation is a read, these bits are from

bits[15:0] of the internal register specified in previous read operation. If previous operation is a write, these data bits are

don’t care (undefined). The data read from current read operation appears on SDO in the next operation cycle.

Product Folder Link(s): AMC7812

AMC7812

SCLK

SDI

SDO

SDI

SDO

W0 W1 W2 W3

XX XX XX

W =WriteCommandforRegister

XX=Don’tcare,undefined

n N

SDI

SDO

R0 R1 R2 R3

XX D0 D1 D2 D3

AnyCommand

XX=Don’tcare,undefined

n N

=ReadCommandforRegister

D =DatafromRegister

AMC7812

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Standalone Operation

In standalone mode, as shown in Figure 105, each AMC7812 has its own SPI bus. The serial clock can be

continuous or gated. The first falling edge of CS starts the operation cycle. Exactly 24 falling clock edges must be

applied before CS is brought high again. If CS is brought high before the 24th falling SCLK edge, or if more than

24 falling SCLK edges are applied before CS is brought high, then the input data are incorrect. The device input

addressed registers as well. In order for another serial transfer to occur, CS must be brought low again.

Figure 106 and Figure 107 show write, and read operations in standalone mode.

Figure 105. Standalone Operation

Figure 106. Write Operation in Standalone Mode

Figure 107. Read Operation in Standalone Mode

Product Folder Link(s): AMC7812

SDI-C SDO-C

SDI-B SDI-A

SDO-B SDO-A

B A

SDO

SDI

SCLK

RA0 RB0 RC0

RA0 RB0

RA0

RA1 RB1 RC1

RA1 RB1

CD0

BD0

CD0 RA1 RB1

CD0 RA1

AD0

BD0 CD0 RA1

BD0 CD0

RA2 RB2 RC2

CD1 RA2 RB2

BD1 CD1 RA2

AD1 BD1 CD1

RA3 RB3 RC3

CD2 RA3 RB3

BD2

CD2 RA3

AD2 BD2 CD2

XX XX

SDI-C

SDO-C

SDI-B

SDO-B

SDI-A

SDO-A

Cycle0 Cycle1 Cycle2 Cycle3

XX=Don’tcare,undefined

n n n N

(RB ,RC )=ReadCommandforRegister ofdeviceA(B,C)

AD (BD ,CD )=DatafromRegister ofdeviceA(B,C)

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Daisy-Chain Operation

For systems that contain several AMC7812s, the SDO pin can be used to daisy-chain multiple devices together.

This daisy-chain feature is useful in reducing the number of serial interface lines. The first falling edge of CS

starts the operation cycle. SCLK is continuously applied to the Input Shift Register when CS is low.

If more than 24 clock pulses are applied, the data ripple out of the Shift Register and appear on the SDO line.

These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the SDO

output of the first device to the SDI input of the next device in the chain, a multiple-device interface is

constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles

must equal 24N, where Nis the total number of AMC7812s in the daisy chain. When the serial transfer to all

devices is complete, CS is taken high. This action transfers the data from the SPI Shifter Registers to the internal

clock can be continuous or gated. A continuous SCLK source can only be used if CS is held low for the correct

number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be

used and CS must be taken high after the final clock in order to latch the data.

Figure 108. Three AMC7812s in a Daisy-Chain Configuration

Figure 109. Reading Multiple Registers

Product Folder Link(s): AMC7812

RA0 WB0 RC0

RA0 WB0

RA0

RA1 WB1 WC1

RA1 WB1

CD0

CD0 RA1 WB1

CD0 RA1

AD0

CD0 RA1

CD0

RA2 RB2 RC2

RA2 RB2

RB2

RA2

AD1

RA3 RB3 RC3

CD2 RA3 RB3

BD2

CD2 RA3

AD2 BD2 CD2

Cycle0 Cycle1 Cycle2 Cycle3

XX XX

XXXXXX

RA2

XX XX

SDI-C

SDO-C

SDI-B

SDO-B

SDI-A

SDO-A

XX=Don’tcare,undefined

n n

n n n N

(WC )=

RA (RB ,RC )=ReadCommandforRegister ofdeviceA(B,C)

AD (BD ,CD )=DatafromRegister ofdeviceA(B,C)

WriteCommandforRegister ofdeviceA(B,C)N

SDI-C

SDO-C

SDI-B

SDO-B

SDI-A

SDO-A

WA0 WB0 RC0

WA0 WB0

WA0

WA1 WB1 RC1

WA1 WB1

WB1

WA2 WB2 RC2

WB2

WA3 WB3 RC3

WB3

Cycle0 Cycle1 Cycle2 Cycle3

XX XX

XXXXXX

CD0

WA1

CD0

WA1

CD0

WA2

CD1

XX CD1

CD1

CD2 WA3

WA3

CD2

CD2 WA3

XX CD2

AMC7812

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Figure 110. Mixed Operation: Reading Devices A and C, and Writing to Device B; then Reading A, and

Writing to B and C; then Reading A, B, and C Twice

Figure 111. Writing to Devices A and B, and Reading Device C

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REGISTERS

The AMC7812 has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8-bit

registers for the AMC7812. Note that the default values are for SPI operation; see the register descriptions for

I2C default values.

Table 10. Register Map

ADDRESS DEFAULT ADDRESS DEFAULT

(HEX) R/W (HEX) REGISTER (HEX) R/W (HEX) REGISTER

00 R 0000 LT-Temperature-Data 45 R/W 0000 DAC-6-CLR-Setting

01 R 0000 D1-Temperature-Data 46 R/W 0000 DAC-7-CLR-Setting

02 R 0000 D2-Temperature-Data 47 R/W 0000 DAC-8-CLR-Setting

0A R/W 003C(1) Temperature Configuration 48 R/W 0000 DAC-9-CLR-Setting

0B R/W 0007(1) Temperature Conversion Rate 49 R/W 0000 DAC-10-CLR-Setting

21 R/W 0000(1) η-Factor Correction (for D1) 4A R/W 0000 DAC-11-CLR-Setting

22 R/W 0000(1) η-Factor Correction (for D2) 4B R/W 000F GPIO

23 R 0000 ADC-0-Data 4C R/W 2000 AMC Configuration 0

24 R 0000 ADC-1-Data 4D R/W 0070 AMC Configuration 1

25 R 0000 ADC-2-Data 4E R/W 0000 Alarm Control

26 R 0000 ADC-3-Data 4F R 0000 Status

27 R 0000 ADC-4-Data 50 R/W 0000 ADC Channel 0

28 R 0000 ADC-5-Data 51 R/W 0000 ADC Channel 1

29 R 0000 ADC-6-Data 52 R/W FFFF ADC Gain

2A R 0000 ADC-7-Data 53 R/W 0004 AUTO-DAC-CLR-SOURCE

2B R 0000 ADC-8-Data 54 R/W 0000 AUTO-DAC-CLR-EN

2C R 0000 ADC-9-Data 55 R/W 0000 SW-DAC-CLR

2D R 0000 ADC-10-Data 56 R/W 0000 HW-DAC-CLR-EN-0

2E R 0000 ADC-11-Data 57 R/W 0000 HW-DAC-CLR-EN-1

2F R 0000 ADC-12-Data 58 R/W 0000 DAC Configuration

30 R 0000 ADC-13-Data 59 R/W 0000 DAC Gain

31 R 0000 ADC-14-Data 5A R/W 0FFF Input-0-High-Threshold

32 R 0000 ADC-15-Data 5B R/W 0000 Input-0-Low-Threshold

33 R/W 0000 DAC-0-Data 5C R/W 0FFF Input-1-High-Threshold

34 R/W 0000 DAC-1-Data 5D R/W 0000 Input-1-Low-Threshold

35 R/W 0000 DAC-2-Data 5E R/W 0FFF Input-2-High-Threshold

36 R/W 0000 DAC-3-Data 5F R/W 0000 Input-2-Low-Threshold

37 R/W 0000 DAC-4-Data 60 R/W 0FFF Input-3-High-Threshold

38 R/W 0000 DAC-5-Data 61 R/W 0000 Input-3-Low-Threshold

39 R/W 0000 DAC-6-Data 62 R/W 07FF LT-High-Threshold

3A R/W 0000 DAC-7-Data 63 R/W 0800 LT-Low-Threshold

3B R/W 0000 DAC-8-Data 64 R/W 07FF D1-High-Threshold

3C R/W 0000 DAC-9-Data 65 R/W 0800 D1-Low-Threshold

3D R/W 0000 DAC-10-Data 66 R/W 07FF D2-High-Threshold

3E R/W 0000 DAC-11-Data 67 R/W 0800 D2-Low-Threshold

3F R/W 0000 DAC-0-CLR-Setting 68 R/W 0810 Hysteresis-0

40 R/W 0000 DAC-1-CLR-Setting 69 R/W 0810 Hysteresis-1

41 R/W 0000 DAC-2-CLR-Setting 6A R/W 2108 Hysteresis-2

42 R/W 0000 DAC-3-CLR-Setting 6B R/W 0000 Power-Down

43 R/W 0000 DAC-4-CLR-Setting 6C R 1220 Device ID

44 R/W 0000 DAC-5-CLR-Setting 7C R/W N/A Software Reset

(1) See register descriptions for I2C default values.

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TEMPERATURE DATA REGISTERS (Read-Only)

In twos complement format, 0.125°C/LSB.

LT-Temperature-Data Register (Address = 00h, Default 0000h, 0°C)

Store the local temperature sensor reading in twos complement data format.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

LT-11 LT-10 LT-9 LT-8 LT-7 LT-6 LT-5 LT-4 LT-3 LT-2 LT-1 LT-0 0 0 0 0

D1-Temperature-Data Register (Address = 01h, Default 0000h, 0°C)

Store the remote temperature sensor D1 reading in twos complement data format.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

D1-11 D1-10 D1-9 D1-8 D1-7 D1-6 D1-5 D1-4 D1-3 D1-2 D1-1 D1-0 0 0 0 0

D2-Temperature-Data Register (Address = 02h, Default 0000h, 0°C)

Store the remote temperature sensor D2 reading in twos complement data format.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

D2-11 D2-10 D2-9 D2-8 D2-7 D2-6 D2-5 D2-4 D2-3 D2-2 D2-1 D2-0 0 0 0 0

TEMPERATURE CONFIGURATION REGISTER (Read/Write, Address = 0Ah)

When using the SPI, the following bit configuration must be used; default = 003Ch.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 0 0 0 0 0 0 D2EN D1EN LTEN RC 0 0

When using the I2C interface, the following bit configuration must be used; default = 3CFFh.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 D2EN D1EN LTEN RC 0 0 1 1 1 1 1 1 1 1

The bit descriptions are shown in Table 11.

Table 11. Temperature Configuration Register Bit Descriptions

NAME DEFAULT R/W DESCRIPTION

Remote temperature sensor D2 enable.

D2EN 1 R/W If this bit = '1', D2 is enabled.

If this bit = '0', D2 is disabled.

Remote temperature sensor D1 enable.

D1EN 1 R/W If this bit = '1', D1 is enabled.

If this bit = '0', D1 is disabled.

Local temperature sensor enable.

LTEN 1 R/W If this bit = '1', LT is enabled.

If this bit = '0', LT is disabled.

Resistance correction enable.

RC 1 R/W If this bit = '1', correction is enabled.

If this bit = '0', correction is disabled.

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TEMPERATURE CONVERSION RATE REGISTER (Read/Write, Address = 0Bh)

When using the SPI, the following bit configuration must be used; default = 0007h.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0000000000000R2R1R0

When using the I2C interface, the following bit configuration must be used; default = 07FFh.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00000R2R1R011111111

The bit descriptions are shown in Table 12.

Table 12. Temperature Conversion Time

R2 R1 R0 CONVERSION TIME

0 0 0 128x minimum

0 0 1 64x minimum

0 1 0 32x minimum

0 1 1 16x minimum

1 0 0 8x minimum

1 0 1 4x minimum

1 1 0 2x minimum

1 1 1 Minimum cycle time

Table 13. Temperature Monitoring Cycle Time

MONITORING

TEMPERATURE SENSOR STATUS CYCLE TIME

Local sensor is active, remote sensors are disabled or in power-down. 15ms

One remote sensor is active and RC = '0', local sensor and one remote sensor are disabled or in power-down. 44ms

One remote sensor is active and RC = '1', local sensor and one remote sensor are disabled or in power-down. 93ms

One remote sensor and local sensor are active and RC = '0', one remote sensor is disabled or in power-down. 59ms

One remote sensor and local sensor are active and RC = '1', one remote sensor is disabled or in power-down. 108ms

Two remote sensors are active and RC = '0', local sensor is disabled or in power-down. 88ms

Two remote sensors are active and RC = '1', local sensor is disabled or in power-down. 186ms

All sensors are active and RC = '0'. 103ms

All sensors are active and RC = '1'. 201ms

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η-FACTOR CORRECTION REGISTER (Read/Write, Addresses = 21h and 22h)

Only the low byte is used; the high byte is ignored.

When using the SPI interface, the following bit configuration must be used; (Default = 0000h).

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

00000000 NADJUST

When using the I2C, the following bit configuration must be used; (Default = 00FFh).

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

NADJUST 11111111

The NADJUST value for ideality correction is stored as shown in Table 14.ηEFF is the actual ideality of the

transistor being used. Refer to the Ideality Factor section for more details.

Table 14. NADJUST and ηEFF Values

NADJUST

BINARY HEX DECIMAL ηEFF

0111 1111 7F 127 1.747977

0000 1010 0A 10 1.042759

0000 1000 08 8 1.035616

0000 0110 06 6 1.028571

0000 0100 04 4 1.021622

0000 0010 02 2 1.014765

0000 0001 01 1 1.011371

0000 0000 00 0 1.008 (Default)

1111 1111 FF –1 1.004651

1111 1110 FE –2 1.001325

1111 1100 FC –4 0.994737

1111 1010 FA –6 0.988235

1111 1000 F8 –8 0.981818

1111 0110 F6 –10 0.975484

1000 0000 80 –128 0.706542

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ADC-n-DATA REGISTERS (Read-Only, Addresses = 23h to 32h)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Bits[11:0] ADC data.

Four ADC data registers are available. The ADC-n-Data Registers (where n = 0 to 15) store the conversion

results of the corresponding analog channel-n, as shown in Table 15.

Table 15. ADC Data Register Definitions

CONVERSION RESULT

INPUT CHANNEL INPUT TYPE STORED IN FORMAT

Channel 0 Single-Ended ADC-0-Data Register Straight binary

Channel 1 Single-Ended ADC-1-Data Register Straight binary

Channel 2 Single-Ended ADC-2-Data Register Straight binary

Channel 3 Single-Ended ADC-3-Data Register Straight binary

CH0+/CH1– Differential ADC-0-Data Register Twos complement

CH2+/CH3– Differential ADC-2-Data Register Twos complement

Channel 4 Single-Ended ADC-4-Data Register Straight binary

Channel 5 Single-Ended ADC-5-Data Register Straight binary

Channel 6 Single-Ended ADC-6-Data Register Straight binary

Channel 7 Single-Ended ADC-7-Data Register Straight binary

Channel 8 Single-Ended ADC-8-Data Register Straight binary

Channel 9 Single-Ended ADC-9-Data Register Straight binary

Channel 10 Single-Ended ADC-10-Data Register Straight binary

Channel 11 Single-Ended ADC-11-Data Register Straight binary

Channel 12 Single-Ended ADC-12-Data Register Straight binary

Channel 13 Single-Ended ADC-13-Data Register Straight binary

Channel 14 Single-Ended ADC-14-Data Register Straight binary

Channel 15 Single-Ended ADC-15-Data Register Straight binary

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DAC-n-DATA REGISTERS (Read/Write, Addresses = 33h to 3Eh, Default 0000h)

Each DAC has a DAC data register to store the data [DAC11:DAC0] that is loaded into the DAC Latches.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Bits[11:0] DAC data.

DAC-n-CLR-SETTING REGISTERS (Read/Write, Addresses = 3Fh to 4Ah, Default 0000h)

Each DAC has a DAC-CLR-Setting Register to store the data to be loaded into the DAC Latch when the DAC is

cleared.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR DCLR

000011109876543210

GPIO REGISTER (Read/Write, Address = 4Bh, Default = 000Fh)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

GPIO- GPIO- GPIO- GPIO- GPIO- GPIO- GPIO- GPIO-

0000000076543210

For write operations, the GPIO pin operates as an output. Writing a '1' to the GPIO-nbit sets the GPIO-npin to

high impedance. Writing a '0' sets the GPIO-npin to logic low. An external pull-up resistor is required when using

the GPIO pin as an output.

For read operations, the GPIO pin operates as an input. Read the GPIO-nbit to receive the status of the GPIO-n

pin. Reading a '0' indicates that the GPIO-npin is low; reading a '1' indicates that the GPIO-npin is high.

After power-on reset, or any forced hardware or software reset, the GPIO-nbit is set to '1' and is in a high-

impedance state.

When D1 is enabled, GPIO-4 and GPIO-5 are ignored.

When D2 is enabled, GPIO-6 and GPIO-7 are ignored.

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AMC CONFIGURATION REGISTER 0 (Read/Write, Address = 4Ch, Default = 2000h)

Table 16. AMC Configuration Register 0

BIT NAME DEFAULT R/W DESCRIPTION

15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

ADC Conversion Mode Bit. This bit selects between the two operating conversion modes

(direct or auto).

CMODE = '0': Direct mode. The analog inputs specified in the ADC Channel Registers are

converted sequentially (see the ADC Channel Registers) one time. When one set of

13 CMODE 1 R/W conversions is complete, the ADC is idle and waits for a new trigger.

CMODE = '1': Auto mode. The analog inputs specified in the AMC Channel Registers are

converted sequentially and repeatedly (see the ADC Channel Registers). When one set of

conversions is complete, the ADC multiplexer returns to the first channel and repeats the

process. Repetitive conversions continue until the CMODE bit is cleared ('0').

Internal conversion bit.

12 ICONV 0 R/W Set this bit to '1' to start the ADC conversion internally. The bit is automatically cleared ('0')

after the ADC conversion starts.

Load DAC bit. Set this bit to '1' to synchronously load the DAC Data Registers, which are

programmed for synchronous update mode (SLDAC-n= 1). The AMC7812 updates the

DAC Latch only if the ILDAC bit is set ('1'), thereby eliminating any unnecessary glitch. Any

11 ILDAC 0 R/W DAC channels that have not been accessed are not reloaded. When the DAC Latch is

updated, the corresponding output changes to the new level immediately. This bit is

cleared ('0') after the DAC Data Register is updated.

ADC VREF select bit.

When this bit = '0', the internal reference buffer is off, and the external reference drives the

10 ADC-REF-INT 0 R/W ADC.

When this bit = '1', the internal buffer is on and the internal reference drives the ADC. Note

that a compensation capacitor is required.

Enable ALARM pin bit.

9 EN-ALARM 0 R/W When this bit = '0', the ALARM pin is disabled.

When this bit = '1', the ALARM pin is enabled.

8 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

ADC Data available flag bit. For Direct mode only. Always cleared (set to '0') in Auto mode.

DAVF = '1': The ADC conversions are complete and new data are available.

DAVF = '0': The ADC conversion is in progress (data are not ready) or the ADC is in Auto

mode.

In Direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF = '1', and goes

7 DAVF R high when DAVF = '0'.

In Auto mode, DAVF is always cleared to '0'. However, a 1µs pulse (active low) appears on

the DAV pin when the last input specified in the ADC Channel Registers is converted.

DAVF is cleared to '0' in one of three ways: (1) reading the ADC Data Register, (2) starting

a new ADC conversion, or (3) writing '0' to this bit. Reading the Status Register does not

clear this bit.

Global alarm bit. This bit is the OR function of all individual alarm bits of the Status

6 GALR 0 R Register. This bit is set ('1') when any alarm condition occurs, and remains '1' until the

Status Register is read. This bit is cleared ('0') after reading the Status Register.

5 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

4 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

3 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

2 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

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AMC CONFIGURATION REGISTER 1 (Read/Write, Address = 4Dh, Default = 0070h)

Table 17. AMC Configuration Register 1

BIT NAME DEFAULT R/W DESCRIPTION

15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

14 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

13 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

12 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

11 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

10 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

9 CONV-RATE-1 0 R/W ADC conversion rate bit. See Table 18.

8 CONV-RATE-0 0 R/W ADC conversion rate bit. See Table 18.

7 CH-FALR- CT-2 0 R/W False alarm protection bit for CH0 to CH3. See Table 19.

6 CH-FALR- CT-1 1 R/W False alarm protection bit for CH0 to CH3. See Table 19.

5 CH-FALR- CT-0 1 R/W False alarm protection bit for CH0 to CH3. See Table 19.

4 TEMP-FALR- CT-1 1 R/W False alarm protection bit for temperature monitor. See Table 20.

3 TEMP-FALR- CT-0 0 R/W False alarm protection bit for temperature monitor. See Table 20.

2 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

Table 18. CONV-RATE-[1:0] Bit Settings

CONV-RATE-1 CONV-RATE-0 ADC CONVERSION RATE

0 0 500 kSPS, the specified rate (default)

0 1 ½ of the specified rate

1 0 1/4 of the specified rate

1 1 1/8 of the specified rate

Table 19. CH-FALR-CT-[2:0] Bit Settings

NCONSECUTIVE SAMPLES

CH-FALR-CT-2 CH-FALR-CT-1 CH-FALR-CT-0 BEFORE ALARM IS SET

0 0 0 1

0 0 1 4

0 1 0 8

0 1 1 16 (default for CH-0 to CH-3)

1 0 0 32

1 0 1 64

1 1 0 128

1 1 1 256

Table 20. TEMP-FALR-CT-[1:0] Bit Settings

TEMP-FALR-CT-1 TEMP-FALR-CT-0 NCONSECUTIVE SAMPLES BEFORE ALARM IS SET

0 0 1

0 1 2

1 0 4 (default)

1 1 8

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ALARM CONTROL REGISTER (Read/Write, Address = 4Eh, Default = 0000h)

The Alarm Control Register determines whether the ALARM pin is accessed when a corresponding alarm event

occurs. However, this register does not affect the status bit in the Status Register. Note that the thermal alarm is

always enabled. When the THERM_ALR bit = '1', the ALARM pin goes low, if the pin is enabled.

Table 21. Alarm Control Register

BIT NAME DEFAULT R/W DESCRIPTION

15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

CH0 and (CH0+/CH1–) alarm enable bit.

If EALR-CH0 = '1', the alarm is enabled, the CH0-ALR bit is set, and the ALARM pin goes

14 EALR-CH0 0 R/W low (if enabled) when the input of CH0 or (CH0+/CH1–) is out of range.

If EALR-CH0 = '0', the alarm is masked. When the input of CH0 or (CH0+/CH1–) is out of

range, the ALARM pin does not go low, but the CH0-ALR bit is set.

CH1 alarm enable bit.

If EALR-CH1 = '1', the alarm is enabled, the CH1-ALR bit is set, and the ALARM pin goes

13 EALR-CH1 0 R/W low (if enabled) when the input of CH1 is out of range.

If EALR-CH1 = '0', the alarm is masked. When the input of CH1 is out of range, the

ALARM pin does not go low, but the CH1-ALR bit is set.

CH2 and (CH2+/CH3–) alarm enable bit.

If EALR-CH2 = '1', the alarm is enabled, the CH2-ALR bit is set, and the ALARM pin goes

12 EALR-CH2 0 R/W low (if enabled) when the input of CH2 or (CH2+/CH3–) is out of range.

If EALR-CH2 = '0', the alarm is masked. When the input of CH2 or (CH2+/CH3–) is out of

range, the ALARM pin does not go low, but the CH2-ALR bit is set.

CH3 alarm enable bit.

If EALR-CH3 = '1', the alarm is enabled, the CH3-ALR bit is set, and the ALARM pin goes

11 EALR-CH3 0 R/W low (if enabled) when the input of CH3 is out of range.

If EALR-CH3 = '0', the alarm is masked. When the input of CH3 is out of range, the

ALARM pin does not go low, but the CH3-ALR bit is set.

Local sensor low alarm enable bit.

If EALR-LT-Low = '1', the LT-Low alarm is enabled. When LT is below the specified range,

10 EALR-LT-Low 0 R/W the LT-Low-ALR bit is set ('1') and the ALARM pin goes low (if enabled).

If EALR-LT-Low = '0', the LT-Low alarm is masked. When LT is below the specified range,

the ALARM pin does not go low, but the LT-Low-ALR bit is set.

Local sensor high alarm enable bit.

If EALR-LT-High = '1', the LT-High alarm is enabled. When LT is above the specified

9 EALR-LT-High 0 R/W range, the LT-High-ALR bit is set ('1') and the ALARM pin goes low (if enabled).

If EALR-LT-High = '0', the LT-High alarm is masked. When LT is above the specified

range, the ALARM pin does not go low, but the LT-High-ALR bit is set.

D1 low alarm enable bit.

If EALR-D1-Low = '1', the D1-Low alarm is enabled. When D1 is below the specified range,

8 EALR-D1-Low 0 R/W the D1-Low-ALR bit is set ('1'), and the ALARM pin goes low (if enabled).

If EALR-D1-Low = '0', the D1-Low alarm is masked. When D1 is below the specified range,

the ALARM pin does not go low, but the D1-Low-ALR bit is set.

D1 high alarm enable bit.

If EALR-D1-High = '1', the D1-High alarm is enabled. When D1 is above the specified

7 EALR-D1-High 0 R/W range, the D1-High-ALR bit is set ('1'), and the ALARM pin goes low (if enabled).

If EALR-D1-High = '0', the D1-High alarm is masked. When D1 is above the specified

range, the ALARM pin does not go low, but the D1-High-ALR bit is set.

D2 low alarm enable bit.

If EALR-D2-Low = '1', the D2-Low alarm is enabled. When D2 is below the specified range,

6 EALR-D2-Low 0 R/W the D2-Low-ALR bit is set ('1'), and the ALARM pin goes low (if enabled).

If EALR-D2-Low = '0', the D2-Low alarm is masked. When D2 is below the specified range,

the ALARM pin does not go low, but the D2-Low-ALR bit is set.

D2 high alarm enable bit.

If EALR-D2-High = '1', the D2-High alarm is enabled. When D2 is above the specified

5 EALR-D2-High 0 R/W range, the D2-High-ALR bit is set ('1'), and the ALARM pin goes low (if enabled).

If EALR-D2-High = '0', the D2-High alarm is masked. When D2 is above the specified

range, the ALARM pin does not go low, but the D2-High-ALR bit is set.

D1 fail alarm enable bit.

If EALR-D1-FAIL = '1', the D1-Fail alarm is enabled. When D1 fails, the D1-FAIL-ALR bit is

4 EALR-D1-FAIL 0 R/W set ('1'), the ALARM pin goes low (if enabled).

If EALR-D1-FAIL = '0', the D1-FAIL alarm is masked. When D1 fails, the ALARM pin does

not go low, but the D1-FAIL-ALR bit is set.

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Table 21. Alarm Control Register (continued)

BIT NAME DEFAULT R/W DESCRIPTION

D2 fail alarm enable bit.

If EALR-D2-FAIL = '1', the D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is

3 EALR-D2-FAIL 0 R/W set ('1'), the ALARM pin goes low (if enabled).

If EALR-D2-FAIL = '0', the D2-FAIL alarm is masked. When D2 fails, the ALARM pin does

not go low, but the D2-FAIL-ALR bit is set.

Alarm latch disable bit.

When ALARM-LATCH-DIS = '1', the Status Register bits are not latched. When the alarm

condition subsides, the alarm bits are cleared regardless of whether the Status Register

ALARM- has been read or not.

2 0 R/W

LATCH-DIS When ALARM-LATCH-DIS = '0', the Status Register bits are latched. When an alarm

occurs, the corresponding alarm bit is set ('1'). The alarm bit remains '1' until the error

condition subsides and the Status Register is read. Before reading, the alarm bit is not

cleared ('0') even if the alarm condition disappears.

1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

STATUS REGISTER (Read Only, Address = 4Fh, Default = 0000h)

The AMC7812 continuously monitors all analog inputs and temperatures during normal operation. When any

input is out of the specified range Nconsecutive times, the corresponding alarm bit is set ('1'). If the input returns

to the normal range before Nconsecutive times, the corresponding alarm bit remains clear ('0'). This

configurations avoids any false alarms.

When an alarm status occurs, the corresponding alarm bit is set ('1'). When the ALARM-LATCH-DIS bit in the

Alarm Control Register is cleared ('0'), the ALARM pin is latched. Whenever an alarm status bit is set, it remains

set until the event that caused it is resolved and the Status Register is read. Reading the Status Registers clears

the alarm status bit. The alarm bit can only be cleared by reading the Status Register after the event is resolved,

or by hardware reset, software reset, or power-on reset. All alarm status bits are cleared when reading the Status

unless otherwise noted.

When the ALARM-LATCH-DIS bit in the Alarm Control Register is set ('1'), the ALARM pin is not latched. The

alarm bit goes to '0' when the error condition subsides, regardless of whether the bit is read or not.

Table 22. Status Register

BIT NAME DEFAULT R/W DESCRIPTION

15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

CH0-ALR = '1' when single-ended channel 0 or differential input pair (CH0+/CH1–) is out of

14 CH0-ALR 0 R the range defined by the corresponding threshold registers.

CH0-ALR = '0' when the analog input is not out of the specified range.

CH1-ALR = '1' when single-ended channel 1 is out of the range defined by the

13 CH1-ALR 0 R corresponding threshold registers.

CH1-ALR = '0' when the analog input is not out of the specified range.

CH2-ALR = '1' when single-ended channel 2 or differential input pair (CH2+/CH3–) is out of

12 CH2-ALR 0 R the range defined by the corresponding threshold registers.

CH2-ALR = '0' when the analog input is not out of the specified range.

CH3-ALR = '1' when single-ended channel 3 is out of the range defined by the

11 CH3-ALR 0 R corresponding threshold registers.

CH3-ALR = '0' when the analog input is not out of the specified range.

Local temperature under-range flag.

LT-Low-ALR = '1' when the local temperature is less than the low-bound threshold.

10 LT-Low-ALR 0 R LT-Low-ALR = '0' when the local temperature is not less than the range.

This bit is only checked when LT is enabled (EN-LT = '1'); it is ignored when EN-LT = '0'.

Local temperature over-range flag.

LT-High-ALR = '1' when the local temperature is greater than the high-bound threshold.

9 LT-High-ALR 0 R LT-High-ALR = '0' when the local temperature is not greater than the range.

This bit is only checked when LT is enabled (EN-LT = '1'); it is ignored when EN-LT = '0'.

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Table 22. Status Register (continued)

BIT NAME DEFAULT R/W DESCRIPTION

Remote temperature reading of D1when less than the range flag.

D1-Low-ALR = '1' when the local temperature is less than the low-bound threshold.

8 D1-Low-ALR 0 R D1-Low-ALR = '0' when the local temperature is not less than the range.

This bit is only checked when D1 is enabled (EN-D1 = '1'); it is ignored when EN-D1 = '0'.

Remote temperature reading of D1 when greater than the range flag.

D1-High-ALR = '1' when the local temperature is greater than the high-bound threshold.

7 D1-High -ALR 0 R D1-High-ALR = '0' when the local temperature is not greater than the range.

This bit is only checked when D1 is enabled (EN-D1 = '1'); it is ignored when EN-D1 = '0'.

Remote temperature reading of D2 when less than the range flag.

D2-Low-ALR = '1' when the local temperature is less than the low-bound threshold.

6 D2-Low-ALR 0 R D2-Low-ALR = '0' when the local temperature is not less than the range.

This bit is only checked when D2 is enabled (EN-D2 = '1'); it is ignored when EN-D2 = '0'.

Remote temperature reading of D2 when greater than the range flag.

D2-High-ALR = '1' when the local temperature is greater than the high-bound threshold.

5 D2-High -ALR 0 R D2-High-ALR = '0' when the local temperature is not greater than the range.

This bit is only checked when D2 is enabled (EN-D2 = '1'); it is ignored when EN-D2 = '0'.

Remote sensor D1 failure flag.

D1-FAIL-ALR = '1' when the sensor is an open-circuit or short-circuit.

4 D1-FAIL-ALR 0 R D1-FAIL-ALR = '0' when the sensor is in a normal condition.

This bit is only checked when D1 is enabled (EN-D1 = '1'); it is ignored when EN-D1 = '0'.

Remote sensor D2 failure flag.

D2-FAIL-ALR = '1' when the sensor is an open-circuit or short-circuit.

3 D2-FAIL-ALR 0 R D2-FAIL-ALR = '0' when the sensor is in a normal condition.

This bit is only checked when D2 is enabled (EN-D2 = '1'); it is ignored when EN-D2 = '0'.

Thermal alarm flag. When the die temperature is equal to or greater than +150°C, the bit is

set ('1') and the THERM-ALR flag activates. The on-chip temperature sensor (LT) monitors

2 THERM-ALR 0 R the die temperature. If LT is disabled, the THERM-ALR bit is always '0'. The hysteresis of

this alarm is 8°C.

1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

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ADC CHANNEL REGISTER 0 (Read/Write, Address = 50h, Default = 0000h)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DF DF

0 SE0 SE1 (CH0+/ SE2 SE3 (CH2+/ SE4 SE5 SE6 SE7 SE8 SE9 SE10 SE11 SE12

CH1–) CH3–)

These bits specify the external analog auxiliary input channels (CH0 to CH12) to be converted. The specified

channel(s) is accessed sequentially in order from bit 14 to bit 0. The input is converted when the corresponding

bit is set ('1').

Bit 15 Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

Bits 14, 13, 11, 10, 8:0 SE0 to SE12. External single-ended analog input for CHn. The result is stored in ADC-n-Data Register in

straight binary format.

Bit 12 DF (CH0+CH1–). External analog differential input pair, CH0 and CH1, with CH0 as positive and CH1 as

negative. The difference of (CH0 – CH1) is converted and the result is stored in the ADC-0-Data Register in twos

complement format.

DF(CH2+/CH3-). External analog differential input pair, CH2 and CH3, with CH2 as positive and CH3 as

Bit 9 negative. The difference of (CH2 – CH3) is converted and the result is stored in the ADC-2-Data Register in twos

complement format.

Table 23. CH0 and CH1 Bit Settings

BIT 14 BIT 13 BIT 12 DESCRIPTION

1 1 0 CH0 and CH1 are both accessed as single-ended inputs. Bit 12 is ignored.

1 0 0 CH0 is accessed as a single-ended input. CH1 is not accessed. Bit 12 is ignored.

0 1 0 CH1 is accessed as a singled-ended. CH0 is not accessed. Bit 12 is ignored.

0 0 1 Differential input pair CH0 + and CH1– is accessed as a differential input.

0 0 0 CH0, CH1, and differential pair CH0+/CH1– are not accessed.

Table 24. CH2 and CH3 Bit Settings

BIT 11 BIT 10 BIT 9 DESCRIPTION

1 1 0 CH2 and CH3 are both accessed as single-ended inputs. Bit 9 is ignored.

1 0 0 CH2 is accessed as a single-ended input. CH3 is not accessed. Bit 9 is ignored.

0 1 0 CH3 is accessed as a singled-end input. CH2 is not accessed. Bit 9 is ignored.

0 0 1 Differential input pair CH2+ and CH3– is accessed as a differential input.

0 0 0 CH2, CH3, and differential pair CH2+/CH3– are not accessed.

Table 25. CH4 to CH12 Bit Settings

BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DESCRIPTION

1 — — — — — — — — CH4 is accessed as a single-ended input

— 1 — — — — — — — CH5 is accessed as a single-ended input

— — 1 — — — — — — CH6 is accessed as a single-ended input

— — — 1 — — — — — CH7 is accessed as a single-ended input

— — — — 1 — — — — CH8 is accessed as a single-ended input

— — — — — 1 — — — CH9 is accessed as a single-ended input

— — — — — — 1 — — CH10 is accessed as a single-ended input

— — — — — — — 1 — CH11 is accessed as a single-ended input

— — — — — — — — 1 CH12 is accessed as a single-ended input

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ADC CHANNEL REGISTER 1 (Read/Write, Address = 51h, Default = 0000h)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 SE13 SE14 SE15 0 0 0 0 0 0 0 0 0 0 0 0

These bits specify the external analog auxiliary input channels (CH13, CH14,and CH 15) to be converted. The

specified channel is accessed sequentially in the order from bit 14 to bit 0 of ADC Channel Register 0, and then

bit 14 to bit 12 of ADC Channel Register 1. The input is converted when the corresponding bit is set ('1').

Bits[14:12] SEn: External single-ended analog input CHn. The result is stored in the ADC-n-Data Register in straight binary format.

ADC GAIN REGISTER (Read/Write, Address = 52h, Default = FFFFh)

MSB

BIT BIT BIT BIT BIT BIT LSB

15 14 13 12 11 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ADG0 ADG1 ADG2 ADG3 ADG4 ADG5 ADG6 ADG7 ADG8 ADG9 ADG10 ADG11 ADG12 ADG13 ADG14 ADG15

Bit 15 ADG0.

When ADG0 = '1', the analog input range of single-ended input CH0 (SE0) is 0 to (2 · VREF) or differential input pair

DF(CH0+/CH1–) is (–2 · VREF) to (+2 · VREF).

When ADG0 = '0', the analog input range of single-ended input CH0 (SE0) is 0 to VREF or differential input pair

DF(CH0+/CH1–) is –VREF to +VREF.

Bit 14 ADG1.

When ADG1 = '1', the analog input range is 0 to (2 · VREF).

When ADG1 = '0', the analog input range of single-ended input CH1 (SE1) is 0 to VREF.

Bit 13 ADG2.

When ADG2 = '1', the analog input range of single-ended input CH2 (SE2) is 0 to (2 · VREF) or differential input pair

DF(CH2+/CH3–) is (–2 · VREF) to (+2 · VREF).

When ADG2 = '0', the analog input range of single-ended input CH2 (SE2) is 0 to VREF or differential input pair

DF(CH2+/CH3–) is –VREF to +VREF.

Bit 12 ADG3.

When ADG3 = '1', the analog input range is 0 to (2 · VREF).

When ADG3 = '0', the analog input range of single-end input CH3 (SE3) is 0 to VREF.

Bit[11:0] ADG4 to ADG15.

When these bits = '1', the analog input range is 0 to (2 · VREF).

When these bits = '0', the analog input range of CHn(where n = 4 to 15) is 0 to VREF

AUTO-DAC-CLR-SOURCE REGISTER (Read/Write, Address = 53h, Default = 0004h)

This register selects which alarm forces the DAC into a clear state, regardless of which DAC operation mode is

active, auto or manual.

Table 26. AUTO-DAC-CLR-SOURCE Register

BIT NAME DEFAULT R/W DESCRIPTION

15 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

CH0 alarm clear bit.

If CH0-ALR_CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register and

14 CH0-ALR-CLR 0 R/W the CH0-ALR bit in the Status Register are set ('1'), then DAC-nis forced to a clear status.

If CH0-ALR_CLR = '0', then CH1-ALR goes to '1' and does not force any DAC to a clear

status.

CH1 alarm clear bit.

If CH1-ALR_CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register and

13 CH1-ALR-CLR 0 R/W the CH1-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear status.

If CH1-ALR_CLR = '0', then CH1-ALR goes to '1' and does not force any DAC to a clear

status.

CH2 alarm clear bit.

If CH2-ALR_CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register and

12 CH2-ALR-CLR 0 R/W the CH2-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear status.

If CH2-ALR_CLR = '0', then CH2-ALR goes to '1' and does not force any DAC to a clear

status.

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Table 26. AUTO-DAC-CLR-SOURCE Register (continued)

BIT NAME DEFAULT R/W DESCRIPTION

CH3 alarm clear bit.

If CH3-ALR_CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register and

11 CH3-ALR-CLR 0 R/W the CH3-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear status.

If CH3-ALR_CLR = '0', then CH3-ALR goes to '1' and does not force any DAC to a clear

status.

Local temperature sensor low alarm clear bit.

If LT-Low-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

LT-Low-ALR- and the LT-Low-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

10 0 R/W

CLR status.

If LT-Low-ALR-CLR = '0', then LT-Low-ALR goes to '1' and does not force any DAC to a

clear status.

Local temperature sensor high alarm clear bit.

If LT-High-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

LT-High-ALR- and the LT-High-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

9 0 R/W

CLR status.

If LT-High-ALR-CLR = '0', then LT-High-ALR goes to '1' and does not force any DAC to a

clear status.

Remote temperature sensor D1 low alarm clear bit.

If D1-Low-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

D1-Low-ALR- and the D1-Low-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

8 0 R/W

CLR status.

If D1-Low-ALR-CLR = '0', then D1-Low-ALR goes to '1' and does not force any DAC to a

clear status.

Remote temperature sensor D1 high alarm clear bit.

If D1-High-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

D1-High-ALR- and the D1-High-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

7 0 R/W

CLR status.

If D1-High-ALR-CLR = '0', then D1-High-ALR goes to '1' and does not force any DAC to a

clear status.

Remote temperature sensor D2 low alarm clear bit.

If D2-Low-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

D2-Low-ALR- and the D2-Low-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

6 0 R/W

CLR status.

If D2-Low-ALR-CLR = '0', then D2-Low-ALR goes to '1' and does not force any DAC to a

clear status.

Remote temperature sensor D2 high alarm clear bit.

If D2-High-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

D2-High-ALR- and the D2-High-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

5 0 R/W

CLR status.

If D2-High-ALR-CLR = '0', then D2-High-ALR goes to '1' and does not force any DAC to a

clear status.

D1 fail alarm clear bit.

If D1-FAIL-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register and

the D2-FAIL-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

4 D1-FAIL-CLR 0 R/W status.

If D1-FAIL-ALR-CLR = '0', then D1-FAIL-ALR goes to '1' and does not force any DAC to a

clear status.

D2 fail alarm clear bit.

If D2-FAIL-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register and

the D2-FAIL-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

3 D2-FAIL-CLR 0 R/W status.

If D2-FAIL-ALR-CLR = '0', then D2-FAIL-ALR goes to '1' and does not force any DAC to a

clear status.

Thermal alarm clear bit.

If THERM-ALR-CLR = '1', and if both the ACLRnbit in the AUTO-DAC-CLR-EN Register

THERM-ALR- and the THERM-ALR bit in the Status Register are set ('1'), then DACnis forced to a clear

2 1 R/W

CLR status.

If THERM-ALR-CLR = '0', then THERM-ALR goes to '1' and does not force any DAC to a

clear status.

1 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

0 — 0 R Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

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AUTO-DAC-CLR-EN REGISTER (Read/Write, Address = 54h, Default = 0000h)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR ACLR

0 0 0 0

11109876543210

Bits[14:3] ACLRn:Auto clear DAC-nenable bit.

If ACLRn= '1', DAC-nis forced into a clear state when the alarm occurs.

If ACLRn= '0', DAC-nis not forced into a clear state when the alarm occurs (default).

NOTE

ACLRnis always ignored when an alarm occurs for a temperature greater than +150°C

(THERM-ALR = '1'). If an alarm activates for a temperature greater than +150°C, and if

the THERM-ALR-CLR bit in the AUTO-DAC-CLR-SOURCE Register is set ('1'), all DACs

are forced into a clear status. However, if THERM-ALR-CLR is cleared ('0'), the over

+150°C alarm does not force any DAC to a clear status.

SW-DAC-CLR REGISTER (Read/Write, Address = 55h, Default = 0000h)

This register uses software to force the DAC into a clear state.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR ICLR

0 0 0 0

11109876543210

Bits[14:3] ICLRn:Software clear DACnbit.

If ICLRn= '1', DACnis forced into a clear state.

If ICLRn= '0', DACnis restored to normal operation.

HW-DAC-CLR-EN 0 REGISTER (Read/Write, Address = 56h, Default = 0000h)

This register determines which DAC is in a clear state when the DAC-CLR-0 pin goes low.

MSB LSB

BIT BIT BIT BIT

15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 2 1 0

H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR H0CLR

0 0 0 0

11 10 9 8 7 6 5 4 3 2 1 0

Bits[14:3] H0CLRn:Hardware clear DAC-nenable 1 bit.

If H0CLRn= '1', DAC-n is forced into a clear state when the DAC-CLR-0 pin goes low.

If H0CLRn= '0', pulling the DAC-CLR-0 pin low does not effect the state of DAC-n.

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HW-DAC-CLR-EN 1 REGISTER (Read/Write, Address = 57h, Default = 0000h)

This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.

MSB LSB

BIT BIT BIT BIT

15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 2 1 0

H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR H1CLR

0 0 0 0

11 10 9 8 7 6 5 4 3 2 1 0

Bits[14:3] H1CLRn:Hardware clear DAC-nenable 1 bit.

If H1CLRn= '1', DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low.

If H1CLRn= '0', pulling the DAC-CLR-1 pin low does not effect the state of DAC-n.

DAC CONFIGURATION REGISTER (Read/Write, Address = 58h, Default = 0000h)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA SLDA

000011109876543210

Bits[11:0] SLDA-n:DAC synchronous load enable bit.

If SLDA-n= '1', synchronous load is enabled. When internal load DAC signal ILDAC occurs, the DAC-n Latch is loaded

with the value of the corresponding DACn-Data Register, and the output of DAC-nis updated immediately. The internal

load DAC signal ILDAC is generated by writing a '1' to the ILDAC bit in the AMC Configuration Register. In synchronous

Load, a write command to the DAC-n-Data Register updates that register only, and does not change the DAC-noutput.

If SLDA-n= '0', asynchronous load is enabled. A write command to the DAC-n-Data Register immediately updates the

DAC-nLatch and the output of DAC-n. The synchronous load DAC signal (ILDAC) does not affect DACn. the default

value of SLDA-n= '0'. The AMC7812 updates the DAC Latch only if the ILDAC bit was set ('1'), thereby eliminating

unnecessary glitch. Any DAC channels that have not been accessed are not reloaded. When the DAC Latch is updated,

the corresponding output changes to the new level immediately. Note that the SLDA-nbit is ignored in auto mode (DAC-n

Mode bits do not equal '00'). In auto mode, the DAC Latch is always updated asynchronously.

NOTE

The DACs can be forced into a clear state immediately by the external DAC-CLR-n signal,

by alarm events, and by writing to the SW-DAC-CLR Register. In these cases, the SLDA-n

bit is ignored.

DAC GAIN REGISTER (Read/Write, Address = 59h, Default = 0000h)

The DACnGAIN bits specify the output range of DACn.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DAC11 DAC10 DAC9 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0

0 0 0 0 GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN GAIN

Bits[11:0] DACnGAIN: DACngain bit.

If DACnGAIN = '1', the gain = 5 and the output is 0 to 5 · VREF

If DACnGAIN = '0', the gain = 2 and the output is 0 to 2 · VREF

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ANALOG INPUT CHANNEL THRESHOLD REGISTERS (Read/Write, Addresses = 5Ah to 61h)

Four analog auxiliary inputs (CH0, CH1, CH2, and CH3) and three temperature sensors (LT, D1, and D2)

implement an out-of-range alarm function. Threshold-High-nand Threshold-Low-n(where n = 0, 1, 2, 3) define

the upper bound and lower bound of the nth analog input range, as shown in Table 27. This window determines

whether the nth input is out-of-range. When the input is outside the window, the corresponding CH-ALR-nbit in

the Status Register is set to '1'.

For normal operation, the value of Threshold-High-nmust be greater than the value of Threshold-Low-n;

otherwise, CH-ALR-nis always set to '1' and an alarm is always indicated. Note that when the analog channel is

accessed as single-ended input, its threshold is in a straight binary format. However, when the channel is

accessed as a differential pair, its threshold is in twos complement format.

Table 27. Threshold Coding

INPUT CHANNEL INPUT TYPE THRESHOLD STORED IN FORMAT

Input-0-Threshold-High-Byte

Channel 0 Single-Ended Straight binary

Input-0-Threshold-Low-Byte

Input-1-Threshold- High-Byte

Channel 1 Single-Ended Straight binary

Input-1-Threshold- Low-Byte

Input-2-Threshold- High-Byte

Channel 2 Single-Ended Straight binary

Input-2-Threshold- Low-Byte

Input-3-Threshold- High-Byte

Channel 3 Single-Ended Straight binary

Input-3-Threshold- Low-Byte

Input-0-Threshold- High-Byte

CH0+/CH1– Differential Twos complement

Input-0-Threshold- Low-Byte

Input-2-Threshold- High-Byte

CH2+/CH3– Differential Twos complement

Input-2-Threshold- Low-Byte

Input-n-High-Threshold Register (where n = 0, 1, 2, 3) (Read/Write, Default = 0FFFh)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH

000011109876543210

Bits[15:12] Reserved. These bits are '0' when read back. Writing to these bits has no effect.

Bits[11:0] THRHn:Data bits of the upper-bound threshold of the nth analog input.

Input-n-Low-Threshold Register (where n = 0, 1, 2, 3) (Read/Write, Default = 0000h)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL

000011109876543210

Bits[15:12] Reserved. These bits are '0' when read back. Writing to these bits has no effect.

Bits[11:0] THRLn:Data bits of the lower-bound threshold of the nth analog input.

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TEMPERATURE THRESHOLD REGISTERS

LT-High-Threshold Register (Read/Write, Address = 62h, Default = 07FFh, +255.875°C)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH

11109876543210

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

LT-Low-Threshold Register (Read/Write, Address = 63h, Default = 0800h, –256°C)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 0 THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL

11109876543210

Bits [15:12] = Reserved. Writing to these bits causes no change. Reading these bits returns '0'.

D1-High-Threshold Register (Read/Write, Address = 64h, Default = 07FFh, +255.875°C)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH

000011109876543210

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

D1-Low-Threshold Register (Read/Write, Address = 65h, Default = 0800h, –256°C)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL

000011109876543210

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

D2-High-Threshold Register (Read/Write, Address = 66h, Default = 07FFh, +255.875°C)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH THRH

000011109876543210

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

D2-Low-Threshold Register (Read/Write, Address = 67h, Default = 0800h, –256°C)

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL THRL

000011109876543210

Bits [15:12] = ‘0' when read back. Writing these bits causes no change

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AMC7812

SBAS513C –JANUARY 2011–REVISED MARCH 2012

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HYSTERESIS REGISTERS

The hysteresis registers define the hysteresis in the alarm detection of an individual alarm.

Hysteresis Register 0 (Read/Write, Address = 68h, Default = 0810h, 8 LSB)

This register contains the hysteresis values for CH0 and CH1.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CH0- CH0- CH0- CH0- CH0- CH0- CH0- CH1- CH1- CH1- CH1- CH1- CH1- CH1-

0 0

HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0

Bits[14:8]CH0-HYS-n:Hysteresis of CH0, 1 LSB per step.

Bits[7:1]CH1-HYS-n:Hysteresis of CH1, 1 LSB per step.

Hysteresis Register 1 (Read/Write, Address = 69h, Default = 0810h, 8 LSB)

This register contains the hysteresis values for CH2 and CH3.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CH2- CH2- CH2- CH2- CH2- CH2- CH2- CH3- CH3- CH3- CH3- CH3- CH3- CH3-

0 0

HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0 HYS-6 HYS-5 HYS-4 HYS-3 HYS-2 HYS-1 HYS-0

Bits[14:8]CH2-HYS-n:Hysteresis of CH2, 1 LSB per step.

Bits[7:1]CH3-HYS-n:Hysteresis of CH3, 1 LSB per step.

Hysteresis Register 2 (Read/Write, Address = 6Ah, Default = 2108h, 8°C)

This register contains the hysteresis values for D2, D1, and LT. The range is 0°C to +32°C.

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

D2- D2- D2- D2- D2- D1- D1- D1- D1- D1- LT- LT- LT- LT- LT-

0HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3 HYS-7 HYS-6 HYS-5 HYS-4 HYS-3

Bits[14:10]D2-HYS-n:Hysteresis of D2, 1°C per step. Note that bits D2-HYS-[2:0] are always '0'.

Bits[9:5]D1-HYS-n:Hysteresis of D1, 1°C per step. Note that bits D1-HYS-[2:0] are always '0'.

Bits[4:0]LT-HYS-n:Hysteresis of LT, 1°C per step. Note that bits LT-HYS-[2:0] are always '0'.

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

POWER-DOWN REGISTER (Read/Write, Address = 6Bh, Default = 0000h)

After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled

by this register are either powered-down or off. The Power-Down Register allows the host to manage the

AMC7812 power dissipation. When not required, the ADC, the reference buffer amplifier, and any of the DACs

can be put into an inactive low-power mode to reduce current drain from the supply. The bits in the Power-Down

MSB LSB

BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC PDAC

0 PADC PREF 0

01234567891011

Bit 14 PADC: Power-down mode control bit.

If PADC = '1', the ADC is in normal operating mode.

If PADC = '0', the ADC is inactive in low-power mode.

Bit 13 PREF: Internal reference in power-down mode control bit.

If PREF = '1', the reference buffer amplifier is powered on.

If PREF = '0', the reference buffer amplifier is inactive in low-power mode.

Bits[12:1]PDACn:DACnpower-down control bit.

If PDACn= '1', DACnis in normal operating mode.

If PDACn= '0', DACnis inactive in low-power mode and its output buffer amplifier is in a Hi-Z state. The output pin of

DACnis internally switched from the buffer output to the analog ground through an internal resistor.

Device ID Register (Read-Only, Address = 6Ch, Default = 1220h)

Model and revision information.

Software Reset Register (Read/Write, Address = 7Ch, Default = NA)

The Software Reset Register resets all registers to default values, except for the DAC Data Register, DAC Latch,

and DAC Clear Register. The software reset is similar to a hardware reset, which resets all registers including

the DAC Data Register, DAC Latch, and DAC Clear Register. After a software reset, make sure that the DAC

Data Register, DAC latch, and DAC Clear Register are set to the desired values before the DAC is powered on.

SPI Mode

In SPI Mode, writing 6600h to this register forces the device reset.

I2C Mode

Writing to this register (with any data) forces the device to perform a software reset. Reading this register returns

an undefined value that must be ignored. Note that this register is 8-bit, instead of 16-bit. Both reading from and

writing to this register are single-byte operations. Writing data to the Software Reset Register in I2C Mode is

shown in the following steps:

1. The master device asserts a start condition.

2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a

write operation.

3. The AMC7812 asserts an acknowledge signal on SDA.

4. The master sends register address 7Ch.

5. The AMC7812 asserts an acknowledge signal on SDA.

6. The master sends a data byte.

7. The AMC7812 asserts an acknowledge signal on SDA.

8. The master asserts a stop condition to end the transaction.

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SBAS513C –JANUARY 2011–REVISED MARCH 2012

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REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (November 2011) to Revision C Page

• Changed Features Bullet From: Small Packages: 9mm x 9mm QFN-64 To: Small Packages: 9mm x 9mm QFN-64,

and 10mm x 10mm HTQFP-64 ............................................................................................................................................. 1

• Added HTQFP-64 package option to the Description .......................................................................................................... 1

• Added HTQFP-64 package to the PACKAGE/ORDERING INFORMATION table .............................................................. 2

• Added PAP (HTQFP) to the Thermal Information table ....................................................................................................... 2

• Added the HTQFP-64 Pin Configuration .............................................................................................................................. 8

• Added text "QFN Package" to Figure 75 and Figure 76 ..................................................................................................... 28

• Added Figure 77 and Figure 78 .......................................................................................................................................... 28

•η-Factor Range Table, Changed From: 0000 0020 To: 0000 0010 ................................................................................... 37

•η-Factor Range Table, Changed From 1111 0000 To: 1000 0000 .................................................................................... 37

Changes from Revision A (March 2011) to Revision B Page

• Added text to Desciption section .......................................................................................................................................... 1

• Added Reset Delay parameter to Electrical Charactieristics ................................................................................................ 6

• Added Convert Pulse Width parameter to Electrical Characteristics .................................................................................... 6

• Added Reset Pulse Width parameter to Electrical Characteristics ....................................................................................... 6

• Changed recommended compensation capacitor from 470nF to 4.7µF .............................................................................. 9

• Changed recommended compensation capacitor value from 470nF to 4.7µF to reflect bench characterization

conditions ............................................................................................................................................................................ 39

• Changed text in first paragraph of Clear DACs section ...................................................................................................... 43

• Clarified voltage condition for hardware reset .................................................................................................................... 48

• Added description of software reset function ...................................................................................................................... 48

• Added voltage condition for initiation of POR ..................................................................................................................... 48

• Added Power Supply Sequence section. ............................................................................................................................ 49

Changes from Original (January 2011) to Revision A Page

• Changed Load Current to include separate source/sink test conditions; updated from one row with typical value of

±7mA at 200mV .................................................................................................................................................................... 3

• Added Direct Mode test condition to Conversion Rate parameter ....................................................................................... 4

• Deleted test condition from Absolute Input Voltage parameter ............................................................................................ 4

• Added note to clarify Power Dissipation conditions .............................................................................................................. 6

• Added missing figure number for Figure 6 ......................................................................................................................... 15

• Updated X axis range in Figure 34 to include –12mA ........................................................................................................ 19

• Changed Y axis label to "Offset Error" in Figure 61 (typo) ................................................................................................. 25

• Added Figure 67 ................................................................................................................................................................. 26

• Updated Programmable Conversion Rate section ............................................................................................................. 33

• Added Nap Enabled column to Table 1 .............................................................................................................................. 33

• Changed latch position in Figure 93 ................................................................................................................................... 43

• Changed Table 9 to show SDI/SDO relationship ............................................................................................................... 56

• Changed bit 12 entries of Table 23 from don't care to 0 .................................................................................................... 71

• Changed bit 9 entries of Table 24 from don't care to 0 ...................................................................................................... 71

Product Folder Link(s): AMC7812

PACKAGE OPTION ADDENDUM

www.ti.com 30-May-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

AMC7812SPAP ACTIVE HTQFP PAP 64 160 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

AMC7812SPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

AMC7812SRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

AMC7812SRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

AMC7812SPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2

AMC7812SRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

AMC7812SRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

AMC7812SPAPR HTQFP PAP 64 1000 367.0 367.0 55.0

AMC7812SRGCR VQFN RGC 64 2000 367.0 367.0 38.0

AMC7812SRGCT VQFN RGC 64 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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