74F657
Octal transceiver with 8-bit parit
generator/checker
Process specification
IC15 Data Handbook
1990 Jul 30
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
2
90 July 30 853 1117 00081
FEATURES
• Combines 74F245 and 74F280A functions in one package
• High impedance base input for reduced loading (70µA in
high and low states)
• Ideal in applications where high output drive and light bus
loading are required (IIL is 70µA vs FAST std of 600µA)
• 3–state buffer outputs sink 64mA and source 15mA
• Input diodes for termination effects
• 24–pin plastic slim DIP (300mil) package
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F657 is an octal transceiver featuring non–inverting
buffers with 3–state outputs and an 8–bit parity
generator/checker, and is intended for bus–oriented
applications. The buffers have a guaranteed current sinking
capability of 24mA at the A ports and 64mA at the B ports.
The transmit/receive (T/R) input determines the direction of
the data flow through the bidirectional transceivers.
Transmit (active high) enables data from A ports to B ports;
receive (active low) enables data from B ports to A ports.
The output enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
high.
The parity select (ODD/EVEN) input gives the user the option of
odd or even parity systems.
The parity (PARITY) pin is an output from the generator/checker
when transmitting from the port A to B (T/R = high) and an input
when receiving from port B to A port ( T/R = low).
When transmitting (T/R = high) the parity select (ODD/EVEN) input
is set, then the A port data is polled to determined the number of
high bits. The parity (PARITY) output then goes to the logic state
determined by the parity select (ODD/EVEN) setting and by the
number of high bits on port A.
For example, if the parity select (ODD/EVEN) is set low (even
parity), and the number of high bits on port A is odd, then the parity
(PARITY) output will be high, transmitting even parity. If the number
of high bits on port A is even, then the parity (PARITY) output will
be low, keeping even parity.
When in receive mode (T/R = low) the B port is polled to determine
the number of high bits. If parity select (ODD/EVEN) is low (even
parity) and the number of highs on port B is:
(1) odd and the parity (PARITY) input is high, then ERROR will be
high, significantly no error.
(2) even and the parity (PARITY) input is high, then ERROR will be
asserted low, indicating an error.
TYPE TYPICAL PROPAGA-
TION DELAY TYPICAL SUPPLY
CURRENT( TOTAL)
74F657 8.0ns 100mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION VCC = 5V ±10%, VCC = 5V ±10%, PKG DWG #
Tamb = 0°C to +70°C Tamb = –40°C to +85°C
24–pin plastic slim
DIP (300mil) N74F657N I74F657N SOT222-1
24–pin plastic SOL N74F657D I74F657D SOT137-1
24–pin plastic SSOP N74F657DB I74F657DB SOT340-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.)
HIGH/LOW LOAD VALUE
HIGH/LOW
A0 – A7 A ports 3–state inputs 3.5/0.117 70µA/70µA
B0 – B7 B ports 3–state inputs 3.5/0.117 70µA/70µA
PARITY Parity input 3.5/0.117 70µA/70µA
T/R T ransmit/receive input 2.0/0.066 40µA/40µA
ODD/EVEN Parity select input 1.0/0.033 20µA/20µA
OE Output enable input (active low) 2.0/0.066 40µA/40µA
A0 – A7 A ports 3–state outputs 150/40 3.0mA/24mA
B0 – B7 B ports 3–state outputs 750/106.7 15mA/64mA
PARITY Parity output 750/106.7 15mA/64mA
ERROR Error output 750/106.7 15mA/64mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
90 July 30 3
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
1312
10
11
9
8
7
6
5
4
3
2
1OE
ERROR
ODD/EVEN
T/R
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
VCC
A5
A6
A7
PARITY
GND
GND
SF00414
IEC/IEEE SYMBOL
2
1
G3
3 EN1/3G5 (REC)
N4
24
1
11 3 EN2 (XMIT)
2
3
4
5
6
8
9
10
23
22
21
20
17
16
15
14
2 k
4, 2
4, 1
13
512
Z11
11
18
.
.
.
SF00416
LOGIC SYMBOL
T/R
OE
B0 B1 B2 B3
ODD/EVEN
B4 B5 B6 B7
1
24
11
A0 A1 A2 A3 A4 A5 A6 A7
234568910
23 22 21 20 17 16 15 14
13
12
PARITY
VCC = Pin 7
GND = Pin 18, 19
ERROR
SF00415
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
90 July 30 4
LOGIC DIAGRAM
VCC = Pin 7,
GND = Pin 18, 19
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
PARITY
ERROR
ODD/EVEN
T/R
OE
2
3
4
5
6
8
9
10
23
22
21
20
17
16
15
14
1
24
13
12
11
SF00417
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
90 July 30 5
FUNCTION TABLE
NUMBER OF INPUTS THAT ARE HIGH INPUTS INPUT/OUTPUT OUTPUTS
OE T/R ODD/EVEN PARITY ERROR OUTPUTS MODE
0, 2, 4, 6, 8
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
L
H
L
H
L
H
L
Z
Z
H
L
L
H
Transmit
Transmit
Receive
Receive
Receive
Receive
1, 3, 5, 7
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
L
L
H
H
L
H
L
Z
Z
L
H
H
L
Transmit
Transmit
Receive
Receive
Receive
Receive
Don’t care H X X Z Z Z
Notes to function table
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. Z = High impedance ”’of f” state
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in high output state –0.5 to VCC V
IOUT Current applied to output in low output state A0 – A7 48 mA
B0 – B7, PARITY, ERROR 128 mA
Tamb Operating free air temperature range Commercial range 0 to +70 °C
Industrial range –40 to +85 °C
Tstg Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
MIN NOM MAX
VCC Supply voltage 4.5 5.0 5.5 V
VIH High–level input voltage 2.0 V
VIL Low–level input voltage 0.8 V
IIk Input clamp current –18 mA
IOH High–level output current A0 – A7 –3 mA
B0 – B7, PARITY, ERROR –15 mA
IOL Low–level output current A0 – A7 24 mA
B0 – B7, PARITY, ERROR 64 mA
Tamb Operating free air temperature range Commercial range 0 +70 °C
Industrial range –40 +85 °C
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
90 July 30 6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL PARAMETER TEST LIMITS UNIT
CONDITIONS1MIN TYP2MAX
All outputs IOH = –3mA4,5 ±10%VCC 2.4 V
VCC = MIN, ±5%VCC 2.7 V
VOH High-level output voltage B0 – B7, VIL = MAX, IOH = –12mA5±10%VCC 2.0 V
PARITY, VIH = MIN ±5%VCC 2.0 V
ERROR IOH = –15mA4±10%VCC 2.0 V
±5%VCC 2.0 V
A0 – A7 IOL = 24mA4,5 ±10%VCC 0.35 0.50 V
VCC = MIN, ±5%VCC 0.35 0.50 V
VOL Low-level output voltage B0 – B7, VIL = MAX, IOL = 48mA4±10%VCC 0.38 0.55 V
PARITY, VIH = MIN IOL = 48mA5±5%VCC 0.42 0.55 V
ERROR IOL = 64mA4±5%VCC 0.42 0.55 V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 -1.2 V
Input current at OE, T/R,
ODD/EVEN VCC = 0.0V, VI = 7.0V 100 µA
IImaximum input voltage A0 – A7 VCC = 5.5V, VI = 5.5V 2 mA
B0 – B7 1 mA
OOD/EVEN 204µA
IIH High–level input current VCC = MAX, VI = 2.7V 405µA
OE, T/R 404µA
805µA
IIL Low–level input current OOD/EVEN VCC = MAX, VI = 0.5V –20 µA
OE, T/R –40 µA
IOZH + IIH Off–state output current,
high–level voltage applied A0 – A7,
B0 – B7, VCC = MAX, VO = 2.7V 70 µA
IOZL + IIL Off–state output current,
low–level voltage applied PARITY VCC = MAX, VO = 0.5V –70 µA
IOZH Off–state output current,
High–level voltage applied ERROR VCC = MAX, VO = 2.7V 50 µA
IOZL Off–state output current,
low–level voltage applied VCC = MAX, VO = 0.5V –50 µA
IOS Short circuit output current3A0 – A7 VCC = MAX -60 -150 mA
B0 – B7 -100 -225 mA
ICCH 90 1254mA
90 1355mA
ICC Supply current (total) ICCL VCC = MAX 106 1504mA
106 1605mA
ICCZ 98 145 mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. For commercial range.
5. For industrial range.
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
90 July 30 7
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb = +25°CTamb = 0°C to +70°CTamb = –40°C to +85°C
SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 10% UNIT
CONDITION CL = 50pF,
RL = 500ΩCL = 50pF,
RL = 500ΩCL = 50pF,
RL = 500Ω
MIN TYP MAX MIN MAX MIN MAX
tPLH
tPHL Propagation delay
An to Bn or Bn to An W aveform 2 2.5
3.0 5.5
6.0 7.5
7.5 2.5
3.0 8.0
8.0 2.0
2.5 9.0
9.0 ns
tPLH
tPHL Propagation delay
An to PARITY Waveform 1, 2 7.0
7.0 10.0
10.0 14.0
15.0 7.0
7.0 16.0
16.0 5.5
6.5 16.5
19.0 ns
tPLH
tPHL Propagation delay
ODD/EVEN to PARITY,
ERROR W aveform 1, 2 4.5
4.5 7.5
8.0 11.0
11.5 4.5
4.5 12.0
12.5 3.5
4.0 13.0
15.5 ns
tPLH
tPHL Propagation delay
Bn to ERROR Waveform 1, 2 8.0
8.0 14.0
14.0 20.5
20.5 7.5
7.5 22.5
22.5 7.5
7.5 24.5
25.0 ns
tPLH
tPHL Propagation delay
PARITY to ERROR Waveform 1, 2 8.0
8.0 11.5
12.0 15.5
15.5 7.5
8.0 16.5
17.0 6.5
6.5 18.5
20.0 ns
tPZH
tPZL Output enable time1
to high or low level W aveform 3, 4 3.0
4.0 5.5
7.0 8.0
9.5 3.0
4.0 9.0
11.0 2.0
4.0 9.0
13.0 ns
tPHZ
tPLZ Output disable time
from high or low level W aveform 3, 4 2.0
2.0 4.5
4.0 7.5
6.0 2.0
2.0 8.0
6.5 1.0
1.0 8.0
7.5 ns
Note to AC electrical characteristics
1. These delay times reflect the 3-state recovery time only and not the signal through the buffers or the parity check circuitry. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry
(same as A to PARITY), and to the ERROR output. VALID data at the ERROR pin > (B to A) + (A to PARITY).
AC WAVEFORMS
VM
VMVM
VM
tPLH
tPHL
An, Bn,
ODD/EVEN,
PARITY
PARITY,
ERROR
SF00418
W aveform 1. Propagation delay for inverting outputs
VM
VMVM
VM
tPHL
tPLH
An, Bn,
PARITY,
ERROR
An, Bn,
ODD/EVEN,
PARITY
SF00420
W aveform 2. Propagation delay for non-Inverting outputs
VM
VM
VM
tPHZ
tPZH
OE
VOH -0.3V
0V
An, Bn,
PARITY,
ERROR
SF00419
Waveform 3. 3-state output enable time to high level and output
disable time from high level
VM
VM
VM
tPLZ
tPZL
OE
VOL +0.3V
3.5V
An, Bn,
PARITY,
ERROR
SF00421
Waveform 4. 3-state output enable time to low level and output
disable time from low level
Note to AC waveforms
1. For all waveforms, VM = 1.5V.
Philips Semiconductors Product specification
74F657Octal transceiver with 8-bit parity generator/checker
90 July 30 8
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Open Collector Outputs
DEFINITIONS:
RL= Load resistor;
see AC electrical characteristics for value.
CL= Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
RL
7.0V
SF00128
TEST SWITCH
tPLZ closed
tPZL closed
All other open
SWITCH POSITION
Philips Semiconductors Product specification
74F657
Octal transceiver with 8-bit parity generator/checker
1990 Jul 30 9
DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1
Philips Semiconductors Product specification
74F657
Octal transceiver with 8-bit parity generator/checker
1990 Jul 30 10
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
Philips Semiconductors Product specification
74F657
Octal transceiver with 8-bit parity generator/checker
1990 Jul 30 11
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
Philips Semiconductors Product specification
74F657
Octal transceiver with 8-bit parity generator/checker
yyyy mmm dd 12
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05171
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
