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FEATURES
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
VCC
2OE
S0
2B4
2B3
2B2
2B1
2A
DBQ, DGV, OR PW PACKAGE
(TOP VIEW) RGY PACKAGE
(TOP VIEW)
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
2OE
S0
2B4
2B3
2B2
2B1
S1
1B4
1B3
1B2
1B1
1A
1OE
2A V
GND
CC
DESCRIPTION/ORDERING INFORMATION
SN74CB3Q3253DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
•Data and Control Inputs Provide UndershootClamp Diodes•High-Bandwidth Data Path (up to 500 MHz
(1)
)
•Low Power Consumption (I
CC
= 0.6 mA Typ)•5-V Tolerant I/Os With Device Powered Up orPowered Down •V
CC
Operating Range From 2.3 V to 3.6 V•Low and Flat ON-State Resistance (r
on
)•Data I/Os Support 0- to 5-V Signal Levels (0.8Characteristics Over Operating Range V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)(r
on
= 4 ΩTyp)
•Control Inputs Can be Driven by TTL or•Rail-to-Rail Switching on Data I/O Ports 5-V/3.3-V CMOS Outputs– 0- to 5-V Switching With 3.3-V V
CC
•I
off
Supports Partial-Power-Down ModeOperation– 0- to 3.3-V Switching With 2.5-V V
CC
•Latch-Up Performance Exceeds 100 mA Per•Bidirectional Data Flow With Near-Zero
JESD 78, Class IIPropagation Delay
•ESD Performance Tested Per JESD 22•Low Input/Output Capacitance MinimizesLoading and Signal Distortion – 2000-V Human-Body Model (A114-B,(C
io(OFF)
= 3.5 pF Typ) Class II)•Fast Switching Frequency (f
OE
= 20 MHz Max) – 1000-V Charged-Device Model (C101)•Supports Both Digital and Analog(1) For additional information regarding the performance
Applications: USB Interface, Differentialcharacteristics of the CB3Q family, refer to the TI application
Signal Interface Bus Isolation, Low-Distortionreport CBT-C, CB3T, and CB3Q Signal-Switch Families,literature number SCDA008. Signal Gating
The SN74CB3Q3253 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage ofthe pass transistor, providing a low and flat ON-state resistance (r
on
). The low and flat ON-state resistance allowsfor minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The devicealso features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.Specifically designed to support high-bandwidth applications, the SN74CB3Q3253 provides an optimizedinterface solution ideally suited for broadband communications, networking, and data-intensive computingsystems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
SN74CB3Q3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
The SN74CB3Q3253 is organized as two 1-of-4 multiplexers/demultiplexers with separate output-enable(1 OE,2 OE) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE is low,the associated multiplexer/demultiplexer is enabled, and the A port is connected to the B port, allowingbidirectional data flow between ports. When OE is high, the associated multiplexer/demultiplexer is disabled, anda high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry prevents damagingcurrent backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Tape and reel SN74CB3Q3253RGYR BU253SSOP (QSOP) – DBQ Tape and reel SN74CB3Q3253DBQR BU253–40 °C to 85 °C Tube SN74CB3Q3253PWTSSOP – PW BU253Tape and reel SN74CB3Q3253PWRTVSOP – DGV Tape and reel SN74CB3Q3253DGVR BU253
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
FUNCTION TABLE(EACH MULTIPLEXER/DEMULTIPLEXER)
INPUTS INPUT/OUTPUT
FUNCTIONOE S1 S0 A
L L L B1 A port = B1 portL L H B2 A port = B2 portL H L B3 A port = B3 portL H H B4 A port = B4 portH X X Z Disconnect
2
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2B1
1B1
2A
1A
S0
S1
1OE
2OE
1B2
1B3
1B4
2B2
2B3
2B4
SW
SW
SW
SW
SW
SW
SW
SW
7
9
14
2
1
15
6
5
4
3
10
11
12
13
A
EN(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
VCC
SN74CB3Q3253DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
3
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN74CB3Q3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 4.6 VV
IN
Control input voltage range
(2) (3)
–0.5 7 VV
I/O
Switch I/O voltage range
(2) (3) (4)
–0.5 7 VI
IK
Control input clamp current V
IN
< 0 –50 mAI
I/OK
I/O port clamp current V
I/O
< 0 –50 mAI
I/O
ON-state switch current
(5)
±64 mAContinuous current through V
CC
or GND ±100 mADBQ package
(6)
90DGV package
(6)
120θ
JA
Package thermal impedance °C/WPW package
(6)
108RGY package
(7)
39T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to ground, unless otherwise specified.(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(4) V
I
and V
O
are used to denote specific conditions for V
I/O
.(5) I
I
and I
O
are used to denote specific conditions for I
I/O
.(6) The package thermal impedance is calculated in accordance with JESD 51-7.(7) The package thermal impedance is calculated in accordance with JESD 51-5.
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 VV
CC
= 2.3 V to 2.7 V 1.7 5.5V
IH
High-level control input voltage VV
CC
= 2.7 V to 3.6 V 2 5.5V
CC
= 2.3 V to 2.7 V 0 0.7V
IL
Low-level control input voltage VV
CC
= 2.7 V to 3.6 V 0 0.8V
I/O
Data input/output voltage 0 5.5 VT
A
Operating free-air temperature –40 85 °C
(1) All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Electrical Characteristics
(1)
Switching Characteristics
SN74CB3Q3253DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(2)
MAX UNIT
V
IK
V
CC
= 3.6 V, I
I
= –18 mA –1.8 VI
IN
Control inputs V
CC
= 3.6 V, V
IN
= 0 to 5.5 V ±1µAV
O
= 0 to 5.5 V, Switch OFF,I
OZ
(3)
V
CC
= 3.6 V, ±1µAV
I
= 0, V
IN
= V
CC
or GNDI
off
V
CC
= 0, V
O
= 0 to 5.5 V, V
I
= 0 1 µAI
I/O
= 0,I
CC
V
CC
= 3.6 V, V
IN
= V
CC
or GND 0.6 2 mASwitch ON or OFF,∆I
CC
(4)
Control inputs V
CC
= 3.6 V, One input at 3 V, Other inputs at V
CC
or GND 30 µAV
CC
= 3.6 V, A and B ports open, OE input 0.15 0.16
mA/I
CCD
(5)
Per control input
MHzControl input switching at 50% duty cycle S input 0.04 0.05C
in
Control inputs V
CC
= 3.3 V, V
IN
= 5.5 V, 3.3 V, or 0 2.5 3.5 pFSwitch OFF,A port V
CC
= 3.3 V, V
I/O
= 5.5 V, 3.3 V, or 0 8 11 pFV
IN
= V
CC
or GND,C
io(OFF)
Switch OFF,B port V
CC
= 3.3 V, V
I/O
= 5.5 V, 3.3 V, or 0 3.5 4.5 pFV
IN
= V
CC
or GND,Switch ON,C
io(ON)
V
CC
= 3.3 V, V
I/O
= 5.5 V, 3.3 V, or 0 13 17 pFV
IN
= V
CC
or GND,V
I
= 0, I
O
= 30 mA 4 10V
CC
= 2.3 V,TYP at V
CC
= 2.5 V
V
I
= 1.7 V, I
O
= –15 mA 4.5 11r
on
(6)
ΩV
I
= 0, I
O
= 30 mA 3.5 8V
CC
= 3 V
V
I
= 2.4 V, I
O
= –15 mA 4 10
(1) V
IN
and I
IN
refer to control inputs. V
I
, V
O
, I
I
, and I
O
refer to data pins.(2) All typical values are at V
CC
= 3.3 V (unless otherwise noted), T
A
= 25 °C.(3) For I/O ports, the parameter I
OZ
includes the input leakage current.(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC
or GND.(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (seeFigure 2 ).(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance isdetermined by the lower of the voltages of the two (A or B) terminals.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 )
V
CC
= 2.5 V V
CC
= 3.3 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX
f
OE
or f
S
(1)
OE or S A or B 10 20 MHzt
pd
(2)
A or B B or A 0.12 0.18 nst
pd(s)
S A 1.5 6.7 1.5 5.9 nsS B 1.5 6.7 1.5 5.9t
en
nsOE A or B 1.5 6.7 1.5 5.9S B 1 6.1 1 6.1t
dis
nsOE A or B 1 6.1 1 6.1
(1) Maximum switching frequency for control input (V
O
> V
CC
, V
I
= 5 V, R
L
≥1 M Ω, C
L
= 0).(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified loadcapacitance, when driven by an ideal voltage source (zero output impedance).
5
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0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VI − V
TYPICAL ron
vs
VI
VCC = 3.3 V
TA = 25°C
IO = −15 mA
ron − ON-State Resistance −
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14 16 18 20
OE or S Switching Frequency − MHz
TYPICAL ICC
vs
CONTROL INPUT SWITCHING FREQUENCY
CC
I− mA
VCC = 3.3 V
TA = 25°C
A and B ports Open
One S Switching
One OE Switching
SN74CB3Q3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
Figure 1. Typical r
on
vs V
I
, V
CC
= 3.3 V and I
O
= –15 mA
Figure 2. Typical I
CC
vs OE or S Switching Frequency, V
CC
= 3.3 V
6
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PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1 2 × VCC
Open
GND
RL
RL
tPLH tPHL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOH
VOL
0 V
VOL + V∆
VOH − V∆
0 V
Output
Control
(VIN)
VCC
VCC
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES (tpd(s))VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50 Ω
VG1
VCC
DUT
50 Ω
VIN
50 Ω
VG2 50 Ω
VI
TEST RL
S1 V∆
CL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
VCC VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
2 × VCC
2 × VCC
GND
GND
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
VCC or GND
VCC or GND
GND
GND
VCC
VCC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2 VCC/2
VCC/2
VO
SN74CB3Q3253DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS145A – OCTOBER 2003 – REVISED MARCH 2005
Figure 3. Test Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74CB3Q3253DBQRE4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
74CB3Q3253DBQRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
74CB3Q3253DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74CB3Q3253DGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74CB3Q3253RGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74CB3Q3253DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74CB3Q3253DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CB3Q3253RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74CB3Q3253DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74CB3Q3253PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74CB3Q3253RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74CB3Q3253DGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74CB3Q3253PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74CB3Q3253RGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
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