Packaging Trends for Mobile Application Morihiro Kada Abstract The advent of the CSP has heralded a new paradigm in semiconductor packaging technology. Previously overshadowed by IC chips, packaging technology has begun to take center stage as a key factor in product competitiveness. Packaging technology will develop into 3D packages, and will create a new era as the core system integration technology. It will lead the electronics industry in the coming 21st century. 1. Introduction The ongoing Information Technology (IT) revolution is transforming our lives dramatically. Digital information networks is beginning to be seen as a key for shaping the industrial and consumption patterns of the early 21st century. Underpinning this new network society is the semiconductor industry, whose market is already changing rapidly. In 1999, the debates on how to boost demand shifted to how to provide customers with products that meet their satisfaction. Large-scale investment to increase production has been well publicized. These developments are occurring due to the rapid expansion of the digital electronic equipment market, for products ranging from PCs to mobile phones. Mobile phones have grown dramatically on a global scale. Production volume in 1999 greatly exceeded expectations, reportedly reaching 280 million units. The number of mobile phone subscribers is projected to reach one billion units in 2003. The mobile phone is likely to emerge as the key product shaping the digital information network society in the early 21st century. The annual demand for mobile phones greatly exceeds that for PCs of 100 million units. As mobile phones expand in terms of sales as well as functions, the electronic components they incorporate will become increasingly sophisticated. Applications are changing from voice-centered to data communication, and the Internet-compatible handheld terminals will exceed PCs in the coming few years. Data emphasis will shift from text to images, and then to color displays and moving images. Instead of mere telephones, mobile phones are becoming sophisticated personal information terminals. Stationary telephones in Japan, which have been established over 100 years, are rapidly being overshadowed by the explosive growth of mobile phones. This is truly a revolution in communications culture. This change has lead to further pressure on the supply of electronic components, especially the state-of-the-art processes required for semiconductor components. As a result, companies have been investing more on plant and equipment. In the medium term, this will not be a transient phenomenon, but the pattern of the advancing digital information network society. Individuals, households and society in general will become seamlessly linked by communications technologies. This is being facilitated by equipment incorporating electronic components such as semiconductors, liquid crystals displays and mobile electronic information devices. 2. The new paradigm in semiconductor package technology Over the past few decades, electronic equipment development has been driven by miniaturization based on the semiconductor wafer process--a trend that will continue in the future. However, for future miniaturization, engineers are now highlighting numerous technical problems concerning design, cost and performance which will need to be solved. Furthermore, even bestselling products like mobile phones and PCs are not highly competitive simply due to electronics. Rather, they must provide all the elements to satisfy constantly diversifying personal and social trends. Appealing to individual tastes and offering products to which people respond emotionally depends not only on the product's basic function but also on design factors such as form, size, weight and color. In Japan, these trends are typified by products like pearl-white mobile phones, and the Apple iMacTM and Sony VaioTM computers. With mobile equipment, size and weight become critical. The Chip Size Packages (CSPs) have undoubtedly made mobile phones smaller and lighter. Mobile phones contain many components like the CSP, which is a semiconductor package. However, I am convinced that CSPs have lead the way toward lighter and more compact mobile phones and contributed to their worldwide dissemination. If mobile phones remained heavy, black and cumbersome, they would never have become the youth fashion accessory that they are today. 2.1 The paradigm shift in design The CSP has led to a new paradigm in semiconductor packaging technology. We need to consider the relationship between package design, chip design and electronic equipment design. Conventional package design was realized with little if any interaction between the IC chip and electronic equipment designers. In addition, the chip designer and the electronic equipment designer knew nothing about packages, and had even less interest in them. CSPs, however, blur the boundaries between chips and packages, and package and electronic equipment design. This makes it impossible to design chips, packages and electronic equipment without taking into account their strong interrelationships. This is especially relevant for highly competitive products like mobile phones in which design is critical. Consequently, the barriers between chip design, package design and equipment design have been reduced, and integration has advanced. This situation is shown in Fig. 1. electronic equipment mounting. In order to fill the gap and cope with future advances in miniaturization, the wafer process must be integrated with the electronic equipment mounting, based on the package. Wafer-level CSPs are already available, and by integrating the semiconductor wafer process and package process, will fundamentally alter the industry's future. These changes are already underway. The downstream impact is the integration of the semiconductor package with substrate technology. Previously, there was no intersection between PCB technology and package technology. An order of magnitude difference stood in the way--a barrier that was not easily overcome. The typically conservative PCB industry, which has continued custom production, was motivated by trends in the semiconductor package industry, and finally began to overcome their inertia. Classic examples were the polyimide tape board and the built-up PCB. These have become used in place of conventional printed circuit boards as the package materials for PC CPU chips and CSPs and for metal lead frames. These are shown in Fig. 2. In board mounting technology, progress was made in achieving the greater density and higher quality required for mounting CSPs, the reliability of which is dependent on the board quality. In the past Wafer Process Package Board Level Mounting Today In the past Chip Wafer Package Board Level Process=CSP Mounting Package System Today Package System =CSP Chip Fig. 2: New paradigm in manufacturing Critical element of chips and system Fig. 1: New paradigm in design 2.2 The new paradigm in manufacturing The advent of the CSP has also caused a revolution in manufacturing processes, specifically, the integration of the package and wafer process. Between the wafer and package process, there is at least two orders of magnitude in the scale of interconnections, with a single order of magnitude between the package and 3. CSPs as system package The CSP has also accelerated the systemization concept. In systemization, there is a debate between SOC (System on Chip) and SOP (System on Package). Previously, the term MCP (Multi Chip Package) was common. However, this did not fully express the system concept as it simply indicated a package composition in which multiple electronic components like Si chips were housed in a single package. SOP is an entirely different concept. Electronic equipment constantly undergoes cycles of alternate expansion and stabilization of function. In my opinion, systemization discussion will be impossible without the concept of the expansion and stabilization of electronic equipment functions. For example, the electronic calculator has evolved with a basically fixed function, and has incorporated SOCs. Conversely, the PC is still developing, so it has not incorporated SOCs. As long as its function continues to expand, the product will be based not on an SOC, but with an SOB (System on Board). The same currently applies to mobile phones. However, when a certain degree of functional stabilization begins, the equipment's functional components first become SOPs, then SOCs. This process is also related to the size of the product's system. This is shown in Fig. 3. Expansion of Function Large System(Ex. PC) SSOC SSOC SOB SOB SSOP SSOC SOB SSOC:SubSSOC:Sub-System on Chip SSOP:SubSSOP:Sub-System on Package SSOC SSOC SOB SOP In the past SOC Today Development trends Wafer level CSP>Cost reduction High performance>for Adv.DRAM Stacking>for System Integration or High density memory Stacked Package Wafer level>Future technology Chip level>Extend current technology Package level>Current technology SSOP Stabilization of Function Small System(Ex. Calculator) 12 3 456 78 9 0 can be combined. However, progress in combining logic devices will also continue. Furthermore, the remaining passive components will be almost certainly be incorporated as package materials, and IC peripheral circuits will become a single package module incorporating a 3D-stacked IC. Fig. 4 shows current development trends for both CSPs, which have had a significant historical impact on the development of package technology, and 3D-stacked package technology. Fig. 4: Development trends in CSPs and 3Dstacked packages SOC In the future Fig. 3: CSPs as system package Recently, stacked CSP technology used for 3D-mounting packages for systems, has attracted attention as an SOP technique. For mobile phones, progress has been made toward the mass production of flash memory and SRAM combination memory. This type of memory is used for baseband processor programs and phone number lists in mobile phones. This has contributed to greater compactness and lighter weight, and led de facto standardization. Japan has emerged as a leader in this area, with the technology spreading subsequently to Europe and the USA. A time lag of about one year is required for each step of this dissemination process. Japanese package technology is becoming the world's de facto standard technology. Sharp is a leader in this area, and has played a leading role in the system package area. However, such massive global adoption was not predicted during its original development. Stacked CSP technology is still in its infancy, and memory/memory combinations are still flawed from the system standpoint. Limitations also exist in the ways in which they 4. 3D-stacked package technology Previously, 3D package technology has been developed for military purposes and other high-end applications. However, development aimed at low-cost, high production volume for civilian applications is beginning in Japan, as explained below. This development is occurring as follows. In 1999, 3D-stacked package technology began to divide into package-stacked, chip-stacked and wafer-stacked technologies. In engineering terms, package-stacked is comparatively easy, although it is hard to create a CSP. Wafer-stacked is the most technically complex, and commercialization is not expected for some time. Chip-stacked is an extension of current technology. Despite being an intermediate technology, conversion to CSP is possible, so it is currently the most suitable candidate for achieving combination memory in mobile phones. Clearly, the time is a critical factor for the success of any given technology. For package-stacked, multi-level stacking has been reportedly employed to successfully construct high-capacity memory. The characteristics of each type of stacked technology are shown in Fig. 5. Wafer Wafer level level Chip Chip level level Package Package level level Integration density Electrical performance Process easiness Design, TTM, Flexibility Fig. 5: Characteristics of stacked package technology Source:Toshiba 2Chips 3Chips Package Stacking Chip Stacking Although multi-level stacking is required to achieve comparatively large systemization and high-capacity memory, this is certainly not an easy goal. Many problems exist, including: *Final test yield and burn-in, and KGD (Known Good Die) issues * Interconnectability between chips, and electrical characteristics * Ease of testing *Package thickness. Fig. 6 shows a summary of the chipstacked and package-stacked approaches. >4Chips Fig. 6: Summary of chip-stacked and packagestacked approaches If the aim is miniaturization, stacking chips to their upper limit is ideal, although the maximum is probably four levels. For three and four levels, chip-stacked must be differentiated from package-stacked, whereas for five or more levels, package-stacked seems to be the first option. 5. Silicon chip mounting efficiency The bare chip is considered by many to 240 220 Silicon chip mounting Efficiency(%) Source:Toshiba be the ultimate high-density mounting system. Wafer-level CSPs are also attracting attention because they help to realize real chip size. However, in terms of high-density mounting, stacked CSPs are superior to wafer-level CSPs and bare chip mounting. If silicon chip mounting efficiency is assumed to be 100%, then bare chip mounting will never exceed this figure. The upper limit for ordinary CSPs is about 80%. However, stacked CSPs can exceed 100%, even rising to 200-300% which is another advantage. Fig. 7 shows the silicon chip mounting efficiency of various package types. This expresses the ratio of mounting area in an SOP system to that in an SOC system. In a stacked CSP, the wafer is very thin, and can then be stacked in a number of layers. In fact, various constraints exist with limits on the number of layers, However the level required by the market is achievable. The conventional evolution of the IC wafer process has strictly limited its application to two dimensions. Stacked technology, however, has paved the way to 3D integration, which is highly significant. 200 180 Triple-chip Stacked CSP 160 140 120 100 Stacked CSP Bare Bare Chip Chip Stacked TSOP/QFP 80 WLP WLP CSP Area Area Array Array Package Package 60 40 TSOP/QFP Peripheral Peripheral Package Package `94 `95 20 Silicon Chip Mounting Efficiency =Si Area / Package Area `96 `97 `98 `99 `00 Fig. 7: Silicon chip mounting efficiency for various types of package 6. The emergence and future development of stacked CSP How was the stacked CSP originally developed, and what does its future hold? In 1996, Sharp developed and began mass-producing highly versatile face-up CSPs employing a polyimide tape substrate, wire bonding and transfer mold technology. Although not a true chip-size package, it was a compact package with a chip size with only a 1.0 mm-excess of its size, supporting both terminal fan-in and fan-out. Sharp deployed this technology in a line of standard square packages, ranging from 6 mm square to 16 mm square in 2 mm steps. To ensure ease of use and miniaturization, a 0.8 mm terminal pitch was used to comply with the EIAJ's 20% terminal pitch reduction, resulting in a line up ranging from 32 to 280 pins. Conversely, for memory devices, Sharp developed packages that are compatible with nextgeneration flash memory and SRAM packages for mobile phones. These were rectangular packages fabricated in 1 mm increments, and were favorable received by numerous customers. In 1999, Sharp developed and massproduced high-pin-count CSPs (maximum 408 pins) with a 0.5 mm pitch for logic applications. The above package development history can thus be linked to the development of the stacked CSP technology. As noted in Section 3, almost all mobile phone manufacturers now use flash memory and SRAM. In contrast with systems which are growing larger, these manufacturers are struggling to meet strong market demand for greater miniaturization and lighter weight. In response to constant requests to reduce component size, Sharp has developed a stacked CSP/flash SRAM combination memory containing two chips in a single CSP. Subsequently, requirements from mobile phone manufacturers grew dramatically. In Japan, the basic functional specifications for mobile phones are controlled by communications vendors called carriers. This means that the miniaturization, light weight and design of mobile phones are decisive factors influencing sales demand. Systems continue to expand with new features like e-mail, Internet connectivity and color displays. However, mobile phone manufacturers remain keen to reduce weight further even slightly, while maintaining the mobile phone appearance that is so popular with users. This is consistent with the development of three-chip stacked CSPs. Next-generation mobile phones, which will be launched in Japan in Spring 2001, will have a huge scale compared with current systems. CSPs hold the key to the high-density mounting which permits greater miniaturization and lighter weight. How many CSPs can be used to realize the next-generation high-performance mobile phone? The industry will not wait for the wafer process to evolve sufficiently to be used to construct systems with fewer packages. Stacked CSPs will respond to these requirements. Fig. 8 shows examples of the development period for SOC (for realizing a system with silicon chips) and SOP (for realizing a package-based system). Systems will move from two to three chips, then on to the next step. The importance of stacked CSP technology could be likened to pizza delivery: it is essential that what you have ordered is supplied within a minimum period. Chip level stacking in a CSP System on a chip Several months ~1year Memory/ 0 month Memory Logic/ 1~2 months Memory (PLD <1month) or Logic Several months ~1year Excluding evaluation and manufacturing time Fig. 8: Development period for SOP and SOC 7. Triple-chip stacked CSP (Stacked system integration package) The basic structure of Sharp's triple-chip stacked CSP is similar to that of single-chip CSP or double-chip stacked CSP. The package structure employs wire bonding and transfer mold technology on a polyimide substrate. The chip thickness is ground to 150 m in order to maintain a maximum package height of 1.4 mm, which is the same as that of double-chip stacked CSPs. The key technologies involved are the handling of the thin wafers, chip-layer die bonding and three-layer wire bonding. Fig. 9 shows the structure of a triple-chip stacked CSP. Gold Wire Insulator Mold 3rd Chip(150 mt) 0.8mm 2nd Chip(150 mt) 1.4mm Max. (1.25mm Typ.) 1st Chip(150 mt) 0.45mm 0.8mm-P Tape Substrate Gold wire 3rd chip 2nd chip 1st chip Polyimide tape Fig. 9: Structure of Triple-chip CSP Sharp has successfully developed a method for reliable and rapid realization of new products, while refining conventional technologies. Needless to say, if chip thickness is ground to 100 m, a triple-chip CSP measuring a maximum of 1.2 mm could be achieved. The first stage of conversion to massproduction is combination memory (flash memory and SRAM). However, Sharp is also researching the stacking of logic devices and memory. Fig. 10 shows an example of systemization for a mobile phone. In Sharp, this kind of stacked CSP is known as an SSIP (Stacked System Integration Package). Stacked System Integration Package Current 4M SR AM C P U C ore ASIC 32M Flash M em ory 32M Flash M em ory C P U C ore ASIC 4M SR AM 4M SR AM 32M Flash M em ory 4M S R AM 16M Flash M em ory 16M Flash M em ory 32M Flash M em ory Fig. 10: Example system integration of devices for mobile phones 8. Standardization trends in stacked CSP flash/SRAM combination memory Flash memory and SRAM combination memory has become the leading device in stacked CSPs. In 1998, when Sharp was conducting development and mass-production conversion of stacked CSP/Flash-SRAM combination memory, Fujitsu and others were shipping a single-package combination memory called MCP, in which two chips were lined up side by side. We did not feel that creating horizontally arranged combination memory was worthwhile, believing instead that mobile phone manufacturers required a CSP containing an SRAM of the same size as a flash memory package. After Sharp perfected the stacked CSP, it was readily adopted by Japanese mobile phone manufacturers. However, memory is a commodity. If no alternative source exists, a global market such as that for mobile phones cannot emerge. This was the biggest issue at the time of development. A conflict existed between the originality of the technology and device standardization. In conjunction with Mitsubishi Electric and Hitachi, Sharp decided to standardize combination memory. Simultaneously, Fujitsu, together with NEC and Toshiba, proposed flash/SRAM combination memory using a stacked CSP with a different standard (called S-MCP), and the industry split into two segments. Subsequently, Intel joined the Sharp group while AMD joined the Fujitsu group. The battleground shifted to the USA, and standardization was debated in JEDEC. In the end, both standards were adopted by JEDEC. However, both camps are essentially enlisting the aid of the Multi-Standard for Current Flash Sharp/Mitsubishi/Hitachi A:x8/x16 F + x8 S B:x16 F + x16 S C:x8/x16 switchable* USA and have obtained the imprimatur of JEDEC, showing the difficulty of standardization in the advanced technology field. Fig. 11 summarizes the JEDEC standards. + Fujitsu/NEC/Toshiba D:x8/x16 switchable * C: Memory density>=64M Flash+8MSRAM Fig. 11: Summary of JEDEC standards for stacked CSP/Flash-SRAM combination memory 9. Conclusion IC design, the wafer process and equipment design/mounting have become integrated centering on the package technology. I feel this represents a new paradigm in package technology, and the CSP has led this shift. At the same time, CSPs are opening up a new era of 3D packages. The significance of this is that a new fourth wave is at hand, being the next phase in a 10-year package development cycle which began in the 1970s. 1970s: Through-hole type packages era 1980s: Surface-mount type packages era 1990s: BGA/CSP era 2000s: 3D packages era In the future, package technology will no longer be a technologically subordinate to the system, and will be acknowledged as a leading technology. I wish to reiterate that no attractive next-generation products can exist without package technology. References [] M. Kada, Stacked CSP / A Solution for System LSI, Chip Scale International 1999 [] M. Kada, L. Smith, Advancements in Stacked Chip Scale Packaging (S-CSP), Pan Pacific Microelectronics Symposium 2000 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. 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