CY7C1049G
CY7C1049GE
4-Mbit (512K words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-95412 Rev. *F Revised April 3, 2018
4-Mbit (512K wo rds × 8-bit) Static RAM with Error -Correcting C ode (ECC)
Features
■High speed
❐tAA = 10 ns
■Embedded ECC for single-bit error correction[1, 2]
■Low active and standby currents
❐Active current: ICC = 38 mA typical
❐Standby current: ISB2 = 6 mA typical
■Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■1.0-V data retention
■TTL-compatible inputs and outputs
■Error indication (ERR) pin to indicate 1-bit error detection and
correction
■Pb-free 36-pin SOJ and 44-pin TSOP II packages
Functional Description
CY7C1049G and CY7C1049GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both devices are
offered in single and dual chip-enable options and in multiple pin
configurations. The CY7C1049GE device includes an ERR pin
that signals an error-detection and correction event during a read
cycle.
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O7 and address on A0 through A18 pins.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O7).
All I/Os (I/O0 through I/O7) are placed in a high-impedance state
during the following events:
■The device is deselected (CE HIGH)
■The control signal OE is de-asserted
On the CY7C1049GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)[1]. See the Truth
Table on page 14 for a complete description of read and write
modes.
The logic block diagram is on page 2.
Product Portfolio
Product[3] Features and Options (see Pin
Configurations on page 4)Range VCC Range
(V)
Speed
(ns)
10/15
Power Dissipation
Operating ICC,
(mA) Standby, ISB2
(mA)
f = fmax
Typ[4] Max Typ[4] Max
CY7C1049G(E)18 Single or Dual Chip Enables
Optional ERR pins
Industrial 1.65 V–2.2 V 15 – 40 6 8
CY7C1049G(E)30 2.2 V–3.6 V 10 38 45
CY7C1049G(E) 4.5 V–5.5 V 10 38 45
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 or details.
3. The ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 15 for details.
4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 2 of 19
Logic Block Diagram – CY7C1049G
512Kx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
A18
ECCENCODER DATAIN
DRIVERS
I/O0‐I/O7
WE
OE
CE
Logic Block Diagram – CY7C1049GE
512Kx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
A18
ECCENCODER DATAIN
DRIVERS
I/O0‐I/O7
WE
OE CE
ERR
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 3 of 19
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
AC Switching Characteristics ......................................... 9
Switching Waveforms .................................................... 10
Truth Table ...................................................................... 14
ERR Output – CY7C1049GE .......................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 4 of 19
Pin Configurations
Figure 1. 36-pin SOJ pinout, Single Chip Enable without ERR - CY7C1049G [5]
SOJ
A18A1235
A17A2334
A16A3433
I/O7I/O0730
OE
631
CE
GNDVCC 928
VCCGND 10 27
I/O5I/O211 26
I/O4I/O312 25
A14
WE 13 24
A13
A514 23
A12
A615 22
A11
A716 21
A10
A817 20
NCA918 19
NCA0136
I/O6I/O1829
A15A4532
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Document Number: 001-95412 Rev. *F Page 5 of 19
Figure 2. 44-pin TSOP II pinout, Single Chip Enable without ERR - CY7C1049G [6]
Figure 3. 44-pin TSOP II pinout, Single Chip Enable with ERR - CY7C1049GE [6, 7]
Pin Configurations (continued)
NCNC 243
NCA0 342
A18A1 441
A15A4 738
A16
639
A3
I/O7I/O0 936
I/O6I/O1 10 35
VSSVCC 11 34
VCCVSS 12 33
I/O5
I/O2 13 32
I/O4
I/O3 14 31
A14
/WE 15 30
A13
A5 16 29
A12A6 17 28
A11A7 18 27
A10A8 19 26
NCA9 20 25
NC
NC 21 24
NC 22 23
NCNC 144
/OE/CE 837
A17A2 540
NC
44-pin TSOP II
NCNC 243
NCA0 342
A18A1 441
A15A4 738
A16
639
A3
I/O7I/O0 936
I/O6I/O1 10 35
VSSVCC 11 34
VCCVSS 12 33
I/O5
I/O2 13 32
I/O4
I/O3 14 31
A14
/WE 15 30
A13
A5 16 29
A12A6 17 28
A11A7 18 27
A10A8 19 26
NCA9 20 25
ERR
NC 21 24
NC 22 23
NCNC 144
/OE/CE 837
A17A2 540
NC
44-pin TSOP II
Notes
6. NC pins are not connected internally to the die.
7. ERR is an output pin.
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CY7C1049GE
Document Number: 001-95412 Rev. *F Page 6 of 19
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND [8] ..................... –0.5 to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [8] ................................... –0.5 V to VCC + 0.5 V
DC input voltage [8].............................. –0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade Ambient Temperature VCC
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 10 ns / 15 ns Unit
Min Typ [9] Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – –
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – –
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1mA VCC – 0.5[10] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4
VIH Input HIGH
voltage
1.65 V to 2.2 V – 1.4 – VCC + 0.2[8] V
2.2 V to 2.7 V – 2 – VCC + 0.3[8]
2.7 V to 3.6 V – 2 – VCC + 0.3[8]
4.5 V to 5.5 V – 2 – VCC + 0.5[8]
VIL Input LOW
voltage
1.65 V to 2.2 V – –0.2[8] –0.4V
2.2 V to 2.7 V – –0.3[8] –0.6
2.7 V to 3.6 V – –0.3[8] –0.8
4.5 V to 5.5 V – –0.5[8] –0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC Operating supply current Max VCC, IOUT = 0 mA,
CMOS levels
f = 100 MHz – 38 45 mA
f = 66.7 MHz – – 40
ISB1 Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
––15mA
ISB2 Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–68mA
Notes
8. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC =3V (for V
CC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
10. This parameter is guaranteed by design and not tested.
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 7 of 19
Capacitance
Parameter [11] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
CIN Input capacitance TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
10 10 pF
COUT I/O capacitance 10 10 pF
Thermal Resistance
Parameter [11] Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52 68.85 C/W
JC Thermal resistance
(junction to case)
31.48 15.97 C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms [12]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
jig and
scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
VTH 0.9 1.5 1.5 V
VHIGH 1.8 3 3 V
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 8 of 19
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 1 – V
ICCDR Data retention current VCC = 1.2 V, CE > VCC – 0.2 V[14],
VIN > VCC – 0.2 V, or VIN < 0.2 V
–8mA
tCDR[13] Chip deselect to data retention
time
0–ns
tR[13, 14] Operation recovery time VCC > 2.2 V 10 – ns
VCC < 2.2 V 15 – ns
Data Retention Waveform
Figure 5. Data Retention Waveform[14]
tCDR tR
VDR = 1.0 V
DATA RETENTION MODE
VCC(min) VCC(min)
VCC
CE
Notes
13. These parameters are guaranteed by design.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
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Document Number: 001-95412 Rev. *F Page 9 of 19
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [15] Description 10 ns 15 ns Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 10 – 15 – ns
tAA Address to data / ERR valid – 10 – 15 ns
tOHA Data / ERR hold from address change 3 – 3 – ns
tACE CE LOW to data / ERR valid – 10 – 15 ns
tDOE OE LOW to data / ERR valid – 4.5 – 8 ns
tLZOE OE LOW to low impedance[16] 0–0–ns
tHZOE OE HIGH to HI-Z[16] –5–8ns
tLZCE CE LOW to low impedance[16] 3–3–ns
tHZCE CE HIGH to HI-Z[16] –5–8ns
tPU CE LOW to power-up[17, 18] 0–0–ns
tPD CE HIGH to power-down[17, 18] –10–15ns
Write Cycle [18, 19]
tWC Write cycle time 10 – 15 – ns
tSCE CE LOW to write end 7 – 12 – ns
tAW Address setup to write end 7 – 12 – ns
tHA Address hold from write end 0–0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7 – 12 – ns
tSD Data setup to write end 5 – 8 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to low impedance[16] 3–3–ns
tHZWE WE LOW to HI-Z[16] –5–8ns
Notes
15. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
le ve l s o f 0 t o 3 V (fo r VCC > 3 V) and 0 to VCC (f or V CC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 4 on page 7, unless specified otherwise.
16. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 4 on page 7. Transition is measured 200 mV from steady state
voltage.
17. These parameters are guaranteed by design and are not tested.
18. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tDS and tHZWE.
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 10 of 19
Switching Waveforms
Figure 6. Read Cycle No. 1 of CY7C1049G (Address Transition Controlled) [20, 21]
Figure 7. Read Cycle No. 1 of CY7C1049GE (Address Transition Controlled) [20, 21]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ERR PREVIOUS ERR VALID ERR VALID
tOHA
tAA
Notes
20. The device is continuously selected, OE = VIL, CE = VIL.
21. WE is HIGH for the read cycle.
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Document Number: 001-95412 Rev. *F Page 11 of 19
Figure 8. Read Cycle No. 2 (OE Controlled) [22, 23]
Switching Waveforms (continued)
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IMPEDANCE DATAOUT
VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
DATA I /O
tHZOE
tHZBE
SUPPLY
CURRENT
VCC
ISB
Notes
22. WE is HIGH for the read cycle.
23. Address valid prior to or coincident with CE LOW transition.
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Document Number: 001-95412 Rev. *F Page 12 of 19
Figure 9. Write Cycle No. 1 (CE Controlled) [24, 25]
Figure 10. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPW E
tHA
tBW
tHD
tHZOE tSD
DATA
IN VALID
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE /
BLE
tAW tHA
tSA tPWE
tLZW E
tHZWE
WE
DATA IN VALID
Notes
24. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
25. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
26. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
CY7C1049G
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Document Number: 001-95412 Rev. *F Page 13 of 19
Figure 11. Write Cycle No. 3 (WE Controlled) [27, 28, 29]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATA IN VALID
tBW
NOTE 30
CE1
ADDRESS
CE2
WE
DATA I/O
OE
BHE/BLE
Notes
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
28. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
29. Data I/O is high impedance if OE = VIH.
30. During this period the I/Os are in output state. Do not apply input signals.
CY7C1049G
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Document Number: 001-95412 Rev. *F Page 14 of 19
Truth Table
CE OE WE I/O0–I/O7Mode Power
HX
[31] X[31] HI-Z Power down Standby (ISB)
L L H Data out Read all bits Active (ICC)
L X L Data in Write all bits Active (ICC)
L H H HI-Z Selected, outputs disabled Active (ICC)
ERR Output – CY7C1049GE
Output [32] Mode
0 Read operation, no single-bit error in the stored data.
1 Read operation, single-bit error detected and corrected.
HI-Z Device deselected or outputs disabled or Write operation.
Notes
31. The input voltage levels on these pins should be either at VIH or VIL.
32. ERR pin is an output pin. It should be left floating when not used.
CY7C1049G
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Document Number: 001-95412 Rev. *F Page 15 of 19
Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram Package Type (all Pb-free) Operating
Range
10 2.2 V–3.6 V CY7C1049G30-10VXI 51-85090 36-pin Molded SOJ Industrial
CY7C1049G30-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel
CY7C1049GE30-10ZSXI 51-85087 44-pin TSOP II, ERR output
CY7C1049GE30-10ZSXIT 51-85087 44-pin TSOP II, ERR output, Tape and Reel
CY7C1049G30-10ZSXI 51-85087 44-pin TSOP II
CY7C1049G30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
15 1.65 V–2.2 V CY7C1049G18-15ZSXI 51-85087 44-pin TSOP II
CY7C1049G18-15ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
10 4.5 V–5.5 V CY7C1049G-10VXI 51-85090 36-pin Molded SOJ
CY7C1049G-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel
CY7C1049G-10ZSXI 51-85087 44-pin TSOP II
CY7C1049G-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = V or ZS
V= 36-pin Molded SOJ; ZS = 44-pin TSOP II
Speed: XX = 10 ns or 15 ns
Voltage Range: XX = 30 or 18 or blank
30 = 2.2 V–3.6 V; 18 = 1.65 V–2.2 V; no character = 4.5 V–5.5 V
X = blank or E
blank = without ERR output;
E = with ERR output Single bit error indication
Process Technology: G = 65 nm
Data Width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 -XX I704 G9 XX
XXX XX
CY7C1049G
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Document Number: 001-95412 Rev. *F Page 16 of 19
Package Diagrams
Figure 12. 44-pin TSOP II Package Outline, 51-85087
Figure 13. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
51-85087 *E
51-85090 *G
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 17 of 19
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degrees Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
CY7C1049G
CY7C1049GE
Document Number: 001-95412 Rev. *F Page 18 of 19
Document History Page
Document Title: CY7C1049G/CY7C1049GE, 4-Mbit (512K words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-95412
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 4685774 VINI 03/13/2015 New data sheet.
*A 4831087 NILE 07/10/2015 Updated Package Diagrams:
Added spec 51-85090 *G (Figure 13).
Removed spec 51-85082 *E.
Removed spec 51-85150 *H.
*B 4968879 NILE 10/16/2015 Fixed typo in bookmarks.
*C 5020573 VINI 11/25/2015 Changed status from Preliminary to Final.
Updated Pin Configurations:
Removed figure “36-pin SOJ Single Chip Enable with ERR CY7C1049GE”.
Updated Ordering Information:
Updated part numbers.
*D 5429076 NILE 09/07/2016 Updated Maximum Ratings:
Updated Note 8 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all
values corresponding to VOH parameter.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding
to Operating Range “4.5 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E 5725349 AESATMP7 05/03/2017 Updated Cypress Logo and Copyright.
*F 6118848 NILE 04/03/2018 Updated Features:
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-95412 Rev. *F Revised April 3, 2018 Page 19 of 19
CY7C1049G
CY7C1049GE
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