www.irf.com
IRAUDAMP5 REV 3.3
IRAUDAMP5
120W x 2 Channel Class D Audio Power Amplifier
Using the IRS2092S and IRF6645
By
Jun Honda, Manuel Rodríguez and Jorge Cerezo
Fig 1
CAUTION: International Rectifier suggests the following guidelines for
safe operation and handling of IRAUDAMP5 Demo Board;
Always wear safety glasses whenever operating Demo Board
Avoid personal contact with exposed metal surfaces when operating
Demo Board
Turn off Demo Board when placing or removing measurement probes
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IRAUDAMP5 REV 3.3
Table of Contents
Page
Introduction………………………………………………………………….. 2
Specifications………………………………………………………………… 3
Connection Setup……………………………………………………….…… 4
Test Procedure………………………………………………………………... 5
Typical Performance…………………………………………………………. 5-9
Theory of Operation…………………………………………………………. 9-10
IRS2092S System Overview………………………………………………… 10-11
Selectable Dead Time………………………………………………………… 11-12
Protection Features…………………………………………………………… 12-17
Efficiency…………………………………………………………………….. 17-18
Thermal Considerations……………………………………………………… 18
Click and Pop Noise Control…………………………………………………. 18-19
Startup and Shutdown Sequencing…………………………………………… 19-21
PSRR…………………………………………………………………………. 21-22
Bus Pumping………………………………………………………………….. 22-23
Input/Output Signal and Volume Control……………………………………. 23-26
Self Oscillating PWM Modulator…………………………………………….. 27
Switches and Indicators………………………………………………………. 28
Frequency Lock, Synchronization Feature…………………………………… 29
Schematics……………………………………………………………………. 31-35
Bill of Materials……………………………………………………………… 36-39
Hardware……………………………………………………………………… 40
PCB specifications……………………………………………………………. 41
Assembly Drawings…………………………………………………………... 42-48
Revision changes descriptions 49
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IRAUDAMP5 REV 3.3
Introduction
The IRAUDAMP5 reference design is a two-channel, 120W half-bridge Class D audio power
amplifier. This reference design demonstrates how to use the IRS2092S Class D audio controller
and gate driver IC, implement protection circuits, and design an optimum PCB layout using the
IRF6645 DirectFET MOSFETs. The resulting design requires no heatsink for normal operation
(one-eighth of continuous rated power). The reference design provides all the required
housekeeping power supplies for ease of use. The two-channel design is scalable for power and
the number of channels.
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Output Power: 120W x 2 channels,
Total Harmonic Distortion (THD+N) = 1%, 1 kHz
Residual Noise: 170V, IHF-A weighted, AES-17 filter
Distortion: 0.005% THD+N @ 60W, 4Ω
Efficiency: 96% @ 120W, 4Ω, single-channel driven, Class D stage
Multiple Protection Features: Over-current protection (OCP), high side and low side
Over-voltage protection (OVP),
Under-voltage protection (UVP), high side and low side
DC-protection (DCP),
Over-temperature protection (OTP)
PWM Modulator: Self-oscillating half-bridge topology with optional clock
synchronization
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IRAUDAMP5 REV 3.3
Specifications
General Test Conditions (unless otherwise noted) Notes / Conditions
Supply Voltage ±35V
Load Impedance 8-4Ω
Self-Oscillating Frequency 400kHz No input signal, Adjustable
Gain Setting 26dB 1Vrms input yields rated power
Electrical Data Typical Notes / Conditions
IR Devices Used IRS2092S Audio Controller and Gate-Driver,
IRF6645 DirectFET MOSFETs
Modulator Self-oscillating, second order sigma-delta modulation, analog input
Power Supply Range ± 25V to ±35V Bipolar power supply
Output Power CH1-2: (1% THD+N) 120W 1kHz
Output Power CH1-2: (10% THD+N) 170W 1kHz
Rated Load Impedance 8-4Ω Resistive load
Standby Supply Current ±100mA No input signal
Total Idle Power Consumption 7W No input signal
Channel Efficiency 96% Single-channel driven,
120W, Class D stage
.
Audio Performance *Before
Demodulator
Class D
Output Notes / Conditions
THD+N, 1W
THD+N, 10W
THD+N, 60W
THD+N, 100W
0.009%
0.003%
0.003%
0.008%
0.01%
0.004%
0.005%
0.010%
1kHz, Single-channel driven
Dynamic Range 101dB 101dB A-weighted, AES-17 filter,
Single-channel operation
Residual Noise, 22Hz - 20kHzAES17 170V
170V
Self-oscillating – 400kHz
Damping Factor 2000 170 1kHz, relative to 4Ω load
Channel Separation 95dB
85dB
75dB
90dB
80dB
65dB
100Hz
1kHz
10kHz
Frequency Response : 20Hz-20kHz
: 20Hz-35kHz
N/A ±1dB
±3dB 1W, 4Ω - 8Ω Load
Thermal Performance Typical Notes / Conditions
Idling TC =30C
TPCB=37C
No signal input, TA=25C
2ch x 15W (1/8 rated power) TC =54C
TPCB=67C
Continuous, TA=25C
2ch x 120W (Rated power) TC =80C
TPCB=106C
At OTP shutdown @ 150 sec,
TA=25C
Physical Specifications
Dimensions 5.8”(L) x 5.2”(W)
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IRAUDAMP5 REV 3.3
Note: Class D Specifications are typical
*Before demodulator refers to audio performance measurements of the Class D output power
stage only, with preamp and output filter bypassed this means performance measured before the
low pass filter.
Connection Setup
Typical Test Setup
Fig 2
Connector Description
CH1 IN J6 Analog input for CH1
CH2 IN J5 Analog input for CH2
POWER J7 Positive and negative supply (+B / -B)
CH1 OUT J3 Output for CH1
CH2 OUT J4 Output for CH2
EXT CLK J8 External clock sync
DCP OUT J9 DC protection relay output
Volume
J6 J5
J3 J4
J7
R113
S3 S2
TP1 TP2
CH1
Output CH2
Output
CH1
Input CH2
Input
G
Protection
Normal
S1
LED
35V, 5A DC supply
4 Ohm4 Ohm
35V, 5A DC supply
250W, Non-inductive Resistors
J8
J9
Audio Signal Generator
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IRAUDAMP5 REV 3.3
Test Procedures
1. Connect 4, 250W load to outputs connectors, J3 and J4 and Audio Precision analyzer
(AP).
2. Connect Audio Signal Generator to J6 and J5 for CH1 and CH2 respectively (AP).
3. Connect a dual power supply to J7, pre-adjusted to ±35V, as shown in Figure 2 above.
4. Set switch S3 to middle position (self oscillating).
5. Set volume level knob R108 fully counter-clockwise (minimum volume).
6. Turn on the power supply. Note: always apply or remove the ±35V at the same time.
7. Orange LED (Protection) should turn on almost immediately and turn off after about 3s.
8. Green LED (Normal) then turns on after orange LED is extinguished and should stay on.
9. One second after the green LED turns on; the two blue LEDS on the Daughter Board
should turn on and stay on for each channel, indicating that a PWM signal is present at
LO
10. With an Oscilloscope, monitor switching waveform at test points TP1 and TP2 of CH1
and CH2 on Daughter Board.
11. If necessary, adjust the self-oscillating switching frequency of AUDAMP5 to 400KHz
5kHz using potentiometer R29P. For IRAUDAMP5, the self-oscillating switching
frequency is pre-calibrated to 400 KHz. To modify the AUDAMP5 frequency, change the
values of potentiometers R21 and R22 for CH1 and CH2 respectively.
12. Quiescent current for the positive supply should be 70mA 10mA at +35V.
13. Quiescent current for the negative supply should be 100mA 10mA at –35V.
14. Push S1 switch, (Trip and Reset push-button) to restart the sequence of LEDs indicators,
which should be the same as noted above in steps 6-9.
Audio Tests:
15. Apply 1 V RMS at 1KHz from the Audio Signal Generator
16. Turn control volume up (R108 clock-wise) to obtain an output reading of 100Watts for
all subsequent tests as shown on the Audio Precision graphs below, where measurements
are across J3 and J2 with an AES-17 Filter
Typical Performance
The tests below were performed under the following conditions:
±B supply = ±35V, load impedance = 4 resistive load, 1kHz audio signal,
Self oscillator @ 400kHz and internal volume-control set to give required output with 1Vrms
input signal, with AES-17 Filter, unless otherwise noted.
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IRAUDAMP5 REV 3.3
THD versus Power:
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 200200m 500m 1 2 5 10 20 50 100
W
Blue, CH1 - 4 Ohm
Red, CH2 - 4 Ohm
Figure 18. Total Harmonics Distortion + Noise (THD+N) versus power output
Fig 3
-10
+4
-9
-8
-7
-6
-5
-4
-3
-2
-1
-0
+1
+2
+3
d
B
r
A
20 200k50 100 200 500 1k 2k 5k 10k 20k 50k 100k
Hz
Frequency Response:
Red CH1 - 4 Ohm, 2V Output
Blue CH1 - 8 Ohm, 2V Output
Frequency Characteristics vs. Load Impedance
Fig 4
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IRAUDAMP5 REV 3.3
.
THD versus Frequency:
0.0001
100
0.0005
0.001
0.01
0.05
0.1
1
5
10
50
%
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Pink CH1, 1W Output
Blue CH1, 10W Output
Cyan CH1, 50W Output
Green CH1, 100W Output
THD+N Ratio vs. Frequency
Fig 5
.
Frequency Spectrum :
-110
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
V
10 20k20 50 100 200 500 1k 2k 5k 10k
Hz
Red CH1, 1V, 1kHz, Self Oscillator @ 400kHz
Blue CH2, 1V, 1kHz, Self Oscillator @ 400kHz
Fig 6 Frequency Spectrum
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IRAUDAMP5 REV 3.3
.
Floor Noise:
-140
+20
-120
-100
-80
-60
-40
-20
+0
d
B
V
10 20k20 50 100 200 500 1k 2k 5k 10k
Hz
Red CH1 - ACD, No signal, Self Oscillator @ 400kHz
Blue CH2 - ACD, No signal, Self Oscillator @ 400kHz
Fig 7 Residual Noise (ACD)
.
Channel Separation:
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Red CH1 – CH2, 60W
Blue CH2 – CH1, 60W
Fig 8 Channel Separation vs. Frequency
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IRAUDAMP5 REV 3.3
.
Clipping Characteristics:
60W / 4
, 1kHz, THD+N=0.008% 174W / 4
, 1kHz, THD+N=10%
Measured Output and Distortion Waveforms
Fig 9
.
IRAUDAMP5 Theory of Operation
Referring to Fig 10 below, the input error amplifier of the IRS2092S forms a front-end second-
order integrator with C1, C21, C23 and R21. This integrator also receives a rectangular feedback
waveform from R31, R33 and C17 into the summing node at IN- from the Class D power stage
switching node (connection of DirectFET Q3 and DirectFET Q4). The quadratic oscillatory
waveform of the switch node serves as a powered carrier signal from which the audio is
recovered at the speaker load through a single-stage LC filter. The modulated signal is created by
the fluctuations of the analog input signal at R13 that shifts the average value of this quadratic
waveform through the gain relationship between R13 and R31 + R33 so that the duty cycle varies
according to the instantaneous signal level of the analog input signal at R13.
R33 and C17 act to immunize the rectangular waveform from possible narrow noise spikes that
may be created by parasitic impedances on the power output stage. The IRS2092S input
integrator then processes the signal from the summing node to create the required triangle wave
amplitude at the COMP output. The triangle wave then is converted to Pulse Width Modulation,
or PWM, signals that are internally level-shifted Down and Up to the negative and positive
supply rails. The level shifted PWM signals are called LO for low output, and HO for high
output, and have opposite polarity. A programmable amount of dead time is added between the
gate signals to avoid cross conduction between the power MOSFETs. The IRS2092S drives two
IRF6645 DirectFET MOSFETs in the power stage to provide the amplified PWM waveform. The
amplified analog output is reconstructed by demodulating the powered PWM at the switch node,
called VS. (Show as VS on the schematic)This is done by means of the LC low-pass filter (LPF)
formed by L1 and C23A, which filters out the Class D switching carrier signal, leaving the audio
powered output at the speaker load. A single stage output filter can be used with switching
Red Trace: Total Distortion + Noise Voltage
Green Trace: Output Voltage
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IRAUDAMP5 REV 3.3
frequencies of 400 kHz and greater; lower switching frequencies may require additional filter
components.
+VCC is referenced to –B and provides the supply voltage to the LO gate driver. D6 and C5 form
a bootstrap supply that provides a floating voltage to the HO gate driver. The VAA and VSS
input supplies are derived from +B and -B via R52 and C18, and R50 and C12, respectively.
Thus, a fully functional Class D PWM amplifier plus driver circuit is realized in an SO16
package with just a few small components.
+
-
.
.
.
R13
IN-
COMP
C23
.
R33
-VSS
+VAA
IRS2092S
LO
VS
VCC
C5
D6
VB 0V
0V
C1
R21
C17
R52
C3
HO
C23A
INPUT
C21
R31
C12
R50
+VCC
Integrator
COM
R30
Modulator
and
Shift level
GND
0V
-B
DirectFet
0VLP Filter
L1
DirectFet
C18
R32
+B
IRF6645
Q4
IRF6645
Q3
Simplified Block Diagram of IRAUDAMP5 Class D Amplifier
Fig 10
System overview
IRS2092S Gate Driver IC
The IRAUDAMP5 uses the IRS2092S, a high-voltage (up to 200V), high-speed power MOSFET
PWM generator and gate driver with internal dead-time and protection functions specifically
designed for Class D audio amplifier applications. These functions include OCP and UVP. Bi-
directional current protection for both the high-side and low-side MOSFETs are internal to the
IRS2092S, and the trip levels for both MOSFETs can be set independently. In this design, the
dead time can be selected for optimized performance by minimizing dead time while preventing
shoot-through. As a result, there is no gate-timing adjustment on the board. Selectable dead time
through the DT pin voltage is an easy and reliable function which requires only two external
resistors, R11 and R9 as shown on Fig11 below.
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IRAUDAMP5 REV 3.3
.
.
CH1
Feedback
R19
.
R18
R13
.
AUDIO_INPUT
+VCC
-B
+B
R5
VS
HO
VB
CSH
DT
COM
LO
VCC
IN-
COMP
VAA
GND
CSD
VREF
VSS
CSLO
IRS2092S
System-level View of Class D Controller and Gate Driver IRS2092S
Fig 11
Selectable Dead-Time
The dead time of the IRS2092S is based on the voltage applied to the DT pin. (Fig 12) An
internal comparator determines the programmed dead time by comparing the voltage at the DT
pin with internal reference voltages. An internal resistive voltage divider based on different ratios
of VCC negates the need for a precise reference voltage and sets threshold voltages for each of
the four programmable settings. Shown in the table below are component values for
programmable dead times between 25 and 105 ns. To avoid drift from the input bias current of
the DT pin, a bias current of greater than 0.5mA is suggested for the external resistor divider
circuit. Resistors with up to 5% tolerance can be used.
Selectable Dead-Time
Dead-time mode Dead time R5 R13 DT voltage
DT1 ~25ns 3.3k 8.2k 0.71 x Vcc Default
DT2 ~40ns 5.6k 4.7k 0.46 x Vcc
DT3 ~65ns 8.2k 3.3k 0.29 x Vcc
DT4 ~105ns open <10k 0 x Vcc
Vcc 0.57xVcc 0.36xVcc 0.23xVcc
Operational Mode
VDT
Dead-time
25nS
40nS
65nS
105nS
0
Fig 12 Dead-time Settings vs. VDT Voltage
Default
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IRAUDAMP5 REV 3.3
Over-Current Protection (OCP)
In the IRAUDAMP5, the IRS2092S gate driver accomplishes OCP internally, a feature discussed
in greater detail in the “Protection” section.
Offset Null (DC Offset)
The IRAUDAMP5 is designed such that no output-offset nullification is required, thanks to
closed loop operation. DC offsets are tested to be less than ±20mV.
Protection
The IRAUDAMP5 has a number of protection circuits to safeguard the system and speaker as
shown in the figure 13 below, which fall into one of two categories – internal faults and external
faults, distinguished by the manner in which a fault condition is treated. Internal faults are only
relevant to the particular channel, while external faults affect the whole board. For internal faults,
only the offending channel is stopped. The channel will hiccup until the fault is cleared. For
external faults, the whole board is stopped using the shutdown sequencing described earlier. In
this case, the system will also hiccup until the fault is cleared, at which time it will restart
according to the startup sequencing described earlier.
. .
D4
OCREF
OCREF
5.1V
CSD
Trip
RESET
OCSET
+
.
UVP
LO
VS
VCC
VB
CSH
R41
OVP
OTP
R25
D1
BAV19
DCP
LP Filter
Green
Yellow
LEDs
R18
HO
To next channel
OCSET COM
10R
R30
CSD
R43
1.2V
+B
R19
10R
R32
-B
IRF6645
Q4
IRF6645
Q3
Functional Block Diagram of Protection Circuit Implementation
Fig 13
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IRAUDAMP5 REV 3.3
Internal Faults
OCP and OTP are considered internal faults, which will only shutdown the particular channel by
pulling low the relevant CSD pin. The channel will shutdown for about one-half a second and
will hiccup until the fault is cleared.
Over-Temperature Protection (OTP, Fig 14)
A separate PTC resistor is placed in close proximity to the high-side IRF6645 DirectFET
MOSFET for each of the amplifier channels. If the resistor temperature rises above 100C, the
OTP is activated. The OTP protection will only shutdown the relevant channel by pulling the
CSD pin low and will recover once the temperature at the PTC has dropped sufficiently. This
temperature protection limit yields a PCB temperature at the MOSFET of about 100C, which is
limited by the PCB material and not by the operating range of the MOSFET.
R31
100K
Rp1
100C
-B
C28
47nF
R48
1K
R47
100K
Q7
OTP CH1
-B
OTP1
Rp1 is thermally connected with Q3
32
1
2 3
Q3
IRF6645
Fig 14
Over-Current Protection (OCP)
The OCP internal to the IRS2092S shuts down the IC if an OCP is sensed in either of the output
MOSFETs. For a complete description of the OCP circuitry, please refer to the IRS2092S
datasheet. Here is a brief description:
Low-Side Current Sensing
Fig 15 shows the low side MOSFET as is protected from an overload condition by measuring the
low side MOSFET drain-to-source voltage during the low side MOSFET on state, and will shut
down the switching operation if the load current exceeds a preset trip level. The voltage setting on
the OCSET pin programs the threshold for low-side over-current sensing. Thus, if the VS voltage
during low-side conduction is higher than the OCSET voltage, the IRS2092S will trip and CSD
goes down. It is recommended to use VREF to supply a reference voltage to a resistive divider
(R19 and R18 for CH1) to generate a voltage to OCSET; this gives better variability against VCC
fluctuations. For IRAUDAMP5, the low-side over-current trip level is set to 0.65V. For IRF6645
DirectFET MOSFETs with a nominal RDS-ON of 28mOhms at 25C, this results in a ~23A
maximum trip level. Since the RDS-ON is a function of temperature, the trip level is reduced to
~15A at 100C.
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IRAUDAMP5 REV 3.3
.
OCREF
OCREF
5.1V
CSD
OCSET
+
.
LO
VS
VCC
VB
CSH
R41
R25
D1
BAV19
LP Filter
R18
HO
OCSET COM
10R
R30
CSD
R43
1.2V
+B
R19
10R
R32
-B
IRF6645
Q4
IRF6645
Q3
Simplified Functional Block Diagram of High -Side and Low-Side Current Sensing (CH1)
Fig 15
High-Side Current Sensing (Fig15)
The high-side MOSFET is protected from an overload condition and will shutdown the switching
operation if the load current exceeds a preset trip level. High-side over-current sensing monitors
detect an overload condition by measuring the high side MOSFET’s drain-to-source voltage
(VDS) through the CSH and VS pins. The CSH pin detects the drain voltage with reference to the
VS pin, which is the source of the high-side MOSFET. In contrast to the low-side current sensing,
the threshold of CSH pin to engage OC protection is internally fixed at 1.2V. An external
resistive divider R43+R25 and R41 (for Ch1) can be used to program a higher threshold. An
additional external reverse blocking diode (D1 for CH1) is required to block high voltage feeding
into the CSH pin during low-side conduction. By subtracting a forward voltage drop of 0.6V at
D1, the minimum threshold which can be set for the high-side is 0.6V across the drain-to-source.
For IRAUDAMP5, the high-side over-current trip level is set to 0.6V across the high-side
MOSFET. For the IRF6645 MOSFETs with a nominal RDS-ON of 28 mOhms at 25C, this results
in a ~21A maximum trip level. Since the RDS-ON is a function of temperature, the trip level is
reduced to ~14A at 100C.
For a complete description of calculating and designing the over-current trip limits, please refer to
the IRS2092S datasheet.
Positive and Negative Side of Short Circuit, versus switching output shut down:
The plots below show the speed that the IRS2092S responds to a short circuit condition. Notice
that the envelope behind the sine wave output is actually the switching frequency ripple. Bus
pumping naturally affects this topology.
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IRAUDAMP5 REV 3.3
Positive and Negative side of Short Circuit, versus switching output shut down:
OCP Waveforms Showing Load Current and Switch Node Voltage (VS)
Fig 16
.
Short Circuit Response:
OCP Waveforms Showing CSD Trip and Hiccup
Fig 17
External Faults
OVP, UVP and DCP are considered external faults. In the event that any external fault condition
is detected, the shutdown circuit will disable the output for about three seconds, during which
time the orange AUDAMP5 “Protection” LED will turn on. If the fault condition has not cleared,
the protection circuit will hiccup until the fault is removed. Once the fault is cleared, the green
“Normal” LED will turn on. There is no manual reset option.
Over-Voltage Protection (OVP Fig 18)
OVP will shut down the amplifier if the bus voltage between GND and -B exceeds 40V. The
threshold is determined by the voltage sum of the Zener diode Z105, R140, and VBE of Q109. As
a result, it protects the board from hazardous bus pumping at very low audio signal frequencies
by shutting down the amplifier. OVP will automatically reset after three seconds. Since the +B
and –B supplies are assumed to be symmetrical (bus pumping, although asymmetrical in time,
Load current
CSD
p
in
VS
p
in
Load current
CSD
p
in
VS
p
in
Load current
CSD
p
in
Load current
VS
p
in
CSD
p
in
VS
p
in
Load current
CSD
p
in
Load current
VS
p
in
CSD
p
in
VS
p
in
Load current
VS
p
in
Load current
VS
p
in
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IRAUDAMP5 REV 3.3
will pump the bus symmetrically in voltage level over a complete audio frequency cycle), it is
sufficient to sense only one of the two supply voltages for OVP. It is therefore up to the user to
ensure that the power supplies are symmetrical.
Q109 Over-Voltage Protection (OVP)
R141
47k
S1
SW-PB
Q109
MMBT5551
R139
47k
-B
SD
D105
1N4148
Z107
18V
R145
47K
R146
47K
Q110
MMBT5551
R144
10k
Trip and restart
R140
10k
Z105
39V
OVP
DCP
R149
47K
C119
0.1uF, 50V
UVP
OT
OT
Q110 Under-Voltage Protection (UVP)
Fig 18
Under-Voltage Protection (UVP, Fig18)
UVP will shutdown the amplifier if the bus voltage between GND and -B falls below 20V. The
threshold is determined by the voltage sum of the Zener diode Z107, R145 and VBE of Q110. As
with OVP, UVP will automatically reset after three seconds, and only one of the two supply
voltages needs to be monitored.
Speaker DC-Voltage Protection (DCP, Fig 19)
DCP is provided to protect against DC current flowing into the speakers. This abnormal condition
is rare and is likely caused when the power amplifier fails and one of the high-side or low-side
IRF6645 DirectFET MOSFETs remain in the ON state. DCP is activated if either of the outputs
has more than ±4V DC offset (typical). Under this fault condition, it is normally required to
shutdown the feeding power supplies. Since these are external to the reference design board, an
isolated relay P1 is provided for further systematic evaluation of DC-voltage protection. This
condition is transmitted to the power supply controller through connector J9, whose pins are
shorted during a fault condition.
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IRAUDAMP5 REV 3.3
R124
10k
R121
47k
R122
47k
CH1 O
CH2 O
Q106
MMBT5401
Q104
MMBT5401
C116
100uF, 16V R123
1K
Q105 MMBT5551
R125
10K
R126
100K
+B
R129
6.8k
DC protection
DCP
R127
6.8k
R128
6.8k
R130
47K
R131
47K
From CH1 Output
From CH2 Output
-B
To DCP
Fig 19
Efficiency
Figs 20 demonstrate that IRAUDAM5 is highly efficient, due to two main factors:
a.) DirectFETs offer low RDS(ON) and very low input capacitance, and b). The PWM operates as
Pulse Density Modulation.
0.0%
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
70.0%
80.0%
90.0%
100.0%
0 20 40 60 80 100 120 140 160 180
Output Power (W)
Power Stage Efficiency (%)
Efficiency vs. Output Power, 4
Single Channel Driven, ±B supply = ±35V, 1kHz Audio Signal
Fig20
www.irf.com Page 18 of 49
IRAUDAMP5 REV 3.3
Thermal Considerations
The daughter-board design can handle one-eighth of the continuous rated power, which is
generally considered to be a normal operating condition for safety standards. Without the addition
of a heatsink or forced air-cooling, the daughter board cannot handle fully rated continuous
power. A thermal image of the daughter board is as shown in Fig 21 below.
Thermal Distribution
Thermal image of Daughter-Voard
Two-Channel x 1/8th Rated Power (15W) in Operation, TC = 54°C at Steady State
±B supply = ±35V, 4
Load, 1kHz audio signal, Temp ambient = 25°C
Fig 21
Click and POP noise:
One of the most important aspects of any audio amplifier is the startup and shutdown procedures.
Typically, transients occurring during these intervals can result in audible pop- or click-noise
from the output speaker. Traditionally, these transients have been kept away from the speaker
through the use of a series relay that connects the speaker to the audio amplifier only after the
startup transients have passed and disconnects the speaker prior to shutting down the amplifier.
Thanks to the click and pop elimination function in the IRS2092S, IRAUDAMP5 does not use
any series relay to disconnect the speaker from the audible transient noise.
54C
67C
54C
67C
www.irf.com Page 19 of 49
IRAUDAMP5 REV 3.3
Click-Noise Reduction Circuit (Solid-State Shunt)
IRS2092S controller is relatively quiet with respect to class AB, but for additional click or POP
noise reduction you may add a shunt circuit that further attenuates click or pop transients during
turn on sequencing. The circuit is not populated on the present demo board; for implementation
details, please refer to the IRAUDAMP4 user’s manual at http://www.irf.com/technical-
info/refdesigns/audiokits.html
Startup and Shutdown Sequencing (Fig 22)
The IRAUDAMP5 sequencing is achieved through the charging and discharging of the CStart
capacitor C117. Along with the charging and discharging of the CSD voltage (C10 on daughter
board for CH1) of the IRS2092S, this is all that is required for complete sequencing. The startup
and shutdown timing diagrams are show in Figure 22A below:
Click Noise Reduction Sequencing at Trip and Reset
Fig 22A
For startup sequencing, the control power supplies start up at different intervals depending on the
±B supplies. As the +/-B supplies reach +5 volts and -5 volts respectively, the +/-5V control
supplies for the analog input start charging. Once +B reaches ~16V, VCC charges. Once –B
reaches -20V, the UVP is released and CSD and CStart (C117) start charging. The Class D
amplifier is now operational, but the preamp output remains muted until CStart reaches Ref2. At
this point, normal operation begins. The entire process takes less than three seconds.
CStart
CSD
External trip
CSD= 2/3VDD
CStart Ref1
CStart Ref2
SP MUTE
CHx_O
A
udio MUTE
Class D shutdown
Time
Music shutdown Class D startup Music startup
CStart Ref1 CStart Ref2
Reset
CStart Ref1
CStart Ref2
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IRAUDAMP5 REV 3.3
For Shutdown (Fig22B) sequencing is initiated once UVP is activated. As long as the supplies do
not discharge too quickly, the shutdown sequence can be completed before the IRS2092S trips
UVP. Once UVP is activated, CSD and CStart are discharged at different rates. In this case,
threshold Ref2 is reached first and the preamp audio output is muted. It is then possible to
shutdown the Class D stage (CSD reaches two-thirds VDD). This process takes less than 200ms.
Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing
Fig22B
For any external fault condition (OTP, OVP, UVP or DCP – see “Protection”) that does not lead
to power supply shutdown, the system will trip in a similar manner as described above. Once the
fault is cleared, the system will reset (similar sequence as startup).
Vcc
-B
+B
+5V
-5V
CStart
CSD
UVP@-20V
CSD= 2/3VDD
CStart Ref1
CStart Ref2
A
udio MUTE
SP MUTE
CHx_O
Class D shutdown
Time
Music shutdown
www.irf.com Page 21 of 49
IRAUDAMP5 REV 3.3
Power Supplies
The IRAUDAMP5 has all the necessary housekeeping power supplies onboard and only requires
a pair of symmetric power supplies ranging from ±25V to ±35V (+B, GND, -B) for operation.
The internally-generated housekeeping power supplies include a ±5V supply for analog signal
processing (preamp etc.), while a +12V supply (VCC), referenced to –B, is included to supply the
low and high side Class D gate-driver stages.
For the externally-applied power, a regulated power supply is preferable for performance
measurements, but is not always necessary. The bus capacitors, C31 and C32 on the motherboard,
along with high-frequency bypass-caps C14, C15; C32 and C33 on the daughter board, address
the high-frequency ripple current that results from switching action. In designs involving
unregulated power supplies, the designer should place a set of external bus capacitors having
enough capacitance to handle the audio-ripple current. Overall regulation and output voltage
ripple for the power supply design are not critical when using the IRAUDAMP5 Class D
amplifier as the power supply rejection ratio (PSRR) of the IRAUDAMP5 is excellent, as shown
on Figure 23 below.
Power Supply Rejection Ratio
Green: IRAUDAMP5, Cyan: VAA/VSS are fed by Vbus
Fig 23
Bus Pumping (Fig24)
Since the IRAUDAMP5 is a half-bridge configuration, bus pumping does occur. Under normal
operation during the first half of the cycle, energy flows from one supply through the load and
into the other supply, thus causing a voltage imbalance by pumping up the bus voltage of the
receiving power supply. In the second half of the cycle, this condition is reversed, resulting in
bus pumping of the other supply.
These conditions worsen bus pumping:
1. Lower frequencies (bus-pumping duration is longer per half cycle)
2. Higher power output voltage and/or lower load impedance (more energy transfers
between supplies)
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IRAUDAMP5 REV 3.3
3. Smaller bus capacitors (the same energy will cause a larger voltage increase)
The IRAUDAMP5 has protection features that will shut down the switching operation if the bus
voltage becomes too high (>40V) or too low (<20V). One of the easiest countermeasures is to
drive both of the channels in a stereo configuration out of phase so that one channel consumes the
energy flow from the other and does not return it to the power supply. Bus voltage detection is
only done on the –B supply, as the effect of the bus pumping on the supplies is assumed to be
symmetrical in amplitude (although opposite in phase) with the +B supply.
Bus Pumping Figure:
Cyan = Positive Rail voltage (+B)
Green = Speaker Output
Pink = Negative Rail voltage (-B)
Fig 24
Input Signal
A proper input signal is an analog signal below 20 kHz, up to ±3.5V peak, having a source
impedance of less than 600 ohms. A 30-60 kHz input signal can cause LC resonance in the output
LPF, resulting in an abnormally large amount of reactive current flowing through the switching
stage (especially at 8 ohms or higher impedance towards open load), and causing OCP activation.
The IRAUDAMP5 has an RC network (Fig25), or Zobel network (R47 and C25 [CH1]), to
dampen the resonance and protect the board in such an event, but is not thermally rated to handle
continuous supersonic frequencies. These supersonic input frequencies therefore should be
avoided. Separate mono RCA connectors provide input to each of the two channels. Although
both channels share a common ground, it is necessary to connect each channel separately to limit
noise and crosstalk between channels.
www.irf.com Page 23 of 49
IRAUDAMP5 REV 3.3
.
.
.
.
0V
0V
LP Filter
L1
C23A
R47
C25
Zobel Filter and Output filter demodulator
Fig 25
Output
Both outputs for the IRAUDAMP5 are single-ended and therefore have terminals labeled (+) and
(-), with the (-) terminal connected to power ground. Each channel is optimized for a 4-Ohm
speaker load for a maximum output power (120W), but is capable of operating with higher load
impedances (at reduced power), at which point the frequency response will have a small peak at
the corner frequency of the output LC low pass filter. The IRAUDAMP5 is stable with
capacitive-loading; however, it should be noted that the frequency response degrades with heavy
capacitive loading of more than 0.1μF.
Gain Setting / Volume Control
The IRAUDAMP5 has an internal volume control (potentiometer R108 labeled, ”VOLUME”, Fig
26) for gain adjustment. Gain settings for both channels are tracked and controlled by the volume
control IC (U_2), setting the gain from the microcontroller IC (U_1). The maximum volume
setting (clockwise rotation) corresponds to a total gain of +37.9dB (78.8V/V). The total gain is a
product of the power-stage gain, which is constant (+23.2dB), and the input-stage gain that is
directly-controlled by the volume adjustment. The volume range is about 100dB, with minimum
volume setting to mute the system with an overall gain of less than -60dB. For best performance
in testing, the internal volume control should be set to a gain of 21.9V/V, such that 1Vrms input
will result in rated output power (120W into 4), allowing for a >11dB overdrive.
J5
J6
R4
100R
ZCEN
CS
SDATAI
VD+
DGRD
SCLK
SDATAO
MUTE
AINL
AGNDR
AOUTL
VA-
VA+
AOUTR
AGNDL
AINR
U_1
CS3310
R3
100R
R1
100K
R2
100K
R7 47R
R8 47R
R9 10R
R10
47R
R11
47R
C1
10uF, 50V
MUTE
-5V
+5V
+5V
VSS
8
VR0
7
VR1
6
CLK
5
VDD 1
CS 2
SDATA 3
SIMUL 4
U_2
3310S06S
R108
CT2265-ND
C107
4.7uF, 16V
C108
10nF, 50V
SCLK
SDATAI
C109
4.7uF, 16V
CS
+5V
Control Volume
+5V
Audio in
Audio in
Level OUT 1
Level OUT 2
Fig 26 Digital volume Control
www.irf.com Page 24 of 49
IRAUDAMP5 REV 3.3
Bridged Output
The IRAUDAMP5 is not intended for a bridge-tied-load, or BTL configuration. However, BTL
operation can be achieved by feeding out-of-phase audio input signals to the two input channels
as shown in the figure 27 below. In BTL operation, minimum load impedance is 8 Ohms and
rated power is 240W non-clipping. The installed clamping diodes D5 – D8 are required for BTL
operation, since reactive energy flowing from one output to the other during clipping can force
the output voltage beyond the voltage supply rails if not clamped.
+
-
.
.
+
-
INPUT
R14
10k 1%
IN-
COMP
C24
.
R34
COMP
C23
C1
R21
R33
.
C17
+VAA
IRS2092S
IRS2092S
LO
VS
VCC
VB
HO
LO
VS
VCC
VB
HO
-B
+B
-B
+B
L2
0V
L1
0V
-B
.
-B
+B
R13
C2
C18
IN-
+VAA
LP Filter
LP Filter
+B
CH2
C22
1
R32
CH1
C21
R31
COM
Integrator
Modulator
and
Shift level
GND
COM
Integrator
Modulator
and
Shift level
GND
D6D8 D7
10k 1%
D5
IRF6645
Q6
IRF6645
Q3
IRF6645
Q5
IRF6645
Q4
Bridged configuration
Fig 27
Output Filter Design, Preamplifier and Performance
The audio performance of IRAUDAMP5 depends on a number of different factors. The section
entitled, “Typical Performance” presents performance measurements based on the overall system,
including the preamp and output filter. While the preamp and output filter are not part of the
Class D power stage, they have a significant effect on the overall performance.
Output filter
Since the output filter is not included in the control loop of the IRAUDAMP5, the reference
design cannot compensate for performance deterioration due to the output filter. Therefore, it is
important to understand what characteristics are preferable when designing the output filter:
www.irf.com Page 25 of 49
IRAUDAMP5 REV 3.3
1) The DC resistance of the inductor should be minimized to 20 mOhms or less.
2) The linearity of the output inductor and capacitor should be high with respect to load
current and voltage.
Preamplifier (Fig 28)
The preamp allows partial gain of the input signal, and controls the volume in the IRAUDAMP5.
The preamp itself will add distortion and noise to the input signal, resulting in a gain through the
Class D output stage and appearing at the output. Even a few micro-volts of noise can add
significantly to the output noise of the overall amplifier.
J5
R5
4.7R
R13
3.3K
R31
47k 1%
J6
R4
100R
R14
3.3K
R32
47k 1%
R34
1K
R33
1K
C17
150pF, 500V
CH2 IN
CH1 IN
R3
100R
R1
100K
C2
10uF, 50V
C3
10uF, 50V
R2
100K
R6
4.7R
-5V
+5V
C5
10uF, 50V
C6
10uF, 50V
SD
IN-1
VCC
VCC
OC
IN-2
+5V
-5V
-5V
R55
0.0
R56
0.0
Feedback
Audio in
Audio in
R71
OPEN
R72
OPEN
1
2
3
4
5
6
J1A
7
8
9
10
11
12
J1B
ZCEN
1
CS
2
SDATAI
3
VD+
4
DGRD
5
SCLK
6
SDATAO
7
MUTE
8
AINL 16
AGNDR 10
AOUTL 14
VA- 13
VA+ 12
AOUTR 11
AGNDL 15
AINR 9
U_?
CS3310
Feedback
IRS2092S MODULE
Preamplifier
Fig28
It is possible to evaluate the performance without the preamp and volume control, by moving
resistors R13 and R14 to R71 and R72, respectively. This effectively bypasses the preamp and
connects the RCA inputs directly to the Class D power stage input. Improving the selection of
preamp and/or output filter components will improve the overall system performance,
approaching that of the stand-alone Class D power stage. In the “Typical Performance” section,
only limited data for the stand-alone Class D power stage is given. For example, Fig 20 below
shows the results for THD+N vs. Output Power are provided, utilizing a range of different
inductors. By changing the inductor and repeating this test, a designer can quickly evaluate a
particular inductor.
www.irf.com Page 26 of 49
IRAUDAMP5 REV 3.3
I
IRAUDAMP5 can be used as output inductors evaluation tool
Results of THD+N vs. Output Power with Different Output Inductors
Fig 29
Self-Oscillating PWM Modulator
The IRAUDAMP5 Class D audio power amplifier features a self-oscillating type PWM
modulator for the lowest component count, highest performance and robust design. This topology
represents an analog version of a second-order sigma-delta modulation having a Class D
switching stage inside the loop. The benefit of the sigma-delta modulation, in comparison to the
carrier-signal based modulation, is that all the error in the audible frequency range is shifted to
the inaudible upper-frequency range by nature of its operation. Also, sigma-delta modulation
allows a designer to apply a sufficient amount of correction.
The self-oscillating frequency (Fig 30) is determined by the total delay time inside the control
loop of the system. The delay of the logic circuits, the IRS2092S gate-driver propagation delay,
the IRF6645 switching speed, the time-constant of front-end integrator (e.g.R13, R33, R31, R21,
P1, C17, C21, C23 and C1 for CH1) and variations in the supply voltages are critical factors of
the self-oscillating frequency. Under nominal conditions, the switching-frequency is around
400kHz with no audio input signal and a +/-35V supply.
0.0001
100
0.001
0.01
0.1
1
10
%
100m 200m 500m 1 2 5 10 20 50 100 200
W
T T T T T T T T T
www.irf.com Page 27 of 49
IRAUDAMP5 REV 3.3
+
-
..
R13
IN-
C23
R21
COMP
.
R33
IRS2092S
LO
COM
VS
VCC
VB
-B
+B
LP Filter
0V
C1
HO
INPUT
CH1
C21
P1
R31
Integrator
Modulator
and
Shift level
GND
C17
IRF6645
Q4
IRF6645
Q3
Self Oscillating determined components
Fig 30
Adjustments of Self-Oscillating Frequency
The PWM switching frequency in this type of self-oscillating switching scheme greatly impacts
the audio performance, both in absolute frequency and frequency relative to the other channels. In
absolute terms, at higher frequencies distortion due to switching-time becomes significant, while
at lower frequencies, the bandwidth of the amplifier suffers. In relative terms, interference
between channels is most significant if the relative frequency difference is within the audible
range. Normally, when adjusting the self-oscillating frequency of the different channels, it is best
to either match the frequencies accurately, or have them separated by at least 25kHz. With the
installed components, it is possible to change the self-oscillating frequency from about 300kHz
up to 450kHz, as shown on Fig 30
Switches and Indicators
There are four different indicators on the reference design as shown in the figure 31 below:
1. An orange LED, signifying a fault / shutdown condition when lit.
2. A green LED on the motherboard, signifying conditions are normal and no fault
condition is present.
3. A blue LED on the daughter board module, signifying there are HO pulses for CH1
4. A blue LED on the daughter board module signifying there are HO pulses for CH2
There are three switches on the reference design:
1. Switch S1 is a trip and reset push-button. Pushing this button has the same effect as a
fault condition. The circuit will restart about three seconds after the shutdown button is
released.
2. Switch S2 is an internal clock-sync frequency selector. This feature allows the designer
to modify the switching frequency in order to avoid AM radio interference. With S3 set
to INT, the two settings “H” and “L” will modify the internal clock frequency by about
www.irf.com Page 28 of 49
IRAUDAMP5 REV 3.3
20 kHz to 40 kHz, either higher “H” or lower “L.” The actual internal frequency is set
by potentiometer R113 - “INT FREQ.”
3. Switch S3 is an oscillator selector. This three-position switch is selectable for internal
self oscillator (middle position – “SELF”), or either internal (“INT”) or external
(“EXT”) clock synchronization.
PROTECTION
NORMAL
MUTE MUTE
+5V
R119
1k
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
U_3
74HC14
R120
100R
C114
10nF, 50V
+5V
I
E
S
SW
S3A
SW-3WAY_A-B
R109
1K
R110
100k
C110
1nF, 50V
C112
1200pF, 50V
D103
1N4148
CLK
R116
47R
CLK
I
E
S
SWS3B
SW-3WAY_A-B
EXT. CLK
A24497
J8
BNC
R115
47R
R114
100R
R113
5K POT
R112
820R
C111
100pF, 50V
Q103
MMBT5551
2
1S2
SW_H-L
R111
10K
C113
100pF, 50V
R117
47R
R118
1k
LED, Switches and Sync frequencies
Fig 31
Switching Frequency Lock / Synchronization Feature
For single-channel operation, the use of the self-oscillating switching scheme will yield the best
audio performance. The self-oscillating frequency, however, changes with the duty ratio. This
varying frequency can interfere with AM radio broadcasts, where a constant-switching frequency
with its harmonics shifted away from the AM carrier frequency is preferred. In addition to AM
broadcasts, multiple channels can also reduce audio performance at low power, and can lead to
increased residual noise. Clock frequency locking/synchronization can address these unwanted
characteristics.
Please note that the switching frequency lock / synchronization feature is not possible for all
frequencies and duty ratios, and operates within a limited frequency and duty-ratio range around
the self-oscillating frequency (Figure 32 below).
www.irf.com Page 29 of 49
IRAUDAMP5 REV 3.3
0
100
200
300
400
500
600
10% 20% 30% 40% 50% 60% 70% 80% 90%
Duty Cycle
Operating Frequency (kHz)
Typical Lock Frequency Range vs. PWM Duty Ratio
(Self-oscillating frequency set to 400 kHz with no input)
Fig 32
The output power range, for which frequency-locking is successful, depends on what the locking
frequency is with respect to the self-oscillating frequency. As illustrated in Figure 33, the locking
frequency is lowered (from 450kHz to 400kHz to 350kHz and then 300kHz) as the output power
range (where locking is achieved) is extended. Once locking is lost, however, the audio
performance degrades, but the increase in THD seems independent from the clock frequency.
Therefore, a 300 kHz clock frequency is recommended, as shown on Fig 34
It is possible to improve the THD performance by increasing the corner frequency of the high
pass filter (HPF) (R17 and C15 for Ch1 Fig 33) that is used to inject the clock signal, as shown in
Figure 33 below.
This drop in THD, however, comes at the cost of reducing the locking range. Resistor values of
up to 100 kOhms and capacitor values down to 10pF may be used.
+
-
..
0V
SYNC
R13
IN-
COMP
.
+VAA
IRS2092S
LO
VS
VCC
VB
-B
+B
LP Filter
0V
22k
R22
HO
INPUT
CH1
Integrator
COM
Modulator
and
Shift level
GND
33pF
C15
IRF6645
Q4
IRF6645
Q3
Switching Frequency Lock / Synchronization Feature
Fig 33
Self-oscillating frequency
Locking range
Self-oscillating frequency
Suggested clock frequency
for maximum locking range
www.irf.com Page 30 of 49
IRAUDAMP5 REV 3.3
In IRAUDAMP5, this switching frequency lock/synchronization feature (Fig 31 and Fig 33) is
achieved with either an internal or external clock input (selectable through S3). If an internal
(INT) clock is selected, an internally-generated clock signal is used, adjusted by setting
potentiometer R113 “INT FREQ.” If external (EXT) clock signal is selected, a 0-5V square-
wave (~50% duty ratio) logic signal must be applied to BNC connector J17.
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
%
100m 200200m 500m 1 2 5 10 20 50 100
W
Red CH1, = Self Oscillator @ 400kHz
Pink CH1, = Sync Oscillator @ 400kHz
Blue CH1, = Sync Oscillator @ 450kHz
Cyan CH1, = Sync Oscillator @ 350kHz
THD+N Ratio vs. Output Power for Different Switching Frequency Lock/Synchronization Conditions
Fig 34
www.irf.com Page 31 of 49
IRAUDAMP5 REV 3.3
Class D, Daughter Board IRS2092S Module CH1 Schematic
D4 R1
100R
R7
10R
R19
8.2k
R13
8.2K
R17
1.2k
D6
R9
10R
R30
10R
R32
10R
R5
3.3K
R41
10k
R43
0.0
R25
10K C14
0.1uF,100V
C18
3.3uF
R40
33k
+B
-B
SD VCC
R12
4.7K
R3
10R
D1
VSS
VAA
GND1
10uFC10
R21
1k
C23
1nF,250V
C21
1nF,250V
CH1
R26
4.7R
C17
0.1uF
R37
1R
R31
100K
Rp1
100C
-B
C28
47nF
R48
1K
R47
100K
Q7
MMBT5401DICT-ND
OTP CH1
R52
open
R50
open
LO 11
VS 13
HO 14
VCC 12
GND
2
VAA
1
COM 10
DT 9
OCSET
8
IN-
3
COMP
4
CSD
5
VSS
6
VREF
7
VB 15
CSH 16
U1
IRS2092S
C1
1nF
C30
10nF
CH1 Output to LPF1
+35V Bus
-35V Bus
+5V
-5V
Audio Gnd 1
SD
-35V Bus
+35V Bus
VAA
VSS
IN-1
CH1 O
+B
CH1
-B
OTP1
OC
Rp1 is thermally connected with Q3
C3
10uF
C32
0.1uF,100V
3 2
1
23
D-FET2
IRF6645
22uF
C5
C12
3.3uF
DS1
TP1
3 2
1
23
D-FET1
IRF6645
9
10
11
12
13
14
15
16
J2A
A26570-ND
1
2
3
4
5
6
J1A
A26568-ND
R46
3.01k
P1 1K
.
Fig 35
www.irf.com Page 32 of 49
IRAUDAMP5 REV 3.3
Class D, Daughter Board IRS2092S Module CH2 Schematic
D3
R20
8.2k
R18
1.2k
R4
10R
OC
-B
C9
47nF
R11
100K
R24
1K
R33
100K
Q1
MMBT5551
Q2
MMBT5401
Rp2
100C
R35
100K
R36
10K
R34
100K
C29
47nF
OTP CH2
C31
10nF,50V
R49
open
D7
R2
100R
R8
10R
R14
8.2K
D5
R10
10R
R28
10R
R27
10R
R6
3.3K
R42
10k
R44
0.0
R29
10K C15
0.1uF,100V
C19
3.3uF
R39
33k
+B
-B
SD
IN-2
VCC
R45
4.7K
D2
-5V
VAA
GND2
C16
3.3uF
10uFC11
R22
1k
C24
1nF,1250V
C22
1nF,250V
CH2
R23
4.7R
C13
0.1uF
R38
1R
R51
open
LO 11
VS 13
HO 14
VCC 12
GND
2
VAA
1
COM 10
DT 9
OCSET
8
IN-
3
COMP
4
CSD
5
VSS
6
VREF
7
VB 15
CSH 16
U2
IRS2092S
C2
1nF
CH2 Output to LPF2
+35V Bus
-35V Bus
+5V
-5V
Audio Gnd 2
SD
-35V Bus
+35V Bus
SDVSS
VCC
CH2 O
-B
CH2
-B
-B
OTP1 OTP2
OTP2
Rp2 is thermally connected with Q5
C4
10uF
C33
0.1uF,100V
22uF
C6
DS2
TP2
3 2
1
23
D-FET3
IRF6645
3 2
1
23
D-FET4
IRF6645
1
2
3
4
5
6
7
8
J2B
A26570-ND
7
8
9
10
11
12
J1B
A26568-ND
R53
3.01k
P2 1K
.
Fig 36
www.irf.com Page 33 of 49
IRAUDAMP5 REV 3.3
D4 R1
100R
R7
10R
R19
8.2k
R13
8.2K
R17
1.2k
D6
R9
10R
R30
10R
R32
10R
R5
3.3K
R41
10k
R43
0.0
R25
10K C14
0.1uF,100V
C18
3.3uF
R40
33k
+B
-B
SD VCC
R12
4.7K
R3
10R
D1
VSS
VAA
GND1
10uFC10
R21
1k
C23
1nF,250V
C21
1nF,250V
D3
R20
8.2k
R18
1.2k
R4
10R
CH1
OC
-B
R26
4.7R
C17
0.1uF
R37
1R
C9
47nF
R11
100K
R31
100K
Rp1
100C
R24
1K
R33
100K
Q1
MMBT5551
Q2
MMBT5401
Rp2
100C
-B
R35
100K
R36
10K
C28
47nF
R48
1K
R47
100K
Q7
MMBT5401DICT-ND
R34
100K
C29
47nF
OTP CH2
OTP CH1
C31
10nF,50V
R52
open
R50
open
R49
open
D7
LO 11
VS 13
HO 14
VCC 12
GND
2
VAA
1
COM 10
DT 9
OCSET
8
IN-
3
COMP
4
CSD
5
VSS
6
VREF
7
VB 15
CSH 16
U1
IRS2092S
C1
1nF
C30
10nF
CH1 Output to LPF1
+35V Bus
-35V Bus
+5V
-5V
Audio Gnd 1
SD
-35V Bus
+35V Bus
R2
100R
R8
10R
R14
8.2K
D5
R10
10R
R28
10R
R27
10R
R6
3.3K
R42
10k
R44
0.0
R29
10K C15
0.1uF,100V
C19
3.3uF
R39
33k
+B
-B
SD
IN-2
VCC
R45
4.7K
D2
-5V
VAA
GND2
C16
3.3uF
10uFC11
R22
1k
C24
1nF,1250V
C22
1nF,250V
CH2
R23
4.7R
C13
0.1uF
R38
1R
R51
open
LO 11
VS 13
HO 14
VCC 12
GND
2
VAA
1
COM 10
DT 9
OCSET
8
IN-
3
COMP
4
CSD
5
VSS
6
VREF
7
VB 15
CSH 16
U2
IRS2092S
C2
1nF
CH2 Output to LPF2
+35V Bus
-35V Bus
+5V
-5V
Audio Gnd 2
SD
-35V Bus
+35V Bus
VAA
SD
VSS
VSS
IN-1
VCC
CH1 O
+B
CH2 O
-B
CH1
CH2
-B
-B
-B
OTP1
OTP1 OTP2
OTP2
OC
Rp1 is thermally connected with Q3
Rp2 is thermally connected with Q5
C3
10uF
C4
10uF
C32
0.1uF,100V
C33
0.1uF,100V
3 2
1
23
D-FET2
IRF6645
22uF
C6
22uF
C5
C12
3.3uF
DS2
DS1
TP2
TP1
Class D, Daughter Board IRS2092S Module Schematic
3 2
1
23
D-FET1
IRF6645
3 2
1
23
D-FET3
IRF6645
3 2
1
23
D-FET4
IRF6645
9
10
11
12
13
14
15
16
J2A
A26570-ND
1
2
3
4
5
6
7
8
J2B
A26570-ND
1
2
3
4
5
6
J1A
A26568-ND
7
8
9
10
11
12
J1B
A26568-ND
R46
3.01k
R53
3.01k
P1 1K
P2 1K
SCH_DB_2092_Rev3.1
Fig 37
www.irf.com Page 34 of 49
IRAUDAMP5 REV 3.3
J5
R5
4.7R
R13
3.3K
1
2
J3
L1 22uH
R31
47k 1%
R58
100K
J6
R4
100R
R14
3.3K
R32
47k 1%
C32
1000uF,50V
C31
1000uF,50V
R57
100K
C27
OPEN
C26
0.1uF, 400V
C28
OPEN
L2
22uH
R48
10, 1W
R34
1K
R33
1K
C18
150pF, 500V
C17
150pF, 500V
CH1 OUT
CH2 OUT
CH 2 IN
CH 1 IN
1
2
J4
C33
OPEN
C34
OPEN
R39
470
R40
470
R49
2.2k
R3
100R
R1
100K
C2
10uF, 50V
C3
10uF, 50V
R2
100K
R6
4.7R
R7 47R
R8 47R
R9 10R
R10
47R
R11
47R
C1
10uF, 50V
R50
2.2k
R17
22k
R18
22k
C16
33pF
MUTE
C25
0.1uF, 400V
R47
10, 1W
C15
33pF
U374AHC1G04
U474AHC1G04
C19
2.2uF,16V
C20
2.2uF,16V
R27
47R
R28
47R
C23
0.47uF, 400V
C24
0.47uF, 400V
-5V
+5V
+5V
+5V
C5
10uF, 50V
C6
10uF, 50V
+5V
CLK
CLK
D5
D7
D8
D6
-B
+B
-B
+B
-B
+B
CH1 O
+B
CH2 O
-B
SD
IN-1
VCC
VCC
OC
IN-2
+5V
-5V
-5V
VSS
8
VR0
7
VR1
6
CLK
5
VDD 1
CS 2
SDATA 3
SIMUL 4
U_2
3310S06S
R108
C107
4.7uF, 16V
C108
10nF, 50V
SCLK
SDATAI
C109
4.7uF, 16V
CS
+5V
Control Vo lum e
R55
0.0
R56
0.0
IRS2092S_ MODULE
CH1 Feedback
CH2 Feedback
+5V
Audio in
Audio in
ZM4732ADICT
Z102
4.7V
R104
47R, 1W
C103
10uF, 50V
IN
GND
OUT
U_5 MC79M05
C102
10uF, 50V
R102
47R, 1W
C101
10uF, 50V
Vin
GND
Vout
U_4 MC78M05
ZM4732ADICT
Z101
4.7V D102
MA2YD2300
D101
MA2YD2300
C104
10uF, 50V
R101
47R, 1W
R103
47R, 1W
-B
-5V+5V
+B
C105
10uF, 50V
R105
10R
C106
10uF, 50V
Vin
GND
Vout
U_6
MC78M12
Z103
15V
Q102
MMBT5401
R107
4.7K
R106
47K
Z104
24V
Q101
FX941
VCC
+B
-B
HS1
VCC Power Supply +5V Power Supply -5V Power Supply
R71
OPEN
R72
OPEN
Class D, Mother Board Control Volume and Power Supplies Schematic
1
2
3
4
5
6
J1A
7
8
9
10
11
12
J1B
9
10
11
12
13
14
15
16
J2A
1
2
3
4
5
6
7
8
J2B
ZCEN
1
CS
2
SDATAI
3
VD+
4
DGRD
5
SCLK
6
SDATAO
7
MUTE
8
AINL 16
AGNDR 10
AOUTL 14
VA- 13
VA+ 12
AOUTR 11
AGNDL 15
AINR 9
U_?
CS3310
Trace under J7
Chassis Gnd
Heat Sink
VCC UVP
1
2
3
J7
+35V
-35V
Gnd
+
-
CH1
CH2
+
-
Fig 38
www.irf.com Page 35 of 49
IRAUDAMP5 REV 3.3
PROTECTION
R124
10k
R121
47k
R122
47k
CH1 O
CH2 O
Q106
MMBT5401
Q104
MMBT5401
C116
100uF, 16V
R141
47k
NORMAL
R123
1K
Q108
MMBT5551
S1
SW-PB
MUTE
1
2
3
6
5
4
P1
PVT412
1
2
J9
DC_PS
MUTE
Q105 MMBT5551
R125
10K
R126
100K
+B
Q10 9
MMBT5551
R139
47k
-B
SD
D10 5
1N4148
R138
4.7k
Z1 0 6
18V
Z1 0 7
18V
R145
47K
R146
47K
Q11 0
MMBT5551
R144
10k
D10 7
1N4148
D10 6
1N4148
C117
100uF, 16V
+5V
R142
68k
+5V
R119
1k
R136
68k
R135
82k
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
U_3
74HC14
R120
100R
C114
10nF, 50V
+5V
I
E
S
SW
S3A
SW-3WAY_A-B
R109
1K
R110
100k
C110
1nF, 50V
C112
1200pF, 50V
D10 3
1N4148
CLK
R116
47R
CLK
I
E
S
SWS3B
SW-3WAY_A-B
EXT. CLK
A24497
J8
BNC
R115
47R
R114
100R
R113
5K POT
R112
820R
C111
100pF, 50V
Q103
MMBT5551
2
1S2
SW_H-L
R111
10K
C113
100pF, 50V
R134
10k
R117
47R
R143
10K
SP MU TE
R118
1k
Tr ip an d re start
R129
6.8k
C115
10uF, 50V
-B
R140
10k
Z1 0 5
39V
DC protec t i on
OVP
R132
47k
Q10 7
MMB T5 5 5 1
D104
1N4148
R133
47k
DCP
DCP
R127
6.8k
R128
6.8k
R130
47K
R131
47K
R148
10k
R147
47k
Q11 1
MMBT5401
+B
R149
47K
C119
0.1uF, 50V
UVP
Z1 0 8
8.2V
R137
47k
-5V
OT
OT
CStart
Q112
MMB T5 5 5 1
-5V +5V
Z109
8.2V
R150
47k
R151
47k
+B
Class D, Mother Board Clock and House Keeping Schematic
Fig 39
www.irf.com Page 36 of 49
IRAUDAMP5 REV 3.3
IRAUDAMP5 Bill of Materials
Class D, Daughter Board:
Amp5_DB_2092_Rev 3.1_BOM
Designator Footprint PartType Quantity PART NO VENDER
C1, C2, C21,C22,C23,C24 805 1nF,250V,COG 6 445-2325-1-ND DIGI KEY
C3, C4 TAN-A 10uF, 16V, Tan 2 495-2236-1-ND DIGI KEY
C5, C6 TAN-B 10uF, 16V, Tan 2 399-3706-1-ND DIGI KEY
C9, C28, C29 0805 47nF,50V, X7R 3 PCC1836CT-ND DIGI KEY
C10, C11 TAN-B 10uF, 16V, Tan 2 399-3706-1-ND DIGI KEY
C12, C16, C18, C19 TAN-B 3.3uF, 16V, X7R 4 445-1432-1-ND DIGI KEY
C13, C17 0805 0.1uF,100V, X7R 2 399-3486-1-ND DIGI KEY
C14, C15, C32, C33 1206 0.1uF,100V, X7R 3 PCC2239CT-ND DIGI KEY
C20 0805 open 1 open
C30, C31 0805 10nF,50V, X7R 2 PCC103BNCT-ND DIGI KEY
D1, D2 SOD-323 BAV19WS-7-F 2 BAV19WS-FDICT-ND DIGI KEY
D3, D4 SOD-323 1N4148WS-7-F 2 1N4148WS-FDICT-ND DIGI KEY
D5, D6 SMA MURA120T3G 2 MURA120T3GOSCT-ND DIGI KEY
D7 SMA ES1D 1 ES1DFSCT-ND DIGI KEY
DS1, DS2 805 LTST-C171TBKT 2 160-1645-1-ND DIGI KEY
J1A CON EISA31 CON EISA31 1 A26568-ND DIGI KEY
J1B CON EISA31 CON EISA31 1 A26568-ND DIGI KEY
J2A CON_POWER CON_POWER 1 A26570-ND DIGI KEY
J2B CON_POWER CON_POWER 1 A26570-ND DIGI KEY
Q1 SOT23-BCE MMBT5551 1 MMBT5551FSCT-ND DIGI KEY
Q2, Q7 SOT23-BCE MMBT5401-7 2 MMBT5401-FDICT-ND DIGI KEY
www.irf.com Page 37 of 49
IRAUDAMP5 REV 3.3
D-FET1, D-FET2, D-FET3, D-FET4 Direct Fet SJ IRF6645 4 IRF6645 IR
R1, R2 0805 100R 2 P100ACT-ND DIGI KEY
R3,R4,R9,R10,R15,R16,R27,R28,R30,R32,R8 0805 10R 11 P10ACT-ND DIGI KEY
R5, R6 0805 3.3K 2 P3.3KACT-ND DIGI KEY
R7 1206 10R 1 P10ECT-ND DIGI KEY
R11, R31, R33, R34, R35, R47 0805 100K 2 P100KACT-ND DIGI KE Y
R12, R45 0805 4.7K 2 P4.7KACT-ND DIGI KEY
R13, R14,R19,R20 0805 8.2K 2 P8.2KACT-ND DIGI KEY
R24, R48 0805 1K 2 P1.0KACT-ND DIGI KEY
R7,R18 805 1.2k RHM1.2KARCT-ND DIGI KEY
R21, R22 0805 1k 2 P1.0KACT-ND DIGI KEY
R23, R26 0805 4.7R 2 P4.7ACT-ND DIGI KEY
R25, R29,R36,R41, R42 0805 10K 5 P10KACT-ND DIGI KEY
R37, R38 0805 1R 3 P1.0ACT-ND DIGI KEY
R39, R40 0805 33K 3 RHM33KARCT-ND DIGI KEY
R43, R44 0805 0 3 RHM0.0ARCT-ND DIGI KE Y
R49, R50, R51, R52, 1206 open 3 open
Rp1, Rp2 805 100C 3 594-2381-675-21007 MOUSER
P1,P2 ST-32 3mm SQ 1k ST32ETB102TR-ND DIGI KEY
R46,R53 805 3.01k RHM3.01KCCT-ND DIGI KEY
U1, U2 SOIC16 IR Driver 3 IRS2092S IR
www.irf.com Page 38 of 49
IRAUDAMP5 REV 3.3
Class D Motherboard:
IRAUDAMP5 MOTHERBOARD BILL OF MATERIAL
NO Designator # Footprint Part Type Part No Vender
1 C1, C5, C6, C101, C102, C103, C104, C105,
C106, C115 10 RB2/5 10uF, 50V 565-1106-ND Digikey
2 C2, C3 2 RB2/5 2.2uF, 50V 565-1103-ND Digikey
3 C7, C8, C9, C10 4 open
4 C11, C12, C13, C14 4 open
5 C15, C16 2 805 33pF 478-1281-1-ND Digikey
6 C17, C18 2 AXIAL0.19R 150pF, 500V 338-2598-ND Digikey
7 C19, C20 2 1206 2.2uF, 16V PCC1931CT-ND Digikey
8 C119 1 1206 0.1uF, 50V PCC104BCT-ND Digikey
9 C23, C24 2 CAP MKP 0.47uF, 400V 495-1315-ND Digikey
10
11 C25, C26 2 CAP MKPs 0.1uF, 400V 495-1311-ND Digikey
12 C27, C28, C29, C30, C40, C41, C42, C43,
C44, C45, C46, C47 12 805 OPEN
13 R29, R30, R55, R56, R60, R61, R62, R63,
R64, R65, R66, R67, R71, R72 14 805 OPEN
14 C31, C32 2 RB5/12_5 1000uF,50V 565-1114-ND Digikey
15 C33, C34, C48, C49 4 AXIAL0.1R OPEN - Digikey
16 C107, C109 2 805 4.7uF, 16V PCC2323CT-ND Digikey
17 C108, C114 2 805 10nF, 50V PCC103BNCT-ND Digikey
18 C110 1 805 1nF, 50V PCC102CGCT-ND Digikey
19 C111, C113 2 805 100pF, 50V PCC101CGCT-ND Digikey
20 C112 1 805 1200pF, 50V 478-1372-1-ND Digikey
21 C116, C117 2 rb2/5 100uF, 16V 565-1037-ND Digikey
22 D103, D104, D105, D106, D107 5 SOD-123 1N4148W-7-F 1N4148W-FDICT-ND Digikey
23 D5, D6, D7, D8 4 SMA MURA120T3G MURA120T3GOSCT-ND Digikey
24 D101, D102 2 SOD-123 MA2YD2300 MA2YD2300LCT-ND Digikey
25 HS1 1 Heat_S6in1 HEAT SINK 294-1086-ND Digikey
26 J1A, J1B 2 CON EISA-31 CON EISA31 A32934-ND Digikey
27 J2A, J2B 2 CON_POWER CON_POWER A32935-ND Digikey
28 J3, J4 2 MKDS5/2-9.5 277-1022 277-1271-ND or 651-1714971 Digikey or
Mouser
29 J5, J6 2 Blue RCA RCJ-055 CP-1422-ND Digikey
30 J7 1 J HEADER3 277-1272 277-1272-ND or 651-1714984 Digikey or
Mouser
31 J8 1 BNC_RA CON BNC A32248-ND Digikey
32 J9 1 ED1567 ED1567 ED1567 Digikey
33 L1, L2 2 Inductor
Sagami 7G17A-
Or
1D17A-220M
Sagami 7G17A-
Or
1D17A-220M
Inductors,
Inc
Or
ICE
Component
s, Inc.
34 NORMAL 1 Led rb2/5 404-1106-ND 160-1143-ND Digikey
35 P1 1 DIP-6 PVT412 PVT412PBF-ND Digikey
36 PROTECTION 1 Led rb2/5 404-1109-ND 160-1140-ND Digikey
37 Q101 1 SOT89 FX941 FCX491CT-ND Digikey
38 Q102, Q104, Q106, Q111 4 SOT23-BCE MMBT5401-7-F MMBT5401-FDICT-ND Digikey
39 Q103, Q105, Q107, Q108, Q109, Q110,
Q112 7 SOT23-BCE MMBT5551 MMBT5551-FDICT-ND Digikey
40 R1, R2, R57, R58, R110, R126 6 805 100K P100KACT-ND Digikey
41 R3, R4, R114 3 805 100R P100ACT-ND Digikey
42 R5, R6 2 1206 4.7R P4.7ECT-ND Digikey
43 R7, R8, R10, R11, R27, R28, R115, R116,
R117 9 805 47R P47ACT-ND Digikey
44 R9, R105 2 805 10R P10ACT-ND Digikey
45 R13, R14 2 805 3.3K, 1% P3.3KZCT-ND Digikey
46 R17, R18 2 805 22k P22KACT-ND Digikey
47
R106, R121, R122, R130, R131, R132,
R133, R137, R139, R141, R145, R146,
R147, R149, R150, R151
16 805 47k P47KACT-ND Digikey
48 R152 1 805 OPEN - Digikey
49 R55, R56 2 805 0.0 Ohms P0.0ACT-ND Digikey
50 R39, R40 2 805 470R P470ACT-ND Digikey
51 R21, R22, R23, R24 4 open
52 R120 1 1206 100R P100ECT-ND Digikey
53 R29P, R30P 2 open
54 R31, R32 2 2512 47K, 1% PT47KAFCT-ND Digikey
55 R33, R34 2 1206 1K P1.0KECT-ND Digikey
www.irf.com Page 39 of 49
IRAUDAMP5 REV 3.3
56 R109, R118, R119, R123 4 805 1K P1.0KACT-ND Digikey
57 R47, R48 2 2512 10, 1W PT10XCT Digikey
58 R49, R50 2 1206 2.2k P2.2KECT-ND Digikey
59 R68, R69 2 AXIAL-0.3 OPEN - Digikey
60 R101, R102, R103, R104 4 2512 47R, 1W PT47XCT-ND Digikey
61 R107, R138 2 805 4.7K P4.7KACT-ND Digikey
62 R108 1 V_Control CT2265 CT2265-ND Digikey
63 R111, R124, R125, R134, R140, R143,
R144, R148 8 805 10K P10KACT-ND Digikey
64 R112 1 805 820R P820ACT-ND Digikey
65 R113 1 POTs 5K POT 3362H-502LF-ND Digikey
66 R127, R128, R129 3 1206 6.8k P6.8KECT-ND Digikey
67 R135 1 805 82k P82KACT-ND Digikey
68 R136, R142 2 805 68k P68KACT-ND Digikey
69 S1 1 Switch SW-PB P8010S-ND Digikey
70 S2 1 SW-EG1908-ND SW_H-L EG1908-ND Digikey
71 S3 1 SW-EG1944-ND SW-3WAY EG1944-ND Digikey
72 U1, U2 2 open
73 U3, U4 2 SOT25 74AHC1G04 296-1089-1-ND Digikey
74 U7, U8 2 MINI5 open open
75 U9, U10 2 SO-8 open open
76 U_1 1 SOIC16 CS3310 73C8016 or 72J5420 Newark
77 U_2 1 N8A 3310S06S 3310-IR01
*Tachyonix
78 U_3 1 M14A 74HC14 296-1194-1-ND Digikey
79 U_4 1 TO-220 MC78M05CTG MC78M05CTGOS-ND Digikey
80 U_5 1 TO-220 LM79M05CT LM79M05CT-ND Digikey
81 U_6 1 TO-220 LM78M12CT LM78M12CT-ND Digikey
82 Z1, Z2, Z103 3 SOD-123 15V BZT52C15-FDICT-ND Digikey
83 Z101, Z102 2 SMA 4.7V 1SMA5917BT3GOSCT-ND Digikey
84 Z104 1 SOD-123 24V BZT52C24-FDICT-ND Digikey
85 Z105 1 SOD-123 39V BZT52C39-13-FDICT-ND Digikey
86 Z106, Z107 2 SOD-123 18V BZT52C18-FDICT-ND Digikey
87 Z108, Z109 2 SOD-123 8.2V BZT52C8V2-FDICT-ND Digikey
88 Volume Knob 1 Blue Knob MC21060 10M7578 Newark
89 Thermalloy TO-220 mounting kit with screw 3 Kit screw, ROHS AAVID 4880G 82K6096 Newark
90 1/2" Standoffs 4-40 5 Standoff 8401K-ND Digikey
91 4-40 Nut 5 100 per bag H724-ND Digikey
92 No. 4 Lock Washer 5 100 per bag H729-ND Digikey
*Tachyonix Corporation, 14 Gonaka Jimokuji Jimokuji-cho, Ama-gun Aichi, JAPAN 490-1111 http://www.tachyonix.co.jp
info@tachyonix.co.jp
www.irf.com Page 40 of 49
IRAUDAMP5 REV 3.3
IRAUDAMP5 Hardware
Voltage regulator mounting:
Fig 40
Item Description
1 Insulator Thermalfilm
2 Shoulder Washer
3 Flat Washer #4
4 No. 4-40 UNC-2B Hex Nu t
5 No. 4-40 UNC-2A X 1/2 Long Phillips
Pan Head Screw
6 Lockwasher, No.4
7 Heatsink
8 PCB
7
8
Item Description
1 Insulator Thermalfilm
2 Shoulder Washer
3 Flat Washer #4
4 No. 4-40 UNC-2B Hex Nu t
5 No. 4-40 UNC-2A X 1/2 Long Phillips
Pan Head Screw
6 Lockwasher, No.4
7 Heatsink
8 PCB
7
8
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IRAUDAMP5 REV 3.3
IRAUDAMP5 PCB Specifications
Figure 41
Motherboard and Daughter-board Layer Stack
Daughter board:
Material: FR4, UL 125C
Layer Stack: 2 Layers, 1 oz. Cu each, Through-hole plated
Dimensions: 3.125” x 1.52” x 0.062”
Solder Mask: LPI Solder mask, SMOBC on Top and Bottom Layers
Plating: Open copper solder finish
Silkscreen: On Top and Bottom Layers
Motherboard:
Material: FR4, UL 125C
Layer Stack: 2 Layers, 1 oz. Cu
Dimensions: 5.2” x 5.8” x 0.062”
Solder Mask: LPI Solder mask, SMOBC on Top and Bottom Layers
Plating: Open copper solder finish
Silkscreen: On Top and Bottom Layers
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IRAUDAMP5 REV 3.3
IRAUDAMP5 PCB layers
Class D, Daughter-board:
Figure 42 PCB Layout – Top-Side Solder-Mask and Silkscreen
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IRAUDAMP5 REV 3.3
Figure 43. PCB Layout – Bottom Layer and Pads and bottom silk screen
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IRAUDAMP5 REV 3.3
PCB Layout Motherboard:
Fig 44 Top Layer
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IRAUDAMP5 REV 3.3
Fig 45 Top silk screen
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IRAUDAMP5 REV 3.3
Fig 46 Bottom
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IRAUDAMP5 REV 3.3
Fig 47
4.0
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IRAUDAMP5 REV 3.3
Fig 48 Bottom Silkscreen
4.0
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IRAUDAMP5 REV 3.3
Revision changes descriptions
Revision Changes description Date
3.0 Released 7/27/07
3.1 Schematic error marked on red pages 31-33
R25 and R29 was connected to CSH
Fig 40 and Fig 41 updated
1/28/08
3.2 ROHS Compliant (BOM updated) 5/29/09
3.3 Deleted drawings author and e-mail 10/21/09
3.4 BOM updated :Ice Components as a second
vender of the inductor
10/28/09
3.5 Correct Deadtime setting graph Fig 12 05/03/11
WORLD HEADQUARTERS: 233 Kansas St., El Segund o, California 90245 Tel: (310) 252- 7105
Data and specifications subject to change wit hout notice. 7/27/2007
www.irf.com Page 50 of 49
IRAUDAMP5 REV 3.3
