0 Spartan-IIE 1.8V FPGA Family: Functional Description R DS077-2 (v1.0) November 15, 2001 0 0 Architectural Description Spartan-IIE Array The Spartan-IIE user-programmable gate array, shown in Figure 1, is composed of five major configurable elements: * * * * * IOBs provide the interface between the package pins and the internal logic CLBs provide the functional elements for constructing most logic Dedicated block RAM memories of 4096 bits each Clock DLLs for clock-distribution delay compensation and clock domain control Versatile multi-level interconnect structure As can be seen in Figure 1, the CLBs form the central logic structure with easy access to all support and routing structures. The IOBs are located around all the logic and memory elements for easy and quick routing of signals on and off the chip. Preliminary Product Specification Values stored in static memory cells control all the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Each of these elements will be discussed in detail in the following sections. Input/Output Block The Spartan-IIE IOB, as seen in Figure 2, features inputs and outputs that support a wide variety of I/O signaling standards. These high-speed inputs and outputs are capable of supporting various state of the art memory and bus interfaces. Table 1 lists several of the standards which are supported along with the required reference, output and termination voltages needed to meet the standard. The three IOB registers function either as edge-triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three registers and independent Clock Enable (CE) signals for each register. DLL BLOCK RAM BLOCK RAM BLOCK RAM BLOCK RAM DLL DLL DLL I/O LOGIC DS077_01_102201 Figure 1: Basic Spartan-IIE Family FPGA Block Diagram (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 R Spartan-IIE 1.8V FPGA Family: Functional Description T SR VCCO D Q Package Pin TFF CLK CK TCE EC VCC OE SR Programmable Bias and ESD Network I/O Package Pin SR O D Q Programmable Output Buffer OFF CK OCE VCC(1) EC Internal Reference Programmable Delay IQ I/O, VREF SR I D Package Pin Programmable Input Buffer Q IFF CK ICE To Next I/O To Other External VREF Inputs of Bank EC Notes: 1. For some I/O standards. DS077-2_01_051501 Figure 2: Spartan-IIE Input/Output Block (IOB) Table 1: Standards Supported by I/O (Typical Values) I/O Standard LVTTL (2-24 mA) LVCMOS2 Input Output Ref. Input Source Volt. Volt. Volt. (VREF) (VCCO) (VCCO) N/A 3.3 3.3 N/A 2.5 2.5 Board Term. Volt. (VTT) N/A N/A LVCMOS18 N/A 1.8 1.8 N/A PCI (3V, 33 MHz/66 MHz) N/A 3.3 3.3 N/A GTL 0.8 N/A N/A 1.2 GTL+ 1.0 N/A N/A 1.5 HSTL Class I 0.75 N/A 1.5 0.75 HSTL Class III 0.9 N/A 1.5 1.5 HSTL Class IV 0.9 N/A 1.5 1.5 SSTL3 Class I and II 1.5 N/A 3.3 1.5 SSTL2 Class I and II 1.25 N/A 2.5 1.25 CTT 1.5 N/A 3.3 1.5 AGP 1.32 N/A 3.3 N/A LVDS, Bus LVDS N/A N/A 2.5 N/A LVPECL N/A N/A 3.3 N/A 2 In addition to the CLK and CE control signals, the three registers share a Set/Reset (SR). For each register, this signal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asynchronous Clear. A feature not shown in the block diagram, but controlled by the software, is polarity control. The input and output buffers and all of the IOB control signals have independent polarity controls. Optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each pad. Prior to configuration all outputs not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive, but inputs may optionally be pulled up.The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins will float. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. All Spartan-IIE IOBs support IEEE 1149.1-compatible boundary scan testing. www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description An optional delay element at the D-input of this flip-flop eliminates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Bank 7 Bank 0 Each input buffer can be configured to conform to any of the low-voltage signaling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can used in close proximity to each other. See I/O Banking. Bank 6 Output Path In most signaling standards, the output high voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See I/O Banking. An optional weak-keeper circuit is connected to each output. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source signal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way helps eliminate bus chatter. Because the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signaling standard requires one. The provision of this voltage must comply with the I/O banking rules. I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification GCLK2 GCLK1 GCLK0 Bank 5 The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. Each output driver can be individually programmed for a wide range of low-voltage signaling standards. Each output buffer can source up to 24 mA and sink up to 48 mA. Drive strength and slew rate controls minimize bus transients. GCLK3 Spartan-IIE Device There are optional pull-up and pull-down resistors at each input for use after configuration. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides synchronous enable and disable. Bank 1 Bank 2 A buffer in the Spartan-IIE IOB input path routes the input signal either directly to internal logic or through an optional input flip-flop. Eight I/O banks result from separating each edge of the FPGA into two banks (see Figure 3). Each bank has multiple VCCO pins which must be connected to the same voltage. Voltage requirements are determined by the output standards in use. Bank 3 Input Path Bank 4 DS077-2_02_051501 Figure 3: Spartan-IIE I/O Banks In the TQ144 and PQ208 packages, the eight banks have VCCO connected together. Thus, only one VCCO level is allowed in these packages, although different VREF values are allowed in each of the eight banks. Within a bank, output standards may be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Table 2: Compatible Output Standards VCCO Compatible Standards 3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, LVPECL, GTL, GTL+ 2.5V SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus LVDS, GTL, GTL+ 1.8V LVCMOS18, GTL, GTL+ 1.5V HSTL I, HSTL III, HSTL IV, GTL, GTL+ Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. About one in six of the I/O pins in the bank assume this role. VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be connected to the external voltage source for correct operation. In a bank, inputs requiring VREF can be mixed with those that do not but only one VREF voltage may be used within a www.xilinx.com 1-800-255-7778 3 R Spartan-IIE 1.8V FPGA Family: Functional Description bank. The VCCO and VREF pins for each bank appear in the device pinout tables. nized in two similar slices; a single slice is shown in Figure 4. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device. All VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. In addition to the four basic LCs, the Spartan-IIE CLB contains logic that combines function generators to provide functions of five or six inputs. Table 3: I/O Banking TQ144 PQ208 FT256 FG456 VCCO Banks Interconnected as 1 8 independent VREF Banks 8 independent 8 independent Package Look-Up Tables Spartan-IIE function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The Spartan-IIE LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing. Configurable Logic Block Storage Elements The basic building block of the Spartan-IIE CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and storage element. The output from the function generator in each LC drives the CLB output or the D input of the flip-flop. Each Spartan-IIE CLB contains four LCs, orga- Storage elements in the Spartan-IIE slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. The D inputs can be driven either by function generators within the slice or directly from slice inputs, bypassing the function generators. 4 www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description COUT YB Y I4 G4 G2 Look-Up I3 Table O I2 G1 I1 G3 S D Carry and Control Logic YQ Q CK EC R F5IN BY SR XB X F4 I4 F2 Look-Up I3 Table O I2 F1 I1 F3 S D Carry and Control Logic XQ Q CK EC R BX CIN CLK CE DS001_04_091400 Figure 4: Spartan-IIE CLB Slice (two identical slices in each CLB) In addition to Clock and Clock Enable signals, each slice has synchronous set and reset signals (SR and BY). SR forces a storage element into the initialization state specified for it in the configuration. BY forces it into the opposite state. Alternatively, these signals may be configured to operate asynchronously. All control signals are independently invertible, and are shared by the two flip-flops within the slice. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification Additional Logic The F5 multiplexer in each slice combines the function generator outputs (Figure 5). This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the two F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected functions of up to 19 inputs. www.xilinx.com 1-800-255-7778 5 R Spartan-IIE 1.8V FPGA Family: Functional Description purposes. Simultaneously driving BUFTs onto the same net will not cause contention. If driven both High and Low, the net will be Low. CLB Slice Block RAM Spartan-IIE FPGAs incorporate several large block RAM memories. These complement the distributed RAM Look-Up Tables (LUTs) that provide shallow memory structures implemented in CLBs. MUXF6 LUT LUT Block RAM memory blocks are organized in columns. All Spartan-IIE devices contain two such columns, one along each vertical edge. These columns extend the full height of the chip. Each memory block is four CLBs high, and consequently, a Spartan-IIE device 16 CLBs high will contain four memory blocks per column, and a total of eight blocks. MUXF5 Slice LUT Table 4: Spartan-IIE Block RAM Amounts LUT MUXF5 Spartan-IIE Device # of Blocks Total Block RAM Bits XC2S50E 8 32K XC2S100E 10 40K XC2S150E 12 48K XC2S200E 14 56K XC2S300E 16 64K DS077-2_05-111501 Figure 5: F5 and F6 Multiplexers Each CLB has four direct feedthrough paths, one per LC. These paths provide extra data input lines or additional local routing that does not consume logic resources. Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capability for high-speed arithmetic functions. The Spartan-IIE CLB supports two separate carry chains, one per slice. The height of the carry chains is two bits per CLB. Each block RAM cell, as illustrated in Figure 6, is a fully synchronous dual-ported 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured independently, providing built-in bus-width conversion. The arithmetic logic includes an XOR gate that allows a 1-bit full adder to be implemented within an LC. In addition, a dedicated AND gate improves the efficiency of multiplier implementations. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions. RAMB4_S#_S# WEA ENA RSTA CLKA ADD[#:0] DIA[#:0] DOA[#:0] BUFTs Each Spartan-IIE CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. The IOBs on the left and right sides can also drive the on-chip busses. See Dedicated Routing, page 8. Each Spartan-IIE BUFT has an independent 3-state control pin and an independent input pin. The 3-state control pin is an active-Low enable (T). When all BUFTs on a net are disabled, the net is High. There is no need to instantiate a pull-up unless desired for simulation 6 www.xilinx.com 1-800-255-7778 WEB ENB RSTB CLKB ADDRB[#:0] DIB[#:0] DOB[#:0] DS001_05_060100 Figure 6: Dual-Port Block RAM DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description Table 5 shows the depth and width aspect ratios for the block RAM. To Adjacent GRM Table 5: Block RAM Port Aspect Ratios Width Depth ADDR Bus Data Bus 1 4096 ADDR<11:0> DATA<0> 2 2048 ADDR<10:0> DATA<1:0> 4 1024 ADDR<9:0> DATA<3:0> 8 512 ADDR<8:0> DATA<7:0> 16 256 ADDR<7:0> To Adjacent GRM GRM To Adjacent GRM To Adjacent GRM Direct Connection To Adjacent CLB DATA<15:0> The Spartan-IIE block RAM also includes dedicated routing to provide an efficient interface with both CLBs and other block RAMs. CLB Direct Connection To Adjacent CLB DS001_06_032300 Figure 7: Spartan-IIE Local Routing General Purpose Routing Programmable Routing It is the longest delay path that limits the speed of any design. Consequently, the Spartan-IIE routing architecture and its place-and-route software were defined jointly to minimize long-path delays and yield the best system performance. The joint optimization also reduces design compilation times because the architecture is software-friendly. Design cycles are correspondingly reduced due to shorter design iteration times. Most Spartan-IIE signals are routed on the general purpose routing, and consequently, the majority of interconnect resources are associated with this level of the routing hierarchy. The general routing resources are located in horizontal and vertical routing channels associated with the rows and columns of CLBs. The general-purpose routing resources are listed below. * The software automatically uses the best available routing based on user timing requirements. The details are provided here for reference. * Local Routing * The local routing resources, as shown in Figure 7, provide the following three types of connections: * * * Interconnections among the LUTs, flip-flops, and General Routing Matrix (GRM), described below. Internal CLB feedback paths that provide high-speed connections to LUTs within the same CLB, chaining them together with minimal routing delay Direct paths that provide high-speed connections between horizontally adjacent CLBs, eliminating the delay of the GRM * Adjacent to each CLB is a General Routing Matrix (GRM). The GRM is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the CLB gains access to the general purpose routing. 24 single-length lines route GRM signals to adjacent GRMs in each of the four directions. 96 buffered Hex lines route GRM signals to other GRMs six blocks away in each one of the four directions. Organized in a staggered pattern, Hex lines may be driven only at their endpoints. Hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). One third of the Hex lines are bidirectional, while the remaining ones are unidirectional. 12 Longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. Vertical Longlines span the full height of the device, and horizontal ones span the full width of the device. I/O Routing Spartan-IIE devices have additional routing resources around their periphery that form an interface between the CLB array and the IOBs. This additional routing, called the VersaRingTM routing, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing PCB layouts. Time-to-market is reduced, since PCBs and other system components can be manufactured while the logic design is still in progress. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 7 R Spartan-IIE 1.8V FPGA Family: Functional Description Dedicated Routing * Some classes of signal require dedicated routing resources to maximize performance. In the Spartan-IIE architecture, dedicated routing resources are provided for two classes of signal. * Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus lines are provided per CLB row, permitting multiple busses within a row, as shown in Figure 8. Two dedicated nets per CLB propagate carry signals vertically to the adjacent CLB. 3-State Lines CLB CLB CLB CLB DS001_07_090600 Figure 8: BUFT Connections to Dedicated Horizontal Bus Lines Global Routing Global Routing resources distribute clocks and other signals with very high fanout throughout the device. Spartan-IIE devices include two tiers of global routing resources referred to as primary and secondary global routing resources. * * selected either from these pads or from signals in the general purpose routing. Global Clock Rows The primary global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. Each global clock net can drive all CLB, IOB, and block RAM clock pins. The primary global nets may only be driven by global buffers. There are four global buffers, one for each global net. The secondary global routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across the bottom. From these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. These secondary resources are more flexible than the primary resources since they are not restricted to routing only to clock pins. Global Clock Column Global Clock Spine GCLKBUF1 GCLKPAD1 GCLKBUF0 GCLKPAD0 DS001_08_060100 Figure 9: Global Clock Distribution Network Clock Distribution The Spartan-IIE family provides high-speed, low-skew clock distribution through the primary global routing resources described above. A typical clock distribution net is shown in Figure 9. Four global buffers are provided, two at the top center of the device and two at the bottom center. These drive the four primary global nets that in turn drive any clock pin. Four dedicated clock pads are provided, one adjacent to each of the global buffers. The input to the global buffer is 8 GCLKPAD2 GCLKBUF2 GCLKPAD3 GCLKBUF3 Delay-Locked Loop (DLL) Associated with each global clock input buffer is a fully digital Delay-Locked Loop (DLL) that can eliminate skew between the clock input pad and internal clock-input pins throughout the device. Each DLL can drive two global clock networks. The DLL monitors the input clock and the distributed clock, and automatically adjusts a clock delay element (Figure 10). Additional delay is introduced such that clock edges reach internal flip-flops exactly one clock period after they arrive at the input. This closed-loop system effectively eliminates clock-distribution delay by ensuring that clock www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description edges arrive at internal flip-flops in synchronism with clock edges arriving at the input. Variable Delay Line CLKIN CLKOUT Clock Distribution Network Boundary Scan x132_01_091799 The TAP uses dedicated package pins that always operate using LVTTL. For TDO to operate using LVTTL, the VCCO for Bank 2 must be 3.3V. Otherwise, TDO switches rail-to-rail between ground and VCCO. The boundary-scan input pins (TDI, TMS, TCK) do not have a VCCO requirement and operate with either 2.5V or 3.3V input signalling levels. Spartan-IIE devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP also supports two USERCODE instructions and internal scan chains. Control CLKFB Figure 10: Delay-Locked Loop Block Diagram In addition to eliminating clock-distribution delay, the DLL provides advanced control of multiple clock domains. The DLL provides four quadrature phases of the source clock, can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. The phase-shifted output have optional duty-cycle correction (Figure 11). 0 90 180 270 0 In order to guarantee that the system clock is operating correctly prior to the FPGA starting up after configuration, the DLL can delay the completion of the configuration process until after it has achieved lock. 90 180 270 t Boundary-scan operation is independent of individual IOB configurations, and unaffected by package type. All IOBs, including unbonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. Retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. Table 6 lists the boundary-scan instructions supported in Spartan-IIE FPGAs. Internal signals can be captured during EXTEST by connecting them to unbonded or unused IOBs. They may also be connected to the unused outputs of IOBs defined as unidirectional input pins. This technique partially compensates for the absence of INTEST support. CLKIN CLK2X CLKDV_DIVIDE=2 CLKDV Table 6: Boundary-Scan Instructions DUTY_CYCLE_CORRECTION=FALSE Boundary-Scan Command Binary Code[4:0] EXTEST 00000 Enables boundary-scan EXTEST operation SAMPLE 00001 Enables boundary-scan SAMPLE operation USR1 00010 Access user-defined register 1 USR2 00011 Access user-defined register 2 CFG_OUT 00100 Access the configuration bus for Readback Figure 11: DLL Output Characteristics CFG_IN 00101 The DLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the DLL can be used to deskew a board level clock among multiple Spartan-IIE devices. Access the configuration bus for Configuration INTEST 00111 Enables boundary-scan INTEST operation CLK0 CLK90 CLK180 CLK270 Description DUTY_CYCLE_CORRECTION=TRUE CLK0 CLK90 CLK180 CLK270 x132_07_092599 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 9 R Spartan-IIE 1.8V FPGA Family: Functional Description Table 6: Boundary-Scan Instructions (Continued) Boundary-Scan Command Binary Code[4:0] USRCODE 01000 Enables shifting out USER code IDCODE 01001 Enables shifting out of ID Code HIZ The public boundary-scan instructions are available prior to configuration. After configuration, the public instructions remain available together with any USERCODE instructions installed during the configuration. While the SAMPLE and BYPASS instructions are available during configuration, it is recommended that boundary-scan operations not be performed during this transitional period. Description 01010 In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA, and also to read back the configuration data. Disables output pins while enabling the Bypass Register JSTART 01100 Clock the start-up sequence when StartupClk is TCK BYPASS 11111 Enables BYPASS RESERVED All other codes Xilinx reserved instructions To facilitate internal scan chains, the User Register provides three outputs (Reset, Update, and Shift) that represent the corresponding states in the boundary-scan internal state machine. Figure 12 is a diagram of the Spartan-IIE family boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. DATA IN IOB.T 0 1 0 IOB IOB IOB IOB sd D D Q 1 LE IOB IOB Q IOB 1 sd D Q D Q 0 IOB IOB LE IOB IOB IOB IOB IOB IOB IOB IOB 1 IOB.I 0 1 IOB TDI 0 Instruction Register Q D Q LE 1 0 IOB.Q IOB Bypass Register sd D M TDO U X IOB.T 0 1 0 sd D Q D Q 1 LE 1 0 sd D Q D Q LE 1 IOB.I 0 DATAOUT SHIFT/ CAPTURE UPDATE CLOCK DATA REGISTER EXTEST DS001_09_032300 Figure 12: Spartan-IIE Family Boundary Scan Logic 10 www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description Bit Sequence The bit sequence within each IOB is: In, Out, 3-State. The input-only pins contribute only the In bit to the boundary scan I/O data register, while the output-only pins contributes all three bits. From a cavity-up view of the chip (as shown in the FPGA Editor), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 13. BSDL (Boundary Scan Description Language) files for Spartan-IIE family devices are available on the Xilinx website, in the File Download area. Bit 0 ( TDO end) Bit 1 Bit 2 For HDL design entry, the Xilinx FPGA development system provides interfaces to several synthesis design environments. A standard interface-file specification, Electronic Design Interchange Format (EDIF), simplifies file transfers into and out of the development system. Spartan-IIE FPGAs are supported by a unified library of standard functions. This library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, I/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. The design environment supports hierarchical design entry, with high-level designs that comprise major functional blocks, while lower-level designs define the logic in these blocks. These hierarchical design elements are automatically combined by the implementation tools. Different design entry tools can be combined within a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design. TDO.T TDO.O Top-edge IOBs (Right to Left) Left-edge IOBs (Top to Bottom) MODE.I Design Implementation Bottom-edge IOBs (Left to Right) Right-edge IOBs (Bottom to Top) (TDI end) BSCANT.UPD DS001_10_032300 Figure 13: Boundary Scan Bit Sequence Development System Spartan-IIE FPGAs are supported by the Xilinx ISE Foundation and Alliance CAE tools. The basic methodology for Spartan-IIE design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and simulation, while Xilinx provides proprietary architecture-specific tools for implementation. The Xilinx development system is integrated under the Xilinx Project Navigator software, providing designers with a common user interface regardless of their choice of entry and verification tools. The software simplifies the selection of implementation options with pull-down menus and on-line help. Application programs ranging from schematic capture to placement and routing can be accessed through the software. The program command sequence is generated prior to execution, and stored for documentation. Several advanced software features facilitate Spartan-IIE design. CORE GeneratorTM functions, for example, include macros with relative location constraints to guide their placement. They help ensure optimal implementation of common functions. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification The place-and-route tools automatically provide the implementation flow described in this section. The partitioner takes the EDIF netlist for the design and maps the logic into the architectural resources of the FPGA (CLBs and IOBs, for example). The placer then determines the best locations for these blocks based on their interconnections and the desired performance. Finally, the router interconnects the blocks. The algorithms support fully automatic implementation of most designs. For demanding applications, however, the user can exercise various degrees of control over the process. User partitioning, placement, and routing information is optionally specified during the design-entry process. The implementation of highly structured designs can benefit greatly from basic floorplanning. The implementation software incorporates timing-driven placement and routing. Designers specify timing requirements along entire paths during design entry. The timing path analysis routines then recognize these user-specified requirements and accommodate them. Timing requirements are entered in a form directly relating to the system requirements, such as the targeted clock frequency, or the maximum allowable delay between two registers. In this way, the overall performance of the system along entire signal paths is automatically tailored to user-generated specifications. Specific timing information for individual nets is unnecessary. Design Verification In addition to conventional software simulation, FPGA users can use in-circuit debugging techniques. Because Xilinx www.xilinx.com 1-800-255-7778 11 R Spartan-IIE 1.8V FPGA Family: Functional Description devices are infinitely reprogrammable, designs can be verified in real time without the need for extensive sets of software simulation vectors. The development system supports both software simulation and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the netlist for use by the simulator. Alternatively, the user can verify timing-critical portions of the design using the static timing analyzer. For in-circuit debugging, Xilinx offers a download and readback cable, which connects the FPGA in the target system to a PC or workstation. After downloading the design into the FPGA, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. Simple modifications can be downloaded into the system in a matter of minutes. Configuration Configuration is the process by which the bitstream of a design, as generated by the Xilinx development software, is loaded into the internal configuration memory of the FPGA. Spartan-IIE devices support both serial configuration, using the master/slave serial and JTAG modes, as well as byte-wide configuration employing the Slave Parallel mode. Configuration File Spartan-IIE devices are configured by sequentially loading frames of data that have been concatenated into a configuration file. Table 7 shows how much nonvolatile storage space is needed for Spartan-IIE devices. It is important to note that, while a PROM is commonly used to store configuration data before loading them into the FPGA, it is by no means required. Any of a number of different kinds of under populated nonvolatile storage already available either on or off the board (for example, hard drives, FLASH cards, and so on) can be used. For more information on configuration without a PROM, refer to XAPP098, The Low-Cost, Efficient Serial Configuration of Spartan FPGAs. Table 7: Spartan-IIE Configuration File Size Device Configuration File Size (Bits) XC2S50E 630,048 XC2S100E 863,840 XC2S150E 1,134,496 XC2S200E 1,442,016 XC2S300E 1,875,648 Modes Spartan-IIE devices support the following four configuration modes: * * * * Slave Serial mode Master Serial mode Slave Parallel mode Boundary-scan mode The Configuration mode pins (M2, M1, M0) select among these configuration modes with the option in each case of having the IOB pins either pulled up or left floating prior to configuration. The selection codes are listed in Table 8. Configuration through the boundary-scan port is always available, independent of the mode selection. Selecting the boundary-scan mode simply turns off the other modes. The three mode pins have internal pull-up resistors, and default to a logic High if left unconnected. Table 8: Configuration Modes Preconfiguration Pull-ups M0 M1 M2 CCLK Direction Data Width Serial DOUT No 0 0 0 Out 1 Yes Yes 0 0 1 Slave Parallel mode (SelectMAP) Yes 0 1 0 In 8 No No 0 1 1 Boundary-Scan mode Yes 1 0 0 N/A 1 No No 1 0 1 Yes 1 1 0 In 1 Yes No 1 1 1 Configuration Mode Master Serial mode Slave Serial mode 12 www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description Signals There are two kinds of pins that are used to configure Spartan-IIE devices: Dedicated pins perform only specific configuration-related functions; the other pins can serve as general purpose I/Os once user operation has begun. The dedicated pins comprise the mode pins (M2, M1, M0), the configuration clock pin (CCLK), the PROGRAM pin, the DONE pin and the boundary-scan pins (TDI, TDO, TMS, TCK). Depending on the selected configuration mode, CCLK may be an output generated by the FPGA, or may be generated externally, and provided to the FPGA as an input. Configuration at Power-up VCCO AND Configuration During User Operation No User Pulls PROGRAM Low VCCINT High? Yes Note that some configuration pins can act as outputs. For correct operation, these pins require a VCCO of 3.3V to drive an LVTTL signal or 2.5V to drive an LVCMOS signal. All the relevant pins fall in banks 2 or 3. FPGA Drives INIT and DONE Low For a more detailed description than that given below, see DS077-4, Spartan-IIE 1.8V FPGA Family: Pinout Tables and XAPP176, Spartan-II FPGA Series Configuration and Readback. Clear Configuration Memory The Process The sequence of steps necessary to configure Spartan-IIE devices are shown in Figure 14. The overall flow can be divided into three different phases. * * * * Yes No Delay Configuration Initiating configuration Configuration memory clear Loading data frames Start-up User Holding INIT Low? The memory clearing and start-up phases are the same for all configuration modes; however, the steps for the loading of data frames are different. Thus, the details for data frame loading are described separately in the sections devoted to each mode. Initiating Configuration There are two different ways to initiate the configuration process: applying power to the device or asserting the PROGRAM input. Configuration on power-up occurs automatically unless it is delayed by the user, as described in a separate section below. The waveform for configuration on power-up is shown in DS077-3, Spartan-IIE 1.8V FPGA Family, DC and Switching Characteristics. Before configuration can begin, VCCO Bank 2 must be greater than 1.0V. Furthermore, all VCCINT power pins must be connected to a 1.8V supply. For more information on delaying configuration, see Clearing Configuration Memory, page 14. Once in user operation, the device can be re-configured simply by pulling the PROGRAM pin Low. The device acknowledges the beginning of the configuration process by driving DONE Low, then enters the memory-clearing phase. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification User Holding PROGRAM Low? Delay Configuration www.xilinx.com 1-800-255-7778 Yes No FPGA Samples Mode Pins Load Configuration Data Frames CRC Correct? No FPGA Drives INIT Low Abort Start-up Yes Start-up Sequence FPGA Drives DONE High, Activates I/Os, Releases GSR net User Operation DS001_11_111501 Figure 14: Configuration Flow Diagram 13 R Spartan-IIE 1.8V FPGA Family: Functional Description Clearing Configuration Memory During start-up, the device performs four operations: The device indicates that clearing the configuration memory is in progress by driving INIT Low. 1. The assertion of DONE. The failure of DONE to go High may indicate the unsuccessful loading of configuration data. 2. The release of the Global Three State (GTS). This activates all the I/Os. 3. The release of the Global Set Reset (GSR). This allows all flip-flops to change state. 4. The assertion of Global Write Enable (GWE). This allows all RAMs and flip-flops to change state. Delaying Configuration At this time, the user can delay configuration by holding either PROGRAM or INIT Low, which causes the device to remain in the memory clearing phase. Note that the bidirectional INIT line is driving a Low logic level during memory clearing. Thus, to avoid contention, use an open-drain driver to keep INIT Low. With no delay in force, the device indicates that the memory is completely clear by driving INIT High. The FPGA samples its mode pins on this Low-to-High transition. Loading Configuration Data Once INIT is High, the user can begin loading configuration data frames into the device. The details of loading the configuration data are discussed in the sections treating the configuration modes individually. The sequence of operations necessary to load configuration data using the serial modes is shown in Figure 16. Loading data using the Slave Parallel mode is shown in Figure 19, page 18. CRC Error Checking After the loading of configuration data, a CRC value embedded in the configuration file is checked against a CRC value calculated within the FPGA. If the CRC values do not match, the FPGA drives INIT Low to indicate that an error has occurred and configuration is aborted. To reconfigure the device, the PROGRAM pin should be asserted to reset the configuration logic. Recycling power also resets the FPGA for configuration. See Clearing Configuration Memory. Start-up The start-up sequence oversees the transition of the FPGA from the configuration state to full user operation. A match of CRC values, indicating a successful loading of the configuration data, initiates the sequence. 14 By default, these operations are synchronized to CCLK. The entire start-up sequence lasts eight cycles, called C0-C7, after which the loaded design is fully functional. The four operations can be selected to switch on any CCLK cycle C1-C6 through settings in the Xilinx Development Software. The default timing for start-up is shown in the top half of Figure 15; heavy lines show default settings. The default Start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle later, the Global Set/Reset (GSR) and Global Write Enable (GWE) signals are released. This permits the internal storage elements to begin changing state in response to the logic and the user clock. The bottom half of Figure 15 shows another commonly used version of the start-up timing known as Sync-to-DONE. This version makes the GTS, GSR, and GWE events conditional upon the DONE pin going High. This timing is important for a daisy chain of multiple FPGAs in serial mode, since it ensures that all FPGAs go through start-up together, after all their DONE pins have gone High. Sync-to-DONE timing is selected by setting the GTS, GSR, and GWE cycles to a value of DONE in the configuration options. This causes these signals to transition one clock cycle after DONE externally transitions High. The sequence can also be paused at any stage until lock has been achieved on any or all DLLs. www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description Default Cycles After INIT Goes High Start-up CLK Phase 0 1 2 3 4 5 6 7 User Load One Configuration Bit on Next CCLK Rising Edge DONE GTS End of Configuration Data File? GSR GWE No Yes To CRC Check Sync to DONE DS001_14_032300 Start-up CLK Figure 16: Loading Serial Mode Configuration Data Phase 0 1 2 3 4 5 6 7 Slave Serial Mode In Slave Serial mode, the FPGA's CCLK pin is driven by an external source, allowing the FPGA to be configured from other logic devices such as microprocessors or in a daisy-chain configuration. Figure 17 shows connections for a Master Serial FPGA configuring a Slave Serial FPGA from a PROM. A Spartan-IIE device in slave serial mode should be connected as shown for the third device from the left. Slave Serial mode is selected by a <11x> on the mode pins (M0, M1, M2). The weak pull-ups on the mode pins make slave serial the default mode if the pins are left unconnected. DONE High DONE GTS GSR GWE DS001_13_090600 The serial bitstream must be setup at the DIN input pin a short time before each rising edge of an externally generated CCLK. Figure 15: Start-Up Waveforms Serial Modes There are two serial configuration modes. In Master Serial mode, the FPGA controls the configuration process by driving CCLK as an output. In Slave Serial mode, the FPGA passively receives CCLK as an input from an external agent (e.g., a microprocessor, CPLD, or second FPGA in master mode) that is controlling the configuration process. In both modes, the FPGA is configured by loading one bit per CCLK cycle. The MSB of each configuration data byte is always written to the DIN pin first. See Figure 16 for the sequence for loading data into the Spartan-IIE FPGA serially. This is an expansion of the "Load Configuration Data Frames" block in Figure 14, page 13. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification Timing for Slave Serial mode is shown in DS077-3, Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics. Daisy Chain Multiple FPGAs in Slave Serial mode can be daisy-chained for configuration from a single source. After an FPGA is configured, data for the next device is sent to the DOUT pin. Data on the DOUT pin changes on the rising edge of CCLK. Note that DOUT changes on the falling edge of CCLK for some Xilinx families but mixed daisy chains are allowed. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are High. For more information, see Start-up, page 14. www.xilinx.com 1-800-255-7778 15 R Spartan-IIE 1.8V FPGA Family: Functional Description 3.3V M0 M1 M2 VCCO VCCINT 1.8V 3.3V 3.3V 3.3V 3.3 K M0 M1 M2 DOUT VCCO VCCINT DIN DOUT CCLK Spartan-IIE (Master Serial) VCC CCLK CLK Xilinx PROM Spartan-IIE (Slave) DATA DIN CE PROGRAM DONE 1.8V CEO RESET/OE INIT GND PROGRAM DONE GND INIT GND PROGRAM DS077-2_04_102201 Notes: 1. If the DriveDone configuration option is not active for any of the FPGAs, pull up DONE with a 3.3K resistor. Figure 17: Master/Slave Serial Configuration Circuit Diagram Master Serial Mode In Master Serial mode, the CCLK output of the FPGA drives a Xilinx PROM which feeds a serial stream of configuration data to the FPGA's DIN input. Figure 17 shows a Master Serial FPGA configuring a Slave Serial FPGA from a PROM. A Spartan-IIE device in Master Serial mode should be connected as shown for the device on the left side. Master Serial mode is selected by a <00x> on the mode pins (M0, M1, M2). The PROM RESET pin is driven by INIT, and the CE input is driven by DONE. For more information on serial PROMs, see the Spartan Serial PROM data sheet at www.xilinx.com/partinfo/ds078.pdf. The interface is identical to the slave serial mode except that an oscillator internal to the FPGA is used to generate the configuration clock (CCLK). Any of a number of different frequencies ranging from 4 to 60 MHz can be set using the ConfigRate option in the Xilinx development software. When selecting a CCLK frequency, ensure that the serial PROM and any daisy-chained FPGAs are fast enough to support the clock rate. On power-up, while the first 60 bytes of the configuration data are being loaded, the CCLK frequency is always 2.5 MHz. This frequency is used until the ConfigRate bits, part of the configuration file, have been loaded into the FPGA, at which point the frequency changes to the selected ConfigRate. Unless a different frequency is specified in the design, the default ConfigRate is 4 MHz. 16 The FPGA accepts one bit of configuration data on each rising CCLK edge. After the FPGA has been loaded, the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge. The timing for Master Serial mode is shown in DS077-3, Spartan-IIE, 1.8V FPGA Family: DC and Switching Characteristics. Slave Parallel Mode (SelectMAP) The Slave Parallel mode, also know as SelectMAP, is the fastest configuration option. Byte-wide data is written into the FPGA. A BUSY flag is provided for controlling the flow of data at a clock frequency above 50 MHz. Figure 18, page 17 shows the connections for two Spartan-IIE devices using the Slave Parallel mode. Slave Parallel mode is selected by a <011> on the mode pins (M0, M1, M2). The agent controlling configuration is not shown. Typically, a processor, a microcontroller, or CPLD controls the Slave Parallel interface. The controlling agent provides byte-wide configuration data, CCLK, a Chip Select (CS) signal and a Write signal (WRITE). If BUSY is asserted (High) by the FPGA, the data must be held until BUSY goes Low. After configuration, the pins of the Slave Parallel port (D0-D7) can be used as additional user I/O. Alternatively, the port may be retained to permit high-speed 8-bit readback. Then data can be read by de-asserting WRITE. If retention is selected, prohibit the D0-D7 pins from being used as user I/O. See Readback, page 18. www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description DATA[7:0] CCLK WRITE BUSY 2.5V 2.5V M1 M2 M1 M2 M0 M0 Spartan-IIE Spartan-IIE D0:D7 D0:D7 CCLK CCLK WRITE WRITE BUSY CS(0) BUSY CS(1) CS CS PROGRAM PROGRAM DONE INIT GND DONE INIT GND DONE INIT PROGRAM DS077-2_06_051501 Figure 18: Slave Parallel Configuration Circuit Diagram Multiple Spartan-IIE FPGAs can be configured using the Slave Parallel mode, and be made to start-up simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, WRITE, and BUSY pins of all the devices in parallel. The individual devices are loaded separately by asserting the CS pin of each device in turn and writing the appropriate data. Sync-to-DONE start-up timing is used to ensure that the start-up sequence does not begin until all the FPGAs have been loaded. See Start-up, page 14. The timing for Slave Parallel mode is shown in DS077-3, Spartan-IIE, 1.8V FPGA Family: DC and Switching Characteristics. For the present example, the user holds WRITE and CS Low throughout the sequence of write operations. Note that when CS is asserted on successive CCLKs, WRITE must remain either asserted or de-asserted. Otherwise an abort will be initiated, as in the next section. 1. Drive data onto D0-D7. Note that to avoid contention, the data source should not be enabled while CS is Low and WRITE is High. Similarly, while WRITE is High, no more than one device's CS should be asserted. 2. On the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance will instead occur on the first clock after BUSY goes Low, and the data must be held until this happens. 3. Repeat steps 1 and 2 until all the data has been sent. 4. De-assert CS and WRITE. Write When using the Slave Parallel Mode, write operations send packets of byte-wide configuration data into the FPGA. Figure 19, page 18 shows a flowchart of the write sequence used to load data into the Spartan-IIE FPGA. This is an expansion of the "Load Configuration Data Frames" block in Figure 14, page 13. DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 17 R Spartan-IIE 1.8V FPGA Family: Functional Description If CCLK is slower than FCCNH, the FPGA will never assert BUSY. In this case, the above handshake is unnecessary, and data can simply be entered into the FPGA every CCLK cycle. Abort After INIT Goes High To abort configuration during a write sequence, de-assert WRITE while holding CS Low. The abort operation is initiated at the rising edge of CCLK. The device will remain BUSY until the aborted operation is complete. After aborting configuration, data is assumed to be unaligned to word boundaries and the FPGA requires a new synchronization word prior to accepting any new packets. User Drives WRITE and CS Low Boundary-Scan Configuration Mode Load One Configuration Byte on Next CCLK Rising Edge FPGA Driving BUSY High? In the boundary-scan mode, no nondedicated pins are required, configuration being done entirely through the IEEE 1149.1 Test Access Port (TAP). Configuration through the TAP uses the special CFG_IN instruction. This instruction allows data input on TDI to be converted into data packets for the internal configuration bus. Yes The following steps are required to configure the FPGA through the boundary-scan port. 1. No End of Configuration Data File? No Yes User Drives WRITE and CS High Load the CFG_IN instruction into the boundary-scan instruction register (IR) 2. Enter the Shift-DR (SDR) state 3. Shift a standard configuration bitstream into TDI 4. Return to Run-Test-Idle (RTI) 5. Load the JSTART instruction into IR 6. Enter the SDR state 7. Clock TCK (if selected) through the startup sequence (the length is programmable) 8. Return to RTI Configuration and readback via the TAP is always available. The boundary-scan mode simply locks out the other modes. The boundary-scan mode is selected by a <10x> on the mode pins (M0, M1, M2). To CRC Check DS001_19_032300 Figure 19: Loading Configuration Data for the Slave Parallel Mode A configuration packet does not have to be written in one continuous stretch, rather it can be split into many write sequences. Each sequence would involve assertion of CS. In applications where multiple clock cycles may be required to access the configuration data before each byte can be loaded into the Slave Parallel interface, a new byte of data may not be ready for each consecutive CCLK edge. In such 18 a case the CS signal may be de-asserted until the next byte is valid on D0-D7. While CS is High, the Slave Parallel interface does not expect any data and ignores all CCLK transitions. However, to avoid aborting configuration, WRITE must continue to be asserted while CS is asserted. Readback The configuration data stored in the Spartan-IIE configuration memory can be read back for verification. Along with the configuration data it is possible to read back the contents of all flip-flops/latches, LUT RAMs, and block RAMs. This capability is used for real-time debugging. For more detailed information see XAPP176, Spartan-II FPGA Family Configuration and Readback. www.xilinx.com 1-800-255-7778 DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification R Spartan-IIE 1.8V FPGA Family: Functional Description Revision History Version No. Date 1.0 11/15/01 Description Initial Xilinx release. The Spartan-IIE Family Data Sheet DS001-1, Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information (Module 1) DS001-2, Spartan-IIE 1.8V FPGA Family: Functional Description (Module 2) DS001-3, Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics (Module 3) DS001-4, Spartan-IIE 1.8V FPGA Family: Pinout Tables (Module 4) DS077-2 (v1.0) November 15, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 19