EVALUATION KIT AVAILABLE MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel General Description The MAX9259 serializer pairs with the MAX9260 deserializer for joint transmission of high-speed video, audio, and control data. The MAX9259/MAX9260 operate up to 3.125Gbps for a 15m shielded twisted-pair (STP) cable. This serial link supports display panels from QVGA (320 x 240) up to XGA (1280 x 768), or dual-view WVGA (2 x 854 x 480). The embedded audio channel supports I2S up to 32 bits per sample and at a 192kHz sample rate. The embedded control channel forms a full-duplex, differential 100kbps to 1Mbps UART link between the serializer and deserializer. The host electronic control unit (ECU) or microcontroller (FC) resides either on the MAX9259 or on the MAX9260. In addition, the control channel enables ECU/FC control of peripherals in the remote side of the serial link through I2C/UART. Preemphasis and channel equalization extend the link length and enhance the link reliability. Spread spectrum is available to reduce EMI on the serial and parallel output data signals. The differential link complies with the ISO 10605 and IEC 61000-4-2 ESD-protection standards. The core supplies for the MAX9259/MAX9260 are 1.8V and 3.3V, respectively. Both devices use an I/O supply from 1.8V to 3.3V. These devices are available in a 64-pin TQFP package (10mm x 10mm) and a 56-pin TQFN/QFND package (8mm x 8mm x 0.75mm) with an exposed pad. Electrical performance is guaranteed over the -40NC to +105NC automotive temperature range. Applications High-Resolution Automotive Navigation Features S Ideal for Digital Video Applications Up to XGA (1280 x 768) or Dual-View WVGA (2 x 854 x 480) Panels with 18- or 24-Bit Color Pre/Deemphasis Allows 15m Cable at Full Speed Up to 192kHz, 32-Bit Sample I2S S Multiple Data Rates for System Flexibility Up to 3.12Gbps Serial-Bit Rate 6.25MHz to 104MHz Pixel Clock Up to 1Mbps UART/UART-to-I2C Control Channel S Reduces EMI and Shielding Requirements Serial Output Programmable for 100mV to 400mV Programmable Spread Spectrum Reduces EMI Bypasses Input PLL for Jitter Attenuation S Peripheral Features for System Verification Built-In Serial Link PRBS BER Tester Interrupt Transmission from Deserializer to Serializer Meets AEC-Q100 Requirements -40NC to +105NC Operating Temperature Range 10kV Contact and 25kV Air ISO 10605 and 10kV IEC 61000-4-2 ESD Protection Simplified Diagram VIDEO/AUDIO C VIDEO/AUDIO MAX9259 I 2C Rear-Seat Infotainment 720p MAX9260 DISPLAY I2C Ordering Information Megapixel Camera Systems PART TEMP RANGE PIN-PACKAGE MAX9259GCB/V+ -40NC to +105NC 64 TQFP-EP* MAX9259GCB/V+T -40NC to +105NC 64 TQFP-EP* MAX9259GTN/V+T -40NC to +105NC 56 TQFN-EP* MAX9259GGN/VY+ -40NC to +105NC 56 QFND-EP* MAX9260GCB/V+ -40NC to +105NC 64 TQFP-EP* MAX9260GCB/V+T -40NC to +105NC 64 TQFP-EP* /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. Typical Applications Circuit appears at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maximintegrated.com. 19-4968; Rev 4; 10/14 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel ABSOLUTE MAXIMUM RATINGS AVDD to AGND MAX9259............................................................-0.5V to +1.9V MAX9260............................................................-0.5V to +3.9V DVDD to GND (MAX9259)....................................-0.5V to +1.9V DVDD to DGND (MAX9260)..................................-0.5V to +3.9V IOVDD to GND (MAX9259)...................................-0.5V to +3.9V IOVDD to IOGND (MAX9260)...............................-0.5V to +3.9V Any Ground to Any Ground..................................-0.5V to +0.5V OUT+, OUT- to AGND (MAX9259).......................-0.5V to +1.9V IN+, IN- to AGND (MAX9260)...............................-0.5V to +1.9V LMN_ to GND (MAX9259) (60kI source impedance).................................-0.5V to +3.9V All Other Pins to GND (MAX9259)........ -0.5V to (IOVDD + 0.5V) All Other Pins to IOGND (MAX9260).... -0.5V to (IOVDD + 0.5V) OUT+, OUT- Short Circuit to Ground or Supply (MAX9259)..................................................Continuous IN+, IN- Short Circuit to Ground or Supply (MAX9260)..................................................Continuous Continuous Power Dissipation (TA = +70NC) 64-Pin TQFP (derate 31.3mW/NC above +70NC)........2508mW 56-Pin TQFN (derate 47.6mW/NC above +70NC).....3809.5mW 56-Pin QFND (derate 42.7mW/NC above +70NC).......3148mW Operating Temperature Range......................... -40NC to +105NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC PACKAGE THERMAL CHARACTERISTICS (Note 1) 64 TQFP Junction-to-Ambient Thermal Resistance (BJA)........31.9NC/W Junction-to-Case Thermal Resistance (BJC)..................1NC/W 56 TQFN Junction-to-Ambient Thermal Resistance (BJA)...........21NC/W Junction-to-Case Thermal Resistance (BJC)..................1NC/W 56 QFND Junction-to-Ambient Thermal Resistance (BJA)........23.4NC/W Junction-to-Case Thermal Resistance (BJC)...............1.6NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAX9259 DC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (DIN_, PCLKIN, PWDN, SSEN, BWS, ES, DRS, MS, CDS, AUTOS, SD, SCK, WS) 0.65 x VIOVDD High-Level Input Voltage VIH1 Low-Level Input Voltage VIL1 Input Current IIN1 VIN = 0 to VIOVDD Input Clamp Voltage VCL ICL = -18mA High-Level Output Voltage VOH1 IOH = -2mA Low-Level Output Voltage VOL1 IOL = 2mA V -10 0.35 x VIOVDD V +10 FA -1.5 V SINGLE-ENDED OUTPUT (INT) Output Short-Circuit Current 2 IOS VO = 0V VIOVDD - 0.2 V 0.2 VIOVDD = 3.0V to 3.6V 16 35 64 VIOVDD = 1.7V to 1.9V 3 12 21 V mA Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT) High-Level Input Voltage VIH2 Low-Level Input Voltage VIL2 Input Current IIN2 Low-Level Open-Drain Output Voltage VOL2 0.7 x VIOVDD VIN = 0 to VIOVDD (Note 2) IOL = 3mA V -110 0.3 x VIOVDD V +5 FA VIOVDD = 1.7V to 1.9V 0.4 VIOVDD = 3.0V to 3.6V 0.3 V DIFFERENTIAL OUTPUT (OUT+, OUT-) Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage, (VOUT+ + VOUT-)/2 = VOS Change in VOS Between Complementary Output States Output Short-Circuit Current VOD Preemphasis off (Figure 1) 300 3.3dB preemphasis setting, VOD(P) (Figure 2) 400 350 610 3.3dB deemphasis setting, VOD(D) (Figure 2) 240 425 DVOD VOS Preemphasis off 1.1 1.4 DVOS IOS VOUT+ or VOUT- = 0V High Switching Threshold VCHR Low Switching Threshold VCLR mV 1.56 V 15 mV 25 45 54 mVP-P 15 -60 VOUT+ or VOUT- = 1.9V Magnitude of Differential Output IOSD VOD = 0V Short-Circuit Current Output Termination Resistance RO From OUT+, OUT- to VAVDD (Internal) REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-) 500 mA 25 mA 63 I 27 mV -27 mV LINE-FAULT-DETECTION INPUT (LMN_) Short-to-GND Threshold VTG Figure 3 Normal Thresholds VTN Figure 3 0.3 V 0.57 1.07 V V V VTO Figure 3 1.45 VIO+ 0.06 Open Input Voltage VIO Figure 3 1.47 1.75 Short-to-Battery Threshold VTE Figure 3 2.47 Open Thresholds V POWER SUPPLY fPCLKIN = 16.6MHz 100 125 fPCLKIN = 33.3MHz 105 145 fPCLKIN = 66.6MHz 116 155 fPCLKIN = 104MHz Worst-Case Supply Current (Figure 4) IWCS 135 175 Sleep-Mode Supply Current ICCS 40 110 FA Power-Down Supply Current ICCZ 5 70 FA Maxim Integrated BWS = GND PWDN = GND mA 3 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.) ESD PROTECTION OUT+, OUT- (Pin to EP) All Other Pins (to EP or Supply) 4 VESD VESD Human Body Model, RD = 1.5kW, CS = 100pF 8 IEC 61000-4-2, RD = 330W, CS = 150pF Contact discharge 10 Air discharge 12 IEC 10605, RD = 2kW, CS = 330pF Contact discharge 10 Air discharge 25 Human Body Model, RD = 1.5kW, CS = 100pF 4 kV FA Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 AC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC.) PARAMETER SYMBOL PARALLEL CLOCK INPUT (PCLKIN) Clock Frequency fPCLKIN Clock Duty Cycle DC Clock Transition Time Clock Jitter tR, tF CONDITIONS MIN TYP MAX VBWS = VGND, VDRS = VIOVDD 8.33 VBWS = VGND, VDRS = VGND 16.66 104 VBWS = VIOVDD, VDRS = VIOVDD VBWS = VIOVDD, VDRS = VGND 6.25 12.5 tHIGH/tT or tLOW/tT (Figure 5) 16.66 12.5 35 UNITS MHz 78 50 (Figure 5) 65 % 4 ns 800 ps(P-P) tJ 3.125Gbps, 300kHz sinusoidal jitter Output Rise Time tR 30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD 20 150 ns Output Fall Time tF 70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD 20 150 ns Input Setup Time tSET I2C only (Figure 6) 100 ns tHOLD SWITCHING CHARACTERISTICS (Note 3) I2C only (Figure 6) 0 ns Differential Output Rise-and-Fall Time 20% to 80%, VOD 400mV, RL = 100I, serial-data rate = 3.125Gbps I2C/UART PORT TIMING (Note 3) Input Hold Time tR, tF Total Serial Output Jitter tTSOJ1 3.125Gbps PRBS signal, measured at VOD = 0V differential, preemphasis disabled (Figure 7) Deterministic Serial Output Jitter tDSOJ2 3.125Gbps PRBS signal 90 150 0.25 ps UI 0.15 UI Parallel Data Input Setup Time tSET (Figure 8) 1 ns Parallel Data Input Hold Time tHOLD (Figure 8) 1.5 ns tSD (Figure 9) Link Start Time tLOCK (Figure 10) 3.5 ms Power-Up Time tPU (Figure 11) 3.5 ms WS Frequency fWS (Table 2) 8 192 kHz Sample Word Length nWS (Table 2) 4 32 Bits (192 x 32) x 2 kHz Serializer Delay (Note 4) Spread spectrum enabled 2830 Spread spectrum disabled 270 Bits I2S INPUT TIMING SCK Frequency fSCK fSCK = fWS x nWS x 2 (8 x 4) x2 SCK Clock High Time (Note 3) tHC VSCK VIH, tSCK = 1/fSCK 0.35 x tSCK ns SCK Clock Low Time (Note 3) tLC VSCK VIL, tSCK = 1/fSCK 0.35 x tSCK ns SD, WS Setup Time tSET (Figure 12, Note 3) 2 ns SD, WS Hold Time tHOLD (Figure 12, Note 3) 2 ns Maxim Integrated 5 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (ENABLE, INT, PWDN, SSEN, BWS, ES, DRS, MS, CDS, EQS, DCS) High-Level Input Voltage VIH1 Low-Level Input Voltage VIL1 0.65 x VIOVDD Input Current IIN1 VIN = 0 to VIOVDD Input Clamp Voltage VCL ICL = -18mA V -10 0.35 x VIOVDD V +10 FA -1.5 V SINGLE-ENDED OUTPUTS (DOUT_, SD, WS, SCK, PCLKOUT) High-Level Output Voltage Low-Level Output Voltage VOH VOL1 VIOVDD - 0.3 VDCS = VIOVDD VIOVDD - 0.2 IOH = -2mA IOL = 2mA DOUT_, SD, WS, SCK Output Short-Circuit Current VDCS = VIOGND V VDCS = VIOGND 0.3 VDCS = VIOVDD 0.2 VO = 0V, VDCS = VIOGND VO = 0V, VDCS = VIOVDD IOS VO = 0V, VDCS = VIOGND PCLKOUT VO = 0V, VDCS = VIOVDD VIOVDD = 3.0V to 3.6V 15 25 39 VIOVDD = 1.7V to 1.9V 3 7 13 VIOVDD = 3.0V to 3.6V 20 35 63 VIOVDD = 1.7V to 1.9V 5 10 21 VIOVDD = 3.0V to 3.6V 15 33 50 VIOVDD = 1.7V to 1.9V 5 10 17 VIOVDD = 3.0V to 3.6V 30 54 97 VIOVDD = 1.7V to 1.9V 9 16 32 V mA I2C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, ERR, GPIO_, LOCK) High-Level Input Voltage VIH2 Low-Level Input Voltage VIL2 Input Current IIN2 Low-Level Open-Drain Output Voltage 6 VOL2 0.7 x VIOVDD V 0.3 x VIOVDD VIN = 0 to VIOVDD (Note 2) IOL = 3mA RX/SDA, TX/SCL -110 +1 GPIO, ERR, LOCK VIOVDD = 1.7V to 1.9V -80 +1 VIOVDD = 3.0V to 3.6V V FA 0.4 V 0.3 V Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIFFERENTIAL OUTPUTS FOR REVERSE CONTROL CHANNEL (IN+, IN-) Differential High Output Peak Voltage, (VIN+) - (VIN-) VROH No high-speed data transmission (Figure 13) 30 60 mV Differential Low Output Peak Voltage, (VIN+) - (VIN-) VROL No high-speed data transmission (Figure 13) -60 -30 mV 90 mV DIFFERENTIAL INPUTS (IN+, IN-) Differential High Input Threshold (Peak), (VIN+) - (VIN-) VIDH(P) (Figure 14) Differential Low Input Threshold (Peak), (VIN+) - (VIN-) VIDL(P) (Figure 14) Input Common-Mode Voltage, ((VIN+) + (VIN-))/2 Differential Input Resistance (Internal) 40 -90 -40 mV VCMR 1 1.3 1.6 V RI 80 100 130 I 2% spread spectrum active 113 166 Spread spectrum disabled 105 155 2% spread spectrum active 122 181 Spread spectrum disabled 110 165 2% spread spectrum active 137 211 Spread spectrum disabled 120 188 2% spread spectrum active 159 247 Spread spectrum disabled 135 214 80 130 FA 19 70 FA POWER SUPPLY VBWS = VIOGND, fPCLKOUT = 16.6MHz VBWS = VIOGND, fPCLKOUT = 33.3MHz Worst-Case Supply Current (Figure 15) IWCS VBWS = VIOGND, fPCLKOUT = 66.6MHz VBWS = VIOGND, fPCLKOUT = 104MHz Sleep-Mode Supply Current ICCS Power-Down Supply Current ICCZ Maxim Integrated VPWDN = VIOGND mA 7 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 DC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) ESD PROTECTION Human Body Model, RD = 1.5kW, CS = 100pF IN+, IN- (Pin to EP) All Other Pins (to EP or Supply) 8 VESD VESD 8 IEC 61000-4-2, RD = 330W, CS = 150pF Contact discharge 8 Air discharge 10 IEC 10605, RD = 2kW, CS = 330pF Contact discharge 8 Air discharge 20 Human Body Model, RD = 1.5kW, CS = 100pF 4 kV FA Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 AC ELECTRICAL CHARACTERISTICS (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PARALLEL CLOCK OUTPUT (PCLKOUT) Clock Frequency Clock Duty Cycle fPCLKOUT DC VBWS = VIOGND, VDRS = VIOVDD 8.33 VBWS = VIOGND, VDRS = VIOGND 16.66 104 VBWS = VIOVDD, VDRS = VIOVDD 6.25 12.5 VBWS = VIOVDD, VDRS = VIOGND tHIGH/tT or tLOW/tT (Figure 16) 12.5 78 40 16.66 50 60 MHz % tJ Period jitter, RMS, spread off, 3.125Gbps, PRBS pattern, UI = 1/fPCLKOUT Output Rise Time tR 30% to 70%, CL = 10pF to 100pF, 1kI pullup to IOVDD 20 150 ns Output Fall Time tF 70% to 30%, CL = 10pF to 100pF, 1kI pullup to IOVDD 20 150 ns Input Setup Time tSET I2C only 100 ns Input Hold Time tHOLD I2C only 0 ns Clock Jitter 0.05 UI I2C/UART PORT TIMING SWITCHING CHARACTERISTICS 20% to 80%, VIOVDD = 1.7V to 1.9V PCLKOUT Rise-and-Fall Time tR, tF 20% to 80%, VIOVDD = 3.0V to 3.6V 20% to 80%, VIOVDD = 1.7V to 1.9V Parallel Data Rise-and-Fall Time (Figure 17) tR, tF 20% to 80%, VIOVDD = 3.0V to 3.6V Deserializer Delay Lock Time tSD tLOCK VDCS = VIOVDD, CL = 10pF 0.4 2.2 VDCS = VIOGND, CL = 5pF 0.5 2.8 VDCS = VIOVDD, CL = 10pF 0.25 1.7 VDCS = VIOGND, CL = 5pF 0.3 2.0 VDCS = VIOVDD, CL = 10pF 0.5 3.1 VDCS = VIOGND, CL = 5pF 0.6 3.8 VDCS = VIOVDD, CL = 10pF 0.3 2.2 VDCS = VIOGND, CL = 5pF 0.4 2.4 ns ns Spread spectrum enabled (Figure 18) 2880 Spread spectrum disabled (Figure 18) 750 Spread spectrum enabled (Figure 19) 1500 Spread spectrum off (Figure 19) 1000 2500 Fs Bits Fs Power-Up Time tPU (Figure 20) Reverse Control-Channel Output Rise Time tR No high-speed transmission (Figure 13) 180 400 ns Reverse Control-Channel Output Fall Time tF No high-speed transmission (Figure 13) 180 400 ns Maxim Integrated 9 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 AC ELECTRICAL CHARACTERISTICS (continued) (VDVDD = VAVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 3.3V, TA = +25NC.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I2S OUTPUT TIMING fWS = 48kHz or 44.1kHz WS Jitter tWS = 1/fWS, rising (falling) edge to fWS = 96kHz falling (rising) edge (Note 5) fWS = 192kHz tAJ-WS SCK Jitter 0.4e - 3 0.5e - 3 x tWS x tWS tAJ-SCK tSCK = 1/fSCK, rising edge to rising edge 1e - 3 x tWS 1.6e - 3 x tWS 2e - 3 x tWS nWS = 16 bits, fWS = 48kHz or 44.1kHz 13e - 3 16e - 3 x tSCK x tSCK nWS = 24 bits, fWS = 96kHz 39e - 3 48e - 3 x tSCK x tSCK nWS = 32 bits, fWS = 192kHz 0.1 x tSCK Audio Skew Relative to Video ASK Video and audio synchronized SCK, SD, WS Rise-and-Fall Time tR, tF 20% to 80% VDCS = VIOVDD, CL = 10pF 0.3 VDCS = VIOGND, CL = 5pF 0.4 SD, WS Valid Time Before SCK tDVB tSCK = 1/fSCK (Figure 21) 0.35 x tSCK SD, WS Valid Time After SCK tDVA tSCK = 1/fSCK (Figure 21) 0.35 x tSCK Note Note Note Note 0.8e - 3 x tWS ns ns 0.13 x tSCK 3 x tWS 4 x tWS 3.1 s ns 3.8 ns 0.5 x tSCK ns 0.5 x tSCK ns Minimum IIN due to voltage drop across the internal pullup resistor. Not production tested. Bit time = 1/(30 x fRXCLKIN) (BWS = 0), = 1/(40 x fRXCLKIN) (BWS = VIOVDD). Rising to rising edge jitter can be twice as large. 2: 3: 4: 5: Typical Operating Characteristics (VDVDD = VAVDD = VIOVDD = 1.8V (MAX9259), VDVDD = VAVDD = VIOVDD = 3.3V (MAX9260), TA = +25NC, unless otherwise noted.) 120 115 110 105 PREEMPHASIS = 0x01 TO 0x04 100 95 PREEMPHASIS = 0x00 90 5 25 45 65 PCLKIN FREQUENCY (MHz) 10 85 105 130 PREEMPHASIS = 0x0B TO 0x0F 125 120 115 110 105 PREEMPHASIS = 0x01 TO 0x04 100 95 5 20 35 50 PCLKIN FREQUENCY (MHz) 65 ALL EQUALIZER SETTINGS 150 145 140 135 130 125 120 115 110 PREEMPHASIS = 0x00 90 155 SUPPLY CURRENT (mA) PREEMPHASIS = 0x0B TO 0x0F 125 MAX9259/60 toc02 SUPPLY CURRENT (mA) 130 135 SUPPLY CURRENT (mA) MAX9259/60 toc01 135 MAX9260 SUPPLY CURRENT vs. PCLKOUT FREQUENCY (24-BIT MODE) MAX9259 SUPPLY CURRENT vs. PCLKIN FREQUENCY (32-BIT MODE) MAX9259/60 toc03 MAX9259 SUPPLY CURRENT vs. PCLKIN FREQUENCY (24-BIT MODE) 80 105 5 25 45 65 85 105 PCLKOUT FREQUENCY (MHz) Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Typical Operating Characteristics (continued) (VDVDD = VAVDD = VIOVDD = 1.8V (MAX9259), VDVDD = VAVDD = VIOVDD = 3.3V (MAX9260), TA = +25NC, unless otherwise noted.) 140 135 130 125 120 170 115 160 2%, 4% SPREAD 150 140 130 120 110 110 MAX9260 SUPPLY CURRENT vs. PCLKOUT FREQUENCY (32-BIT MODE) 180 170 SUPPLY CURRENT (mA) 5 20 35 50 65 150 140 130 120 NO SPREAD 100 5 80 2%, 4% SPREAD 110 NO SPREAD 100 105 160 25 45 65 85 5 105 20 35 50 65 80 PCLKOUT FREQUENCY (MHz) PCLKOUT FREQUENCY (MHz) PCLKOUT FREQUENCY (MHz) SERIAL LINK SWITCHING PATTERN WITHOUT PREEMPHASIS (PARALLEL BIT RATE = 104MHz, 10m STP CABLE) SERIAL LINK SWITCHING PATTERN WITH 14dB PREEMPHASIS (PARALLEL BIT RATE = 104MHz, 10m STP CABLE) OUTPUT POWER SPECTRUM vs. PCLKOUT FREQUENCY (MAX9259 SPREAD ON, MAX9260 SPREAD OFF) MAX9259/60 toc07 MAX9259/60 toc08 3.12Gbps 0 3.12Gbps 250.0mV PCLKOUT OUTPUT POWER (dBm) 400.0mV fPCLKOUT = 20MHz -10 0% SPREAD 0.5% SPREAD -20 MAX9259/60 toc09 SUPPLY CURRENT (mA) 145 180 MAX9259/60 toc05 ALL EQUALIZER SETTINGS 150 SUPPLY CURRENT (mA) MAX9259/60 toc04 155 MAX9260 SUPPLY CURRENT vs. PCLKOUT FREQUENCY (24-BIT MODE) MAX9259/60 toc06 MAX9260 SUPPLY CURRENT vs. PCLKOUT FREQUENCY (32-BIT MODE) -30 -40 -50 -60 -70 -400.0mV 52.00ps/div -250.0mV 52.00ps/div -80 18.5 2% SPREAD 4% SPREAD 19.5 20.5 19.0 20.0 21.0 21.5 PCLKOUT FREQUENCY (MHz) -20 -30 -40 -50 -60 -10 0% SPREAD -20 -30 -40 -50 2% SPREAD -80 39 40 41 4% SPREAD 42 43 PCLKOUT FREQUENCY (MHz) Maxim Integrated 45 OPTIMUM PE/EQ SETTINGS 80 60 NO PE, EQS = LOW 40 NO PE, EQS = HIGH 20 2% SPREAD -80 44 100 -60 -70 -70 120 MAX9259/60 toc12 0.5% SPREAD 0% SPREAD fPCLKOUT = 42MHz FREQUENCY (MHz) -10 0 MAXIMUM PCLKIN FREQUENCY vs. STP CABLE LENGTH (BER < 10-9) MAX9259/60 toc11 fPCLKOUT = 42MHz OUTPUT POWER SPECTRUM vs. PCLKOUT FREQUENCY (MAX9260 SPREAD ON, MAX9259 SPREAD OFF) PCLKOUT OUTPUT POWER (dBm) PCLKOUT OUTPUT POWER (dBm) 0 MAX9259/60 toc10 OUTPUT POWER SPECTRUM vs. PCLKOUT FREQUENCY (MAX9259 SPREAD ON, MAX9260 SPREAD OFF) 39 40 41 4% SPREAD 42 43 PCLKOUT FREQUENCY (MHz) 44 45 BER CAN BE < 10-12 FOR CABLE LENGTHS LESS THAN 10m 0 0 5 10 15 20 CABLE LENGTH (m) 11 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel DOUT23 DOUT22 DOUT21 DOUT19 DOUT20 DOUT18 DOUT17 DOUT16 DOUT15 DOUT14 DOUT13 DOUT12 DOUT11 DOUT9 CDS PWDN RX/SDA SSEN TX/SCL LMN1 AGND OUT- OUT+ AVDD LMN0 LFLT INT DRS BWS ES DOUT10 TOP VIEW TOP VIEW PCLKOUT Pin Configurations 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DIN0 49 32 MS DOUT8 49 32 DOUT24 GND 50 31 GND IOGND 50 31 IOGND IOVDD 51 30 IOVDD IOVDD 51 30 IOVDD DIN1 52 29 AUTOS DOUT7 52 29 DOUT25 DIN2 53 28 WS DOUT6 53 28 DOUT26 DIN3 54 27 SCK DOUT5 54 27 DOUT27 DIN4 55 26 SD DOUT4 55 26 DOUT28/MCLK DIN5 56 25 DIN28 DOUT3 56 24 DIN27 DOUT2 57 DIN7 58 23 DIN26 DOUT1 58 23 WS DIN8 59 22 DIN25 DOUT0 59 22 LOCK DIN9 60 21 DIN24 IOGND 60 21 IOGND GND 61 20 GND SSEN 61 19 DVDD DRS 62 DIN10 63 18 AGND AVDD 63 18 TX/SCL DIN11 64 17 DIN23 AGND 64 17 RX/SDA 20 ERR 19 PWDN DGND MS DVDD DCS GPIO1 10 11 12 13 14 15 16 EQS 9 AGND 8 IN- ES 7 IN+ 6 AVDD 5 GPIO0 4 INT BWS 3 CDS 2 PWDN RX/SDA TQFP (10mm x 10mm x 1mm) TX/SCL OUT- OUT+ AVDD LMN0 LFLT INT DRS ES BWS 1 ENABLE DIN22 DIN21 DIN20 TQFP (10mm x 10mm x 1mm) TOP VIEW 24 SCK EP* 10 11 12 13 14 15 16 DIN19 9 DIN18 8 DIN17 DIN15 7 AVDD DIN14 6 AGND DIN13 5 GND 4 IOVDD 3 PCLKIN 2 DIN16 1 DIN12 EP* SSEN DVDD 62 25 SD MAX9260 LMN1 MAX9259 DIN6 57 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 CDS DIN0 43 27 MS IOVDD 44 DIN1 45 26 IOVDD DIN2 46 25 AUTOS DIN3 47 24 WS DIN4 48 23 SCK DIN5 49 22 SD MAX9259 DIN6 50 21 DIN28 DIN7 51 20 DIN27 DIN8 52 19 DIN26 DIN9 53 18 DIN25 17 DIN24 DVDD 54 EP* + DIN10 55 16 DVDD 15 DIN23 6 7 8 9 DIN13 DIN14 DIN15 DIN16 PCLKIN IOVDD AVDD DIN17 10 11 12 13 14 DIN22 5 DIN21 4 DIN20 3 DIN19 2 DIN18 1 DIN12 DIN11 56 TQFN/QFND (8mm x 8mm x 0.75mm) *CONNECT EP TO GROUND PLANE 12 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 Pin Description PIN NAME FUNCTION TQFP TQFN/QFND 1-5, 11-17, 21-25, 49, 52-60, 63, 64 1-5, 9-15, 17-21, 43, 45-53, 55, 56 DIN0- DIN28 Data Input[0:28]. Parallel data inputs. All pins internally pulled down to GND. Selected edge of PCLKIN latches input data. Set BWS = low (24-bit mode) to use DIN0-DIN20 (RGB and SYNC). DIN21-DIN28 are not used in 24-bit mode. Set BWS = high (32-bit mode) to use DIN0-DIN28 (RGB, SYNC, and two extra inputs). 6 6 PCLKIN Parallel Clock Input. Latches parallel data inputs and provides the PLL reference clock. 7, 30, 51 7, 26, 44 IOVDD I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to IOVDD. 8, 20, 31, 50, 61 -- GND 9, 18, 39 -- AGND Analog Ground 10, 42 8, 36 AVDD 1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to AVDD. 19, 62 16, 54 DVDD 1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to DVDD. 26 22 SD 27 23 SCK I2S Serial-Clock Input with Internal Pulldown to GND 28 24 WS I2S Word-Select Input with Internal Pulldown to GND 29 25 AUTOS 32 27 MS 33 28 CDS 34 29 PWDN 35 30 RX/SDA Maxim Integrated Digital and I/O Ground I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD as an additional data input latched on the selected edge of PCLKIN. Autostart Setting. Active-low power-up mode selection input requires external pulldown or pullup resistors. Set AUTOS = high to power up the device with no link active. Set AUTOS = low to have the MAX9259 power up the serial link with autorange detection (see Tables 11 and 12). Mode Select. Control-link mode-selection input requires external pulldown or pullup resistors. Set MS = low, to select base mode. Set MS = high to select the bypass mode. Control-Direction Selection. Control-link-direction selection input requires external pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial link. Set CDS = high for FC use on the MAX9260 side of the serial link. Power-Down. Active-low power-down input requires external pulldown or pullup resistors. Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9259's UART. In I2C mode, RX/SDA is the SDA input/output of the MAX9259's I2C master. 13 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9259 Pin Description (continued) PIN TQFP TQFN/QFND 36 31 NAME FUNCTION TX/SCL Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259's UART. In I2C mode, TX/SCL is the SCL output of the MAX9259's I2C master. 37 32 SSEN Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN = low to use the serial link without spread spectrum. 38 33 LMN1 Line-Fault Monitor Input 1 (see Figure 3 for details) 40, 41 34, 35 OUT-, OUT+ Differential CML Output -/+. Differential outputs of the serial link. 43 37 LMN0 Line-Fault Monitor Input 0 (see Figure 3 for details) 44 38 LFLT Line Fault. Active-low open-drain line-fault output with a 60kI internal pullup resistor. LFLT = low indicates a line fault. LFLT is output high when PWDN = low. 45 39 INT Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259's INT output. Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode). 14 46 40 DRS 47 41 ES 48 42 BWS -- -- EP Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on the falling edge of PCLKIN. Bus-Width Select. Parallel input bus-width selection input requires external pulldown or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode. Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND (TQFN package). MUST externally connect EP to the AGND plane to maximize thermal and electrical performance. Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 Pin Description PIN NAME FUNCTION 1 ENABLE Enable. Active-low parallel output-enable input requires external pulldown or pullup resistors. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and the parallel outputs, DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ to high impedance. 2 BWS Bus-Width Select. Parallel output bus-width selection input requires external pulldown or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode. 3 INT Interrupt. Interrupt input requires external pulldown or pullup resistors. A transition on the INT input of the MAX9260 toggles the MAX9259's INT output. 4 CDS Control-Direction Selection. Control-link-direction selection input requires external pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial link. Set CDS = high for FC use on the MAX9260 side of the serial link. 5 GPIO0 6 ES Edge Select. PCLKOUT edge-selection input requires external pulldown or pullup resistors. Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger. 7, 63 AVDD 3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1F and 0.001F capacitors as close as possible to the device with the smallest value capacitor closest to AVDD. 8,9 IN+, IN- 10, 64 AGND GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to IOVDD. GPIO0 is high impedance during power-up and when PWDN = low. Differential CML Input +/-. Differential inputs of the serial link. Analog Ground 11 EQS Equalizer Select. Deserializer equalizer-selection input requires external pulldown or pullup resistors. The state of EQS latches upon power-up or rising edge of PWDN. Set EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB equalizer boost (EQTUNE = 0100). 12 GPIO1 GPIO1. Open-drain general-purpose input/output with internal 60kI pullup resistors to IOVDD. GPIO1 is high impedance during power-up and when PWDN = low. DCS Drive Current Select. Driver current-selection input requires external pulldown or pullup resistors. Set DCS = high for stronger parallel data and clock output drivers. Set DCS = low for normal parallel data and clock drivers (see the MAX9260 DC Electrical Characteristics table). 13 14 MS Mode Select. Control-link mode-selection/autostart mode selection input requires external pulldown or pullup resistors. MS sets the control-link mode when CDS = high (see the Control-Channel and Register Programming section). Set MS = low to select base mode. Set MS = high to select the bypass mode. MS sets autostart mode when CDS = low (see Tables 11 and 12). 15 DVDD 3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to DVDD. 16 DGND Digital Ground 17 RX/SDA Maxim Integrated Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9260's UART. In I2C mode, RX/SDA is the SDA input/output of the MAX9259's I2C master. 15 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel MAX9260 Pin Description (continued) PIN NAME FUNCTION 18 TX/SCL Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259's UART. In I2C mode, TX/SCL is the SCL output of the MAX9260's I2C master. 19 PWDN Power-Down. Active-low power-down input requires external pulldown or pullup resistors. Error. Active-low open-drain video data error output with internal pullup to IOVDD. ERR goes low when the number of decoding errors during normal operation exceed a programmed error threshold or when at least one PRBS error is detected during PRBS test. ERR is output high when PWDN = low. 20 ERR 21, 31, 50, 60 IOGND Input/Output Ground LOCK Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs are not locked or incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active. LOCK is output high when PWDN = low. 22 23 WS Word Select. I2S word-select output. 24 SCK Serial Clock. I2S serial-clock output 25 SD Serial Data. I2S serial-data output. Disable I2S to use SD as an additional data output latched on the selected edge of PCLKOUT. 26-29, 32-40, 42-49, 52-59 DOUT0- DOUT27, DOUT28/MCLK Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0-DOUT20 (RGB and SYNC). DOUT21-DOUT28 are not used in 24-bit mode and are set to low. Set BWS = high (32-bit mode) to use DOUT0-DOUT28 (RGB, SYNC, and two extra outputs). DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio Applications section). 30, 51 IOVDD 41 PCLKOUT Parallel Clock Output. Used for DOUT0-DOUT28. SSEN Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires external pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2% spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs without spread spectrum. 62 DRS Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode). -- EP 61 16 1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value capacitor closest to IOVDD. Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the AGND plane to maximize thermal and electrical performance. Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Functional Diagram LFLT PCLKIN FILTER PLL SPREAD PLL LINEFAULT DET CLKDIV DIN[N:0] 8B/10B ENCODE PARITY FIFO P S LMN0 LMN1 CML Tx OUT+ WS, SD, SCK AUDIO FIFO PRBS GEN TX/SCL RX/SDA TERM MAX9259 OUT- REV CH Rx UART/I2C SERIALIZER SPREAD PLL CDR PLL PCLKOUT STP CABLE (Z0 = 50) EQ CLKDIV DOUT[N:0] 8B/10B DECODE PARITY FIFO P S CML Rx IN- WS, SD, SCK TX/SCL RX/SDA AUDIO FIFO PRBS CHECK MAX9260 UART/I2C TERM IN+ REV CH Tx DESERIALIZER Maxim Integrated 17 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel RL/2 OUT+ VOD VOS OUT- RL/2 GND ((OUT+) + (OUT-))/2 OUTVOS(+) VOS(-) VOS(-) OUT+ DVOS = |VOS(+) - VOS(-)| VOD(+) VOD = 0V VOD(-) VOD(-) DVOD = |VOD(+) - VOD(-)| (OUT+) - (OUT-) Figure 1. MAX9259 Serial Output Parameters OUT+ VOD(P) VOS VOD(D) OUT- SERIAL-BIT TIME Figure 2. Output Waveforms at OUT+ and OUT- 18 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel 1.7V TO 1.9V MAX9259 45.3kI* 45.3kI* LMN0 LMN1 OUTPUT LOGIC (OUT+) 4.99kI* OUT+ 4.99kI* TWISTED PAIR OUT49.9kI* LFLT 1.5V 0.5V 49.9kI* CONNECTORS 2.1V REFERENCE VOLTAGE GENERATOR OUTPUT LOGIC (OUT-) *Q1% TOLERANCE Figure 3. Fault-Detector Circuit PCLKIN DIN_ NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE. Figure 4. MAX9259 Worst-Case Pattern Input Maxim Integrated 19 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel tT VIH MIN tHIGH PCLKIN VIL MAX tR tF tLOW Figure 5. MAX9259 Parallel Input Clock Requirements START CONDITION (S) PROTOCOL BIT 7 MSB (A7) tLOW tSU;STA BIT 6 (A6) tHIGH BIT 0 (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1/fSCL VIOVDD x 0.7 SCL VIOVDD x 0.3 tBUF tr tSP tf VIOVDD x 0.7 SDA VIOVDD x 0.3 tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO Figure 6. I2C Timing Parameters 800mV t TSOJ1 2 t TSOJ1 2 Figure 7. Differential Output Template 20 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel VIH MIN PCLKIN VIL MAX tSET tHOLD VIH MIN VIH MIN VIL MAX VIL MAX DIN_ NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE. Figure 8. MAX9259 Input Setup-and-Hold Times EXPANDED TIME SCALE DIN_ N N+1 N+3 N+2 N+4 PCLKIN N-1 N OUT+/tSD FIRST BIT LAST BIT Figure 9. MAX9259 Serializer Delay Maxim Integrated 21 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel PCLKIN tLOCK 350Fs SERIAL LINK INACTIVE SERIAL LINK ACTIVE REVERSE CONTROL CHANNEL ENABLED REVERSE CONTROL CHANNEL AVAILABLE CHANNEL DISABLED PWDN MUST BE HIGH Figure 10. MAX9259 Link Startup Time PCLKIN VIH1 PWDN tPU POWERED DOWN POWERED UP, SERIAL LINK INACTIVE POWERED UP, SERIAL LINK ACTIVE 350s REVERSE CONTROL CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED REVERSE CONTROL CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED Figure 11. MAX9259 Power-Up Delay WS tHOLD tSCK tSET tLC SCK tHOLD tSET tHC SD Figure 12. MAX9259 Input I2S Timing Parameters 22 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel RL/2 IN+ MAX9260 VOD REVERSE CONTROL-CHANNEL TRANSMITTER IN- VCMR RL/2 IN+ IN- IN- IN+ VCMR VROH 0.9 x VROH 0.1 x VROH (IN+) - (IN-) 0.1 x VROL tR 0.9 x VROL VROL tF Figure 13. MAX9260 Reverse Control-Channel Output Parameters RL/2 IN+ VIN+ PCLKOUT VID(P) RL/2 IN- _ + _ VIN- + _ CIN CIN DOUT_ NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE. VID(P) = | VIN+ - VIN- | VCMR = (VIN+ + VIN-)/2 Figure 14. MAX9260 Test Circuit for Differential Input Measurement Maxim Integrated Figure 15. MAX9260 Worst-Case Pattern Output 23 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel tT VOH MIN tHIGH PCLKOUT VOL MAX tLOW Figure 16. MAX9260 Clock Output High-and-Low Times CL MAX9260 SINGLE-ENDED OUTPUT LOAD 0.8 x VI0VCC 0.2 x VI0VCC tR tF Figure 17. MAX9260 Output Rise-and-Fall Times SERIAL-WORD LENGTH SERIAL WORD N SERIAL WORD N+1 SERIAL WORD N+2 IN+/FIRST BIT DOUT_ LAST BIT PARALLEL WORD N-1 PARALLEL WORD N-2 PARALLEL WORD N PCLKOUT tSD NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE. Figure 18. MAX9260 Deserializer Delay 24 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel IN+ - IN- tLOCK LOCK VOH PWDN MUST BE HIGH Figure 19. MAX9260 Lock Time IN+/- VIH1 PWDN tPU LOCK VOH Figure 20. MAX9260 Power-Up Delay WS tDVA tR tDVB SCK tDVB tDVA tF SD Figure 21. MAX9260 Output I2S Timing Parameters Maxim Integrated 25 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Detailed Description The MAX9259/MAX9260 chipset presents Maxim's GMSL technology. The MAX9259 serializer pairs with the MAX9260 deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data for video-display or image-sensing applications. The serial-payload data rate can reach up to 2.5Gbps for a 15m STP cable. The parallel interface is programmable for 24-bit or 32-bit width modes at the maximum bus clock of 104MHz or 78MHz, respectively. The minimum bus clock is 6.25MHz for the 32-bit mode and 8.33MHz for the 24-bit mode. With such a flexible data configuration, the GMSL is able to support XGA (1280 x 768) or dual-view WVGA (2 x 854 x 480) display panels. For image sensing, it supports three 10-bit camera links simultaneously with a pixel clock up to 78MHz. The 24-bit mode handles 21-bit data and control signals plus an I2S audio signal. The 32-bit mode handles 29-bit data and control signals plus an I2S audio signal. Any combination and sequence of color video data, video sync, and control signals make up the 21-bit or 29-bit parallel data on DIN_ and DOUT_. The I2S port supports the sampled audio data at a rate from 8kHz to 192kHz and the audio word length of anywhere between 4 to 32 bits. The embedded control channel forms a UART link between the serializer and deserializer. The UART link can be set to half-duplex mode or full-duplex mode depending on the application. The GMSL supports UART rates from 100kbps to 1Mbps. Using this control link, a host ECU or FC communicates with the serializer and deserializer, as well as the peripherals in the remote 26 side, such as backlight control, grayscale gamma correction, camera module, and touch screen. All serial communication (forward and reverse) uses differential signaling. The peripheral programming uses I2C format or the default GMSL UART format. A separate bypass mode enables communication using a full-duplex, userdefined UART format. The control link between the MAX9259 and MAX9260 allows FC connectivity to either device or peripherals to support video-display or imagesensing applications. The AC-coupled serial link uses 8B/10B coding. The MAX9259 serializer features a programmable driver preemphasis and the MAX9260 deserializer features a programmable channel equalizer to extend the link length and enhance the link reliability. Both devices have a programmable spread-spectrum feature for reducing EMI on the serial link output (MAX9259) and parallel data outputs (MAX9260). The differential serial link input and output pins comply with the ISO 10605 and IEC 610004-2 ESD-protection standards. The core supplies for the MAX9259/MAX9260 are 1.8V and 3.3V, respectively. Both devices use an I/O supply from 1.8V to 3.3V Register Mapping The FC configures various operating conditions of the GMSL through registers in the MAX9259/MAX9260. The default device addresses stored in the R0 and R1 registers of the MAX9259/MAX9260 are 0x80 and 0x90, respectively. Write to the R0/R1 registers in both devices to change the device address of the MAX9259 or MAX9260. Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Parallel Inputs and Outputs The parallel bus uses two selectable bus widths, 24 bits and 32 bits. BWS selects the bus width according to Table 1. In 24-bit mode, DIN21-DIN28 are not used and are internally pulled down. For both modes, SD, SCK, and WS pins are dedicated for I2S audio data. The assignments of the first 21 or 29 signals are interchangeable and appear in the same order at both sides of the serial link. In image-sensing applications, disabling the I2S audio channel (through the MAX9259 and MAX9260 internal registers) allows the MAX9259 to serialize three 10-bit camera data streams through DIN[0:28] plus SD inputs. The parallel bus accepts data clock rates from 8.33MHz to 104MHz for the 24-bit mode and 6.25MHz to 78MHz for the 32-bit mode. Serial Link Signaling and Data Format The MAX9259 high-speed data serial output uses CML signaling with programmable preemphasis and AC-coupling. The MAX9260 high-speed receiver uses AC-coupling and programmable channel equalization. Together, the GMSL operates at up to 3.125Gbps over STP cable lengths up to 15m. The serializer scrambles and encodes the parallel input bits, and sends the 8B/10B coded signal through the serial link. The deserializer recovers the embedded serial clock and then samples, decodes, and descrambles the data onto the parallel output bus. Figures 22 and 23 show the serial-data packet format prior to scrambling and 8B/10B coding. For the 24-bit or 32-bit mode, the first 21 or 29 serial bits come from DIN[20:0] or DIN[28:0], respectively. The audio channel bit (ACB) contains an encoded audio signal derived from the three I2S inputs (SD, SCK, and WS). The forward control channel (FCC) bit carries the forward control data. The last bit (PCB) is the parity bit of the previous 23 or 31 bits. Reverse Control Channel The MAX9259/MAX9260 use the reverse control channel to send I2C/UART and interrupt signals in the opposite direction of the video stream from the deserializer to the serializer. The reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. The reverse control channel operates independently from the forward control channel. The reverse control channel is available 500Fs after powerup. The MAX9259 temporarily disables the reverse control channel for 350Fs after starting/stopping the forward serial link. Table 1. Bus-Width Selection Using BWS BWS INPUT STATE BUS WIDTH PARALLEL BUS SIGNALS USED Low 24 DIN[0:20]/DOUT[0:20], WS, SCK, SD High 32 DIN[0:28]/DOUT[0:28], WS, SCK, SD 24 BITS DIN0 DIN1 32 BITS DIN17 DIN18 DIN19 DIN20 18-BIT RGB DATA HSYNC, VSYNC, DE ACB FCC PCB FORWARD CONTROLCHANNEL BIT Figure 22. 24-Bit Mode Serial Link Data Format Maxim Integrated PACKET PARITY CHECK BIT DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB ADDITIONAL AUDIO VIDEO CHANNEL DATA/ BIT CONTROL FORWARD BITS CONTROLCHANNEL BIT PACKET NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE PARITY INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK. CHECK BIT 24-BIT RGB DATA AUDIO CHANNEL BIT NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK. DIN0 DIN1 HSYNC, VSYNC, DE Figure 23. 32-Bit Mode Serial Link Data Format 27 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 2. Maximum Audio Sampling Rates for Various PCLK_ Frequencies PCLK_ FREQUENCY (DRS = LOW) (MHz) WORD LENGTH (Bits) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192 Parallel Data-Rate Selection The MAX9259/MAX9260 use the DRS inputs to set the parallel data rate. Set DRS high to use a low-speed parallel data rate in the range of 6.25MHz to 12.5MHz (32-bit mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS low for normal operation with parallel data rates higher than 12.5MHz (32-bit mode) or 16.66MHz (24-bit mode). Audio Channel The I2S audio channel supports audio sampling rates from 8kHz to 192kHz and audio word lengths from 4 bits to 32 bits. The audio bit clock (SCK) does not need to be synchronized with PCLKIN. The MAX9259 automatically encodes audio data into a single bit stream synchronous with PCLKIN. The MAX9260 decodes the audio stream and stores audio words in a FIFO. Audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in I2S format. The audio channel is enabled by default. When the audio channel is disabled, the SD pins on both sides are treated as a regular parallel data pin. PCLK_ frequencies can limit the maximum supported audio sampling rate. Table 2 lists the maximum audio sampling rate for various PCLK_ frequencies. Spreadspectrum settings do not affect the I2S data rate or WS clock frequency. 28 PCLK_ FREQUENCY (DRS = HIGH) (MHz) Additional MCLK Output for Audio Applications Some audio DACs such as the MAX9850 do not require a synchronous main clock (MCLK), while other DACs require MCLK to be a specific multiple of WS. If an audio DAC chip needs the MCLK to be a multiple of WS, synchronize the I2S audio data with PCLK_ of the GMSL, which is typical for most applications. Select the PCLK_ to be the multiple of WS, or use a clock synthesis chip, such as the MAX9491, to regenerate the required MCLK from PCLK_ or SCK. For audio applications that cannot directly use the PCLKOUT output, the MAX9260 provides a divided MCLK output on DOUT28 at the expense of one less parallel line in 32-bit mode (24-bit mode is not affected). By default, DOUT28 operates as a parallel data output and MCLK is turned off. Set MCLKDIV (MAX9260 register 0x12, D[6:0]) to a non-zero value to enable the MCLK output. Set MCLKDIV to 0x00 to disable MCLK and set DOUT28 as a parallel data output. The output MCLK frequency is: fMCLK = fSRC MCLKDIV where fSRC is the MCLK source frequency (Table 3) and MCLKDIV is the divider ratio from 1 to 127. Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 3. MAX9260 fSRC Settings MCLKSRC SETTING (REGISTER 0x12, D7) DATA-RATE SETTING High speed 0 Low speed 1 -- BIT-WIDTH SETTING MCLK SOURCE FREQUENCY (fSRC) 24-bit mode 3 x fPCLKOUT 32-bit mode 4 x fPCLKOUT 24-bit mode 6 x fPCLKOUT 8 x fPCLKOUT 32-bit mode -- Internal oscillator (120MHz typ) Choose MCLKDIV values so that fMCLK is not greater than 60MHz. MCLK frequencies derived from PCLK_ (MCLKSRC = 0) are not affected by spread-spectrum settings in the deserializer (MAX9260). Enabling spread spectrum in the serializer (MAX9259), however, introduces spread spectrum into MCLK. Spread-spectrum settings of either device do not affect MCLK frequencies derived from the internal oscillator. The internal oscillator frequency ranges from 100MHz to 150MHz over all process corners and operating conditions. MAX9259 or MAX9260 to I2C. The converted I2C bit rate is the same as the original UART bit rate. Control-Channel and Register Programming The MAX9259 embeds control signals going to the MAX9260 in the high-speed forward link. Do not send a low value longer than 100Fs in either base or bypass mode. The MAX9260 uses a proprietary differential line coding to send signals back towards the MAX9259. The speed of the control link ranges from 100kbps to 1Mbps in both directions. The MAX9259/MAX9260 automatically detect the control-channel bit rate in base mode. Packet bit rates can vary up to 3.5x from the previous bit rate (see the Changing the Data Frequency section). Figure 24 shows the UART protocol for writing and reading in base mode between the FC and the MAX9259/MAX9260. The FC uses the control link to send and receive control data over the STP link simultaneously with the high-speed data. Configuring the CDS pin allows the FC to control the link from either the MAX9259 or the MAX9260 side to support video-display or image-sensing applications. The control link between the FC and the MAX9259 or MAX9260 runs in base mode or bypass mode according to the mode selection (MS) input of the device connected to the FC. Base mode is a half-duplex control link and the bypass mode is a full-duplex control link. In base mode, the FC is the host and accesses the registers of both the MAX9259 and MAX9260 from either side of the link by using the GMSL UART protocol. The FC can also program the peripherals on the remote side by sending the UART packets to the MAX9259 or MAX9260, with UART packets converted to I2C by the device on the remote side of the link (MAX9260 for LCD or MAX9259 for image-sensing applications). The FC communicates with a UART peripheral in base mode (through INTTYPE register settings) using the half-duplex default GMSL UART protocol of the MAX9259 and MAX9260. The device addresses of the MAX9259 and MAX9260 in the base mode are programmable. The default values are 0x80 and 0x90, respectively. In base mode, when the peripheral interface uses I2C (default), the MAX9259/MAX9260 only convert packets that have device addresses different from those of the Maxim Integrated In bypass mode, the FC bypasses the MAX9259/ MAX9260 and communicates with the peripherals directly using its own defined UART protocol. The FC cannot access the MAX9259/MAX9260's registers in this mode. Peripherals accessed through the forward control channel using the UART interface need to handle at least one PCLK_ period of jitter due to the asynchronous sampling of the UART signal by PCLK_. Figure 25 shows the UART data format. Even parity is used. Figures 26 and 27 detail the formats of the SYNC byte (0x79) and ACK byte (0xC3). The FC and the connected slave chip generate the SYNC byte and ACK byte, respectively. Certain events such as device wake-up and interrupt generate signals on the control path and should be ignored by the FC. All data written to the internal registers do not take affect until after the acknowledge byte is sent. This allows the FC to verify that write commands are processed without error, even if the result of the write command directly affects the serial link. The slave uses the SYNC byte to synchronize with the host UART data rate automatically. If the INT or MS inputs of the MAX9260 toggles while there is control-channel communication, the control-channel communication can be corrupted. In the event of a missed acknowledge, the FC should 29 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel WRITE DATA FORMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N ACK MASTER WRITES TO SLAVE MASTER READS FROM SLAVE READ DATA FRMAT SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N MASTER READS FROM SLAVE Figure 24. UART Protocol for Base Mode 1 UART FRAME START D0 D1 D2 D3 FRAME 1 D4 D5 D6 D7 PARITY FRAME 2 STOP STOP FRAME 3 START STOP START BASE MODE USES EVEN PARITY Figure 25. UART Data Format for Base Mode START D0 D1 D2 D3 D4 D5 D6 D7 1 0 0 1 1 1 1 0 PARITY STOP Figure 26. SYNC Byte (0x79) assume there was an error in the packet transmission or response. In base mode, the FC must keep the UART Tx/ Rx lines high no more than four bit times between bytes in a packet. Keep the UART Tx/Rx lines high for at least 16 bit times before starting to send a new packet. As shown in Figure 28, the remote-side device converts the packets going to or coming from the peripherals from the UART format to the I2C format and vice versa. The remote device removes the byte number count and adds or receives the ACK between the data bytes of I2C. The I2C's data rate is the same as the UART data rate. 30 START D0 D1 D2 D3 D4 D5 D6 D7 1 1 0 0 0 0 1 1 PARITY STOP Figure 27. ACK Byte (0xC3) Interfacing Command-Byte-Only I2C Devices The MAX9259/MAX9260 UART-to-I2C conversion interfaces with devices that do not require register addresses, such as the MAX7324 GPIO expander. Change the communication method of the I2C master using the I2CMETHOD bit. I2CMETHOD = 1 sets command-byteonly mode, while I2CMETHOD = 0 sets normal mode where the first byte in the data stream is the register address. In this mode, the I2C master ignores the register address byte and directly reads/writes the subsequent data bytes (Figure 29). Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0) MAX9259/MAX9260 FC 11 SYNC FRAME 11 DEVICE ID + WR MAX9259/MAX9260 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 DATA 0 11 DATA N 11 ACK FRAME PERIPHERAL 1 S 7 DEV ID 1 1 W A 8 REG ADDR 8 DATA 0 1 A 1 A 8 DATA N 1 1 A P UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0) MAX9259/MAX9260 FC 11 SYNC FRAME 11 DEVICE ID + RD MAX9259/MAX9260 11 REGISTER ADDRESS 11 NUMBER OF BYTES 11 ACK FRAME 11 DATA 0 11 DATA N PERIPHERAL 1 S 7 DEV ID 8 REG ADDR 1 1 W A 1 1 A S : SLAVE TO MASTER : MASTER TO SLAVE 7 DEV ID 1 1 R A S: START 8 DATA 0 P: STOP 1 A 8 DATA N 1 1 A P A: ACKNOWLEDGE Figure 28. Format Conversion between UART and I2C with Register Address (I2CMETHOD = 0) UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1) FC 11 SYNC FRAME MAX9259/MAX9260 11 DEVICE ID + WR MAX9259/MAX9260 FC 11 REGISTER ADDRESS PERIPHERAL 1 7 S DEV ID 11 NUMBER OF BYTES 11 DATA N 1 1 W A 8 DATA 0 UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1) MAX9259/MAX9260 11 11 11 SYNC FRAME DEVICE ID + RD REGISTER ADDRESS MAX9259/MAX9260 11 DATA 0 11 NUMBER OF BYTES 11 ACK FRAME 11 ACK FRAME 1 A 8 DATA N 11 DATA 0 1 1 A P 11 DATA N PERIPHERAL 1 S : MASTER TO SLAVE : SLAVE TO MASTER 7 DEV ID S: START 1 1 R A 8 DATA 0 P: STOP 1 A 8 DATA N 1 1 A P A: ACKNOWLEDGE Figure 29. Format Conversion between UART and I2C in Command-Byte-Only Mode (I2CMETHOD = 1) Maxim Integrated 31 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 4. MAX9259 CML Driver Strength (Default Level, CMLLVL = 11) PREEMPHASIS LEVEL (dB)* PREEMPHASIS SETTING (0x05, D[3:0]) ICML (mA) IPRE (mA) -6.0 0100 12 -4.1 0011 -2.5 0010 -1.2 SINGLE-ENDED VOLTAGE SWING MAX (mV) MIN (mV) 4 400 200 13 3 400 250 14 2 400 300 0001 15 1 400 350 0 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.3 1010 16 3 475 325 4.4 1011 16 4 500 300 6.0 1100 15 5 500 250 8.0 1101 14 6 500 200 10.5 1110 13 7 500 150 14.0 1111 12 8 500 100 *Negative preemphasis levels denote deemphasis. Interrupt Control The INT of the MAX9259 is the interrupt output and the INT of the MAX9260 is the interrupt input. The interrupt output on the MAX9259 follows the transitions at the interrupt input of the MAX9260. This interrupt function supports remote-side functions such as touch-screen peripherals, remote power-up, or remote monitoring. Interrupts that occur during periods where the reverse control channel is disabled, such as link startup/shutdown, are automatically resent once the reverse control channel becomes available again. Bit D4 of register 0x06 in the MAX9260 also stores the interrupt input state. Writing to the SETINT register bit also sets the INT output of the MAX9259. In addition, the FC sets the INT output of the MAX9259 by writing to the SETINT register bit. In normal operation, the state of the interrupt output changes when the interrupt input on the MAX9260 toggles. Preemphasis Driver The serial line driver in the MAX9259 employs currentmode logic (CML) signaling. The driver generates an adjustable preemphasized waveform according to the cable length and characteristics. There are 13 preemphasis settings, as shown in Table 4. Negative 32 preemphasis levels are deemphasis levels in which the preemphasized swing level is the same as normal swing, but the no-transition data is deemphasized. Program the preemphasis levels through register 0x05 D[3:0] of the MAX9259. This preemphasis function compensates the high-frequency loss of the cable and enables reliable transmission over longer link distances. Additionally, a lower power drive mode can be entered by programming CMLLVL bits (0x05 D[5:4]) to reduce the driver strength down to 75% (CMLLVL = 10), or 50% (CMLLVL = 01) from 100% (CMLLVL = 11, default). Line Equalizer The MAX9260 includes an adjustable line equalizer to further compensate cable attenuation at high frequencies. The cable equalizer has 11 selectable levels of compensation from 2.1dB to 13dB (Table 5). The EQS input selects the default equalization level at power-up. The state of EQS is latched upon power-up or when resuming from power-down mode. To select other equalization levels, set the corresponding register bits in the MAX9260 (0x05 D[3:0]). Use equalization in the MAX9260, together with preemphasis in the MAX9259 to create the most reliable link for a given cable. Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 5. MAX9260 Cable Equalizer Boost Levels BOOST SETTING (0x05 D[3:0]) TYPICAL BOOST GAIN (dB) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 Power-up default (EQS = high) 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 Power-up default (EQS = low) 1010 11.7 1011 13 Spread Spectrum To reduce the EMI generated by the transitions on the serial link and parallel outputs, both the MAX9259 and MAX9260 support spread spectrum. Turning on spread spectrum on the MAX9260 spreads the parallel video outputs. Turning on spread spectrum on the MAX9259 spreads the serial link, along with the MAX9260 parallel outputs. Do not enable spread spectrum for both the MAX9259 and MAX9260. The six selectable spreadspectrum rates at the MAX9259 serial output are Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6). Some spread-spectrum rates can only be used at lower PCLK_ frequencies (Table 7). There is no PCLK_ frequency limit for the 0.5% spread rate. The two selectable spreadspectrum rates at the MAX9260 parallel outputs are Q2% and Q4% (Table 8). Set the MAX9259 SSEN input high to select 0.5% spread at power-up and SSEN input low to select no spread at power-up. Set the MAX9260 SSEN input high to select 2% spread at power-up and SSEN input low to select no spread at power-up. The state of SSEN is latched upon power-up or when resuming from power-down mode. Whenever the MAX9259 spread spectrum is turned on Table 6. Serial Output Spread SS SPREAD (%) 000 No spread spectrum. Power-up default when SSEN = low. 001 Q0.5% spread spectrum. Power-up default when SSEN = high. 010 Q1.5% spread spectrum 011 Q2% spread spectrum 100 No spread spectrum 101 Q1% spread spectrum 110 Q3% spread spectrum 111 Q4% spread spectrum Table 7. MAX9259 Spread-Spectrum Rate Limitations 24-BIT MODE PCLKIN FREQUENCY (MHz) 32-BIT MODE PCLKIN FREQUENCY (MHz) SERIAL LINK BIT RATE (Mbps) AVAILABLE SPREAD RATES < 33.3 < 25 < 1000 All rates available 33.3 to < 66.7 20 to < 50 1000 to < 2000 1.5%, 1.0%, 0.5% 66.7+ 50+ 2000+ 0.5% Maxim Integrated 33 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 8. MAX9260 Parallel Output Spread SS SPREAD (%) 00 No spread spectrum. Power-up default when SSEN = low. 01 Q2% spread spectrum. Power-up default when SSEN = high. 10 No spread spectrum 11 Q4% spread spectrum Table 9. MAX9259 Modulation Coefficients and Maximum SDIV Settings BIT-WIDTH MODE SPREAD-SPECTRUM SETTING (%) MODULATION COEFFICIENT (decimal) SDIV UPPER LIMIT (decimal) 32-Bit 24-Bit 1 104 40 0.5 104 63 3 152 27 1.5 152 54 4 204 15 2 204 30 1 80 52 0.5 80 63 3 112 37 1.5 112 63 4 152 21 2 152 42 Table 10. MAX9260 Modulation Coefficients and Maximum SDIV Settings SPREAD-SPECTRUM SETTING (%) MODULATION COEFFICIENT (decimal) SDIV UPPER LIMIT (decimal) 4 208 15 2 208 30 or off, the serial link automatically restarts and remains unavailable while the MAX9260 relocks to the serial data. Manual Programming of the SpreadSpectrum Divider Turning on spread spectrum on either the MAX9259 or MAX9260 side does not affect the audio data stream. Changes in the MAX9259 spread settings only affect MCLK output if it is derived from PCLK_ (MCLKSRC = 0). The modulation rates for the MAX9259 or the MAX9260 relate to the PCLK_ frequency as follows: Both devices include a sawtooth divider to control the spread-modulation rate. Autodetection or manual programming of the PCLK_ operation range guarantees a spread-spectrum modulation frequency within 20kHz to 40kHz. Additionally, manual configuration of the sawtooth divider (SDIV, 0x03 D[5:0]) allows the user to set a specific modulation frequency for a specific PCLK_ rate. Always keep the modulation frequency between 20kHz to 40kHz to ensure proper operation. where: 34 fM= (1 + DRS) fPCLK_ MOD x SDIV fM = Modulation frequency DRS = DRS pin input value (0 or 1) fPCLK_ = Parallel clock frequency (12.5MHz to 104MHz) MOD = Modulation coefficient given in Table 9 for the MAX9259 and Table 10 for the MAX9260 SDIV = 6-bit (MAX9259) or 5-bit (MAX9260) SDIV setting, manually programmed by the FC Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel To program the SDIV setting, first look up the modulation coefficient according to the part number and desired bit-width and spread-spectrum settings. Solve the above equation for SDIV using the desired parallel clock and modulation frequencies. If the calculated SDIV value is larger than the maximum allowed SDIV value in Tables 9 or 10, set SDIV to the maximum value. Sleep Mode The serializer/deserializer include a low-power sleep mode to reduce power consumption on the device not attached to the FC (MAX9260 in LCD applications and MAX9259 in camera applications). Set the corresponding remote IC's SLEEP bit to 1 to initiate sleep mode. The MAX9259 sleeps immediately after setting its SLEEP = 1. The MAX9260 sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its SLEEP = 1. See the Link Startup Procedure section for details on waking up the device for different FC and starting conditions. The FC side device cannot enter into sleep mode, and its SLEEP bit remains at 0. Use the PWDN input pin to bring the FC side device into a low-power state. Configuration Link Mode The MAX9259/MAX9260 include a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid parallel clock input. In either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. An internal oscillator provides PCLK_ for establishing the serial configuration link between the MAX9259 and MAX9260. The parallel output clock and data lines are disabled in the MAX9260. The LOCK output remains low even after a successful configuration link lock. Set CLINKEN = 1 on the MAX9259 to turn on the configuration link. The configuration link remains active as long as the video link has not been enabled. The video link overrides the configuration link and attempts to lock when SEREN = 1. Link Startup Procedure Table 11 lists four startup cases for video-display applications. Table 12 lists two startup cases for imagesensing applications. In either display or image-sensing applications, the control link is always available after the high-speed data link or the configuration link is established and the MAX9259/MAX9260 registers or the peripherals are ready for programming. Maxim Integrated Video-Display Applications For the video-display application, with a remote display unit, connect the FC to the serializer (MAX9259) and set CDS = low for both the MAX9259 and MAX9260. Table 11 summarizes the four startup cases based on the settings of AUTOS and MS. Case 1: Autostart Mode After power-up or when PWDN transitions from low to high for both the serializer and deserializer, the serial link establishes if a stable PCLK_ is present. The MAX9259 locks to PCLK_ and sends the serial data to the MAX9260. The MAX9260 then detects activity on the serial link and locks to the input serial data. Case 2: Standby Start Mode After power-up, or when PWDN transitions from low to high for both the serializer and deserializer, the MAX9260 starts up in sleep mode, and the MAX9259 stays in standby mode (does not send serial data). Use the FC and program the MAX9259 to set SEREN = 1 to establish a video link or CLINKEN = 1 to establish the configuration link. After locking to a stable PCLK_ (for SEREN = 1) or the internal oscillator (for CLINKEN = 1), the MAX9259 sends a wake-up signal to the deserializer. The MAX9260 exits sleep mode after locking to the serial data and sets SLEEP = 0. If after 8ms the deserializer does not lock to the input serial data, the MAX9260 goes back to sleep, and the internal sleep bit remains uncleared (SLEEP = 1). Case 3: Remote Side Autostart Mode After power-up, or when PWDN transitions from low to high, the remote device (MAX9260) starts up and tries to lock to an incoming serial signal with sufficient power. The host side (MAX9259) is in standby mode and does not try to establish a link. Use the FC and program the MAX9259 to set SEREN = 1 (and apply a stable PCLK_) to establish a video link, or CLINKEN = 1 to establish the configuration link. In this case, the MAX9260 ignores the short wake-up signal sent from the MAX9259. Case 4: Remote Side in Sleep Mode After power-up or when PWDN transitions from low to high, the remote device (MAX9260) starts up in sleep mode. The high-speed link establishes automatically after MAX9259 powers up with a stable PCLK_ and sends a wake-up signal to the MAX9260. Use this mode in applications where the MAX9260 powers up before the MAX9259. 35 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 11. Startup Selection for Video-Display Applications (CDS = Low) CASE AUTOS (MAX9259) MAX9259 POWER-UP STATE MS (MAX9260) MAX9260 POWER-UP STATE LINK STARTUP MODE 1 Low Serialization enabled Low Normal (SLEEP = 0) Both devices power up with serial link active (autostart) Sleep mode (SLEEP = 1) Serial link is disabled and the MAX9260 powers up in sleep mode. Set SEREN = 1 or CLINKEN = 1 in the MAX9259 to start the serial link and wake up the MAX9260. Normal (SLEEP = 0) Both devices power up in normal mode with the serial link is disabled. Set SEREN = 1 or CLINKEN = 1 in the MAX9259 to start the serial link. Sleep mode (SLEEP = 1) MAX9260 starts in sleep mode. Link autostarts upon MAX9259 power-up. Use this case when the MAX9260 powers up before the MAX9259. 2 High 3 Serialization disabled High 4 Serialization disabled Low AUTOS PIN SETTING LOW HIGH High Serialization enabled Low High SEREN BIT POWER-UP VALUE CLINKEN = 0 OR SEREN = 1 1 0 POWER-DOWN OR POWER-OFF PWDN = HIGH, POWER-ON AUTOS = LOW CLINKEN = 0 OR SEREN = 1 POWER-ON IDLE CLINKEN = 1 CONFIG LINK STARTING CONFIG LINK UNLOCKED CONFIG LINK OPERATING CONFIG LINK PROGRAM REGISTERS LOCKED PWDN = LOW OR POWER-OFF ALL STATES PWDN = HIGH POWER-ON, AUTOS = LOW SEREN = 0, NO PCLKIN SEREN = 1, PCLKIN RUNNING SEREN = 0, OR NO PCLKIN VIDEO LINK LOCKING VIDEO LINK LOCKED PRBSEN = 0 VIDEO LINK OPERATING PRBSEN = 1 VIDEO LINK PRBS TEST VIDEO LINK UNLOCKED Figure 30. MAX9259 State Diagram, CDS = Low (LCD Application) 36 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel SLEEP = 1, VIDEO LINK OR CONFIG LINK NOT LOCKED AFTER 8ms MS PIN SETTING SLEEP BIT POWER-UP VALUE LOW HIGH 0 1 SLEEP WAKE-UP SIGNAL POWER-ON IDLE SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER FC SETS SLEEP = 1 SEND INT TO INT CHANGES FROM LOW TO HIGH OR HIGH TO LOW MAX9259 SIGNAL DETECTED PWDN = HIGH, POWER-ON CONFIG LINK UNLOCKED SERIAL PORT LOCKING CONFIG LINK OPERATING PROGRAM REGISTERS CONFIG LINK LOCKED VIDEO LINK LOCKED VIDEO LINK UNLOCKED 0 SLEEP PRBSEN = 0 ALL STATES PWDN = LOW OR POWER-OFF POWER-DOWN OR POWER-OFF VIDEO LINK OPERATING 0 PRBSEN = 1 VIDEO LINK PRBS TEST SLEEP Figure 31. MAX9260 State Diagram, CDS = Low (LCD Application) Image-Sensing Applications For image-sensing applications, with remote camera unit(s), connect the FC to the deserializer (MAX9260) and set CDS = high for both the MAX9259 and MAX9260. The MAX9260 powers up normally (SLEEP = 0) and continuously tries to lock to a valid serial input. Table 12 summarizes the two startup cases, based on the state of the MAX9259 AUTOS pin. Case 1: Autostart Mode After power-up, or when PWDN transitions from low to high, the MAX9259 locks to a stable PCLKIN and sends the high-speed data to the MAX9260. The MAX9260 locks to the serial data and outputs the parallel video data and PCLKOUT. Case 2: Sleep Mode After power-up, or when PWDN transitions from low to high, the MAX9259 starts up in sleep mode. To wake up the MAX9259, use the FC to send a regular UART frame containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1Mbps. The low-power wake-up receiver of the MAX9259 detects the wake-up frame over the reverse control channel and powers up. Reset the sleep bit (SLEEP = 0) of the MAX9259 using a regular control-channel write packet to power up the device fully. Send the sleep bit write packet at least 500Fs after the wake-up frame. The MAX9259 goes back to sleep mode if its sleep bit is not cleared within 8ms (typ) after detecting a wake-up frame. Table 12. Startup Selection for Image-Sensing Applications (CDS = High) CASE AUTOS (MAX9259) MAX9259 POWER-UP STATE MAX9260 POWER-UP STATE 1 Low Serialization enabled Normal (SLEEP = 0) Autostart 2 High Sleep mode (SLEEP = 1) Normal (SLEEP = 0) MAX9259 is in sleep mode. Wake up the MAX9259 through the control channel (FC attached to MAX9260). Maxim Integrated LINK STARTUP MODE 37 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel AUTOS PIN SETTING LOW HIGH POWER-UP VALUE SEREN SLEEP 1 0 0 1 SLEEP CLINKEN = 0 OR SEREN = 1 CLINKEN = 0 OR SEREN = 1 SLEEP = 1 FOR > 8ms SLEEP = 0, WAKE-UP REVERSE LINK POWER-ON IDLE SEREN = 0 CONFIG LINK STARTED CLINKEN = 1 WAKE-UP SIGNAL PWDN = HIGH, POWER-ON, AUTOS = HIGH SLEEP = 1 ALL STATES PWDN = LOW OR POWER-OFF POWER-DOWN OR POWER-OFF SLEEP = 0, SLEEP = 1 SEREN = 1, PCLKIN RUNNING PWDN = HIGH, POWER-ON AUTOS = LOW CONFIG LINK LOCKED CONFIG LINK OPERATING PROGRAM REGISTERS SEREN = 0 OR NO PCLKIN SEREN = 0 OR NO PCLKIN VIDEO LINK LOCKING CONFIG LINK UNLOCKED VIDEO LINK LOCKED VIDEO LINK OPERATING PRBSEN = 0 PRBSEN = 1 VIDEO LINK PRBS TEST VIDEO LINK UNLOCKED Figure 32. MAX9259 State Diagram, CDS = High (Camera Application) POWER-ON IDLE (REVERSE CHANNEL ACTIVE) NO SIGNAL DETECTED ALL STATES SIGNAL DETECTED PWDN = HIGH, POWER ON PWDN = LOW OR POWER-OFF SERIAL PORT LOCKING VIDEO LINK LOCKED POWER-DOWN OR POWER-OFF CONFIG LINK UNLOCKED CONFIG LINK OPERATING CONFIG LINK LOCKED PROGRAM REGISTERS VIDEO LINK UNLOCKED PRBSEN = 0 VIDEO LINK OPERATING PRBSEN = 1 VIDEO LINK PRBS TEST Figure 33. MAX9260 State Diagram, CDS = High (Camera Application) 38 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Applications Information MAX9260 Error Checking The MAX9260 checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register (DECERR, 0x0D). If a large number of decoding errors are detected within a short duration, the deserializer loses lock and stops the error counter. The deserializer then attempts to relock to the serial data. DECERR resets upon successful video link lock, successful readout of DECERR (through UART), or whenever autoerror reset is enabled. The MAX9260 does not check for decoding errors during the internal PRBS test and DECERR is reset to 0x00. ERR Output The MAX9260 has an open-drain ERR output. This output asserts low whenever the number of decoding errors exceed the error threshold (ERRTHR, 0x0C) during normal operation, or when at least one PRBS error is detected during PRBS test. ERR reasserts high whenever DECERR (0x0D) resets, due to DECERR readout, video link lock, or autoerror reset. Autoerror Reset The default method to reset errors is to read the respective error registers in the MAX9260 (0x0D, 0x0E). Autoerror reset clears the decoding-error counter (DECERR) and the ERR output ~1Fs after ERR goes low. Autoerror reset is disabled on power-up. Enable autoerror reset through AUTORST (0x06 D6). Autoerror reset does not run when the device is in PRBS test mode. Self PRBS Test The MAX9259/MAX9260 link includes a PRBS pattern generator and bit-error verification function. Set PRBSEN = 1 (0x04 D5) first in the MAX9259 and then the MAX9260 to start the PRBS test. Set PRBSEN = 0 (0x04 D5) first in the MAX9260 and then the MAX9259 to exit the PRBS self test. The MAX9260 uses an 8-bit register (0x0E) to count the number of detected errors. The control link also controls the start and stop of the error counting. During PRBS mode, the device does not count decoding errors and the ERR output reflects PRBS errors only. Autoerror reset does not run when the device is in PRBS mode. Microcontrollers on Both Sides of the GMSL Link (Dual C Control) Usually the FC is either on the serializer (MAX9259) side for video-display applications, or on the deserializer (MAX9260) side for image-sensing applications. For the former case, both the CDS pins of the MAX9259/ Maxim Integrated MAX9260 are set to low, and for the later case, the CDS pins are set to high. However, if the CDS pin of the MAX9259 is low and the CDS pin of the MAX9260 is high, then the MAX9259/MAX9260 can both connect to FCs simultaneously. In such a case, the FCs on either side can communicate with the MAX9259/MAX9260 UART protocol. Contentions of the control link may happen if the FCs on both sides are using the link at the same time. The MAX9259/MAX9260 do not provide the solution for contention avoidance. The serializer/deserealizer do not send an acknowledge frame when communication fails due to contention. Users can always implement a higherlayer protocol to avoid the contention. In addition, if UART communication across the serial link is not required, the FCs can disable the forward and reverse control channel through the FWDCCEN and REVCCEN bits (0x04 D[1:0]) in the MAX9259/MAX9260. UART communication across the serial link is stopped and contention between FCs no longer occurs. During the dual FC operation, if one of the CDS pins on either side changes state, the link resumes the corresponding state described in the Link Startup Procedure section. As an example of dual FC use in an image-sensing link, the MAX9259 may be in sleep mode and waiting to be waked up by the MAX9260. After wake-up, the serializerside FC sets the MAX9259 CDS pin low and assumes master control of the MAX9259 registers. Jitter-Filtering PLL In some applications, the parallel bus input clock to the MAX9259 (PCLKIN) includes noise, which reduces link reliability. The MAX9259 has a narrow-band jitter-filtering PLL to attenuate frequency components outside the PLL's bandwidth (< 100kHz typ). Enable the jitter-filtering PLL by setting DISFPLL = 0 (0x05 D6). Changing the Data Frequency Both the video data rate (fPCLK_) and the control data rate (fUART) can be changed on-the-fly to support applications with multiple clock speeds. Slow speed/ performance modes allow significant power savings when a system's full capabilities are not required. Enable the MAX9259/MAX9260 link after PCLK_ stabilizes. Stop PCLKIN for 5s and restart the serial link or toggle SEREN after each change in the parallel clock frequency to recalibrate any automatic settings if a clean frequency change cannot be guaranteed. The reverse control channel remains unavailable for 350Fs after serial link start or stop. Limit on-the-fly changes in fUART to factors of less than 3.5 at a time to ensure that the device 39 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 13. MAX9259 Line-Fault Mapping REGISTER ADDRESS BITS NAME D[3:2] VALUE LFNEG 0x08 D[1:0] LFPOS 00 Negative cable wire shorted to battery 01 Negative cable wire shorted to ground 10 Normal operation 11 Negative cable wire open 00 Positive cable wire shorted to battery 01 Positive cable wire shorted to ground 10 Normal operation 11 Positive cable wire open Line-Fault Detection Table 14. Staggered Output Delay OUTPUT OUTPUT DELAY RELATIVE TO DOUT0 (ns) DISSTAG = 0 DISSTAG = 1 DOUT0-DOUT5, DOUT21, DOUT22 0 0 DOUT6-DOUT10, DOUT23, DOUT24 0.5 0 DOUT11-DOUT15, DOUT25, DOUT26 1 0 DOUT16-DOUT20, DOUT27, DOUT28 1.5 0 PCLKOUT 0.75 0 recognizes the UART sync pattern. For example, when lowering the UART frequency from 1Mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively. LOCK Output Loopback Connect the LOCK output to the INT input of the MAX9260 to loopback LOCK to the MAX9259. The interrupt output on the MAX9259 follows the transitions at the LOCK output of the MAX9260. Reverse-channel communication does not require an active forward link to operate and accurately tracks the LOCK status of the video link. LOCK asserts for video link only and not for the configuration link. MAX9260 GPIOs The MAX9260 has two open-drain GPIOs available. GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output state of the GPIOs. The GPIO input buffers are always enabled. The input states are stored in GPIO1 and GPIO0 (0x06 D2, D0). Set GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0 as an input. 40 LINE-FAULT TYPE The line-fault detector in the MAX9259 monitors for line failures such as short to ground, short to power supply, and open link for system fault diagnosis. Figure 3 shows the required external resistor connections. LFLT = low when a line fault is detected and LFLT = high when the line returns to normal. The line-fault type is stored in 0x08 D[3:0] of the MAX9259. The fault-detector threshold voltages are referenced to the MAX9259 ground. Additional passive components set the DC level of the cable (Figure 3). If the MAX9259 and MAX9260 grounds are different, the link DC voltage during normal operation can vary and cross one of the fault-detection thresholds. For the fault-detection circuit, select the resistor's power rating to handle a short to the battery. Table 13 lists the mapping for line-fault types. Staggered Parallel Data Outputs The MAX9260 staggers the parallel data outputs to reduce EMI and noise. Staggering outputs also reduce the power-supply transient requirements. By default, the deserializer staggers outputs according to Table 14. Disable output staggering through the DISSTAG bit (0x06 D7) Choosing I2C/UART Pullup Resistors Both I2C/UART open-drain lines require pullup resistors to provide a logic-high level. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the I2C specifications in the Electrical Characteristics table for details). To meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time tR = 0.85 x RPULLUP x CBUS < 300ns. The waveforms Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel are not recognized if the transition time becomes too slow. The MAX9259/MAX9260 support I2C/UART rates up to 1Mbps. AC-Coupling AC-coupling isolates the receiver from DC voltages up to the voltage rating of the capacitor. Four capacitors--two at the serializer output and two at the deserializer input-- are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. Selection of AC-Coupling Capacitors Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is finite, starting the signal transition from different voltage levels causes timing jitter. The time constant for an AC-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. The RC network for an AC-coupled link consists of the CML receiver termination resistor (RTR), the CML driver termination resistor (RTD), and the series AC-coupling capacitors (C). The RC time constant for four equal-value series capacitors is (C x (RTD + RTR))/4. RTD and RTR are required to match the transmission line impedance (usually 100I). This leaves the capacitor selection to change the system time constant. Use at least 0.22FF (100V) high-frequency surface-mount ceramic capacitors to pass the lower speed reverse-channel signal. Use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. Power-Supply Circuits and Bypassing The MAX9259 uses an AVDD and DVDD of 1.7V to 1.9V. The MAX9260 uses an AVDD and DVDD of 3.0V to 3.6V. All single-ended inputs and outputs on the MAX9259/ MAX9260 derive power from an IOVDD of 1.7V to 3.6V. The input levels or output levels scale with IOVDD. Proper voltage-supply bypassing is essential for highfrequency circuit stability. Cables and Connectors Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magneticfield canceling effects. Balanced cables pick up noise as common mode rejected by the CML receiver. Table 15 lists the suggested cables and connectors used in the GMSL link. Board Layout Separate the parallel signals and CML high-speed serial signals to prevent crosstalk. Use a four-layer PCB with separate layers for power, ground, CML, and digital signals. Layout PCB traces close to each other and have a 100I differential characteristic impedance. The trace dimensions depend on the type of trace used (microstrip or stripline). Note that two 50I PCB traces do not have 100I differential impedance when brought close together--the impedance goes down when the traces are brought closer. Route the PCB traces for a CML channel (there are two conductors per CML channel) in parallel to maintain the differential characteristic impedance. Avoid vias. If vias must be used, use only one pair per CML channel and place the via for each line at the same point along the length of the PCB traces. This way, any reflections occur at the same time. Do not make vias into test points for Table 15. Suggested Connectors and Cables for GMSL SUPPLIER JAE Electronics, Inc. Nissei Electric Co., Ltd. Rosenberger Hochfrequenztechnik GmbH Maxim Integrated CONNECTOR CABLE MX38-FF A-BW-Lxxxxx GT11L-2S F-2WME AWG28 D4S10A-40ML5-Z Dacar 538 41 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel 1MI HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 100pF ATE. Keep PCB traces that make up a differential pair equal in length to avoid skew within the differential pair. RD 1.5kI ESD Protection DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 34. Human Body Model ESD Test Circuit RD 330I HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 150pF The MAX9259/MAX9260 ESD tolerance is rated for Human Body Model, IEC 61000-4-2, and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. Serial outputs on the MAX9259 and serial inputs on the MAX9260 meet ISO 10605 ESD protection and IEC 61000-4-2 ESD protection. All other pins meet the Human Body Model ESD tolerances. The Human Body Model discharge components are CS = 100pF and RD = 1.5kI (Figure 34). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330I (Figure 35). The ISO 10605 discharge components are CS = 330pF and RD = 2kI (Figure 36). DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit RD 2kI HIGHVOLTAGE DC SOURCE CHARGE-CURRENTLIMIT RESISTOR CS 330pF DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 36. ISO 10605 Contact Discharge ESD Test Circuit 42 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16. MAX9259 Register Table REGISTER ADDRESS 0x00 0x01 BITS NAME VALUE D[7:1] SERID XXXXXXX D0 -- 0 D[7:1] DESID XXXXXXX D0 -- 0 D[7:5] SS 0x02 D4 D[3:2] D[1:0] D[7:6] AUDIOEN PRNG SRNG Maxim Integrated Reserved Deserializer device address Reserved 000 001 Q0.5% spread spectrum. Power-up default when SSEN = high. 010 Q1.5% spread spectrum 011 Q2% spread spectrum 100 No spread spectrum 101 Q1% spread spectrum 110 Q3% spread spectrum 111 Q4% spread spectrum 0 Disable I2S channel 1 Enable I2S channel 00 12.5MHz to 25MHz pixel clock 01 25MHz to 50MHz pixel clock 10 50MHz to 104MHz pixel clock 11 Automatically detect the pixel clock range 00 0.5 to 1Gbps serial-data rate 01 1 to 2Gbps serial-data rate 10 2 to 3.125Gbps serial-data rate 11 Automatically detect serial-data rate 00 Calibrate spread-modulation rate only once after locking 01 Calibrate spread-modulation rate every 2ms after locking 10 Calibrate spread-modulation rate every 16ms after locking 11 Calibrate spread-modulation rate every 256ms after locking AUTOFM SDIV Serializer device address No spread spectrum. Power-up default when SSEN = low. 0x03 D[5:0] FUNCTION 000000 Autocalibrate sawtooth divider XXXXXX Manual SDIV setting (see the Manual Programming of the Spread-Spectrum Divider section) DEFAULT VALUE 1000000 0 1001000 0 000, 001 1 11 11 00 000000 43 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16. MAX9259 Register Table (continued) REGISTER ADDRESS BITS D7 NAME CLINKEN D5 PRBSEN 0x04 D[3:2] FUNCTION 0 Disable serial link. Power-up default when AUTOS = high. Reverse-channel communication remains unavailable for 350Fs after the MAX9259 starts/stops the serial link. 1 Enable serial link. Power-up default when AUTOS = low. Reverse-channel communication remains unavailable for 350Fs after the MAX9259 starts/stops the serial link. 0 Disable configuration link 1 Enable configuration link 0 Disable PRBS test 1 Enable PRBS test 0 Normal mode. Default value depends on CDS and AUTOS pin values at power-up. 1 Activate sleep mode. Default value depends on CDS and AUTOS pin values at power-up. 00 Base mode uses I2C peripheral interface 01 Base mode uses UART peripheral interface SEREN D6 D4 VALUE 0, 1 SLEEP INTTYPE 10, 11 D1 D0 44 DEFAULT VALUE Disable reverse control channel from deserializer (receiving) 1 Enable reverse control channel from deserializer (receiving) 0 Disable forward control channel to deserializer (sending) 1 Enable forward control channel to deserializer (sending) FWDCCEN 0 0, 1 00 Base mode peripheral interface disabled 0 REVCCEN 0 1 1 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16. MAX9259 Register Table (continued) REGISTER ADDRESS BITS NAME D7 I2CMETHOD D6 DISFPLL D[5:4] CMLLVL 0x05 D[3:0] PREEMP VALUE FUNCTION 0 I2C conversion sends the register address 1 Disable sending of I2C register address (command-byte-only mode) 0 Filter PLL active 1 Filter PLL disabled 00 Do not use 01 200mV CML signal level 10 300mV CML signal level 11 400mV CML signal level 0000 Preemphasis off 0001 -1.2dB preemphasis 0010 -2.5dB preemphasis 0011 -4.1dB preemphasis 0100 -6.0dB preemphasis 0101 Do not use 0110 Do not use 0111 Do not use 1000 1.1dB preemphasis 1001 2.2dB preemphasis 1010 3.3dB preemphasis 1011 4.4dB preemphasis 1100 6.0dB preemphasis 1101 8.0dB preemphasis 1110 10.5dB preemphasis 1111 14.0dB preemphasis DEFAULT VALUE 0 1 11 0000 0x06 D[7:0] -- 01000000 Reserved 01000000 0x07 D[7:0] -- 00100010 Reserved 00100010 D[7:4] -- 0000 Reserved 0000 (read only) D[3:2] LFNEG 0x08 D[1:0] Maxim Integrated LFPOS 00 Negative cable wire shorted to battery 01 Negative cable wire shorted to ground 10 Normal operation 11 Negative cable wire open 00 Positive cable wire shorted to battery 01 Positive cable wire shorted to ground 10 Normal operation 11 Positive cable wire open 10 (read only) 10 (read only) 45 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 16. MAX9259 Register Table (continued) REGISTER ADDRESS BITS D7 NAME 0x1F FUNCTION 0 Set INT low when SETINT transitions from 1 to 0 1 Set INT high when SETINT transitions from 0 to 1 SETINT 0x0D 0x1E VALUE DEFAULT VALUE 0 D[6:4] -- 000 Reserved 000 D[3:0] -- 1111 Reserved 1111 D[7:0] ID 00000001 D[7:4] -- D[3:0] REVISION Device identifier (MAX9259 = 0x01) 00000001 (read only) 0000 Reserved 0000 (read only) XXXX Device revision (read only) X = Don't care. Table 17. MAX9260 Register Table REGISTER ADDRESS 0x00 0x01 BITS NAME VALUE D[7:1] SERID XXXXXXX D0 -- 0 D[7:1] DESID XXXXXXX D0 -- 0 Reserved 00 No spread spectrum. Power-up default when SSEN = low. 01 Q2% spread spectrum. Power-up default when SSEN = high. 10 No spread spectrum 11 Q4% spread spectrum 0 Reserved 0 Disable I2S channel 1 Enable I2S channel 00 12.5MHz to 25MHz pixel clock 01 25MHz to 50MHz pixel clock 10 50MHz to 104MHz pixel clock 11 Automatically detect the pixel clock range 00 0.5 to 1Gbps serial-data rate 01 1 to 2Gbps serial-data rate 10 2 to 3.125Gbps serial-data rate 11 Automatically detect serial-data rate D[7:6] D5 0x02 D4 D[3:2] D[1:0] 46 SS -- AUDIOEN PRNG SRNG FUNCTION Serializer device address Reserved Deserializer device address DEFAULT VALUE 1000000 0 1001000 0 00, 01 0 1 11 11 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 17. MAX9260 Register Table (continued) REGISTER ADDRESS BITS D[7:6] NAME D[4:0] SDIV D7 LOCKED D6 D5 0x04 -- D4 D[3:2] Calibrate spread-modulation rate only once after locking 01 Calibrate spread-modulation rate every 2ms after locking 10 Calibrate spread-modulation rate every 16ms after locking 11 Calibrate spread-modulation rate every 256ms after locking 0 Reserved 00000 Autocalibrate sawtooth divider XXXXX Manual SDIV setting (see the Manual Programming of the Spread-Spectrum Divider section) 0 LOCK output is low 1 LOCK output is high 0 Enable DOUT_, PCLKOUT, and I2S outputs. A transition on ENABLE changes the state of OUTENB. 1 Disable DOUT_, PCLKOUT, and I2S outputs. A transition on ENABLE changes the state of OUTENB. OUTENB PRBSEN 0 Disable PRBS test 1 Enable PRBS test 0 Normal mode default value depends on CDS and MS pin values at power-up) 1 Activate sleep mode default value depends on CDS and MS pin values at power-up) 00 Base mode uses I2C peripheral interface 01 Base mode uses UART peripheral interface SLEEP INTTYPE 10, 11 D1 D0 Maxim Integrated FUNCTION 00 AUTOFM 0x03 D5 VALUE Disable reverse control channel to serializer (sending) 1 Enable reverse control channel to serializer (sending) 0 Disable forward control channel from serializer (receiving) 1 Enable forward control channel from serializer (receiving) FWDCCEN 00 0 00000 0 (read only) 0, 1 0 0, 1 00 Base mode peripheral interface disabled 0 REVCCEN DEFAULT VALUE 1 1 47 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 17. MAX9260 Register Table (continued) REGISTER ADDRESS BITS D7 D[6:5] D4 NAME I2CMETHOD HPFTUNE PDHF 0x05 D[3:0] D7 D6 0x06 48 EQTUNE DISSTAG VALUE 0 I2C conversion sends the register address 1 Disable sending of I2C register address (command-byte-only mode) 00 7.5MHz Equalizer highpass cutoff frequency 01 3.75MHz cutoff frequency 10 2.5MHz cutoff frequency 11 1.87MHz cutoff frequency 0 High-frequency boosting enabled 1 High-frequency boosting disabled 0000 2.1dB equalizer boost gain 0001 2.8dB equalizer boost gain 0010 3.4dB equalizer boost gain 0011 4.2dB equalizer boost gain 0100 5.2dB equalizer boost gain. Power-up default when EQS = high. 0101 6.2dB equalizer boost gain 0110 7dB equalizer boost gain 0111 8.2dB equalizer boost gain 1000 9.4dB equalizer boost gain 1001 10.7dB equalizer boost gain. Power-up default when EQS = low. 1010 11.7dB equalizer boost gain 1011 13dB equalizer boost gain 11XX Do not use 0 Enable staggered outputs 1 Disable staggered outputs 0 Do not automatically reset error registers and outputs 1 Automatically reset error registers and outputs AUTORST D5 DISINT D4 INT D3 GPIO1OUT D2 GPIO1 D1 GPIO0OUT D0 GPIO0 FUNCTION 0 Enable interrupt transmission to serializer 1 Disable interrupt transmission to serializer 0 INT input = low (read only) 1 INT input = high (read only) 0 Output low to GPIO1 1 Output high to GPIO1 0 GPIO1 is low 1 GPIO1 is high 0 Output low to GPIO0 1 Output high to GPIO0 0 GPIO0 is low 1 GPIO0 is high DEFAULT VALUE 0 01 0 0100, 1001 0 0 0 0 (read only) 1 1 (read only) 1 1 (read only) Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Table 17. MAX9260 Register Table (continued) REGISTER ADDRESS BITS NAME VALUE 0x07 D[7:0] -- 01010100 Reserved 01010100 0x08 D[7:0] -- 00110000 Reserved 00110000 0x09 D[7:0] -- 11001000 Reserved 11001000 0x0A D[7:0] -- 00010010 Reserved 00010010 0x0B D[7:0] -- 00100000 Reserved 00100000 0x0C D[7:0] ERRTHR XXXXXXXX Error threshold for decoding errors. ERR = low when DECERR > ERRTHR. 00000000 0x0D D[7:0] DECERR XXXXXXXX Decoding error counter. This counter remains zero while the device is in PRBS test mode. 00000000 (read only) 0x0E D[7:0] PRBSERR XXXXXXXX PRBS error counter 00000000 (read only) D7 MCLKSRC D[6:0] MCLKDIV D[7:0] 0x12 0x1E 0x1F DEFAULT VALUE FUNCTION 0 MCLK derived from PCLKOUT (see Table 3) 1 MCLK derived from internal oscillator 0 0000000 MCLK disabled XXXXXXX MCLK divider ID 00000010 Device identifier (MAX9260 = 0x02) 00000010 (read only) D[7:4] -- 0000 Reserved 0000 (read only) D[3:0] REVISION XXXX Device revision (read only) 0000000 X = Don't care. Typical Application Circuit 1.8V ECU VIDEO MAX9259 PCLK RGB HSYNC VSYNC PCLKIN DIN(0:27) DIN28 CDS AUTOS MAX9260 45.3kI 45.3kI 4.99kI 4.99kI PCLKOUT DOUT(0:27) CDS LMN1 PCLK RGB HSYNC VSYNC DISPLAY LMN0 INT TO PERIPHERALS RX/SDA UART TX RX LFLT INT IMS AUDIO WS SCK SD Maxim Integrated RX/SDA TX/SCL LFLT INT MS WS SCK SD OUT+ IN+ OUT- IN- 49.9kI TX/SCL LOCK SCL SDA 49.9kI WS SCK SD DOUT28/MCLK WS SCK SD MCLK MAX9850 49 MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Chip Information PROCESS: CMOS 50 Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 56 TQFN-EP T5688+2 21-0135 90-0046 64 TQFP-EP C64E+10 21-0084 90-0329 56 QFND-EP G5688Y+1 21-0704 90-0423 Maxim Integrated MAX9259/MAX9260 Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel Revision History REVISION NUMBER REVISION DATE 0 9/09 Initial release 1 7/10 Added clarification of fault thresholds and updated Pin Description table 2 11/10 Added TQFN package to Ordering Information, Absolute Maximum Ratings, Pin Configurations, Pin Description, and Package Information 3 1/11 Added Patent Pending to Features 4 10/14 Updated General Description and Features sections and Figure 6, clarified function, added QFND package, removed Tables 1 and 2, and renumbered subsequent tables DESCRIPTION PAGES CHANGED -- 3, 4, 8, 11, 12, 13, 15, 16, 17, 25, 28, 33, 39, 44, 48 1, 2, 10, 11, 50 1 1, 2, 4, 6, 10-12, 18, 24, 26-30, 32-34, 36 37, 40, 41, 43-50 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2014 Maxim Integrated 51 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.