DS007902-0708 P R E L I M I N A R Y
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
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document has been verified according to the general principles of electrical and mechanical engineering.
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Warning:
DS007902-0708 P R E L I M I N A R Y Revision History
Z16C30
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
Date Revision Level Description Page No
July 2008 02 Updated as per latest template and
style guide.
All
Jan 2000 01 Original issue
DS007902-0708 P R E L I M I N A R Y Table of Contents
Z16C30
Product Specification
iv
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
USC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Communications Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Character Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Baud Rate Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Digital Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
I/O Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Block Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DS007902-0708 P R E L I M I N A R Y Architectural Overview
Z16C30
Product Specification
1
Architectural Overview
Features
The key features of Zilog’s Z16C30 device include:
•
Two Independent 0-to-10 Mbps Full-Duplex Channels, each with Two Baud Rate Gener-
ators and One digital phase-locked loop (DPLL) for Clock Recovery
•
32-byte Data FIFO’s for each Receiver and Transmitter
•
110 ns Bus Cycle Time, 16-bit Data Bus Bandwidth
•
Multi-Protocol Operation under Program Control with Independent Mode Selection for
Receiver and Transmitter
•
Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character in 1/16-bit Incre-
ments, Programmable Clock Factor, Break Detect and Generation, Odd, Even, Mark,
Space or no Parity and Framing Error Detection, Supports One Address/Data Bit and MIL
STD 1553B Protocols
•
Byte Oriented Synchronous Mode with One to Eight Bits/Character, Programmable Idle
Line Condition, Optional Receive Sync Stripping; Optional Preamble Transmission, 16-
or 32-bit CRC, and Transmit-to-Receive Slaving (for X.21)
•
Bisync Mode with 2- to 16-bit Programmable Sync Character, Programmable Idle Line
Condition, Optional Receive Sync Stripping, Optional Preamble Transmission, 16- or 32-
bit CRC
•
Transparent Bisync Mode with EBCDIC or ASCII Character Code, Automatic CRC Han-
dling, Programmable Idle Line Condition, Optional Preamble Transmission, Automatic
Recognition of DLE, SYN, SOH, ITX, ETX, ETB, EOT, ENQ, and ITB
•
External Character Sync Mode for Receive
•
HDLC/SDLC Mode with Eight-Bit Address Compare, Extended Address Field Option,
16- or 32-bit CRC, Programmable Idle Line Condition, Optional Preamble Transmission
and Loop Mode
•
DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmit-
ter
•
Channel Load Command for DMA Controlled Initialization
•
Flexible Bus Interface for Direct Connection to Most Microprocessors, User Programma-
ble for 8 or 16 Bits Wide, Directly Supports 680X0 Family or 8X86 Family Bus Interfaces
•
Low Power CMOS
•
68-Pin PLCC/100-Pin VQFP Packages
DS007902-0708 P R E L I M I N A R Y Architectural Overview
Z16C30
Product Specification
2
General Description
Zilog’s Z16C30 USC Universal Serial Controller is a dual-channel multi-protocol data
communications peripheral designed for use with any conventional multiplexed or non-
multiplexed bus. The USC functions as a serial-to-parallel, parallel-to-serial converter/
controller and may be software configured to satisfy a wide variety of serial communica-
tions applications. The device contains a variety of new, sophisticated internal functions
including two baud rate generators per channel, one digital phase-locked loop (DPLL) per
channel, character counters for both receive and transmit in each channel and 32-byte data
FIFO’s for each receiver and transmitter (Figure 1 on page 3).
Zilog now offers a high speed version of the USC with improved bus bandwidth. CPU bus
accesses have been shortened from 160 ns per access to 110 ns per access. The USC has a
transmit and receive clock range of up to 10 MHz (20 MHz when using the DPLL, BRG,
or CTR) and data transfer rates as high as 10 Mbits/sec full duplex.
The USC handles asynchronous formats, synchronous byte-oriented formats such as
BISYNC, and synchronous bit-oriented formats such as HDLC. This device supports vir-
tually any serial data transfer application.
The device can generate and check CRC in any synchronous mode and can be pro-
grammed to check data integrity in various modes. The USC also has facilities for modem
controls in both channels. In applications where these controls are not needed, the modem
controls may be used for general-purpose I/O (GPIO). The same is true for most of the
other pins in each channel.
Interrupts are supported with a daisy-chain hierarchy, with the two channels having com-
pletely separate interrupt structures.
High-speed data transfers through DMA are supported by a Request/Acknowledge signal
pair for each receiver and transmitter. The device supports automatic status transfer
through DMA and also allows device initialization under DMA control.
When written to, all reserved bits must be programmed to 0.
To aid in efficiently programming the USC, support tools are available. The Technical
Manual describes in detail all features presented in this Product Specification and gives
programming sequence hints. The Programmer’s Assistant is a MS-DOS disk-based pro-
gramming initialization tool to be used in conjunction with the Technical Manual. There
are also available assorted application notes and development boards to assist in the hard-
ware/software development.
All Signals with an overline, are active Low. For example: B/W, in which WORD is active
Low, and B/W, in which BYTE is active Low.
Power connections follow these conventional descriptions:
Note:
DS007902-0708 P R E L I M I N A R Y Architectural Overview
Z16C30
Product Specification
3
Table 1. Power connection conventions
Connection Circuit Device
Power VCC VDD
Ground GND VSS
Figure 1. Z16C30 Block Diagram
To Other Channel
Receive
Receive
FIFO
Interrupt
Control
Channel
Control
Transmit
FIFO
Transmit
DMA
I/O Data Buffer
CPU
(32 byte)
Control
DMA
(32 byte)
Control
Receive Data
Receiver
Receive/
Transmit
Clocks
Transmitter
Transmit Data
Clock MUX
1. DPLL
2. Counters
3. BRG0
4. BRG1
I/O and
Device
Status
DS007902-0708 P R E L I M I N A R Y Pin Description
Z16C30
Product Specification
4
Pin Description
Figure 2. Z16C30 Pin Functions
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AS
DS
RD
WR
CS
A/B
D/C
R/W
PITACK
SITACK
WAIT/RDY
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TxDA
RxDA
TxCA
RxCA
CTSA
DCDA
RxREQA
RxACKA
TxREQA
TxACKA
INTA
IEIA
IEOA
TxDB
RxDB
Serial
Data
Channel
Clocks
Channel
I/O
Channel
DMA
Interface
Reset
Device
TxCB
RxCB
CTSB
DCDB
RxREQB
RxACKB
TxREQB
TxACKB
INTB
IEIB
IEOB
RESET
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
Channel
Interrupt
Interface
Ground
Interrupt
Control
Bus
Timing
Address/
Data
Bus
Serial
Data
Channel
Clocks
Channel
I/O
Channel
DMA
Interface
Channel
Interrupt
Interface
Power
DS007902-0708 P R E L I M I N A R Y Pin Description
Z16C30
Product Specification
5
Figure 3. Z16C30 68-Pin PLCC Pin Assignments
60
44
10
26
RxACKA
INTA
IEIA
IEOA
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
RXREQA
TXACKA
WAIT/RDY
SITACK
A/B
D/C
CS
RESET
VCC
VCC
VCC
AS
DS
RD
WR
R/W
PITACK
TXACKB
4327
619
68-Pin PLCC
1
RXACKB
INTB
IEIB
IEOB
GND
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND
VCC
RXREQB
TXREQA
RXCA
RXDA
DCDA
TXCA
TXDA
CTSA
GND
GND
GND
CTSB
TXDB
TXCB
DCDB
RXDB
RXCB
TXREQB
DS007902-0708 P R E L I M I N A R Y Pin Description
Z16C30
Product Specification
6
The Z16C30 contains 13 pins per channel for channel I/O, 16 pins for address and data, 12
pins for CPU handshake, and 14 pins for power and ground.
Three separate bus interface types are available for the device. The Bus Configuration
Register (BCR) and external connections to the AD bus control selection of the bus type.
A 16-bit bus is selected by setting BCR bit 2 to a 1. The 8-bit bus is selected by setting
BCR bit 2 to 0 and tying AD15–AD8 to VSS.
Figure 4. 100-Pin VQFP Pin Assignments
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
NC
NC
NC
NC
TXACKB
PITACK
R/W
WR
RD
DS
AS
VCC
VCC
VCC
RESET
CS
D/C
A/B
SITACK
WAIT/RDY
TXACKA
NC
NC
NC
NC
NC
NC
NC
NC
TXREQB
RXCB
RXDB
DCDB
TXCB
TXDB
CTSB
GND
GND
GND
CTSA
TXDA
TXCA
DCDA
RXDA
RXCA
TXREQA
NC
NC
NC
NC
RXACKA
INTA
IEIA
IEOA
GND
VCC
AD0
NC
NC
NC
NC
AD1
AD2
AD3
NC
NC
NC
NC
AD4
AD5
AD6
AD7
GND
VCC
RXREQA
RXACKB
INTB
IEIB
IEOB
GND
VCC
AD8
NC
NC
NC
NC
AD9
AD10
AD11
NC
NC
NC
NC
AD12
AD13
AD14
AD15
GND
VCC
RXREQB
510152025
70 65 60 55 5175
100-Pin VQFP
DS007902-0708 P R E L I M I N A R Y Pin Description
Z16C30
Product Specification
7
The 8-bit bus with separate address is selected by setting BCR bit 2 to 0 and, during the
BCR write, forcing AD15 to a 1 and forcing AD14–AD8 to 0.
The multiplexed bus is selected for the USC if there is an Address Strobe prior to or during
the transaction which writes the BCR. If no Address Strobe is present prior to or during
the transaction which writes the BCR, a nonmultiplexed bus is selected (see Figure 29 on
page 49).
Pin Functions
RESET Reset (input, active Low)—This signal resets the device to a known state. The
first write to the USC after a reset accesses the BCR to select additional bus options for the
device.
AS Address Strobe (input, active Low)—This signal is used in the multiplexed bus
modes to latch the address on the AD lines. The AS signal is not used in the nonmulti-
plexed bus modes and should be tied to VDD.
DS Data Strobe (input, active Low)—This signal strobes data out of the device during a
read and may strobe an interrupt vector out of the device during an interrupt acknowledge
cycle. DS also strobes data into the device on the state of R/W.
RD Read Strobe (input, active Low)—This signal strobes data out of the device during a
read and may strobe an interrupt vector out of the device during an interrupt acknowledge
cycle.
WR Write Strobe (input, active Low)—This signal strobes data into the device during a
write.
R/W Read/Write (input)—This signal determines the direction of data transfer for a read
or write cycle in conjunction with DS.
CS Chip Select (input, active Low)—This signal selects the device for access and must
be asserted for read and write cycles, but is ignored during interrupt acknowledge and fly-
by DMA transfers. In the case of a multiplexed bus interface, CS is latched by the rising
edge of AS.
A/B Channel A/Channel B Select (input)—This signal selects between the two channels
in the device. High selects channel A and Low selects channel B. This signal is sampled
and the result is latched during the BCR (Bus Configuration Register) write. It programs
the sense of the WAIT/RDY signal appropriate for different bus interfaces.
D/C Data/Control Select (input)—This signal, when High, provides for direct access to
the RDR and TDR. In the case of a multiplexed bus interface, D/C High overrides the
address provided to the device.
SITACK Status Interrupt Acknowledge (input, active Low)—This signal is a status sig-
nal that indicates that an interrupt acknowledge cycle is in progress. The device is capable
of returning an interrupt vector that may be encoded with the type of interrupt pending
during this acknowledge cycle. This signal is compatible with 680X0 family microproces-
sors.
DS007902-0708 P R E L I M I N A R Y Pin Description
Z16C30
Product Specification
8
PITACK Pulsed Interrupt Acknowledge (input, active Low)—This signal is a strobe
signal that indicates that an interrupt acknowledge cycle is in progress. The device is capa-
ble of returning an interrupt vector that may be encoded with the type of interrupt pending
during this acknowledge cycle. PITACK may be programmed to accept a single pulse or
double pulse acknowledge type. This programming is done in the BCR. With the double
pulse type selected, the first PITACK is recognized but no action takes place. The interrupt
vector is returned on the second pulse if the no vector option is not selected. The double
pulse type is compatible with 8X86 family microprocessors.
WAIT/RDY Wait/Data Ready (output, active Low)—This signal serves to indicate when
the data is available during a read cycle, when the device is ready to receive data during a
write cycle, and when a valid vector is available during an interrupt acknowledge cycle. It
may be programmed to function either as a Wait signal or a Ready signal using the state of
the A/B pin during the BCR write. When A/B is High during the BCR write, this signal
functions as a wait output and thus supports the READY function of 8X86 family micro-
processors. When A/B is Low during the BCR write, this signal functions as a ready out-
put and thus supports the DTACK function of 680X0 family microprocessors.
AD15–AD0 Address/Data Bus (bidirectional, active High, tri-state)—The AD signals
carry addresses to, and data to and from, the device. When the 16-bit nonmultiplexed bus
is selected, AD15–AD0 carry data to and from the device. Addresses are provided using a
pointer within the device that is loaded with the desired register address. When selecting
the 8-bit nonmultiplexed bus (without separate address) only AD7–AD0 are used to trans-
fer data. The pointer is used for addressing, with AD15–AD8 unused. When selecting the
8-bit nonmultiplexed bus (with separate address), AD7–AD0 are used to transfer data with
AD15–AD8 used as address bus. When the 16-bit multiplexed bus is selected, addresses
are latched from AD7–AD0 and data transfers are sixteen bits wide. When selecting the 8-
bit multiplexed bus (without separate address) only AD7–AD0 are used to transfer
addresses and data, with AD15–AD8 unused. When the 8-bit multiplexed bus with sepa-
rate address is selected, only AD7–AD0 are used to transfer data, while AD15–AD8 are
used as an address bus.
INTA, INTB Interrupt Request (outputs, active Low)—These signals indicate that the
channel has an interrupt condition pending and is requesting service. These outputs are
NOT open-drain.
IEIA, IEIB Interrupt Enable In (inputs, active High)—The IEI signal for each channel is
used with the accompanying IEO signal to form an interrupt daisy chain. An active IEI
indicates that no device having higher priority is requesting or servicing an interrupt.
IEOA, IEOB Interrupt Enable Out (outputs, active High)—The IEO signal for each
channel is used with the accompanying IEI signal to form an interrupt daisy chain. IEO is
Low if IEI is Low, an interrupt is under service in the channel, or an interrupt is pending
during an interrupt acknowledge cycle.
TxACKA, TxACKB Transmit Acknowledge (inputs or outputs, active Low)—The pri-
mary function of these signals is to perform fly-by DMA transfers to the transmit FIFOs.
They may also be used as bit inputs or outputs.
DS007902-0708 P R E L I M I N A R Y Pin Description
Z16C30
Product Specification
9
RxACKA, RxACKB Receive Acknowledge (inputs or outputs, active Low)—The pri-
mary function of these signals is to perform fly-by DMA transfers from the receive FIFOs.
They may also be used as bit inputs or outputs.
TxDA, TxDB Transmit Data (outputs, active High, tri-state)—These signals carry the
serial transmit data for each channel.
RxDA, RxDB Receive Data (inputs, active High)—These signals carry the serial receive
data for each channel.
TxCA, TxCB Transmit Clock (inputs or outputs, active Low)—These signals are used
as clock inputs for any of the functional blocks within the device. They may also be used
as outputs for various transmitter signals or internal clock signals.
RxCA, RxCB Receive Clock (inputs or outputs, active Low)—These signals are used
as clock inputs for any of the functional blocks within the device. They may also be used
as outputs for various receiver signals or internal clock signals.
TxREQA, TxREQB Transmit Request (inputs or outputs, active Low)—The primary
function of these signals is to request DMA transfers to the transmit FIFOs. They may also
be used as simple inputs or outputs.
RxREQA, RxREQB Receive Request (inputs or outputs, active Low)—The primary
function of these signals is to request DMA transfers from the receive FIFOs. They may
also be used as simple inputs or outputs.
CTSA, CTSB Clear To Send (inputs or outputs, active Low)—These signals are used
as enables for the respective transmitters. They may also be programmed to generate inter-
rupts on either transition or used as simple inputs or outputs.
DCDA, DCDB Data Carrier Detect (inputs or outputs, active Low)—These signals are
used as enables for the respective receivers. They may also be programmed to generate
interrupts on either transition or used as simple inputs or outputs.
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
10
Electrical Characteristics
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; operation of the device at any condition
above those indicated in the operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Standard Test Conditions
The DC Characteristics and Capacitance section below apply for the following standard
test conditions, unless otherwise noted. All voltages are referenced to GND. Positive cur-
rent flows into the referenced pin (Figure 5 on page 11). Standard conditions are as fol-
lows:
•
+4.5 V < VCC < +5.5 V
•
GND = 0 V
•
TA as specified in Ordering Information on page 97
Table 2. Absolute Maximum Ratings
Symbol Description Min Max Units
VCC Supply Voltage (*) –0.3 +7.0 V
TSTG Storage Temp. –65° +150° C
TAOper Ambient
Tem p
†C
Power Dissipation 2.2 W
*Voltage on all pins with respect to GND.
†See Ordering Information on page 97.
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
11
Capacitance
Miscellaneous
Transistor Count: 174,000
Temperature Ratings
Standard = 0 °C to ±70 °C
Extended = –40 °C to +85 °C
Figure 5. Test Load Diagram
Table 3. Capacitance
Symbol Parameter Min Max Unit Condition
CIN Input Capacitance 10 pF Unmeasured Pins
COUT Output Capacitance 15 pF Returned to Ground.
CI/O Bidirectional Capacitance 20 pF
Note: f = 1 MHz over specified temperature range.
From Pin
50 pF
CL
IOL
IOH
VOL max +VOH min
2
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
12
DC Characteristics
AC Characteristics
Table 4. Z16C30 DC Characteristics
Symbol Parameter Min Typ Max Unit Condition
VIH Input High Voltage 2.2 VCC+0.3 V
VIL Input Low Voltage –0.3 0.8 V
VOH1 Output High
Voltage
2.4 V IOH = –1.6 mA
VOH2 Output High
Voltage
VCC–0.8 V IOH = –250 µA
VOL Output Low
Voltage
0.4 V IOL = +2.0 mA
IIL Input Leakage ±10.00 µA 0.4 < VIN < +2.4 V
IOL Output Leakage ±10.00 µA 0.4 < VOUT < +2.4 V
ICCl VCC Supply
Current
750mAV
CC = 5 V VIH = 4.8 V VIL =
0.2V
Note: VCC= 5 V ±10% unless otherwise specified, over specified temperature range.
Table 5. Z16C30 AC Characteristics
No Symbol Parameter Min Max Units Note
1 Tcyc Bus Cycle Time 110 ns
2 TwASl AS Low Width 30 ns
3 TwASh AS High Width 60 ns
4 TwDSl DS Low Width 60 ns
5 TwDSh DS High Width 50 ns
6 TdAS(DS) AS Rise to DS Fall Delay
Time
5ns
7 TdDS(AS) DS Rise to AS Fall Delay
Time
5ns
8 TdDS(DRa) DS Fall to Data Active Delay 0 ns
9 TdDS(DRv) DS Fall to Data Valid Delay 60 ns
10 TdDS(DRn) DS Rise to Data Not Valid
Delay
0ns
11 TdDS(DRz) DS Rise to Data Float Delay 20 ns
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
13
12 TsCS(AS) CS to AS Rise Setup Time 15 ns
13 ThCS(AS) CS to AS Rise Hold Time 5 ns
14 TsADD(AS) Direct Address to AS Rise
Setup Time
15 ns 1
15 ThADD(AS) Direct Address to AS Rise
Hold Time
5ns1
16 TsSIA(AS) SITACK to AS Rise Setup
Time
15 ns
17 ThSIA(AS) SITACK to AS Rise Hold
Time
5ns
18 TsAD(AS) Address to AS Rise Setup
Time
15 ns
19 ThAD(AS) Address to AS Rise Hold
Time
5ns
20 TsRW(DS) R/W to DS Fall Setup Time 0 ns
21 ThRW(DS) R/W to DS Fall Hold Time 25 ns
22 TsDSf(RRQ) DS Fall to RxREQ Inactive
Delay
60 ns 4
23 TdDSr(RRQ) DS Rise to RxREQ Active
Delay
0ns
24 TsDW(DS) Write Data to DS Rise Setup
Time
30 ns
25 ThDW(DS) Write Data to DS Rise Hold
Time
0ns
26 TdDSf(TRQ) DS Fall to TxREQ Inactive
Delay
65 ns 5,6
27 TdDSr(TRQ) DS Rise to TxREQ Active
Delay
0ns
28 TwRDl RD Low Width 60 ns
29 TwRDh RD High Width 50 ns
30 TdAS(RD) AS Rise to RD Fall Delay
Time
5ns
31 TdRD(AS) RD Rise to AS Fall Delay
Time
5ns
32 TdRD(DRa) RD Fall to Data Active Delay 0 ns
33 TdRD(DRv) RD Fall to Data Valid Delay 60 ns
34 TdRD(DRn) RD Rise to Data Not Valid
Delay
0ns
Table 5. Z16C30 AC Characteristics (Continued)
No Symbol Parameter Min Max Units Note
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
14
35 TdRD(DRz) RD Rise to Data Float Delay 20 ns
36 TdRDf(RRQ) RD Fall to RxREQ Inactive
Delay
60 ns 4
37 TdRDr(RRQ) RD Rise to RxREQ Active
Delay
0ns
38 TwWRl WR Low Width 60 ns
39 TwWRh WR High Width 50 ns
40 TdAS(WR) AS Rise to WR Fall Delay
Time
5ns
41 TdWR(AS) WR Rise to AS Fall Delay
Time
5ns
42 TsDW(WR) Write Data to WR Rise Setup
Time
30 ns
43 ThDW(WR) Write Data to WR Rise Hold
Time
0ns
44 TdWRf(TRQ) WR Fall to TxREQ Inactive
Delay
65 ns 5
45 TdWRr(TRQ) WR Rise to TxREQ Active
Delay
0ns
46 TsCS(DS) CS to DS Fall Setup Time 0 ns 2
47 ThCS(DS) CS to DS Fall Hold Time 25 ns 2
48 TsADD(DS) Direct Address to DS Fall
Setup Time
5ns1,2
49 ThADD(DS) Direct Address to DS Fall
Hold Time
25 ns 1,2
50 TsSIA(DS) SITACK to DS Fall Setup
Time
5ns2
51 ThSIA(DS) SITACK to DS Fall Hold Time 25 ns 2
52 TsCS(RD) CS to RD Fall Setup Time 0 ns 2
53 ThCS(RD) CS to RD Fall Hold Time 25 ns 2
54 TsADD(RD) Direct Address to RD Fall
Setup Time
5ns1,2
55 ThADD(RD) Direct Address to RD Fall
Hold Time
25 ns 1,2
56 TsSIA(RD) SITACK to RD Fall Setup
Time
5ns2
57 ThSIA(RD) SITACK to RD Fall Hold Time 25 ns 2
58 TsCS(WR) CS to WR Fall Setup Time 0 ns 2
Table 5. Z16C30 AC Characteristics (Continued)
No Symbol Parameter Min Max Units Note
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
15
59 ThCS(WR) CS to WR Fall Hold Time 25 ns 2
60 TsADD(WR) Direct Address to WR Fall
Setup Time
5ns1,2
61 ThADD(WR) Direct Address to WR Fall
Hold Time
25 ns 1,2
62 TsSIA(WR) SITACK to WR Fall Setup
Time
5ns2
63 ThSIA(WR) SITACK to WR Fall Hold
Time
25 ns 2
64 TwRAKl RxACK Low Width 60 ns
65 TwRAKh RxACK High Width 50 ns
66 TdRAK(DRa) RxACK Fall to Data Active
Delay
0ns
67 TdRAK(DRv) RxACK Fall to Data Valid
Delay
60 ns
68 TdRAK(DRn) RxACK Rise to Data Not
Valid Delay
0ns
69 TdRAK(DRz) RxACK Rise to Data Float
Delay
20 ns
70 TdRAKf(RRQ) RxACK Fall to RxREQ
Inactive Delay
60 ns 4
71 TdRAKr(RRQ) RxACK Rise to RxREQ
Active Delay
0ns
72 TwTAKl TxACK Low Width 60 ns
73 TwTAKh TxACK High Width 50 ns
74 TsDW(TAK) Write Data to TxACK Rise
Setup Time
30 ns
75 ThDW(TAK) Write Data to TxACK Rise
Hold Time
0ns
76 TdTAKf(TRQ) TxACK Fall to TxREQ
Inactive Delay
65 ns 5
77 TdTAKr(TRQ) TxACK Rise to TxREQ Active
Delay
0ns
78 TdDSf(RDY) DS Fall (INTACK) to RDY Fall
Delay
200 ns
79 TdRDY(DRv) RDY Fall to Data Valid Delay 40 ns
80 TdDSr(RDY) DS Rise to RDY Rise Delay 40 ns
Table 5. Z16C30 AC Characteristics (Continued)
No Symbol Parameter Min Max Units Note
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
16
81 TsIEI(DSI) IEI to DS Fall (INTACK)
Setup Time
10 ns
82 ThIEI(DSI) IEI to DS Rise (INTACK) Hold
Time
0ns
83 TdIEI(IEO) IEI to IEO Delay 30 ns
84 TdAS(IEO) AS Rise (Intack) to IEO Delay 60 ns
85 TdDSI(INT) DS Fall (INTACK) to INT
Inactive Delay
200 ns 7
87 TdDSI(Wr) DS Fall (INTACK) to WAIT
Rise Delay
200 ns
88 TdW(DRv) WAIT Rise to Data Valid
Delay
40 ns
89 TdRDf(RDY) RD Fall (INTACK) to RDY
Fall Delay
200 ns
90 TdRDr(RDY) RD Rise to RDY Rise Delay 40 ns
91 TsIEI(RDI) IEI to RD Fall (INTACK)
Setup Time
10 ns
92 ThIEI(RDI) IEI to RD Rise (INTACK) Hold
Time
0ns
93 TdRDI(INT) RD Fall (INTACK) to INT
Inactive Delay
200 ns
94 TdRDI(Wf) RD Fall (INTACK) to WAIT
Fall Delay
40 ns
95 TdRDI(Wr) RD Fall (INTACK) to WAIT
Rise Delay
200 ns
96 TwPIAl PITACK Low Width 60 ns
97 TwPIAh PITACK High Width 50 ns
98 TdAS(PIA) AS Rise to PITACK Fall
Delay Time
5ns
99 TdPIA(AS) PITACK Rise to AS Fall
Delay Time
5ns
100 TdPIA(DRa) PITACK Fall to Data Active
Delay
0ns
101 TdPIA(DRn) PITACK Rise to Data Not
Valid Delay
0ns
102 TdPIA(DRz) PITACK Rise to Data Float
Delay
20 ns
Table 5. Z16C30 AC Characteristics (Continued)
No Symbol Parameter Min Max Units Note
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
17
103 TsIEI(PIA) IEI to PITACK Fall Setup
Time
10 ns
104 ThIEI(PIA) IEI to PITACK Rise Hold
Time
0ns
105 TdPIA(IEO) PITACK Fall to IEO Delay 60 ns
106 TdPIA(INT) PITACK Fall to INT Inactive
Delay
200 ns
107 TdPIAf(RDY) PITACK Fall to RDY Fall
Delay
200 ns
108 TdPIAr(RDY) PITACK Rise to RDY Rise
Delay
40 ns
109 TdPIA(Wf) PITACK Fall to WAIT Fall
Delay
40 ns
110 TdPIA(Wr) PITACK Fall to WAIT Rise
Delay
200 ns
111 TdSIA(INT) SITACK Fall to IEO Inactive
Delay
200 ns 2
112 TwSTBh Strobe High Width 50 ns 3
113 TwRESl RESET Low Width 170 ns
114 TwRESh RESET High Width 60 ns
115 Tdres(STB) RESET Rise to STB Fall 60 ns 3
116 TdDSf(RDY) DS Fall to RDY Fall Delay 50 ns
117 TdWRf(RDY) WR Fall to RDY Fall Delay 50 ns
118 TdWRr(RDY) WR Rise to RDY Rise Delay 40 ns
119 TdRDf(RDY) RD Fall to RDY Fall Delay 50 ns
120 TdRAKf(RDY) RxACK Fall to RDY Fall
Delay
50 ns
121 TdRAKr(RDY) RxACK Rise to RDY Rise
Delay
40 ns
122 TdTAKf(RDY) TxACK Fall to RDY Fall
Delay
50 ns
Table 5. Z16C30 AC Characteristics (Continued)
No Symbol Parameter Min Max Units Note
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
18
USC Timing
The USC interface timing is similar to that found on a static RAM, except that it is much
more flexible. Up to eight separate timing strobe signals may be present on the interface:
DS, RD, WR, PITACK, RxACKA, RxACKB, TxACKA, and TxACKB. Only one of
these timing strobes may be active at any time. Should the external logic activate more
than one of these strobes at the same time the USC will enter a pre-reset state that is only
exited by a hardware reset. Do not allow overlap of timing strobes. The timing diagrams
beginning on the next page illustrate the different bus transactions possible with the neces-
sary setup hold and delay times.
123 TdTAKr(RDY) TxACK Rise to RDY Rise
Delay
40 ns
Notes
1. Direct address is any of A/B, D/C, or AD15–AD8 used as an address bus.
2. The parameter applies only when AS is not present.
3. Strobe (STB) is any of DS, RD, WR, PITACK, RxACK or TxACK.
4. Parameter applies only if read empties the receive FIFO.
5. Parameter applies only if write fills the transmit FIFO.
6. For extended temperature part TdDSI(Wf) max = 220 ns.
7. For extended temperature part TdDSF(TRQ) max = 75 ns.
Figure 6. Reset Timing
Table 5. Z16C30 AC Characteristics (Continued)
No Symbol Parameter Min Max Units Note
RESET
STB
Note: STB is any of DS, RD, WR, PITACK, RxACK, or TxACK
113
114
115
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
19
Figure 7. Bus Cycle Timing
Figure 8. DMA Read Cycle
STB
112
1
1
64 65
66
67
68
69
70 71
120
79
121
RxACK
AD15–AD0
RxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
Note: STB is any of DS, RD, WR, PITACK, RxACK, or TxACK
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
20
Figure 9. DMA Write Cycle
72 73
74 75
76 77
122 123
TxACK
AD15–AD0
TxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
21
Figure 10. Multiplexed DS Read Cycle
12 13
14 15
16 17
2
6
1
3
7
20 21
45
18 19 8
9
10
11
22 23
116
79 80
CS
A/B, D/C
ACK
AS
R/W
DS
AD15–AD0
RxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
22
Figure 11. Multiplexed DS Write Cycle
CS
A/B, D/C
SITACK
AS
R/W
DS
AD15–AD0
TxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
12 13
14 15
16 17
26
1
7
20 21
45
18 19 24 25
26 27
116 80
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
23
Figure 12. Multiplexed RD Read Cycle
CS
A/B, D/C
SITACK
AS
RD
AD15–AD0
RxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
12 13
14 15
16 17
230
1
31
28
18 19
36 37
119 90
CS
29
32
33
34
35
79
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
24
Figure 13. Multiplexed WR Write Cycle
A/B, D/C
SITACK
AS
WR
AD15–AD0
TxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
CS
12 13
14 15
16 17
240
1
41
38 39
18 19 42 43
44 45
117 118
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
25
Figure 14. Nonmultiplexed DS Read Cycle
A/B, D/C
SITACK
AS
WR
AD15–AD0
TxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
CS
12 13
14 15
16 17
240
1
41
38 39
18 19 42 43
44 45
117 118
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
26
Figure 15. Nonmultiplexed DS Write Cycle
A/B, D/C
SITACK
R/W
DS
AD15–AD0
TxREQ
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
CS
46 47
48 49
50 51
20 21
45
1
24 25
26 27
116
80
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
27
Figure 16. Nonmultiplexed RD Read Cycle
A/B, D/C
SITACK
RD
AD15–AD0
RxREQ
WAIT/RDY
(Ready)
WAIT/RDY
(Ready)
CS
WAIT/RDY
(Wait)
52 53
54 55
56 57
28
1
29
32
33
34
35
36 37
119
79 90
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
28
Figure 17. Nonmultiplexed WR Write Cycle
A/B, D/C
SITACK
WR
AD15–AD0
TxREQ
WAIT/RDY
(Ready)
CS
WAIT/RDY
(Wait)
58 59
60
62 63
61
38
1
39
42 43
44
117 118
45
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
29
Figure 18. Multiplexed DS Interrupt Acknowledged Cycle
SITACK
DS
AD15–AD0
WAIT/RDY
(Ready)
AS
WAIT/RDY
(Wait)
IEI
IEO
INT
267
17
16
45
18
19
8
86
10
11
87 88
79
78 80
81 82
83 84
85
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
30
Figure 19. Multiplexed RD Interrupt Acknowledge Cycle
SITACK
RD
AD15–AD0
WAIT/RDY
(Ready)
AS
WAIT/RDY
(Wait)
IEI
IEO
INT
230 31
16
17
28 29
18
19
32
94
34
35
88
79
95
89 90
91 92
83 84
93
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
31
Figure 20. Multiplexed Pulsed Interrupt Acknowledge Cycle
AS
PITACK
AD15–AD0
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
IEI
IEO
INT
298
1
99
96 97
18
19
100
109
101
102
110
88
79
107 108
103 104
83
105
106
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
32
Figure 21. Nonmultiplexed DS Interrupt Acknowledge Cycle
DS
SITACK
AD15–AD0
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
IEI
IEO
INT
50 51
4 5
1
810
11
86
87 88
79
78 80
81 82
83
111
85
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
33
Figure 22. Nonmultiplexed RD Interrupt Acknowledge Cycle
RD
SITACK
AD15–AD0
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
IEI
IEO
INT
50 51
4 5
1
810
11
86
87 88
79
78 80
81 82
83
111
85
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
34
Figure 23. Nonmultiplexed Pulsed Interrupt Acknowledge Cycle
SITACK
AD15–AD0
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
IEI
IEO
INT
PITACK
96 97
1
79
107
100 101
102
108
103 104
83
106
105
109
88
110
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
35
Figure 24. Multiplexed Double-Pulse Intack Cycle
AD15–AD0
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
IEI
IEO
INT
PITACK
(2-Pulse)
AS
298 99
2
98
99
1 1
96 97 96 97
18
19
18
19
100 101
102
107
79
108
83
109
110
88
104
103
105
106
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
36
Figure 25. Nonmultiplexed Double-Pulse Intack Cycle
AD15–AD0
WAIT/RDY
(Wait)
WAIT/RDY
(Ready)
IEI
IEO
INT
PITACK
(2-Pulse)
96
1
97 96 97
1
100 101
102
107
79
108
109
110
88
103 104
83
105
106
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
37
AC Characteristics
Table 6 lists Z16C30 General Timing.
Table 6. Z16C30 General Timing
No Symbol Parameter Min Max Units Notes
1 TsRxD(RxCr) RxD to RxC Rise Setup Time (x1 Mode) 0 ns 1
2 ThRxD(RxCr) RxD to RxC Rise Hold Time (x1 Mode) 40 ns 1
3 TsRxd(RxCf) RxD to RxC Fall Setup Time (x1 Mode) 0 ns 1,3
4 ThRxD(RxCf) RxD to RxC Fall Hold Time (x1 Mode) 40 ns 1,3
5 TsSy(RxC) DCD as SYNC to RxC Rise Setup Time 0 ns 1
6 ThSy(RxC) DCD as SYNC to RxC Rise Hold Time (x1
Mode)
40 ns 1
7TdTxCf(TxD)TxC
Fall to TxD Delay 50 ns 2
8 TdTxCr(TxD) TxC Rise to TxD Delay 50 ns 2,3
9 TwRxCh RxC High Width 40 ns 1
11 TcRxC RxC Cycle Time 100 ns 1
12 TwTxCh TxC High Width 40 ns 2
13 TwTxCl TxC Low Width 40 ns 2
14 TcTxC TxC Cycle Time 100 ns 2
15 TwExT DCD or CTS Pulse Width 70 ns
16 TWSY DCD as SYNC Input Pulse Width 70 ns
17 TwCLKh CLK High Width 20 ns 4
18 TwCLKI CLK High Width 20 ns 4
19 TcCLK CLK Cycle Time 50 ns 4
Notes
1. RxC is RxC or TxC, whichever is supplying the receive clock.
2. TxC is TxC or RxC, whichever is supplying the transmit clock.
3. Parameter applies only to FM encoding/decoding.
4. CLK is RxC or TxC, when supplying DPLL, BRG, or CTR clock.
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
38
Table 7 lists Z16C30 System Timing
Figure 26. Z16C30 System Timing
1
2
3
4
5
6
7
RxC, TxC
Receive
RxEQ
Request
INT
RxC as
Receiver
Output
RxC, TxC
Transmit
TxREQ
TxC as
Transmitter
Output
CTS, DCD,
TxREQ,
RxREQ
Note: CLK is RxC or TxC when supplying DPLL, BRG, or CTR clock.
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
39
Architecture
The USC internal structure includes two completely independent full-duplex serial chan-
nels, each with two baud rate generators, a digital phase-locked loop for clock recovery,
transmit and receive character counters and a full-duplex DMA interface. The two serial
channels share a common bus interface. The bus interface is designed to provide easy
interface to most microprocessors, whether they employ a multiplexed or nonmultiplexed,
8-bit or16-bit bus structure. Each channel is controlled by a set of thirty 16-bit registers,
nearly all of which are readable and writable. There is one additional 16-bit register in the
bus interface used to configure the nature of the bus interface. The BCR functions are
shown as follows:
Table 7. Z16C30 System Timing
No Symbol Parameter Min Max Units Notes
1 TdRxC(REQ) RxC Rise to RxREQ Valid Delay 100 ns 1
2 TdRxC(RxC) TxC Rise to RxC as Receiver Output Valid Delay 100 ns 1
3 TdRxC(INT) RxC Rise to INT Valid Delay 100 ns 1
4 TdTxC(REQ) TxC Fall to TxREQ Valid Delay 100 ns 2
5 TdTxC(TxC) RxC Fall to TxC as Transmitter Output Valid
Delay
100 ns 2
6 TdTxC(INT) TxC Fall to INT Valid Delay 100 ns 2
7 TdEXT(INT) CTS, DCD, TxREQ, RxREQ transition to INT
Valid Delay
100 ns
Notes
1. RxC is RxC or TxC, whichever is supplying the receive clock.
2. TxC is TxC or RxC, whichever is supplying the transmit clock.
DS007902-0708 P R E L I M I N A R Y Electrical Characteristics
Z16C30
Product Specification
40
Figure 27. Bus Configuration Register
Data Path
Both the transmitter and the receiver in the channel are actually microcoded serial proces-
sors. As the data shifts through the transmit or receive shift register, the microcode
watches for specific bit patterns, counts bits, and at the appropriate time transfers data to
or from the FIFOs. The microcode also checks status and generates status interrupts as
appropriate.
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: None
Shift Right Addresses
Double-Pulse INTACK
16-Bit Bus
0*
Reserved
3-State All Pins
Separate Address for 8-Bit Bus
* Must be programmed as 0.
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
41
Functional Description
The functional capabilities of the USC are described from two different points of view: as
a data communications device, it transmits and receives data in a wide variety of data
communications protocols; as a microprocessor peripheral, the USC offers such features
as read/write registers, a flexible bus interface, DMA interface support, and vectored inter-
rupts.
Data Communications Capabilities
The USC provides two independent full-duplex channels programmable for use in any
common data communication protocol. The receiver and transmitter modes are com-
pletely independent, as are the two channels. Each receiver and transmitter is supported by
a 32-byte deep FIFO and a 16-bit message length counter. All modes allow optional even,
odd, mark or space parity. Synchronous modes allow the choice of two 16-bit or one 32-bit
CRC polynomial. Selection of from one to eight bits-per-character is available in both
receiver and transmitter, independently. Error and status conditions are carried with the
data in the receive and transmit FIFOs to greatly reduce the CPU overhead required to
send or receive a message. Specific, appropriately timed interrupts are available to signal
such conditions as overrun, parity error, framing error, end-of-frame, idle line received,
sync acquired, transmit underrun, CRC sent, closing sync/flag sent, abort sent, idle line
sent, and preamble sent. In addition, several useful internal signals such as receive FIFO
load, received sync, transmit FIFO read and transmission complete may be sent to pins for
use by external circuitry.
Asynchronous Mode—The receiver and transmitter can handle data at a rate of 1/16, 1/
32, or 1/64 the clock rate. The receiver rejects start bits less than one-half a bit time and
will not erroneously assemble characters following a framing error. The transmitter is
capable of sending one, two, or anywhere in the range of 1/16 to two stop bits per charac-
ter in 1/16 bit increments.
External Sync Mode—The receiver is synchronized to the receive data stream by an
externally-supplied signal on a pin for custom protocol applications.
Isochronous Mode—Both transmitter and receiver may operate on start-stop (async) data
using a 1x clock. The transmitter can send one or two stop bits.
Asynchronous With Code Violations—This is similar to Isochronous mode except that
the start bit is replaced by a three bit-time code violation pattern as in MIL-STD 1553B.
The transmitter can send zero, one or two stop bits.
Monosync Mode—In this mode, a single character is used for synchronization. The sync
character can be either eight bits long with an arbitrary data character length, or pro-
grammed to match the data character length. The receiver is capable of automatically
stripping sync characters from the received data stream. The transmitter may be pro-
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
42
grammed to automatically send CRC on either an underrun or at the end of a programmed
message length.
Bisync Mode—This mode is identical to monosync mode except that character synchroni-
zation requires two successive characters for synchronization. The two characters need not
be identical.
HDLC Mode—In this mode, the receiver recognizes flags, performs optional address
matching, accommodates extended address fields, 8- or 16-bit control fields and logical
control fields, performs zero deletion and CRC checking. The receiver is capable of
receiving shared-zero flags, recognizes the abort sequence and can receive arbitrary length
messages. The transmitter automatically sends opening and closing flags, performs zero
insertion and can be programmed to send an abort, an extended abort, a flag or CRC, and a
flag on transmit underrun. The transmitter can also automatically send the closing flag
with optional CRC at the end of a programmed message length. Shared-zero flags are
selected in the transmitter and a separate character length may be programmed for the last
character in the frame.
Bisync Transparent Mode—In this mode, the synchronization pattern is DLE–SYN, pro-
grammable selected from either ASCII or EBCDIC encoding. The receiver recognizes
control character sequences and automatically handles CRC calculation without CPU
intervention. The transmitter can be programmed to send either SYN, DLE–SYN, CRC–
SYN, or CRC–DLE–SYN upon underrun and can automatically send the closing DLE–
SYN with optional CRC at the end of a programmed message length.
NBIP Mode—This mode is identical to async except that the receiver checks for the status
of an additional address/data bit between the parity bit and the stop bit. The value of this
bit is FIFO’ed along with the data. This bit is automatically inserted in the transmitter with
the value that is FIFO’ed with the transmit data.
802.3 Mode—This mode implements the data format of IEEE 802.3 with 16-bit address
compare. In this mode, DCD and CTS are used to implement the carrier sense and colli-
sion detect interactions with the receiver and transmitter.
Slaved Monosync Mode—This mode is available only in the transmitter and allows the
transmitter (operating as though it were in monosync mode) to send data that is byte-syn-
chronous to the data being received by the receiver.
HDLC Loop Mode—This mode is also available only in the transmitter and allows the
USC to be used in an HDLC loop configuration. In this mode, the receiver is programmed
to operate in HDLC mode so that the transmitter echoes received messages. Upon receipt
of a particular bit pattern (actually a sequence of seven consecutive ones) the transmitter
breaks the loop and inserts its own frame(s).
Data Encoding
The USC may be programmed to encode and decode the serial data in any of eight differ-
ent ways as displayed in Figure 28 on page 44. The transmitter encoding method is
selected independently of the receiver decoding method.
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
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43
NRZ—In NRZ, a 1 is represented by a High level for the duration of the bit cell and a 0 is
represented by a Low level for the duration of the bit cell.
NRZB—Data is inverted from NRZ.
NRZI-Mark—In NRZI-Mark, a 1 is represented by a transition at the beginning of the bit
cell. That is, the level present in the preceding bit cell is reversed. A 0 is represented by the
absence of a transition at the beginning of the bit cell.
NRZI-Space—In NRZI-Space, a 1 is represented by the absence of a transition at the
beginning of the bit cell. That is, the level present in the preceding bit cell is maintained. A
0 is represented by a transition at the beginning of the bit cell.
Biphase-Mark—In Biphase-Mark, a 1 is represented by a transition at the beginning of the
bit cell and another transition at the center of the bit cell. A 0 is represented by a transition
at the beginning of the bit cell only.
Biphase-Space—In Biphase-Space, a 1 is represented by a transition at the beginning of
the bit cell only. A 0 is represented by a transition at the beginning of the bit cell and
another transition at the center of the bit cell.
Biphase-Level—In Biphase-Level, a 1 is represented by a High during the first half of the
bit cell and a Low during the second half of the bit cell. A 0 is represented by a Low dur-
ing the first half of the bit cell and a High during the second half of the bit cell.
DS007902-0708 P R E L I M I N A R Y Functional Description
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44
Differential Biphase-Level—In Differential Biphase-Level, a 1 is represented by a transi-
tion at the center of the bit cell, with the opposite polarity from the transition at the center
of the preceding bit cell. A 0 is represented by a transition at the center of the bit cell with
the same polarity as the transition at the center of the preceding bit cell. In both cases there
may be transitions at the beginning of the bit cell to set up the level required to make the
correct center transition.
Character Counters
Each channel in the USC contains a 16-bit character counter for both receiver and trans-
mitter. The receive character counter may be preset either under software control or auto-
matically at the beginning of a receive message. The counter decrements with each receive
character and at the end of the receive message the current value in the counter is automat-
Figure 28. Data Encoding
Data110010
NRZ
NRZB
NRZI-M
NRZI-S
BI-PHASE-M
BIPHASE-S
BIPHASE-L
DIFFERENTIAL
BIPHASE-L
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Z16C30
Product Specification
45
ically loaded into a four-deep FIFO. This allows DMA transfer of data to proceed without
CPU intervention at the end of a received message, as the values in the FIFO allow the
CPU to determine message boundaries in memory. Similarly, the transmit character
counter is loaded either under software control or automatically at the beginning of a
transmit message. The counter is decremented with each write to the transmit FIFO. When
the counter has decremented to 0, and that byte is sent, the transmitter automatically termi-
nates the message in the appropriate fashion (usually CRC and the closing flag or sync
character) without requiring CPU intervention.
Baud Rate Generators
Each channel in the USC contains two baud rate generators. Each generator consists of a
16-bit time constant register and a 16-bit down counter. In operation, the counter decre-
ments with each baud rate generator clock, with the time constant automatically reloaded
when the count reaches zero. The output of the baud rate generator toggles when the
counter reaches a count of one-half of the time constant and again when the counter
reaches zero.A new time constant may be written at any time but the new value will not
take effect until the next load of the counter. The outputs of both baud rate generators are
sent to the clock multiplexer for use internally or externally. The baud rate generator out-
put frequency is related to the baud rate generator input clock frequency by the following
equation:
Output frequency = Input frequency/(time constant + 1)
This allows an output frequency in the range of 1 to 1/65536 of the input frequency, inclu-
sive.
Digital Phase-Locked Loop
Each channel in the USC contains a Digital Phase-Locked Loop (DPLL) to recover clock
information from a data stream with NRZI or Biphase encoding. The DPLL is driven by a
clock that is nominally 8, 16 or 32 times the receive data rate. The DPLL uses this clock,
along the data stream, to construct a clock for the data. This clock may then be routed to
the receiver, transmitter, or both, or to a pin for use externally. In all modes, the DPLL
counts the input clock to create nominal bit times. As the clock is counted, the DPLL
watches the incoming data stream for transitions. Whenever a transition is detected, the
DPLL makes a count adjustment (during the next counting cycle), to produce an output
clock which tracks the incoming bit cells. The DPLL provides properly phased transmit
and receive clocks to the clock multiplexer.
Counters
Each channel contains two 5-bit counters, which are programmed to divide an input clock
by 4, 8, 16, or 32. The inputs of these two counters are sent to the clock multiplexer. The
counters are used as prescalers for the baud rate generators, or to provide a stable transmit
clock from a common source when the DPLL is providing the receive clock.
DS007902-0708 P R E L I M I N A R Y Functional Description
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Product Specification
46
Clock Multiplexer
The clock multiplexer in each channel selects the clock source for the various blocks in the
channel and selects an internal clock signal to potentially be sent to either the RxC or TxC
pin.
Test Modes
The USC can be programmed for local loopback or auto echo operation. In local loopback,
the output of the transmitter is internally routed to the input of the receiver. This allows
testing of the USC data paths without any external logic. Auto echo connects the RxD pin
directly to the TxD pin. This is useful for testing serial links external to the USC.
I/O Interface Capabilities
The USC offers the choice of polling, interrupt (vectored or nonvectored) and block trans-
fer modes to transfer data, status and control information to and from the CPU.
Polling
All interrupts are disabled. The registers in the USC are automatically updated to reflect
current status. The CPU polls the Daisy Chain Control Register (DCCR) to determine sta-
tus changes and then reads the appropriate status register to find and respond to the change
in status. USC status bits are grouped according to function to simplify this software
action.
Interrupt
When a USC responds to an interrupt acknowledge from the CPU, an interrupt vector may
be placed on the data bus. This vector is held in the Interrupt Vector Register (IVR). To
speed interrupt response time, the USC modifies three bits in this vector to indicate which
type of interrupt is being requested.
Each of the six sources of interrupts in each channel of the USC (Receive Status, Receive
Data, Transmit Status, Transmit Data, I/O Status, and Device Status) has three bits associ-
ated with the interrupt source: Interrupt Pending (IP), Interrupt-Under-Service (IUS), and
Interrupt Enable (IE). If the IE bit for a given source is set, that source can request inter-
rupts. Note that individual sources within the six groups also have interrupt enable bits
which are set for the particular source. In addition, there is a Master Interrupt Enable
(MIE) bit in each channel which globally enables or disables interrupts within the channel.
The other two bits are related to the interrupt priority chain. A channel in the USC may
request an interrupt only when no higher priority interrupt source is requesting one, e.g.,
when IEI is High for the channel. In this case the channel activates the INT signal. The
CPU then responds with an interrupt acknowledge cycle, and the interrupting channel
places a vector on the data bus.
DS007902-0708 P R E L I M I N A R Y Functional Description
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47
In the USC, the IP bit signals that an interrupt request is being serviced. If an IUS is set, all
interrupt sources of lower priority within the channel and external to the channel are pre-
vented from requesting interrupts. The internal interrupt sources are inhibited by the state
of the internal daisy chain, while lower priority devices are inhibited by the IEO output of
the channel being pulled Low and propagated to subsequent peripherals. An IUS bit is set
during an interrupt acknowledge cycle if there are no higher priority devices requesting
interrupts.
There are six sources of interrupt in each channel: Receive Status, Receive Data, Transmit
Status, Transmit Data, I/O Status, and Device Status, prioritized in that order within the
channel. There are six sources of Receive Status interrupt, each individually enabled:
exited hunt, idle line, break/abort, code violation/end-of-transmission/end-of-frame, parity
error, and overrun error. The Receive Data interrupt is generated whenever the receive
FIFO fills with data beyond the level programmed in the Receive Interrupt Control Regis-
ter (RICR).
There are six sources of Transmit Status interrupt, each individually enabled: preamble
sent, idle line sent, abort sent, end-of-frame/end-of-transmission sent, CRC sent, and
underrun error. The Transmit Data interrupt is generated whenever the transmit FIFO
empties below the level programmed in the Transmit Interrupt Control Register (TICR).
The I/O Status interrupt serves to report transitions on any of six pins. Interrupts are gener-
ated on either or both edges with separate selection and enables for each pin. The pins pro-
grammed to generate I/O Status interrupts are RxC, TxC, RxREQ, TxREQ, DCD, and
CTS. These interrupts are independent of the programmed function of the pins. The
Device Status interrupt has four separately enabled sources: receive character count FIFO
overflow, DPLL sync acquired, BRG1 zero count, and BRGO zero count.
Block Transfer Mode
The USC accommodates block transfers through DMA through the RxREQ, TxREQ,
RxACK, and TxACK pins. The RxREQ signal is activated when the fill level of the
receive FIFO exceeds the value programmed in the RICR. The DMA may respond with
either a normal bus transaction or by activating the RxACK pin to read the data directly
(fly-by transfer). The TxREQ signal is activated when the empty level of the transmit
FIFO falls below the value programmed in the TICR. The DMA may respond either with a
normal bus transaction or by activating the TxACK pin to write the data directly (fly-by
transfer). The RxACK and TxACK pin functions for this mode are controlled by the Hard-
ware Configuration Register (HCR). Then using the RxACK and TxACK pins to transfer
data, no chip select is necessary; these are dedicated strobes for the appropriate FIFO.
Programming
The registers in each USC channel are programmed by the system to configure the chan-
nels. Before this can occur, however, the system must program the bus interface by writing
to the Bus Configuration Register (BCR). The BCR has no specific address and is only
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
48
accessible immediately after a hardware reset of the device. The first write to the USC,
after a hardware reset, programs the BCR. From that time on, the normal channel registers
may be accessed. No specific address need be presented to the USC for the BCR write
because the first write after a hardware reset is automatically programmed for the BCR.
In the multiplexed bus case, all registers are directly addressable through the address
latched by AS at the beginning of a bus transaction. The address is decoded from either
AD6–AD0 or AD7–AD1. This is controlled by the Shift Right/Shift Left bit in the BCR.
The address maps for these two cases are listed in Table 8. The D/C pin is still used to
directly access the receive and transmit data registers (RDR and TDR) in the multiplexed
bus; if D/C is High the address latched by AS is ignored and an access of RDR or TDR is
performed.
In the nonmultiplexed bus case, the registers in each channel are accessed indirectly using
the address pointer in the Channel Command/Address Register (CCAR) in each channel.
The address of the desired register is first written to the CCAR and then the selected regis-
ter is accessed; the pointer in the CCAR is automatically cleared after this access. The
RDR and TDR are accessed directly using the D/C pin, without disturbing the contents of
the pointer in the CCAR.
1. The Channel Reset bit in the CCAR places the channel in the reset state. To exit this
reset state either a word of all zeros must be written to the CCAR (16-bit bus), or a byte
of all zeros must be written to the lower byte of the CCAR (8-bit bus).
2. After reset, the transmit and receive clocks are not connected. The first thing that
should be done in any initialization sequence is a write to the Clock Mode Control
Register (CMCR) to select a clock source for the receiver and transmitter.
The register addressing is listed in Table 9 on page 50 while the bit assignments for the
registers are displayed in Figure 29.
Table 8. Multiplexed Bus Address Assignments
Address Signal Shift Left Shift Right
Byte/Word Access AD7 AD6
Address 4 AD6 AD5
Address 3 AD5 AD4
Address 2 AD4 AD3
Address 1 AD3 AD2
Address 0 AD2 AD1
Upper/Lower Byte Select AD1 AD0
Notes:
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
49
Figure 29. BCR Reset Sequence and Bit Assignments
Reset
Multiplexed
Bus
At Least One AS
No AS
Any Transaction
Up To and Including
BCR W rite
BCR
Write
Transaction
8-Bit With
Separate
Address
8-Bit Without
Separate
Address
16-Bit
BCR[2]=0
BCR[15]=1
BCR[2]=0
BCR[15]=0
BCR[2]=1
Note:
The presence of one transaction with an /AS active between reset, up to
and including the BCR write, chooses a multiplexed type of bus.
Non-Multiplexed
Bus
8-Bit With
Separate
Address
8-Bit Without
Separate
Address
16-Bit
BCR[2]=0
BCR[15]=1
BCR[2]=0
BCR[15]=0
BCR[2]=1
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
50
Table 9. Register Address List
Address A4–A0
00000 CCAR Channel Command/Address
Register
00001 CMR Channel Mode Register
00010 CCSR Channel Command/Status Register
00011 CCR Channel Control Register
00110 TMDR Test Mode Data Register
00111 TMCR Test Mode Control Register
01000 CMCR Clock Mode Control Register
01001 HCR Hardware Configuration Register
01010 IVR Interrupt Vector Register
01011 IOCR I/O Control Register
01100 ICR Interrupt Control Register
01101 DCCR Daisy-Chain Control Register
01110 MISR Misc Interrupt Status Register
01111 SICR Status Interrupt Control Register
1X000 RDR Receive Data Register (Read Only)
10001 RMR Receive Mode Register
10010 RCSR Receive Command/Status Register
10011 RICR Receive Interrupt Control Register
10100 RSR Receive Sync Register
10101 RCLR Receive Count Limit Register
10110 RCCR Receive Character Count Register
10111 TC0R Time Constant 0 Register
1X000 TDR Transmit Data Register (Write Only)
11001 TMR Transmit Mode Register
11010 TCSR Transmit Command/Status Register
11011 TICR Transmit Interrupt Control Register
11100 TSR Transmit Sync Register
11101 TCLR Transmit Count Limit Register
11110 TCCR Transmit Character Count Register
11111 TC1R Time Constant 1 Register
XXXXX BCR Bus Configuration Register
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Z16C30
Product Specification
51
Control Registers
Figure 30. Channel Command/Address Register
7RRGT.QYGT$[VG5GNGEV9
#FFTGUU9
#FFTGUU9
#FFTGUU9
#FFTGUU9
#FFTGUU9
$[VG9QTF#EEGUU9
&/#%QPVKPWG9
%JCPPGN4GUGV
5GNGEVGFCV4GUGV
%JCPPGN
%QOOCPF
9
0QTOCN1RGTCVKQP
#WVQ'EJQ
'ZVGTPCN.QECN.QQRDCEM
+PVGTPCN.QECN.QQRDCEM
/QFG
%QPVTQN
&&&&&& &&&&&&&&&&
#FFTGUU
0WNN%QOOCPF
4GUGTXGF
4GUGV*KIJGUV+75
4GUGTXGF
6TKIIGT%JCPPGN.QCF&/#
6TKIIGT4Z&/#
6TKIIGT6Z&/#
6TKIIGT4Z6Z&/#
4GUGTXGF
4Z(+(12WTIG
6Z(+(12WTIG
4Z6Z(+(12WTIG
4GUGTXGF
.QCF4Z%JCTCEVGT%QWPV
.QCF6Z%JCTCEVGT%QWPV
.QCF4Z6Z%JCTCEVGT%QWPV
4GUGTXGF
.QCF6%
.QCF6%
.QCF6%6%
5GNGEV5GTKCN&CVC.5$(KTUV
5GNGEV5GTKCN&CVC/5$(KTUV
5GNGEV5VTCKIJV/GOQT[&CVC
5GNGEV5YCRRGF/GOQT[&CVC
4GUGTXGF
4Z2WTIG
4GUGTXGF
4GUGTXGF
4GUGTXGF
4GUGTXGF
4GUGTXGF
4GUGTXGF
DS007902-0708 P R E L I M I N A R Y Functional Description
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Product Specification
52
Figure 31. Channel Mode Register
0 0 0 0 Asynchronous
0 0 0 1 External synchronous
0 0 1 0 Isochronous
0 0 1 1 Asynchronous with CV
0 1 0 0 Monosync
0 101 Bisync
0 110 HDLC
0 1 1 1 Transparent Bisync
1 000 NBIF
1 0 0 1 802.3
1 010 Reserved
1 011 Reserved
1 100 Reserved
1 101 Reserved
1 110 Reserved
1 111 Reserved
Receive
Mode
Rx Submode 0
Rx Submode 1
Rx Submode 2
Rx Submode 3
0000
0001
0010
0011
0100
01 01
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Asynchronous
Reserved
Isochronous
Asynchronous with CV
Monosync
Bisync
HDLC
Transparent Bisync
NBIP
802.3
Reserved
Reserved
Slaved Monosync
Reserved
HDLC Loop
Reserved
Transmitter
Mode
Tx Submode 0
Tx submode 1
Tx Submode 2
Tx submode 3
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
DS007902-0708 P R E L I M I N A R Y Functional Description
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53
Figure 32. Channel Mode Register, Asynchronous Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
0 0 0 0 Asynchronous Receiver
Mode
0 0 16X Data Rate
0 1 32X Data Rate
1 0 64X Data Rate
11 Reserved
Rx Clock Rate
Reserved
Reserved
0 0 0 0 Asynchronous Transmitter
Mode
0 0 16X Data Rate
0 1 32X Data Rate
1 0 64X Data Rate
11 Reserved
Tx Clock Rate
00 One Stop Bit
0 1 Two Stop Bits
1 0 One Sop Bit, Shared
1 1 Two Stop Bits, Shared
Tx Stop Bits
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
54
Figure 33. Channel Mode Register, External Sync Mode
Figure 34. Channel Mode Register, Isochronous Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
Transmitter
Mode
00 0 1
00 0 1
External Sync
Reserved
Reserved
Reserved
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
0010
0010
Receiver
Isochronous Mode
Transmitter
Isochronous Mode
Reserved
Tx Two Stop Bits
Reserved
Reserved
DS007902-0708 P R E L I M I N A R Y Functional Description
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Product Specification
55
Figure 35. Channel Mode Register, Asynchronous Mode with
Code Violation (MIL STD 1553)
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
0 0 1 1 Asynchronous with CV Receiver
Mode
Rx Extended Word
Reserved
0000 Asynchronous with CV Transmitter
Mode
CV Polarity
Tx Extended Word
0 0 One Stop Bit
0 1 Two Stop Bits
1 0 No Stop Bit
1 1 Reserved
Tx Stop Bits
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
56
Figure 36. Channel Mode Register, Monosync Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
0 0 1 0 Monosync
0 0 1 0 Monosync Transmitter
Mode
Rx Short Sync Character
Rx Sync Strip
Reserved
Tx Short Sync Character
Tx Preamble Enable
Reserved
Tx CRC on Underrun
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Z16C30
Product Specification
57
Figure 37. Channel Mode Register, Bisync Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
0101 Bisync
0101 Bisync Transmitter
Mode
Rx Short Sync Character
Rx Sync Strip
Reserved
Tx Short Sync Character
Tx Preamble Enable
0 0 SYN1
0 1 SYN0/SYN1
1 0 CRC/SYN1
1 1 CRC/SYN0/SYN1
Tx
Underrun
Condition
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58
Figure 38. Channel Mode Register, HDLC Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
0 1 1 0 HDLC
0110 HDLC Transmitter
Mode
Shared Zero Flags
Tx Preamble Enable
00 Abort
0 1 Extended Abort
10 Flag
1 1 CRC/Flag
Tx
Underrun
Condition
00 Disabled
0 1 One Byte, No Control
1 0 One Byte, Plus Control
1 1 Extended, Plus Control
Rx Address
Search
Mode
Rx 16-Bit Control
Rx Logical
Control Enable
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Product Specification
59
Figure 39. Channel Mode Register, Transparent Bisync Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
0111 Transparent Bisync
0111 Transparent Bisync Transmitter
Mode
EBCDIC
Reserved
EBCDIC
Tx Preamble Enable
00 SYN
0 1 DLE/SYN
1 0 CRC/SYN
1 1 CRC/DLE/SYN
Tx
Underrun
Condition
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Figure 40. Channel Mode Register, NBIP Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
100 0 NBIP
1000 NBIP
Transmitter
Mode
0 0 16X Data Rate
0 1 32X Data Rate
1 0 64X Data Rate
11 Reserved
Rx Parity on Data
Reserved
0 0 16X Data Rate
0 1 32X Data Rate
1 0 64X Data Rate
11 Reserved
Tx Parity on Data
Tx Address Bit
Tx Clock
Rate
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61
Figure 41. Channel Mode Register, 802.3 Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
1 0 0 1 802.3
1 0 0 1 802.3
Transmitter
Mode
Rx Address Search
Reserved
Tx CRC on Underrun
Reserved
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62
Figure 42. Channel Mode Register, Slaved Monosync Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
110 0 Reserved
1 1 0 0 Slaved Monosync Transmitter
Mode
Reserved
Reserved
Tx Short Sync Character
Tx Active on Received Sync
Tx CRC on Underrun
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Figure 43. Channel Mode Register, HDLC Loop Mode
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00001
Receiver
Mode
1110 Reserved
1 1 1 0 HDLC Loop
Shared Zero Flags
Tx Active on Poll
00 Abort
0 1 Extended Abort
10 Flag
1 1 CRC/Flag
Tx
Underrun
Condition
Reserved
Transmitter
Mode
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
64
Figure 44. Channel Command/Status Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00010
000 8 Bits
001 1 Bit
010 2 Bits
011 3 Bits
100 4 Bits
101 5 Bits
1 1 0 6 Bits
111 7 Bits
0 0 Both Edges
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Adjust/Sync Input
DPLL
Adjust/
Sync Edge
HDLC Tx Last
Character Length
Reserved
Loop Sending (R0)
On Loop (R0)
Clock Missed Latched/Unlatch
Clocks Missed Latched/Unlatch
DPLL in Sync/Quick Sync
RCC FIFO Clear (W0)
RCC FIFO Valid (R0)
RCC FIFO Overflow (R0)
RxACK (R0)
TxACK (R0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
65
Figure 45. Channel Control Register
Figure 46. Primary Reserved Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00011
0 0 8 Bits
0 1 16 Bits
1 0 32 Bits
1 1 64 Bits
Tx Preamble
Length
0 0 All Zeros
0 1 All Ones
1 0 Alternating 1 and 0
1 1 Alternating 0 and 1
Tx Preamble
Pattern
00No Status Block
0 1 One Word Status Block
1 0 Two Word Status Block
11 Reserved
Rx Status
Block Transfer
Reserved
Wait for Rx DMA Trigger
(All Sync)
Tx Flag Preamble
Wait for Tx DMA Trigger
Tx Shaved Bit Length
(Async Only)
00No Status Block
0 1 One Word Status Block
1 0 Two Word Status Block
11 Reserved
Tx Status
Block Transfer
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00100
Reserved
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
66
Figure 47. Secondary Reserved Register
Figure 48. Test Mode Data Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00101
Reserved
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00110
Test Data <0>
Test Data <1>
Test Data <2>
Test Data <3>
Test Data <4>
Test Data <5>
Test Data <6>
Test Data <7>
Test Data <8>
Test Data <9>
Test Data <10>
Test Data <11>
Test Data <12>
Test Data <13>
Test Data <14>
Test Data <15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
67
Figure 49. Test Mode Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 00111
0 0 0 0 0 Null Address
0 0 0 0 1 High Byte of Shifters
00010CRC Byte 0
00011CRC Byte 1
0 0 1 0 0 Rx FIFO (Write)
0 0 1 0 1 Clock Multiplexer
Outputs
0 0 1 1 0 CTR0 and CTR1
Counters
0 0 1 1 1 Clock Multiplexer Inputs
01000DPLL Status
0 1 0 0 1 Low Byte of Shifters
01010CRC Byte 2
01011CRC Byte 3
0 1 1 0 0 Tx FIFO (Read)
0 1 1 0 1 Reserved
0 1 1 1 0 I/O and Device Status
Latches
0 1 1 1 1 Internal Daisy Chain
1 0 0 0 0 Reserved
1 0 0 0 1 Reserved
1 0 0 1 0 Reserved
1 0 0 1 1 Reserved
1 0 1 0 0 Reserved
1 0 1 0 1 Reserved
1 0 1 1 0 Reserved
1 0 1 1 1 Reserved
1 1 0 0 0 4044H
1 1 0 0 1 4044H
1 1 0 1 0 4044H
Reserved
Test
Register
Address
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
68
Figure 50. Clock Mode Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01000
000 Disabled
0 0 1 RxC Pin
0 1 0 TxC Pin
0 1 1 DPLL Output
1 0 0 BRG0 Output
1 0 1 BRG1 Output
1 1 0 CTR0 Output
1 1 1 CTR1 Output
0 0 0 Disabled
0 0 1 RxC Pin
0 1 0 TxC Pin
0 1 1 DPLL Output
1 0 0 BRG0 Output
1 0 1 BRG1 Output
110CTR0 Output
1 1 1 CTR1 Output
00 CTR0 Output
01 CTR1 Output
1 0 RxC Pin
11 TxC Pin
0 0 BRG0 Output
0 1 BRG1 Output
1 0 RxC Pin
11 TxC Pin
0 0 CTR0 Output
0 1 CTR1 Output
1 0 RxC Pin
11 TxC Pin
00 Disabled
01 Disabled
1 0 RxC Pin
11 TxC Pin
00 Disabled
01 Disabled
1 0 RxC Pin
11 TxC Pin
CTR1 Clock
Source
CTR0 Clock
Source
BRG1 Clock
Source
BRG0 Clock
Source
DPLL Clock
Source
Transmit Clock
Source
Receive Clock
Source
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
69
Figure 51. Hardware Configuration Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01000
00 Disabled
01 NRZ/NRZI
1 0 Biphase-Mark/Space
1 1 Biphase-Level
0 0 32x Clock Mode
0 1 16x Clock Mode
1 0 8x Clock Mode
1 1 4x Clock Mode
TxACK
Pin Control
CTR0 Clock
Rate
DPLL Clock
Rate
DPLL
Mode
BRG0 Enable
BRG0 Single Cycle/Continuous
0 0 3-State Output
0 1 Rx Acknowledge Input
1 0 Output 0
1 0 Output 1
BRG1 Enable
BRG1 single Cycle/continuous
0 0 3-State Output
0 1 Tx Acknowledge Input
1 0 Output 0
1 0 Output 1
0 0 32x Clock Mode
0 1 16x Clock Mode
1 0 8x Clock Mode
11 Reserved
RxACK
Pin Control
Accept Code Violations
CTR1 Rate Match DPLL/CTR0
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
70
Figure 52. Interrupt Vector Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01010
IV<0>
IV<1>
IV<2>
IV<3>
IV<4>
IV<5>
IV<6>
IV<7>
IV<0>(R0)
IV<4>(R0)
IV<5>(R0)
IV<6>(R0)
IV<7>(R0)
000 None
0 0 1 Device Status
0 1 0 I/O Status
0 1 1 Transmit Data
1 0 0 Transmit Status
1 0 1 Receive Data
1 1 0 Receive Status
1 1 1 Not Used
Modified
Vector (R0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
71
Figure 53. I/O Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01001
0 0 0 Input Pin
0 0 1 Rx Clock Output
0 1 0 Rx Byte Clock Output
0 1 1 SYNC Output
1 0 0 BRG0 Output
1 0 1 BRG1 Output
1 1 0 CTR0 Output
1 1 1 DPLL Rx Output
000 Input Pin
0 0 1 Tx clock Output
0 1 0 Tx Byte clock Output
0 1 1 Tx Complete Output
1 0 0 BRG0 Output
1 0 1 BRG1 Output
110 CTR0 Output
111 DPLL Output
0 0 3-State Output
0 1 Rx Request Output
1 0 Output 0
1 1 Output 1
0 0 Tx Data Output
0 1 3-State Output
10 Output 0
11 Output 1
0 0 3-State Output
0 1 Tx Request Output
1 0 Output 0
1 1 Output 1
0 0 DCD Input
0 1 DCD/SYNC Input
1 0 Output 0
1 1 Output 1
0 0 CTS Input
0 1 CTS Input
1 0 Output 0
1 1 Output 1
CTS Pin
Control
DCD Pin
Control
TxREQ Pin
Control
RxREQ Pin
Control
TxD Pin
Control
TxC Pin
Control
RxC Pin
Control
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
72
Figure 54. Interrupt Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01100
Device Status IE
I/O Status IE
Transmit Data IE
Transmit Status IE
Receive Data IE
Receive Status IE
Received
VIS
NV
DLC
MIE
000 All
001 All
0 1 0 I/O Status and Above
0 1 1 Transmit Data and Above
1 0 0 Transmit Status and Above
1 0 1 Receive Data
1 1 0 Receive Status Only
1 1 1 None
VIS
Level
0 0 Null command
0 1 Null command
10 Reset IE
11 Set IE
IE Command
(W0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
73
Figure 55. Daisy-Chain Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01101
Device Status IP
I/O Status IP
Transmit Data IP
Transmit Status IP
Receive Data IP
Receive Status IP
Device Status IUS
I/O Status IUS
Transmit Data IUS
Transmit Status IU
S
Receive Data IUS
0 0 Null command
0 1 Reset IP and IUS
10 Reset IP
11 Set IP
IP Command
(W0)
0 0 Null command
0 1 Null command
10 Reset IUS
11 Set IUS
IUS Command
(W0)
Receive Status IUS
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
74
Figure 56. Miscellaneous Interrupt Status Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01110
BRG0 ZC Latched/Unlatch
BRG1 ZC latched/Unlatch
DPLL SYNC latched/Unlatch
RCC Overflow Latched/Unlatch
CTS (R0)
CTS Latched/Unlatch
DCD (R0)
DCD Latched/Unlatch
TxREQ (R0)
TxREQ Latched/Unlatch
RxREQ (R0)
RxREQ Latched/Unlatch
TxC (R0)
TxC Latched/Unlatch
RxC (R0)
RxC Latched/Unlatch
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
75
Figure 57. Status Interrupt Control Register
00 Disabled
0 0 Rising Edge Only
0 1 Falling Edge Only
0 1 Both Edges
CTS
Interrupts
DCD
Interrupts
00 Disabled
0 0 Rising Edge Only
0 1 Falling Edge Only
01 Both Edges
TxREQ
Interrupts
00 Disabled
0 0 Rising Edge Only
0 1 Falling Edge Only
0 1 Both Edges
00 Disabled
0 0 Rising Edge Only
0 1 Falling Edge Only
01 Both Edges
RxREQ
Interrupts
TxC
Interrupts
00 Disabled
0 0 Rising Edge Only
0 1 Falling Edge Only
0 1 Both Edges
RxC
Interrupts
BRG0 ZC IE
BRG1 ZC IE
DPLL SYNC IE
RCC Overflow IE
00 Disabled
0 0 Rising Edge Only
0 1 Falling Edge Only
0 1 Both Edges
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 01111
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
76
Figure 58. Receive Data Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 0x110
Rx DAT <0>(R0)
Rx DAT <1>(R0)
Rx DAT <2>(R0)
Rx DAT <3>(R0)
Rx DAT <4>(R0)
Rx DAT <5>(R0)
Rx DAT <6>(R0)
Rx DAT <7>(R0)
Rx DAT <8>(R0)
Rx DAT <9>(R0)
Rx DAT <10>(R0)
Rx DAT <11>(R0)
Rx DAT <12>(R0)
Rx DAT <13>(R0)
Rx DAT <14>(R0)
Rx DAT <15>(R0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
77
Figure 59. Receive Mode Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10001
0 0 Disable Immediately
0 1 Disable After Reception
1 0 Enable Without Auto-Enables
1 1 Enable With Auto-Enable
Rx
Enable
0 0 0 8 Bits
001 1 Bit
0 1 0 2 Bits
0 1 1 3 Bits
1 0 0 4 Bits
1 0 1 5 Bits
1 1 0 6 Bits
1 1 1 7 Bits
Rx Character
Length
00 Even
01 Odd
1 0 Space
11 Mark
Rx Parity
Sense
0 0 CRC-CCITT
0 1 CRC-16
1 0 CRC-32
11 Reserved
Rx CRC
Polynomial
000 NRZ
0 0 1 NRZB
0 1 0 NRZI-Mark
0 1 1 NRZI-Space
1 0 0 Biphase-Mark
1 0 1 Biphase-Space
1 1 0 Biphase-Level
1 1 1 Diff. Biphase-Level
Rx Data
Decoding
Queue Abort
Rx CRC Enable
Rx CRC Preset Value
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
78
Figure 60. Receive Command Status Register
0000Null Command
0001Reserved
0 0 1 0 Preset CRC
0 0 1 1 Enter Hunt Mode
0100Reserved
0 1 0 1 Select FIFO Status
0 1 1 0 Select FIFO Interrupt Level
0 1 1 1 Select FIFO Status Level
1000Reserved
1001Reserved
1010Reserved
1011Reserved
1100Reserved
1101Reserved
1110Reserved
1111Reserved
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10010
Receive
Command (R0)
First Byte in Error (R0)
Second Byte in Error (R0)
Rx Character Available (R0)
Rx Overrun
Parity Error/Frame Abort
CRC/Framing Error
Rx CV/EOT/EOF
Rx Break/Abort
Rx Idle
Exited Hunt
Short Frame/CV Polarity (R0)
Residue Code 0 (R0)
Residue Code 1 (R0)
Residue Code 2 (R0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
79
Figure 61. Receive Interrupt Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10011
TC0R Read Count/TC
Rx Overrun IA
Parity Error/Frame Abort IA
Status on Words
Rx CV/EOT/EOF IA
Rx Break/Abort IA
Rx Idle IA
Exited Hunt IA
Rx FIFO Control and Status
(Fill/Interrupt/DMA Level)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
80
Figure 62. Receive Sync Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10100
RSYN<0>
RSYN<1>
RSYN<2>
RSYN<3>
RSYN<4>
RSYN<5>
RSYN<6>
RSYN<7>
RSYN<8>
RSYN<9>
RSYN<10>
RSYN<11>
RSYN<12>
RSYN<13>
RSYN<14>
RSYN<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
81
Figure 63. Receive Count Limit Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10101
RCL<0>
RCL<1>
RCL<2>
RCL<3>
RCL<4>
RCL<5>
RCL<6>
RCL<7>
RCL<8>
RCL<9>
RCL<10>
RCL<11>
RCL<12>
RCL<13>
RCL<14>
RCL<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
82
Figure 64. Receive Character Count Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10110
RCC<0> (R0)
RCC<1>(R0)
RCC<2>(R0)
RCC<3>(R0)
RCC<4>(R0)
RCC<5>(R0)
RCC<6>(R0)
RCC<7>(R0)
RCC<8>(R0)
RCC<9>(R0)
RCC<10>(R0)
RCC<11>(R0)
RCC<12>(R0)
RCC<13>(R0)
RCC<14>(R0)
RCC<15>(R0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
83
Figure 65. Time Constant 0 Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 10111
TC0<0>
TC0<1>
TC0<2>
TC0<3>
TC0<4>
TC0<5>
TC0<6>
TC0<7>
TC0<8>
TC0<9>
TC0<10>
TC0<11>
TC0<12>
TC0<13>
TC0<14>
TC0<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
84
Figure 66. Transmit Data Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 1x000
TxDAT<0>(W0)
TxDAT<1>(W0)
TxDAT<2>(W0)
TxDAT<3>(W0)
TxDAT<4>(W0)
TxDAT<5>(W0)
TxDAT<6>(W0)
TxDAT<7>(W0)
TxDAT<8>(W0)
TxDAT<9>(W0)
TxDAT<10>(W0)
TxDAT<11>(W0)
TxDAT<12>(W0)
TxDAT<13>(W0)
TxDAT<14>(W0)
TxDAT<15>(W0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
85
Figure 67. Transmit Mode Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11001
0 0 Disable Immediately
0 1 Disable After Reception
1 0 Enable Without Auto-Enables
1 1 Enable With Auto-Enable
Tx
Enable
000 8 Bits
001 1 Bit
010 2 Bits
011 3 Bits
100 4 Bits
101 5 Bits
1 1 0 6 Bits
111 7 Bits
Rx Character
Length
0 0 Even
01 Odd
1 0 Space
11 Mark
Tx Parity
Sense
0 0 CRC-CCITT
0 1 CRC-16
1 0 CRC-32
1 1 Reserved
Tx CRC
Polynomial
000 NRZ
0 0 1 NRZB
0 1 0 NRZI-Mark
0 1 1 NRZI-Space
1 0 0 Biphase-Mark
1 0 1 Biphase-Space
1 1 0 Biphase-Level
1 1 1 Diff. Biphase-Level
Tx Data
Decoding
Tx CRC on EOF/EOM
Tx CRC Enable
Tx CRC Preset Value
Tx Parity enable
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
86
Figure 68. Transmit Command/Status Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11010
0000Null Command
0001Reserved
0010Preset CRC
0 0 1 1 Enter Hunt Mode
0100Reserved
0 1 0 1 Select FIFO Status
0 1 1 0 Select FIFO Interrupt Level
0 1 1 1 Select FIFO Status Level
1000
Send Frame Message
1001
Send Abort
1010
Reserved
1011
Reserved
1100
Reset DLE Inhibit
1101
Set DLE Inhibit
1110
Reset EOF/EOM
1111
Set EOT/EOM
0 0 0 Null Command
0 0 0 Reserved
0 1 0 Preset CRC
0 1 1 Enter Hunt Mode
1 0 0 Reserved
1 0 1 Select FIFO Status
1 1 0 Select FIFO Interrupt Level
1 1 1 Select FIFO Status Level
Tx Buffer Empty (R0)
Tx Underrun
All Sent (R0)
Tx CRC Sent
Tx EOF/EOT Sent
Tx Abort Sent
Tx Idle Sent
Tx Preamble Sent
Tx Idle Line
Condition
Tx Wait on Underrun
Transmit
Command (W0)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
87
Figure 69. Transmit Interrupt Control Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11011
TC1R Read Count/TC
Tx Overrun IA
Wait for Send Command
Tx CRC Sent IA
Tx EOF/EOT Sent IA
Tx Abort Sent IA
Tx Idle Sent IA
Tx Preamble Sent IA
Tx FIFO Control and Status
(Fill/Interrupt/DMA level)
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
88
Figure 70. Transmit Sync Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11100
TSYN<0>
TSYN<1>
TSYN<2>
TSYN<3>
TSYN<4>
TSYN<5>
TSYN<6>
TSYN<7>
TSYN<8>
TSYN<9>
TSYN<10>
TSYN<11>
TSYN<12>
TSYN<13>
TSYN<14>
TSYN<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
89
Figure 71. Transmit Count Limit Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11101
TCL<0>
TCL<1>
TCL<2>
TCL<3>
TCL<4>
TCL<5>
TCL<6>
TCL<7>
TCL<8>
TCL<9>
TCL<10>
TCL<11>
TCL<12>
TCL<13>
TCL<14>
TCL<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
90
Figure 72. Transmit Character Count Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11110
TCC<0>
TCC<1>
TCC<2>
TCC<3>
TCC<4>
TCC<5>
TCC<6>
TCC<7>
TCC<8>
TCC<9>
TCC<10>
TCC<11>
TCC<12>
TCC<13>
TCC<14>
TCC<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
91
Figure 73. Time Constant 1 Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: 11111
TC1<0>
TC1<1>
TC1<2>
TC1<3>
TC1<4>
TC1<5>
TC1<6>
TC1<7>
TC1<8>
TC1<9>
TC1<10>
TC1<11>
TC1<12>
TC1<13>
TC1<14>
TC1<15>
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
92
Figure 74. Receive Status Block Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: None*
RCC<0>
Rx Overrun
Parity Error/Frame Abort
CRC Error
Rx CV/EOT/EOF
RCC FIFO Overflow
0
0
Short Frame/CV Polarity
Residue Code 0
Residue Code 1
Residue Code 2
0
0
First Byte in Error
Second Byte in Error
* Refer to Figure 22, Channel Control Register Bits 6–7 for Access Method
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
93
Figure 75. Transmit Status Block Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: None*
* Refer to Figure 22, Channel Control Register Bits 6–7 for Access Method
0008 Bits
0001 Bit
0102 Bits
0113 Bits
1004 Bits
1015 Bits
1106 Bits
1117 Bits
HDLC Tx Last
Character Length
Reserved
Reserved
Tx Submode 1
Tx Submode 2
Tx Submode 3
Tx Submode 0
DS007902-0708 P R E L I M I N A R Y Functional Description
Z16C30
Product Specification
94
Figure 76. Bus Configuration Register
D10D11D12D13D14D15 D0D1D2D3D4D5D6D7D8D9
Address: None
Shift Right Addresses
Double-Pulse INTACK
16-Bit Bus
0*
Reserved
3-State All Pins
Separate Address for 8-Bit Bus
*Must be programmed as zero.
DS007902-0708 P R E L I M I N A R Y Ordering Information
Z16C30
Product Specification
97
Ordering Information
Order the Z16C30 Series from Zilog®, using the following part numbers. For more infor-
mation on ordering, consult your local Zilog sales office. The Zilog website
(www.zilog.com) lists all regional offices and provides additional Z16C30 product infor-
mation.
For fast results, contact your local Zilog® sales office for assistance in ordering the part
desired.
Codes
Z16C30 (10 MHz)
68-Pin PLCC Z16C3010VSC
Z 16C30 10 V S C
Environmental Flow
C= Plastic Standard Flow
Temperature Range
S = 0 °C to 70 °C (Standard)
Package
V= Plastic Leaded Chip Carrier
Speed
10= 10 MHz
Product Number
16C30
Zilog® Prefix
DS007902-0708 P R E L I M I N A R Y Customer Support
Z16C30
Product Specification
98
Customer Support
For answers to technical questions about the product, documentation, or any other
issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at
http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit
Zilog’s Technical Support at http://support.zilog.com.
