CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-00061 Rev. *E Revised September 16, 2009
Features
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 110 mA at 10 ns
■Low CMOS standby power
❐ISB2 = 20 mA
■2.0V data retention
■Automatic power down when deselected
■TTL-compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free 44-pin TSOP II package
■Offered in standard and high reliability (Q) grades
Functional Description
The CY7C1059DV33[1] is a high performance CMOS Static RAM
organized as 1M words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. To write to the device,
take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data
on the eight IO pins (IO0 through IO7) is then written into the
location specified on the address pins (A0 through A19).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
The eight input or output pins (IO0 through IO7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
The CY7C1059DV33 is available in 36-ball FBGA and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
A0
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A13
A14
A15
A16
A17
ROW DECODER
COLUMN DECODER
1M x 8
ARRAY
INPUT BUFFER
A10
A18
A11
A12
A19
Logic Block Diagram
Note
1. For guidelines about SRAM system design, refer to the Cypress application note AN1064, SRAM System Guidelines available at www.cypress.com.
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Document #: 001-00061 Rev. *E Page 2 of 10
Pin Configuration
Figure 1. 44-Pin TSOP II
A6
1
2
3
4
5
6
7
8
9
10
11
14 31
32
36
35
34
33
37
40
39
38
Top View
12
13
41
44
43
42
16
15
29
30
VCC
A7
A8
A9
NC
NC
NC
NC
A18
VSS
NC
A15
A0
IO0
A4
CE
A17
A12
A1
18
17
20
19
IO1
27
28
25
26
22
21
23
24
NC
VSS
WE
IO2
IO3
A5
NC
A16
VCC
OE
IO 7
IO 6
IO 5
IO 4
A14
A13
A11
A10
A19
NC
NC
A2
A3
Selection Guide
Description –10 –12 Unit
Maximum Access Time 10 12 ns
Maximum Operating Current 110 100 mA
Maximum CMOS Standby Current 20 20 mA
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Document #: 001-00061 Rev. *E Page 3 of 10
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VCC to Relative GND[2] ....–0.5V to + 4.6V
DC Voltage Applied to Outputs
in High-Z State[2].................................... –0.3V to VCC + 0.3V
DC Input Voltage[2] ................................ –0.3V to VCC + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............. ...............................>2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40°C to +85°C3.3V ± 0.3V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions –10 –12 Unit
Min Max Min Max
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIL Input LOW Voltage[2] –0.3 0.8 –0.3 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 μA
IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled–1+1–1+1μA
ICC VCC Operating
Supply Current
VCC = Max., f = fMAX = 1/tRC 110 100 mA
ISB1 Automatic CE Power Down
Current —TTL Inputs
Max. VCC, CE > VIH VIN > VIH
or VIN < VIL, f = fMAX
40 35 mA
ISB2 Automatic CE Power Down
Current —CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
20 20 mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.]
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.3V
12 pF
COUT IO Capacitance 12 pF
Notes
2. VIL(min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions TSOP II Unit
ΘJA Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, four-layer printed
circuit board
51.43 °C/W
ΘJC Thermal Resistance
(Junction to Case)
15.8 °C/W
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Document #: 001-00061 Rev. *E Page 4 of 10
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all
speeds using the test load shown in Figure 2 (c).
Figure 2. AC Test Loads and Waveforms
Figure 3. Data Retention Waveform
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50Ω
50Ω
1.5V
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317Ω
R2
351Ω
High-Z characteristics:
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions[4] Min Max Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
20 mA
tCDR[3] Chip Deselect to Data
Retention Time 0ns
tR[5] Operation Recovery Time tRC ns
3.0V3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
Notes
4. No inputs may exceed VCC + 0.3V.
5. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs.
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Document #: 001-00061 Rev. *E Page 5 of 10
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. tPOWER is the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 4. Transition is measured when
the outputs enter a high impedance state.
9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
10. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
AC Switching Characteristics
Over the Operating Range[6]
Parameter Description –10 –12 Unit
Min Max Min Max
Read Cycle
tpower[7] VCC(typical) to the First Access 100 100 μs
tRC Read Cycle Time 10 12 ns
tAA Address to Data Valid 10 12 ns
tOHA Data Hold from Address Change 2.5 2.5 ns
tACE CE LOW to Data Valid 10 12 ns
tDOE OE LOW to Data Valid 5 6 ns
tLZOE OE LOW to Low-Z 0 0 ns
tHZOE OE HIGH to High-Z[8, 9] 56ns
tLZCE CE LOW to Low-Z[9] 33ns
tHZCE CE HIGH to High-Z[8, 9] 56ns
tPU CE LOW to Power up 0 0 ns
tPD CE HIGH to Power down 10 12 ns
Write Cycle[10, 11]
tWC Write Cycle Time 10 12 ns
tSCE CE LOW to Write End 7 8 ns
tAW Address Setup to Write End 7 8 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Setup to Write Start 0 0 ns
tPWE WE Pulse Width 7 8 ns
tSD Data Setup to Write End 5 6 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low-Z[9] 33ns
tHZWE WE LOW to High-Z[8, 9] 56ns
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Document #: 001-00061 Rev. *E Page 6 of 10
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[12, 13]
Figure 5. Read Cycle No. 2 (OE Controlled)[13, 14]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
Notes
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid before or coincident with CE transition LOW.
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Document #: 001-00061 Rev. *E Page 7 of 10
Figure 6. Write Cycle No. 1 (WE Controlled, OE High During Write)[15, 16]
Figure 7. Write Cycle No. 2 (WE Controlled, OE Low)[16]
Switching Waveforms(continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 17
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 17
Notes
15. Data IO is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the IOs are in the output state and input signals must not be applied.
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Document #: 001-00061 Rev. *E Page 8 of 10
Truth Table
CE OE WE IO0–IO7Mode Power
H X X High-Z Power Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High-Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range Grade
10 CY7C1059DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-Free) Industrial Standard
12 CY7C1059DV33-12ZSXQ 51-85087 44-pin TSOP II (Pb-Free) Industrial High reliability
(< 100 ppm)
CY7C1059DV33-12ZSXI 51-85087 44-pin TSOP II (Pb-Free) Industrial Standard
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 8. 44-Pin TSOP II (51-85087)
51-85087-*A
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Document #: 001-00061 Rev. *E Page 9 of 10
Document History Page
Document Title: CY7C1059DV33, 8-Mbit (1M x 8) Static RAM
Document Number: 001-00061
REV. ECN NO. Orig. of
Change
Submission
Date Description of Change
** 342195 PCI See ECN New Data Sheet
*A 380574 SYT See ECN Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8, 10
and 12 ns speed bins respectively
ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8, 10
and 12 ns speed bins respectively
Changed the Capacitance values from 8 pF to 10 pF on Page # 3
*B 485796 NXR See ECN Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed -8 and -12 Speed bins from product offering,
Removed Commercial Operating Range option,
Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and
VCC + 0.5V to VCC + 0.3V
Updated footnote #7 on High-Z parameter measurement
Added footnote #11
Changed the Description of IIX from Input Load Current to
Input Leakage Current.
Updated the Ordering Information table and Replaced Package Name column
with Package Diagram.
*C 1513285 VKN/AESA See ECN Converted from preliminary to final
Added 12 ns speed bin
Changed CIN and COUT specs from 16 pF to 12 pF
Changed tOHA spec from 3 ns to 2.5 ns
Updated Ordering information table
*D 2594352 NXR/PYRS 10/21/08 Added Q-Grade part
*E 2764423 AJU 09/16/2009 Corrected typo in the ordering information table
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CY7C1059DV33
© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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