PML45002101AA - Intel Corporation

Pentium III Processor Mobile Module:

Mobile Module Connector 2 (MMC-2)

Datasheet

Product Features

■Mobile Pentiu m III processor at speeds of

450 MHz and 500 MHz

■On-die, primary 16-K Instruction cache and

16-K Write Back Data cache

■On-die, 256-K L2 cache

—Eight-way set associative

—Runs at the speed of the processor core

■Fully compatible with previou s Intel

mobile microprocessors

—Binary compatible with all applications

—Support for MMX technology

■Support s st reami n g SIMD

■Power management features that provide

low-power dissipation

—Quick Start mode

—Deep Sleep mode

■Integrated math co-processor

■Integrated Active Thermal Feedback (ATF)

system

■Programmable tr ip po int inter rupt or poll

mode for temperature reading

■Intel 82443BX Hos t Br idge system

controller

—DRAM co ntroller su pports 3.3-V

SDRAM at 100 MHz

—Supports PCI CLKRUN# protocol

—SDRAM clock enable support and self-

refresh of SDRAM during Suspend

mode

—PCI bus control 3.3V only, PCI

Specification Revision 2.1 compliant

■Supports single AGP 66-MHz, 3.3-V

device

■Two-piece TTP thermal transfer plate

(TTP) for heat dissipation

—The CPU TTP is made of nickel-plated

copper

—The BX TTP is made of aluminum

■Pentium III processor core voltage

regulation su pports input vol tages fro m

7.5V to 21.0V DC

—Above 80% peak efficiency

—Integrated VR solution

245304-004

Datasheet 245304-004

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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Pentium III processor mobile module may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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548-4725 or by visiting Intel’s website at http://www.intel.com.

*Other brands and names are the property of their respective owners.

245304-004 Datasheet iii
Pentium III Processor Mobile Module MMC-2
Contents
0 Introduction.........................................................................................................................1
1 References............................................................................................................1
0 Architectur e Overv ie w........................... ....... ...... ...... ....... ................... ....... ...... ....... ............2
0 Signal Information ..............................................................................................................4
1 Signal Definitions...................................................................................................4
1.1 Signal List.................................................................................................5
1.2 Memory Signal Description ......................................................................6
1.3 AGP Signals.............................................................................................7
1.4 PCI Signals...............................................................................................9
1.5 Processor and PIIX4E/M Sideband Signals...........................................11
1.6 Power Management Signals ..................................................................12
1.7 Clock Signa ls.. ....... ................... ...... ....... ...... .................... ...... ....... ...... ....1 3
1.8 Voltage Signals ......................................................................................14
1.9 ITP and JTAG Pins.................................................................................15
1.10 Miscellaneous Pins.................................................................................15
2 Connecto r Pin Assig nme nts............ ...... ...... ....... ................... ....... ...... ....... ..........16
3 Pin and Pad Assignments...................................................................................18
0 Function al Des criptio n.................................. ...... ...... ....... ................... ....... ...... ....... ..........20
1 Pentium III Processor Mobile Module MMC-2.....................................................20
2 L2 Cache.............................................................................................................20
3 The 82443BX Host Bridge System Controller.....................................................20
3.1 Memory Organization.............................................................................20
3.2 Reset Strap Options...............................................................................21
3.3 PCI Interface ..........................................................................................21
3.4 AGP Interface.........................................................................................22
4 Power Management ............................................................................................22
4.1 Clock Control Archi tectur e.............. ....... ...... ....... ...... .................... ...... ....22
4.1.1 Normal State .............................................................................24
4.1.2 Auto Halt State ............................... ....... ...... ....... ................... ....24
4.1.3 Stop Grant State.......... ...... ....... ...... ....... ...... .................... ...... ....25
4.1.4 Quick Start State .......................................................................25
4.1.5 HALT/Grant Snoop State ..........................................................26
4.1.6 Sleep State................................................................................26
4.1.7 Deep Sleep State ......................................................................26
5 Power Consumption in Power Management Mode.............................................27
0 Electrical Specifications....................................................................................................28
1 System Bus Clock Signal Quality Specifications.................................................28
1.1 BCLK DC Specifications.........................................................................28
1.2 BCLK AC Specifications.........................................................................28
2 System Power Requirements..............................................................................30
3 Processor Core Voltage Regulation....................................................................30
3.1 Voltage Regulator Efficiency..................................................................30
3.2 Voltage Regulator Control......................................................................32

Pentium III Processor Mobile Module MMC-2
iv  Datasheet 245304-004
3.3 Power Planes: Bulk Capacitance Requirements....................................34
3.4 System Power Supply Protection Guidelines.........................................36
3.4.1 DC Power System Protection....................................................36
3.4.2 V_DC Power Supply..................................................................37
3.4.3 Overcurrent Protection..............................................................37
3.4.4 Current Limit Shift Point ............................................................39
3.4.5 Slew Rate Control .....................................................................41
3.4.6 Undervoltage Lockout ...............................................................43
3.4.7 Overvoltage Lockout .................................................................44
4 Active Thermal Feedback ...................................................................................48
5 Thermal Sensor Configuration Register..............................................................48
0 Mechanical Specification..................................................................................................49
1 Module Dimensions.............................................................................................49
1.1 Pin 1 Location of the MMC-2 Connector................................................49
1.2 Printed Cir cuit Boa r d................... ...... ....... ...... .................... ...... ....... ...... .50
1.3 Height Restrictions.................................................................................51
2 Thermal Transfer Plate .......................................................................................51
3 Module Physical Support ....................................................................................53
3.1 Module Mounting Requirements ............................................................53
3.2 Module Weight.......................................................................................54
0 Thermal Specification.......................................................................................................55
1 Thermal Design Power........................................................................................55
0 Labeling Information.........................................................................................................56
0 Environmental Standards.................................................................................................58
Figures 1 Pentium III Processor Mobile Module Block Diagram...........................................3
MMC-2 Connector Pad Footprint........................................................................19
Clock Control States ...........................................................................................24
BCLK Waveform at the Processor Core Pins .....................................................29
VR Efficiency Chart ............................................................................................31
Power Sequence Timing.....................................................................................34
V_DC Ripple Current ..........................................................................................36
V_DC Power System Protection Block Diagram.................................................37
Overcurrent Protection Circuit.............................................................................38
Current Shift Model .............................................................................................39
Undervoltage Lockout.........................................................................................43
Undervoltage Lockout Model ..............................................................................44
Overv olt age Lock out ...... .................... ...... ...... ....... ................... ....... ...... ....... .......45
Overv olt age Lock out Mode l ........ ....... ...... ...... ....... ...... ....... ................... ....... ...... .45
Recommended Power Supply Protection Circuit for the System Electronics .....47
Simulation of V_DC Voltage Skew......................................................................47
Board Dimensions and MMC-2 Connector Orientation.......................................49
Board Dimensions and MMC-2 Connector—Pin 1 Orientation...........................50

245304-004 Datasheet v
Pentium III Processor Mobile Module MMC-2
Printed Circuit Board Thickness..........................................................................50
Keep-out Zone.....................................................................................................51
82443BX Thermal Transfer Plate (Reference Only)  ..........................................52
82443BX Thermal Transfer Plate Detail..............................................................52
CPU Thermal Transfer Plate (Reference Only)...................................................53
Standoff Holes, Board Edge Clearance, and EMI Containment Ring .................54
Product Tracking Code........................................................................................57
Tables 1 Connector Si gnal Summ ary ............ ................... ...... ....... ...... .................... ...... ......4
Memory Signal Descriptions..................................................................................6
AGP Signal Descriptions.......................................................................................7
PCI Signal Descriptions.........................................................................................9
Processor and PIIX4E/M Sideband Signal Descriptions.....................................11
Power Management Signal Descriptions ............................................................12
Clock Signa l Descript ion s......... ....... ...... ................... ....... ...... ....... ................... ....13
Voltage Descriptions ...........................................................................................14
ITP and JTAG Pins..............................................................................................15
Miscellaneous Pin Descriptions...........................................................................15
Connecto r Pin Assig nme nt.............. ...... ...... ....... ...... ....... ...... ....... ................... ....16
Connecto r Speci ficat ion s.... ...... ....... ...... ...... ....... ...... ....... ................... ....... ...... ....1 9
Configuration Straps for the 82443BX Host Bridge System Controller...............21
Clock State Char acter isti cs......................... ....... ...... ....... ...... .................... ...... ....23
Power Consumption Values I..............................................................................27
Power Consumption Values II.............................................................................27
BCLK DC Specifications......................................................................................28
BCLK AC Specifications at the Processor Core Pins..........................................28
BCLK Signal Quality AC Specifications at the Processor Core...........................29
System Power Requirements..............................................................................30
Vcore Power Conversion Efficiency ...................................................................31
Voltage Signal Definitions and Sequences .........................................................32
VR_ON In-rush Current.......................................................................................33
Bulk Capacitance Requirements.........................................................................35
Thermal Sensor SMBus Address........................................................................48
Thermal Sensor Configuration Register..............................................................48
Thermal Design Power Specification ..................................................................55
Environ men tal Sta nda rds......... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ..........58

Pentium III Processor Mobile Module MMC-2

vi Datasheet 245304-004

Revision History

Date Revision Updates

October 1999 1.0 Initial Release

February 2000 2.0 Revision 2.0 contains the following updates:

•All PIIX4M references have changed to PIIX4E/M because both parts may

be used

•Added Section 4.5, which now contains the power consumption values in

power management modes

•Updated the entire Sections of 5.1 and 5.2 for clarity

•Section 5.3.4 was updated for accuracy and clarity

•The VR efficiency values were updated in Table 20 and Figure 5. Previously ,

the values were shown at 1.35V

•Updated Figure 6. An Intel SpeedStep technology signal was removed

•Updated Table 24 to be consistent with the schematics

•Added a note in Figure 17 for clarification

•Figure 22 was added for additional thermal transfer plate detail

•Specification clarifications were made to Section 6.2 and Section 6.3.1

April 2000 3.0 Revision 3.0 contains the following updates:

•Added Table 16, “Power Consum ption Values II”, which contains power

management data on conversion modules and B-step modules

•In Table 19, “BCLK Signal Quality AC Specifications at the Processor Core”

note 3 was updated for clarification

•Added maximum and minimum designators to Figure 4, “BCLK Waveform at

the Processor Core Pins” for clarity

•Rewrote Section 5.3.3, “Power Planes: Bulk Capacitance Requirements” for

clarity

September 2000 4.0 Revision 4.0 contains the following updates:

•Added new product tracking numbers to Table 16.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 1

1.0 Introduction

This document provides th e technical specifications for integrating the Intel Pen tium III processo r

mobile module connector 2 (MMC-2) into the latest noteb ook systems for tod ay’s notebook

market.

Building around this design gives the system manufacturer these advantages:

•Avoids complexities associated with designing high-speed processor core logic boards.

•Provides an upgrade path from previous Intel mobile modules using a standard interface.

1.1 References

Refer to the following documents for additional info rmation relating to the Pentium III processor

mobile mod ule .

Mobile Pentium III Processor Datasheet

Intel 440BX AGPSet: 82443BX Host Bridge/Controller Datasheet (Order Number: 290633-001)

82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) (Order Number: 290562-001)

Intel 82371MB (PIIX4E/M) Specification Update*

CK97 Clock Synthes i ze r/ Dri ver Specif icat ion (OR -10 89)

Intel Pentium III Processor Mobile Module M MC-2 Simulation and Validation Kit Rev. 2.0 (OR-

1781)

Intel Pentium III Processor Mobile Module System Electronics 100-MHz Layout Guidelines Rev.

1.0 (OR-1780)

Mobile Pentium III Processor/440BX AGPset Recommended Design and Debug Practices

(RDDP-A) 100 MHz Rev. 2.0 (SC-2760)

66/100MHz PC SDRAM Unbuffered SO-DIMM Specification Rev 1.0*

Intel Mobile Module Design Guide (AP-590)

Pentium® II Processor Mobile Module MMC-2 Insertion & Extraction User Manual Rev 1.0*

Mobile Pentium II Processor Mobile Module 400-Pin BGA Connector Assembly Development

Guide Rev. 1.0*

Focused Discussion on Intel Mobile Modules Design for Mfg. & Best Methods for MHPG

Customers Rev. 1.0 (OR-1385)

EMI Design Guide (ORMD6-0859)

Intel Mobile Module Newsletters*

Intel Mobile Module Thermal Diode Temperature Sensor Application Note*

Intel MMC-2 Standoff/Receptacle Height Spreadsheet*

AGP Interface Specification Revision 2.0*

*Available now, contact your Intel Field Representative

Pentium III Processor Mobile Module MMC-2

2Datasheet 245304-004

2.0 Architecture Overview

A highly integrated ass e m bly, the Pentium III processor mobile module contains the mobile

Pentium III processor core that runs at speeds of 450 MHz and 500 MHz with a 100-MHz processor

system bus speed (PSB).

The Intel 440BX AGPset provides immediate system-level support and includes the PIIX4E/M

PCI/ISA Bridge and the 82443BX Host Bridge. The PIIX4E/M provides extensive power

management capabilities and supports the Intel 82443BX Host Bridge. A notebook’s system

electronics must includ e a PIIX4E/M device to conn ect to the Pentium III processor mobi le modu le.

Key features of the Intel 82443BX Host Bridge include: the DRAM controller supporting SDRAM

at 3.3Vwith a burst read at 4-1-1-1; a PCI CLKRUN# signal to request the PIIX4E/M to regulate

the PCI clock on the PCI bus; the 82443BX clock enables Self-Refresh mode of SDRAM during

Suspend mode and is compatible with SMRAM (C_SMRAM) and Extended SMRAM

(E_SMRAM) modes of power management ; and E_SMRAM mode supports write-back cacheable

SMRAM up to 1 MB.

The thermal transfer plates (TTP) on the mobile Pentium III processor and the 82443BX Host

Bridge provide heat dissipation and thermal attach points for the manufacturer’s thermal solution .

An on-board voltage regulator converts the system DC voltage to the processor’s core and I/O

voltage. Isolating the processor voltage requirements allows the system manufacturer to

incorporate different processor variants into a single notebook system. Supporting input voltages

from 7.5V to 21.0V, the integrated modu le voltage regulator enables an above 8 0% peak ef ficiency

and de-couples the processor voltage requirements from the system.

Also incorpor ated is active thermal feed back (ATF) s ensing, compliant with the ACPI Specification

Rev 1.0. Figure 1 illustrates the block diagram of the mobile module .

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 3

Figure 1. Pentium III Processor Mobile Module Block Diagram

400-Pin, Board-to-Board Connector

CPU

Voltage

Reg

Memory Bus

82443BX

"Northbridge"

V_3

ATF

Sense

Mobile

Pentium III

Processor

Core

Sideband Pullup (V_CPUPU)

V_DC (7.5V- 21.0V)

Processor Core Voltage

VTT

GCLKO

GCLKI

HCLK0

PSBAGP Bus

PCLK

PCI Bus

Memory Bus

DCLKO

DCLKWR

SMBUS

VTT

Clock Driver (V_CLK)

PIIX4E/M Sidebands

Pentium III Processor Mobile Module MMC-2

4Datasheet 245304-004

3.0 Signal Information

This section provid es information on the sign al gro ups f or th e Pentium III pro cessor mob ile

module. The signals are defined for compatib ility with future Intel mobile modules.

3.1 Signal Definitions

Table 1 provides a list of signals by category and the corresponding number of signals in each

category. For proper signal termination, please contact your Intel Field Representative for more

information.

Table 1. Connector Signal Summary

Signal Group Number of Pins

Memory 109

AGP 60

PCI 58

Processor/PIIX4E/M Sideband 8

Power Management 7

Clocks 9

Voltage: V_DC 20

Voltage: V_3S 9

Voltage: V_3 16

Voltage: V_5 3

Voltage: VCCAGP 4

Voltage: V_CPUPU 1

Voltage: V_CLK 1

ITP/JTAG 9

Module ID 4

Ground 45

Reserved 37

Total 400

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 5

3.1.1 Signal List

The following notations are used to denote signal type:

I Input pin

O Output pi n

O D Open-drain output pin requiring a pullup resistor

I D Open-drain input pin requiring a pullup resistor

I/O D Input/Open-drain output pin requiring a pullup resistor

I/O Bi-directiona l input/output pin

The signal description also includes the type of buffer used for a particular signal:

GTL+ Open-drain GTL+ interface signal

PCI PCI bus interface signals

AGP AGP bus interface signals

CMOS The CMOS signals, depending on functional group, are 1.5V, 2.5V, or 3.3V.

Pentium III Processor Mobile Module MMC-2

6Datasheet 245304-004

3.1.2 Memory Signal Description

Table 2 provides descriptions of the memory interface signals.

Table 2. Memory Signal Descriptions

Name Type Voltage Description

MECC[7:0] I/O

CMOS V_3 Memory ECC Data: These signals carry Memo ry ECC data during

access to DRAM .

ECC is not supported on th e mobi le m odule.

CSA[5:O]# O

CMOS V_3 Chip Select (SDRAM): These pins activate the SDRAMs. S DRAM

accepts any command when its CS# pin is active low.

DQMA[7:0] O

CMOS V_3 Input/Output Data Mask (SDRAM): These pins act as synchronized

output enables during a read cycle and as a byte mask during a write

cycle.

MAB[9:0]#

MAB[10]

MAB[12:11]#

MAB[13]

CMOS V_3

Memory Address (SDRAM): This is the row and column address for

DRAM. The 82443BX Host Bridge system controller has two identical

sets of address lines (MAA and MAB#). The mobile module supports

only the MAB set of address lines. For additional addressing features,

please refer to the Intel 440BX AGPSet: 82443BX Host Bridge/

Controller Datasheet (Order Number: 290633-001).

MWEA# O

CMOS V_3 Memory Write Enable (SDRAM): MWEA# should be used as the

write enable for the memory data bus.

SRASA# O

CMOS V_3 SDRAM Row Address Strobe (SDRAM): When active low, this

signal latches Row Address on the positive edge of the clock. This

signal also allows Row access and pre-charge.

SCASA# O

CMOS V_3 SDRAM Column Address Strobe (SDRAM): When act ive low, this

signal latches Column Address on the positive edge of the clock. This

signal also allows Column access.

CKE[5:0] O

CMOS V_3 SDRAM Clock Enable (SDRA M): SDRAM clock enable pin. When

these signals are deasserted, SDRAM enters power-down mode.

Each row is individually controlled by its own clock enable.

MD[63:0] O

CMOS V_3 Memory Data: These signals are connected to the DRAM data bus.

They are not terminated on the mobile module.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 7

3.1.3 AGP Signals

Table 3 provides descriptions of the AGP interface signals.

Table 3. AGP Signal Descriptions

Name Type Voltage Description

GAD[31:] I/O

AGP V_3

AGP Address/Dat a: The standard AGP address and data lines. This

bus functions in the same way as the PCI AD[31:0] bus. The address

is driven with FRAME# assertion, and data is driven or received in

following clocks.

GC/BE[3:0]# I/O

AGP V_3

AGP Command/Byte Enable: This bus carries the command

information during AGP cycles when PIPE# is used. During an AGP

write, this bus contains byte enable information. The command is

driven with FRAME# assertion, and byte enables corresponding to

supplied or requested data are driven on the following clocks.

GFRAME# I/O

AGP V_3

AGP Frame: GFRAME# is not used during AGP transactions. This

signal remains deasserted by an internal pullup resistor. Assertion

indicates the address phase of a PCI transfer. Negation indicates that

the cycle initiator desires one more data transfer.

GDEVSEL# I/O

AGP V_3

AGP Device Select: This signal provides the same function as PCI

DEVSEL#, and it is not used during AGP transactions. The 82443BX

Host Bridge system controller drives this signal when a PCI initiator is

attempting to access DRAM. DEVSEL# is asserted at medium

decode time.

GIRDY# I/O

AGP V_3 AGP Initiator Ready: GIRDY# indicates the AGP-compliant target is

ready to provide all write data for the current transaction. This signal

is asserted when the initiator is ready for a data transfer.

GTRDY# I/O

AGP V_3 AGP Target Ready: This signal indicates the AGP-compliant master

is ready to provide all write data for the current transaction. GTRDY#

is asserted when the target is ready for a data transfer.

GSTOP# I/O

AGP V_3 AGP Stop: This signal provides the same function as PCI STOP#,

and it is not used during AGP transactions. GSTOP# is asserted by

the target to request the master to stop the current transaction.

GREQ# I

AGP V_3 AGP Request: AGP master requests for AGP.

GGNT# O

AGP V_3 AGP Grant: GGNT# provides the same function as on PCI.

Additional information is provided on the ST[2:0] bus.

PCI Grant: Permission is given to the master to use PCI.

GPAR I/O

AGP V_3 AGP Parity : A single parity bit is provided over GAD[31:0] and GC/

BE[3:0]. This signal is not used during AGP transactions.

PIPE# I

AGP V_3

Pipelined Request : PIPE# is asserted by the current master to

indicate that a full-width address is to be queued by the target. The

master queues one request each rising clock edge while PIPE# is

asserted.

SBA[7:0] I

AGP V_3 Sideband Address: This bus provides an additional conduit to pass

address and commands to the 82443BX Host Bridge System

Controller from the AGP master.

RBF# I

AGP V_3 Read Buffer Full: Indicates if the master is ready to accept

previously requested, low-priority read data.

Pentium III Processor Mobile Module MMC-2

8Datasheet 245304-004

ST[2:0] O

AGP V_3 Status Bus: This bus provides information from the arbiter to an AGP

Master on what it may do. These bits only have meaning when GGNT

is asserted.

ADSTB[B:A] I/O

AGP V_3 AD Bus Strobes: These signals provide timing for double-clocked

data on the GAD bus. The agent providing data drives these signals,

and the signals are identical copies of each other.

SBSTB I/O

AGP V_3 Sideband Str obe: This signal provides timing for a sideband bus.

The SBA[7:0] (AGP master) drives the sideband strobe.

Table 3. AGP Signal Descriptions

Name Type Voltage Description

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 9

3.1.4 PCI Signals

Table 4 provides descriptions of the PCI signals.

Table 4. PCI Signal Descriptions

Name Type Voltage Description

AD[31:0] I/O

PCI V_3 Address/Data: The standard PCI address and data lines. The

address is driven with FRAME# assertion, and data is driven or

received in the following clocks.

C/BE[3:0] I/O

PCI V_3 Command/Byte Enable: The command is driven with FRAME#

assertion, and byte enables corresponding to supplied or requested

data are driven on the following clocks.

FRAME# I/O

PCI V_3 Frame: Assertion indicates the address phase of a PCI transfer.

Negation indicates that the cycle initiator desires one more data

transfer.

DEVSEL# I/O

PCI V_3 Device Select: The 82443BX Host Bridge drives this signal when a

PCI initiator is attempting to access DRAM. DEVSEL# is asserted at

medium decode time.

IRDY# I/O

PCI V_3 Initiator Ready: Assert ed when the initiator is ready for data transfer.

TRDY# I/O

PCI V_3 Target Ready: A sserted when the target is ready for a data transfer.

STOP# I/O

PCI V_3 Stop: Asserted by the target to request the master to stop the current

transaction.

PLOCK# I/O

PCI V_3

Lock: Indicates an exclusive bus operation and may require multiple

transactions to complete. When LOCK# is asserted, non-exclusive

transactions may proceed. The 82443BX supports lock for CPU

initiated cycles only. PCI initiated locked cycles are not supported.

REQ[4:0]# I

PCI V_3 PCI Request: PCI master requests for PCI.

GNT[4:0]# O

PCI V_3 PCI Grant: Permission is given to the master to use PCI.

PHOLD# I

PCI V_3

PCI Hold: T his signal comes from the expansion bridge. It is the

bridge request for PCI. The 82443BX Host Bridge will drain t he DRAM

write buffers, drain the processor-to-PCI posting buff ers, and acquire

the host bus before granting the request via PHLDA#. These

processes ensure that GAT timing is met for ISA masters. The

PHOLD# protocol has been modified to include support for passive

release.

PHLDA# O

PCI V_3 PCI Hold Acknowled ge: The 82443BX Host Bridge drives this signal

to grant PCI to the expansion bridge. The PHLDA# protocol has been

modified to include support for passive release.

PAR I/O

PCI V_3 Parity: A single parity bit is provided over AD[31:0] and C/BE[3:0]#.

Pentium III Processor Mobile Module MMC-2

10 Datasheet 245304-004

SERR# I/O

PCI V_3

System Error: The 82443BX asserts this signal to indicate an error

condition. For further information, refer to the Intel 440BX AGPSet:

82443BX Host Bridge/Controller Datasheet (Order Numbe r: 290633-

001).

CLKRUN# I/O D

PCI V_3

Clock Run: An open-drain output and input. The 82443BX Host

Bridge requests the central resource, PIIX4E/M, to start or maintain

the PCI clock by asserting CLKRUN#. The 82443BX Host Bridge tri-

states CLKRUN# upon deassertion of Reset (since CLK is running

upon deassertion of Reset).

PCI_RST# I

CMOS V_3 Reset: When asserted, this signal asynchronously resets the

82443BX Host Bridge. The PCI signals also tri-state, compliant with

PCI Revision 2.1 Specifications.

Table 4. PCI Signal Descriptions

Name Type Voltage Description

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 11

3.1.5 Processor and PIIX4E/M Sideband Signals

Table 5 provides descriptions of the processor and PIIX4E/M sideband signals.

NOTE: See Table 8 for V_CPUPU definition.

Table 5. Proc ess or and PIIX4E/M Sideband Signal Descriptions

Name Type Voltage Description

FERR# O D

CMOS V_CPUPU

Numeric Co-processor Error: This signal functions as an FERR#

signal supporting co-processor error s. This signal is tied to the co-

processor error signal on the processor and is pulled active low by the

processor to the PIIX4E/M.

IGNNE# I D

CMOS V_CPUPU Ignore Error: This open-drain signal is connected to the Ignore Error

pin on the processor and is driven by the PIIX4E/M.

INT# I D

CMOS V_CPUPU Initialization: INIT# is asserted by the PIIX4E/M to the processor for

system initialization. This signal is an open-drain.

INTR I D

CMOS V_CPUPU Processor Interrupt: The PIIX4E/M drives INTR to signal the

processor that an interrupt request is pending and needs to be serviced.

This signal is an open-drain.

NMI I D

CMOS V_CPUPU

Non-maskable Interrupt: NMI is used to force a non-maskable

interrupt to the processor. The PIIX4E/M ISA bridge generates an NMI

when either SERR# or IOCHK# is asserted, depending on how the NMI

Status and Control Register is programmed. This signal is an open-

drain.

A20M# I D

CMOS V_CPUPU Address Bit 20 Mask: When enabled, this open-drain signal causes

the processor to emulate the address wraparound at 1 MB, which

occurs on the Intel 8086 processor.

SMI# I D

CMOS V_CPUPU

System Management Interrupt: SMI# is an active-low synchronous

output from the PIIX4E/M that is asserted in response to one of many

enabled hardware or software events. The SMI# open-drain signal can

be an asynchronous input to the processor. Howev er, in this chipset

SMI# is synchronous to PCLK.

STPCLK# I D

CMOS V_CPUPU

Stop Clock: STPCLK# is an active-low , synchronous open-drain output

from the PIIX4E/M that is asserted in response to one of many

hardware or software events. STP CLK# connec ts directly to the

processor and is synchronous to PCICLK. When the processor samples

STPCLK# asserted, it responds by entering a low-power state (Quick

Start). The processor will only exit this mode when this signal is

deasserted.

Pentium III Processor Mobile Module MMC-2

12 Datasheet 245304-004

3.1.6 Power Management Signals

Table 6 provides descriptions of the power management signals. The SM_CLK and SM_DATA

signals refer to the two-wire serial SMBus interface. Although this interface is currently used

solely for the digital thermal sensor, the SMBus contains reserved serial addresses for future use.

NOTE: V_3ALWAYS is a 3.3-V supply. It is generated whenever V_DC is available and supplied to PIIX4E/M

resume well.

Table 6. Power Management Signal Descriptions

Name Type Voltage Description

SUS_STAT1# I

CMOS V_3ALWAYS Suspend St atus: This signal connects to the SUS_STAT1#

output of PIIX4E/M. It provides information on host clock status

and is asserted during all suspend states.

VR_ON I

CMOS V_3

VR_ON: Voltage regulator ON. This 3.3-V (5.0-V tolerant) signal

controls the operation of the voltage regulator. VR_ON should

be generated as a function of the PIIX4E/M SUSB# signal,

which is used for controlling the “Suspend State B” voltage

planes. This signal should be driven by a digital signal with a

rise/fall time of less than or equal to 1 µS. (VIL (max) = 0.4V, VIH

(min) = 3.0V.)

VR_PWRGD O V_3

VR_PWRGD: The mobile module drives this signal high to

indicate that the voltage regulator is stable. The signal is pulled

low using a 100-K resistor when inactive, and it can be used in

some combination to generate the system PWRGOOD signal.

BXPWROK I

CMOS V_3 Power OK t o BX: This signal must go active at least 1 mS after

the V_3 power rail is stable and 1 mS prior to deassertion of

PCIRST#.

SM_CLK I/O D

CMOS V_3 Serial Clock: This clock signal is used on the SMBus interface

to the digital thermal sensor.

SM_DATA I/O D

CMOS V_3 Serial Data: Open-drain data signal on the SMBus interface to

the digital thermal sensor.

ATF_INT# O D

CMOS V_3 ATF Interrupt: This signal is an open-drain output signal of the

digital thermal sensor.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 13

3.1.7 Clock Signals

Table 7 provides descriptions of the clock signals.

Table 7. Clock Signal Descriptions

Name Type Voltage Description

PCLK I

PCI V_3

PCI Clock In : PCLK, an input to the mobile module, is one of the

system’s PCI clocks. All of the 82443BX Host Bridge logic uses this

clock in the PCI clock domain. This clock is stopped when the PIIX4E/

M PCI_STP# signal is asserted and/or during all suspend states.

HCLK0 I

CMOS V_CLK

Host Clock In: This clock is an input to the mobile module from the

CK100-M/CK100-SM clock source. The processor and the 82443BX

Host Bridge system controller use HCLK0. This clock is stopped when

the PIIX4E/M CPU_STP# signal is asserted and/or during all suspend

states.

Note: HCLK0 and BCLK are used interchangeably.

HCLK1 I

CMOS V_CLK Ho st Clo ck In: This clock is an input to the mobile module from the

CK100-M/CK100-SM clock sou rce.

This signal is not implemented on the mobile module.

DCLK0 O

CMOS V_3

SDRAM Clock Out: A 66-MHz SDRA M clock reference generat ed

internally by the 82443BX Host Bridge system controller onboard PLL.

It feeds an external buffer that produces multiple copies for the SO-

DIMMs.

DCLKRD I

CMOS V_3

SDRAM Read Clock: Feedback ref erence f rom the SDRAM clock

buff er. The 82443BX Host Bridge System Controller uses this clock

when reading data from the SDRAM array.

This signal is not implemented on the mobile module.

DCLKWR I

CMOS V_3 SDRAM Write Clock: Feedback reference from the SDRAM clock

buff er. The 82443BX Host Bridge system controller uses this clock

when writing data to the SDRAM array.

GCLKIN I

CMOS V_3 AGP Clock In: The GCLKIN input is a feedback reference from the

GCLKO signal.

GCLKO O

CMOS V_3

AGP Clock Out: T his signal is generated by the 82443BX Host

Bridge system controller onboard PLL from the HCLK0 host clock

reference. The frequency of GCLKO is 66 MHz. The GCLKO output is

used to feed both the PLL reference input pins on the 82443BX Host

Bridge system controller and the AGP device. The board layout must

maintain complete symmetry on loading and trace geometry to

minimize AGP clock skew.

FQS O

CMOS V_3S Frequency Select: This output indicates the desired host clock

frequency for the mobile module.

Pentium III Processor Mobile Module MMC-2

14 Datasheet 245304-004

3.1.8 Voltage Signals

Table 8 provides descriptions of the voltage signals.

Table 8. Voltage Descriptions

Name Type Number

of pins Description

V_DC I 20 DC Input: 7.5V ~ 21.0V

V_3S I 9 SUSB# Controlled 3.3V : Power managed 3.3-V supply. An output

of the voltage regulator on the system electronics. This rail is off

during STR, STD, and Soff.

V_5 I 3 SUSC# Controlled 5.0V : Power managed 5.0-V supply. An output

of the voltage regulator on the system electronics. This rail is off

during STD and Soff.

V_3 I 16 SUSC# Controlled 3.3V : Power managed 3.3-V supply . An output

of the voltage regulator on the system electronics. This rail is off

during STD and Soff.

VCCAGP I 4

AGP I/O Volt a ge: This voltage rail is not implemented on the

mobile module and is defined for upgrade purposes only. Intel

recommends that this voltage rail be connected to V_3 on the

system electronics.

V_CPUPU O 1

Processor I/O Ring: The mobile module drives V_CPUPU to

power processor interface signals, such as the PIIX4E/M open-

drain pullups for the processor and PIIX4E/M sideband signals.

V_CPUPU is tied to 1.5V.

V_CLK O 1 Processor Clock Rail: The mobile module drives V_CLK to power

CK100-M VDDCPU rail.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 15

3.1.9 ITP and JTAG Pins

Table 9 provides des criptions of th e ITP and JTAG signals, which the system manufacturer can use

to implement a JTAG chain and an ITP port if desired.

NOTE: FS_RESET# and FS_PRDY# are pulled up to VTT inside the mobile Pentium III processor core.

3.1.10 Miscellaneous Pins

Table 10 provides descriptions of the miscellaneous signal pins.

Table 9. ITP and JTAG Pins

Name Type Voltage Description

TDO O V_CPUPU JTAG Test Data Out: A serial output port. TAP instructions and data

are shifted out of the processor from this port.

TDI I VTT JTAG Test Data In: A serial input port. TAP instructions and data are

shifted into the processor from this port.

TMS I VTT JTAG Test Mode Select: Controls the TAP controller change

sequence.

TCLK I VTT JTAG Test Clock: Testabilit y clock for clocking the JTAG boundary

scan sequence.

TRST# I VTT JTAG Test Reset: Asynchronously resets the TAP controller in the

processor.

FS_PREQ# I VTT Debug Mode Request: Driven by the ITP – mak es request to enter

debug mode.

FS_PRDY# O VTT Debug Mode Ready: Driven by the processor – informs the ITP that

the processor is in debug mode.

FS_RESET# O VTT Processor Reset: Processor reset status to the ITP.

VTT O VTT GTL+ Termination Voltage: The POWERON pin uses VTT on the

ITP debug port to determine when target system is on. The

POWERON pin is pulled up using a 1-KΩ resistor to VTT. Other ITP

signals might use this power rail for pullup.

Table 10. Miscellaneous Pin Descriptions

Name Type Number Description

Module ID[3:0] O

CMOS 4Module Revision ID: These pins track the revision level of the mobile

module. A 100-K pullup resistor to V_3S must be placed on the system

electronics for these signals. See Section 8.0 for more detail.

Ground I 45 Ground

Reserved RSVD 33 Unallocated Reserved pins.

All Reserved pins must not be connected.

Pentium III Processor Mobile Module MMC-2

16 Datasheet 245304-004

3.2 Connector Pin Assignments

Table 11 lists the signals for each pin of the connector to the system electronics. Refer to Section

3.3 for the pin assign ment s .

Table 11. Connector Pin Assignment

Number Row A Row B Row C Row D Row E

1 SBA5 ADSTBB GND GAD31 SBA7

2 GAD25 GAD24 SBA6 SBA4 SBA0

3 GAD30 GAD29 GAD26 GAD27 GND

4 GND VCCAGP GAD4 GAD6 GDA8

5 RBF# GAD1 GAD3 GAD5 GC/BE0#

6 BXPWROK RESERVED GAD2 ADSTBA GND

7 MD0 MD1 V_3 CLKRUN# GAD7

8 MD2 MD33 GND MD32 MD34

9 MD36 MD4 MD3 MD35 MD34

10 MD7 MD38 MD37 MD6 MD5

11 MD41 MD42 MD40 MD39 MD8

12 MD43 MD11 GND MD10 MD9

13 MD14 MD45 MD44 MD13 MD12

14 MECC4 MECC0 ND15 ND47 ND46

15 SCASA# MWEA# MECC5 RESERVED GND

16 GND MID1 DQMA0 DQMA1 RESERVED

17 V_3 DQMA4 MID0 DQMA5 CSA#

18 CSA1# CSA2# CSA4# CSA3# GND

19 SRASA# CSA5# MAB0# MAB1# RESERVED

20 RESERVED RESERVED MAB2# RESERVED MAB3#

21 RESERVED MAB4# GND RESERVED MAB6#

22 RESERVED RESERVED MAB5# RESERVED MAB7#

23 MAB8# RESERVED RESERVED MSB9# MAB10

24 RESERVED MAB11# MAB12# RESERVED DCLK0

25 MAB13 V_3 GND CKE0 DCLKRD

26 CKE1 MID2 CKE3 CE4 GND

27 CKE5 CKE2 MID3 RESERVED RESERVED#

28 RESERVED RESERVED DQMA2 DCLKWR GND

29 GND VTT RESERVED FS_PREQ# DQMA3

30 FS_RESET# V_3 MD26 GND MD25

31 FS_PRDY# GND MD58 MD57 MD60

32 RESERVED SMCLK TDO TCLK FERR#

33 RESERVED SMDAT TDI TMS IGNNE#

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 17

34 RESERVED FQS RESERVED TRST# ATF_INT#

35 RESERVED V_5 V_3S V_3S V_3S

36 V_CPUPU V_5 V_3S V_3S V_3S

37 V_CLK V_5 V_3S V_3S V_3S

38 RESERVED RESERVED RESERVED RESERVED RESERVED

39 V_DC V_DC V_DC V_DC V_DC

40 V_DC V_DC V_DC V_DC V_DC

Table 11. Connector Pin Assignment

Number Row A Row B Row C Row D Row E

Number Row F Row G Row H Row J Row K

1 GREQ# GND PIP# SBA3 GND

2 ST0 ST1 SBA1 SBSTB GCLKI

3 GGNT# ST2 SBA2 GND CGLK0

4 GAD13 GSTOP# GAD16 GAD20 GAD23

5 GAD12 GPAR GAD18 GAD17 GC/BE3#

6 GAD10 GAD15 GFRAME# GND GAD22

7 GAD11 GC/BE1# GTRDY# GC/BE2# GAD21

8 GAD9 GAD14 GDEVESEL# GIRDY# GAD19

9 GND VCCAGP GND VCCAGP GAD28

10 AD0 AD4 AD2 AD3 AD1

11 GND C/BE0# AD6 GND AD5

12 VCCAGP AD10 AD7 AD8 AD9

13 MECC1 AD13 GND AD12 AD11

14 SERR# PAR AD15 C/BE1# AD14

15 AD16 TRDY# STOP# DEVSEL# PLOCK#

16 AD19 GND AD17 GND AD18

17 AD23 AD30 AD24 C/BE2# AD21

18 AD27 AD22 C/BE3# AD26 PCLK

19 PCI_RST# GND AD20 AD28 GND

20 RESERVED PHOLD# AD31 AD29 AD25

21 IRDY# FRAME# GND REQ1# REQ0#

22 GND GNT2# REQ2# REQ3# GNT3#

23 GNT1# GNT4# GNT0# REQ4# GND

24 GND PHLDA# GND V_3 MD59

25 DQMA6 MECC7 MD50 MD51 MD54

26 MECC2 MD48 MD18 MD52 MD24

Pentium III Processor Mobile Module MMC-2

18 Datasheet 245304-004

3.3 Pin and Pad Assignments

The 400-pin MMC-2 connector has a 1.27-mm pitch and a BGA style surface mount. Refer to

Sectio n 6.1.3 for size information. Figure 2 shows the MMC-2 connector pad assignments.

27 DQMA7 MD16 MD19 GND MD23

28 MECC6 MD17 MD21 MD53 MD55

29 MECC3 MD49 MD20 MD22 MD56

30 MD27 MD28 GND MD62 MD63

31 GND MD29 MD61 MD30 MD31

32 DMI# INTR VR_ON GND GND

33 NMI SUS_STAT1# VR_PWRGD GND HCLK0

34 A20M# STPCLK# INIT# GND GND

35 V_3 V_3 V_3 GND HCLK1

36 V_3 V_3 V_3 GND GND

37 V_3 V_3 V_3 V_3 V_3

38 RESERVED RESERVED RESERVED RESERVED RESERVED

39 V_DC V_DC V_DC V_DC V_DC

40 V_DC V_DC V_DC V_DC V_DC

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 19

Figure 2. MMC-2 Connector Pad Footprint

Table 12 summarizes some of the connector key specifications.

400-Pin Connector Footprint

OEM Pad Assi gnme nts

40 1

Table 12. Connector Specifications

Parameter Condition Specification

Material Contact Copper Alloy

Housing Thermo-Plastic Molded Compound: LCP

Electrical

Current 0.5A

Voltage 50 VAC

Insulation Resistance 100 MΩ

Termination Resistance 20-mΩ maximum at 20-mV open circuit with 10 mA

Capacitance 5-pF maximum per contact

Mechanical

Mating Cycles 50 Cycles

Connector Mating Force 50 lbs (22.7 kg) maximum

Contact Unmating Force 30 lbs (13.6 kg) maximum

Pentium III Processor Mobile Module MMC-2

20 Datasheet 245304-004

4.0 Functional Description

4.1 P entium III Processor Mobile Module MMC-2

The mobile Pentium III processor core runs at speeds of 450 MHz and 500 MHz with a 100-MHz

PSB.

4.2 L2 Cache

The on-die L2 cache has 256 KB, is eight-way set associative, and runs at the speed of the

processor core.

4.3 The 82443BX Host Bridge System Controller

Intel’s 82443BX Host Bridge system controller is a highly integrated device that combines the bus

controller, the DRAM controller, and the PCI bus controller into one component. The 82443BX

Host Bridge has multiple power management features designed specifically for notebook systems

such as:

•CLKRUN#, a feature that enables controlling of the PCI clock on or off.

•The 82443B X Hos t B ri dge su spend mod e s, w hic h i nclude Suspend - To-RAM (STR), Suspend-

To-Disk (STD), and Power-On-Suspend (POS).

•System Managemen t RAM (S MRA M) p ower management mo des , w hich includ e C ompa tib le

SMRAM (C_S MRAM) and Extended SMRAM (E_SMRAM). C_SM RAM is the traditional

SMRAM feature implemented in all Intel PCI chipsets. E_SMRAM is a new feature that

supports write-back cacheable SMRAM space up to 1 MB. To minimize power consumption

while the system is idle, the internal 82443BX Host Bridge clock is turned off (gated off) when

there is no processor and PCI activity. Thi s is accompli shed by setting the G_CLK enable bit

in the power management register in the 82443BX through the system BIOS.

4.3.1 Memory Organization

The memory interface of the 82443BX Host Bridge is available at connector. This allows for the

following:

•One set of memory control sign als, suf ficien t to support up to three SO-DIM M sockets and six

banks of SDRAM at 100 MHz.

•One CKE signal for each bank.

Memory features not supported by the 82443BX Host Bridge system controller standard MMC-2

mode are:

•Eight banks of memory

•256-Mb memory devices

•Second set of memory address lines (MAA[13:0])

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 21

•Extended Data Out (EDO) DRAM

•66-MHz memory bus

The clocking architecture supp orts the use of SDRAM. The clock ing mod e for 100- MHz SDRAM

memory confi gurations allows all host and SDRA M clocks to be generate d from the same cloc king

source on the sys tem electroni cs. For comp lete detai ls about memo ry device supp ort, or g anizati on,

size, and addressing when using SDRAM memory and trace length guidelines, refer to the Intel®

Pentium® III Processor Mobile Module System Electronics 100-MHz Layout Guidelines Revision.

1.0 (OR-1780).

4.3.2 Reset Strap Options

Several strap options on the memory address bus define the behavior of the Pentium III processor

mobile module after reset. Other straps are allowed to override the default settings. Table 13 shows

the various straps and their implementation.

4.3.3 PCI Interface

The PCI interface of the 82443BX Host Bridge is available at the MMC-2 connector. The

82443BX Hos t B ri dge su pports the P CI Cl o c kru n p rot oco l for P CI bus p ow er manageme nt. In this

protocol, PCI devices assert the C LKRUN# open-drain s ignal when they req uire the use of the PCI

interface. Refer to the PCI Mobile Design Gu ide for complete details on the PCI Clockrun

protocol.

The 82443BX Host Bridge is responsible for arbitrating the PCI bus. The 82443BX Host Bridge

can support up to five PCI bus masters. There are five PCI Request/Grant pairs (REQ[4:0]# and

GNT[4:0]#) available on the connector to the system electronics.

Note: The PCI interface on the MMC-2 connector is 3.3V only. PCI devices that are 5.0V are not

supported.

The 82443BX Host Bridge system controller is compliant with the PCI 2.1 Specification , whi ch

improves the worst case PCI bus access latency from earlier PCI specifications. The 82443BX

Host Bridge supports only Mechanism #1 for accessing PCI configuration space. This implies that

signals AD[31:11] are available for PCI IDSEL sign als. Ho wever, since the 82443BX Hos t Bridg e

Table 13. Configuration Straps for the 82443BX Host Bridge System Controller

Signal Functio n Module Default Setting Optional Override on

System Electronics

MAB[12]# Host Frequency Select Strapped high on the module for 100

MHz None

MAB[11]# In Order Queue Depth No strap, maximum queue depth is set

at 8 None

MAB[10]# Quick Start Select S trapped high on the module for Quick

Start mode None

MAB[9]# AGP Disable No strap (AGP is enabled) Strap high to disable AGP

MAB[7]# MM Configuration No strap (standard MMC-2 mode) None

MAB[6]# Host Bus Buffer Mode

Select Strapped high on the module for

mobile PSB buffers None

Pentium III Processor Mobile Module MMC-2

22 Datasheet 245304-004

is always device #0, AD11 will never be asserted during PCI configuration cycles as an IDSEL.

The 82443BX reserves AD12 for the AGPbus. Thus , AD13 is the first available address line us able

as an IDSEL. Intel recommends that AD18 be used by the PIIX4E/M.

4.3.4 AGP Interface

The 82443BX Host Bridge s ystem controll er is comp liant with the AGP Interface Specification

Revision 2.0, which supports an asynchronous AGP interface coupling to the 82443BX core

frequency. The AGP interface can achieve real data throughput in excess of 500 MB per second

using an AGP 2X graphics device. Actual bandwidth may vary depending on specific hardware

and software implementations.

4.4 Power Management

4.4.1 Clock Control Arch itec ture

The clock control architecture has been optimized for notebook designs. The clock control

architecture consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start,

HALT/Grant Snoop, Sleep, and Deep Sleep s tates. The Auto Halt s tate provides a low-power clock

state that can be controlled throug h the s of tware execution of the HLT instruction. The Quick Start

state provides a very low-power, low-exit latency clock state that can be used for hardware

controlled "idle" states. The Deep Sleep state provides an extremely low-power state that can be

used for Power-On-Suspend states, which is an alternative to shutting off the processor’s power.

The exit latency of the Deep Sleep state is 30 µS in the mobile module. The Stop Grant state and

the Quick S tart clock s tate are mu tually ex clusiv e. For ex ample, a st rap ping option on sign al A15#

chooses which state is entered when th e STPCLK# signal is asserted. S trap ping the A15# signal to

ground at Reset enables the Quick Start state. Otherwise, asserting the STPCLK# signal puts the

processor into the Stop Grant state.

Table 14 provides information on the clock control states and Figure 3 illustrates the clock control

architecture. Performing state transitions not shown in Figure 3 are neither recommended nor

supported.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 23

Table 14. Clock State Characteristics

NOTES:

1. Intel mobile modules do not support the Sleep and Stop Grant clock states.

2. These values are not 100% tested and are specified at 50°C by design and characterization.

3. This value is not 100% tested and is specified at 35°C by design and characterization.

4. Specification labeled N/A are not available.

Clock State Exit Latency Snooping System Uses Notes

Normal N/A Yes Normal program execution Note 4

Auto Halt Approximately 10 bus clocks Yes Software controlled entry idle

mode Note 2

Stop Grant 10 bus clocks Yes Har dware controlled entry/ exit

mobile throttling Note 1

Quick St a r t

Through Snoop, to HALT/Grant

Snoop state: immediate

Through STPCLK#, to Normal state:

10 bus clocks

Yes Har dware controlled entry/ exit

mobile throttling Note 2

HALT/Grant

Snoop A few bus clocks after the end of

snoop activity Yes Supports snooping in the low-

power states

Sleep To Stop Grant state 10 bus clocks No Hardware controlled entry/exit

desktop idle mode support Note 1

Deep Sleep 30 µSNo

Hardware controlled entry/exit

mobile POS support Note 3

Pentium III Processor Mobile Module MMC-2

24 Datasheet 245304-004

Figure 3. Clock Control States

4.4.1.1 Normal State

The Normal states is the normal operating mode where the processor’s cor e clock is running, and

the processor is actively executing instructions.

4.4.1.2 Auto Halt S tate

This is a low-power mode entered by the process or throu gh the execu tion o f the HLT instruction.

The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is

made by a halt break event (one of th e following signals go ing active: NMI, INTR, BINIT#, INIT#,

RESET#, FLUSH#, or SMI#).

HALT/Grant

Snoop

Normal

State

HS=false

Stop

Grant

Auto

Halt

HS=true

Quick

Start

Sleep

Deep

Sleep

(!STPCLK#

and !HS) or

stop break

STP CLK # an d

!QSE an d SGA

Snoop

occurs

Snoop

serviced

STP CLK # an d

QSE and SGA

(!STPCLK# and !HS)

or RESET#

Snoop

serviced Snoop

occurs

!STPCLK#

and HS

STPCLK# and

!QSE and SGA

HLT and

halt bus cycle

halt

break

Snoop

serviced

Snoop

occurs

STPCLK# and

QS E an d SGA

!STPCLK#

and HS

!SLP # or

RESET#

SLP# BCLK

stopped

BCLK on

and !QSE

BCLK

stopped

BCLK on

and QSE

NOTES: Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#

HLT – HLT instr uction executed

HS – Proces so r Halt St ate

QSE – Quick Sta rt S t at e Enab led

SGA – Stop Grant Ac kn owledge bus cy c le is sued

Sto p br ea k – BINIT#, FLUSH#, RESET#

Intel mobile modules do not support shaded clock control states

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 25

Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to

the Stop Grant state or the Quick Start state, where a Stop Grant Acknowledge bus cycle will be

issued. Deassertin g STP CLK# will cause the processor to return to the Auto H alt state without

issuing a new Halt bus cycle.

The SMI# (System Management Interrupt) is recognized in the Auto Halt state. The return from the

SMI handler can be to either the Normal state or the Auto Halt state. See the Intel® Architect ure

Software Developer's Manual, Vo lume III: System Programmer's Guide for more information. No

Halt bus cycle is issued when returning to the Auto Halt state from System Management Mode

(SMM).

The FLUSH# signal is ser viced in the Auto Halt state. After flushing the on-chip, the pr oces so r

will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in the A20M# and

PREQ# signals are recognized while in the Auto Halt state.

4.4.1.3 Stop Grant State

Intel mobile modules do not supp ort th e Stop Grant state.

In desktop systems, the processor enters this mode with the as sertion of the STPCLK# signal when

it is configured for Stop Grant state (via the A15# strapping opti on) . The processo r is still able to

respond to snoop request s and latch int erru pt s. Latched int errupts will be serviced when the

processor returns to the Normal state. Only one occurrence of each interrupt event will be latched.

A transition back to the Normal state can b e made by the deass ertion of the STPCLK# s ignal, or the

occurrence of a stop break event (a BINIT#, FLUSH#, or RESET# assertion).

The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization

unless STPCLK# has been deasserted. RESET# assertion will cause the processor to immediately

initialize itself. Howe ver, the processor will stay in the Stop Grant state after initialization until

STPCLK# is deasserted. If th e FLUSH# signal is asserted, the pro cesso r w ill f lush the on-chip

caches and return to the Stop Grant state. A transition to the Sleep state can be made by the

assertion of the SLP# signal.

While in the Stop Grant state, assertions of SMI#, INIT#, INTR, and NMI (or LINT[1:0]) will be

latched by the processor . These latched events will not be serviced until the processor returns to the

Normal state. Only one of each event will be recognized upon return to the Normal state.

4.4.1.4 Quick Start State

This is a mode entered by the process or with the assertion of the STPCLK# signal when it is

configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the

processor is only capable of acting on snoop transactions generated by the PSB priority device.

Because of its snooping behavior, Quick Start can only be used in single processor configurations.

A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A

transition back to the Normal state (from the Quick S tart state) is made only if the STPCLK# signal

is deasserted.

While in this state the processor is limited in its ability to respond to input. It is incapable of

latching any i n t errup t s, s ervi cing s no op transact ions from symmetric b us mast ers , or respon ding to

FLUSH# and BINIT# assertions. In the Quick Start state, the processor will not respond properly to

any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal changes, then

the behavio r of the pro cessor wi ll be unpr edictable. No serial int errupt mess ages may begin or be in

progress while the processor is in the Quick Start state.

Pentium III Processor Mobile Module MMC-2

26 Datasheet 245304-004

RESET# assertion will cause the processor to imme diat ely initialize itself, but the processor will

stay in the Quick Start state after initialization until STPCLK# is deasserted.

4.4.1.5 HALT/Grant Snoop State

The processor will respond to snoop transactions on the PSB while in the Auto Halt, Stop Grant, or

Quick S tart state. When a snoop transaction is presented o n the sys tem bus , the p rocessor will enter

the HALT/Grant Snoop state. The processor w ill r emain in this state until the snoop has b een

serviced and the PSB is quiet. After the snoop has been serviced, the processor will return to its

previous state. If the HALT/Grant Snoop state is entered from the Quick Start state, then the input

signal restrictions o f the Quick Start state still apply in th e HALT/Grant Snoop state ( except for

those signal transitions that are required to perform the snoop).

4.4.1.6 Sleep State

Intel mobile mo dules do not support the Sleep state.

In desktop systems, the Sleep state is a very low-power state in which the processor maintains its

context and the phase locked loop (PLL) maintains phase lock. The Sleep state can only be entered

from the Stop Grant state. After entering the Stop Grant state the SLP# signal can be asserted,

causing the processor to enter the Sleep state. The SLP# signal is not recognized in the Normal

state or the Auto Halt state.

The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven

active while the processor is in the Sleep state, then SLP# and STPCLK# must immediately be

driven inactive to ensu r e that the pro cessor correctly initializes itself.

Input signals (other than RESET#) may not change while the processor is in or transitioning into or

out of the Sleep state. Input signal changes at these ti mes will cause unpredictable behavior. Thus,

the processor is incapable of snooping or latching any events in the Sleep state.

While in the Sleep state the processor can enter its lowest power state, the Deep Sleep state.

Removing the proces so r’s input clock puts the processor in the Deep Sleep state. PICCLK may be

removed in the Sleep state.

4.4.1.7 Deep Sleep State

The Deep Sleep state is the lowest power mode the processor can enter while maintaining its

context. Stopping the BCLK input to the processor enters the Deep Sleep state, while it is in the

Sleep state or t h e Q uick Start st at e. Fo r pr oper operat ion, t h e BCL K in put s hou l d be st op ped i n the

low state.

The processor will return to the Sleep state or the Quick Start state from the Deep Sleep state when

the BCLK input is restarted. Due to the PLL lock latency, there is a 30-µS delay after the clocks

have started before this state transition happens. PICCLK may be removed in the Deep Sleep state.

PICCLK should be designed to turn on when BCLK turns on when transitioning out of the Deep

Sleep state.

The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except that

RESET# assertion will result in unpredictable behavior.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 27

4.5 Power Consumption in Power Management Mode

The power data is broken down into each power rail. Each power rail is supplied to the module

through the MMC-2 connector. The total power values are based on typical power consumption.

The data is captured at Tamb = 25°C, T TTP = 25 °C, and V_DC = 18.0V.

Note: All power comumption values are not 100% tested and have been characterized by design.

Table 15 and Table 16 provide the module power consumption values in various power

management modes. Because mobile modules with the same frequencies may have different

printed circuit board (PCB) revisions, refer to the product tracking code (PTC) lists before each

table below to match the correct power consumptio n inf ormation with the correct mobile module.

Table 15 applies to mobile modules with the following PTCs.

•PML50002001AB

•PML45002001AB

•PML50002201AC

•PML45002201AC

Table 15. Power Consumption Values I

NOTE: These power values should be used as power supply guidelines for power management modes. They

have some guardband added for design margin. Therefore, the total power does not necessarily add up

as the sum of each power rail. "Total Power" is the sum of the individual "raw" power requirements with

guardband added.

Table 16 applies to mobile modules with the following PTCs.

•PML50002101AA

•PML45002101AA

Table 16. Power Consumption Values II

NOTE: These power values should be used as power supply guidelines for power management modes. They

have some guardband added for design margin. Therefore, the total power does not necessarily add up

as the sum of each power rail. "Total Power" is the sum of the individual "raw" power requirements with

guardband added.

State V_DC V_5 V_3 V_3S Total Power

Auto Halt 2.19W 0.08W 2.27W 0.57W 4.17W

Quick Start 1.77W 0.08W 2.04W 0.62W 3.43W

Deep Sleep 1.29W 0.08W 0.24W 0.45W 1.35W

STR 0.04W 0.01W 0.01W 0.00W 0.05W

State V_DC V_5 V_3 V_3S Total Power

Auto Halt 2.19W 0.08W 2.27W 0.57W 4.17W

Quick Start 1.77W 0.08W 2.04W 0.62W 3.43W

Deep Sleep 1.29W 0.08W 0.24W 0.45W 1.35W

STR 0.04W 0.01W 0.01W 0.00W 0.05W

Pentium III Processor Mobile Module MMC-2

28 Datasheet 245304-004

5.0 Electrical Specifications

The following section provides the electrical specifications for the Pentium III processor mobile

module.

5.1 System Bus Clock Signal Quality Specifications

The HCLK0 and BCLK signal names are used interchangeably.

5.1.1 BCLK DC Specifications

NOTE: VILX,min and VIH,max only apply when BCLK is stopped. BCLK should be stopped in the low state. See

Table 18 for the BCLK voltage range specifications when BCLK is running.

5.1.2 BCLK AC Specifications

NOTES:

1. All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V. All CMOS

signals are referenced at 0.75V.

2. The internal core clock frequency is derived from the PSB clock . The PSB clock to core clock ratio is

determined during initialization and is predetermined by the Intel mobile module. The BCLK period allows a

+0.5 nS tolerance for clock driver variation.

3. This value is measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted

for as a component of BCLK skew between devices.

4. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the

jitter created by the clock driver. The -20.0 dB attenuation point, as measured into a 10.0-pF to a 2.0-pF load,

should be less than 500 kHz. This specification may be ensured by design characterization and/or measured

with a spectrum analyzer. See the CK97 Clock Synthesizer/Driver Specification (OR-1089) for further details.

5. These values are not 100% tested and are specified by design characterization as a clock driver

requirement.

6. Specifications labeled N/A are not available.

Table 17. BCLK DC Specifications

Symbol Parameter Min Max Unit

VIL,BCLK Input Low Volt age, BCLK - 0.3 0.5 V

VIH,BCLK Input High Voltage, BCLK 2.0 2.625 V

Table 18. BCLK AC Specifications at the Processor Core Pins

T# Parameter Min Nom Max Unit Note

System Bus Frequency N/A 100.0 N/A MHz Notes 5, 6

BCLK Period N/A 10. 0 N/A nS Notes 2, 5, 6

BCLK Period Stability N/A N/A ± 250 pS Notes 3, 4, 5, 6

T3: B CLK High Time 2.85 N/A N/A nS At > 1.7V, Notes 5, 6

T4: B CLK Low Time 2.55 N/A N/A nS A t > 0.7V, Notes 5, 6

T5: B CLK Rise Time 0.175 N/A 0.875 nS 0.9V ~ 1.6V, Notes 5, 6

T6: B CLK Fall Time 0.175 N/A 0.875 nS 1.6V ~ 0.9V, Notes 5, 6

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 29

Table 19 describes the signal quality specifications at the processor core for the PSB clock (BCLK)

signal. Figure 4 describes the signal quality wavef orms for the PSB clock at the processor core p ins

For proper signa l ter mination, refer to the “Clocking Guidelines” section in the Mobile Pentium

III Pr ocessor/4 40BX AGPset Recommen ded Design and D ebug Practi ces (RDDP-A) 100 MH z Rev.

2.0 (SC-2760).

NOTES:

1. On the rising edge of BCLK, there must be a minimum overshoot to 2.0V. The clock must rise monotonically

between VIL,BCLK and 2.0V and fall monotonically between VIH,BCLK and VIL,BCLK.

2. These specifications apply only when BCLK is running. See Table 17 for the DC specifications when BCLK is

stopped. BCLK may not be above VIH,BCLK,MAX or below VIL,BCLK,MIN for more than 50% of the clock cycle.

3. The rising edge ringback voltage specified is the minimum (rising) absolute voltage that the BCLK signal can

dip back to after it passes the VIH,BCLK,MIN (rising) voltage limits.The falling edge ringback voltage specified

is the maximum (falling) absolute voltage that the BCLK signal can dip back to after it passes the

VIL,BCLK,MAX (falling) voltage limits.

4. Specifications labeled N/A are not available.

Figure 4. BCLK Waveform at the Processor Core Pins

Table 19. BCLK Signal Quality AC Specifications at the Processor Core

T# Parameter Min Max Unit Notes

V1 VIL,BCLK -0.3 0.7 V Notes 1, 4

V2 VIH,BCLK 1.7 2.625 V Notes 1, 4

V3 VIN Absolute Voltage Range -0.7 3.5 V Undershoot, Overshoot, Note 2

V4 Rising Edge Ringback 1.7 N/A V Absolute Value, Notes 3, 4

V5 Falling Edge Ringback N/A 0.7 V Absolute Value, Notes 3, 4

BCLK Rising/Falling Slew Rate 0.8 4.0 V/nS

V1MAX

V3MAX

V2MIN

V3MIN

V0012-00

T6 T4 T5

Pentium III Processor Mobile Module MMC-2

30 Datasheet 245304-004

5.2 System Power Requirements

Table 20 provides the DC power supply design criteria.

NOTES:

1. V_DC is set for 12.0V in order to determine typical V_DC current.

2. V_DC is set for 7.5V in order to determine maximum V_DC current.

3. A 20-µS duration.

4. This is V_DC dependent. See Figure 7 for data of IDC-RMS vs. V_DC.

5. These values are system dependent.

6. Specifications labeled N/A are not applicable.

5.3 Processor Core Voltage Regulation

The DC voltage regulator (DC/DC converter) supports the core voltage and I/O ring voltage. The

DC voltage regulator provides the appropriate processor core voltage, the GTL+ bus termination

voltage, th e process or si deban d sig nal pul lup vol tage, and the clock driver buffer vol tage. O f thes e

voltages, only the processor sideband pullup voltage (V_CPUPU) and the clock driver buffer

voltage (V_CLK) are delivered to the system electronics.

The DC voltage range is 7.5V ~ 21.0V from the system battery or power supply for mobile

applications.

5.3.1 Voltage Regulator Efficiency

There are three voltage regulators on the mobile module. These vol tage regu lato rs generate the

core voltage used by the CPU and the voltage for the CPU I/O ring voltage. The core voltage

regulator provides the required current from the V_DC supply and its relative efficiencies are

shown in Table 21 and Figure 5. The V_CLK and Vtt voltage regulators tap the V_3 plane.

Table 20. System Power Requirements

Symbol Parameter Min Nom Max Unit Notes

VDC DC Input Voltage 7.5 12.0 21.0 V

IDC DC Input Current 0.1 2.6 5.0 A Notes 1, 2

IDC_RMS RMS Ripple Current N/A N/A 7.5 A Note s 4, 6

IDC_Surge Maximum Surge Current for VDC N/A N/A 20.0 A Notes 3, 6

V5Power Managed 5.0-V Supply 4.75 5.0 5.25 V

I5Power Managed 5.0-V Current, Operating 20.0 50.0 100.0 mA

I5_Surge Maximum Surge Current for V5N/A N/A 1.5 A Notes 3, 6

V3Power Managed 3.3-V Supply 3.135 3.3 3.465 V

I3Power Managed 3.3-V Current 0.8 1.2 3.0 A

I3_Surge Maximum Surge Current for V3N/A N/A 4.0 A Notes 3, 6

VCPUPU Processor I/O Ring Voltage 1.375 1.5 1.625 V

ICPUPU Processor I/O Ring Current 0.0 10.0 20.0 mA

VCLK Processor Clock Rail Voltage 2.375 2.5 2.625 V

ICLK Processor Clock Rail Current 24.0 35.0 80.0 mA Note 5

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 31

Table 21. Vcore Power Conversion Efficiency

Figure 5. VR Efficiency Chart

Vcore

Icore

(A) Efficiency at

V_DC + 7.50V Efficiency at

V_DC + 12.0V Efficiency at

V_DC + 21.0V

1 77% 71% 63%

2 85% 82% 78%

3 87% 85% 81%

4 87% 86% 82%

5 86% 86% 83%

6 85% 85% 83%

7 84% 84% 82%

8 83% 83% 81%

9 81% 82% 81%

10 80% 81% 80%

11 79% 80% 79%

VR Eff ici ency

60%

62%

64%

66%

68%

70%

72%

74%

76%

78%

80%

82%

84%

86%

88%

90%

1234567891011

Icore(A)

Efficiency(%)

V_DC = 7.5V

V_DC = 12V

V_DC = 21V

Pentium III Processor Mobile Module MMC-2

32 Datasheet 245304-004

5.3.2 Voltage Regulator Control

The VR_ON pin on the connector allows a 3.3-V signal to control the voltage regulator. The

system manufacturer can use this signal to turn the voltage regulator on or off. VR_ON should be

controlled as a function of the same signal (SUSB#) used to control the system’s switched 5.0 -V

and 3.3-V power planes. The PIIX4E/M defines Suspend B as the Power Management state in

which power is physically removed from the processor and the voltage regulator. In this state, the

SUSB# pin on the PIIX4E/M controls these power planes. The mobile module provides the

VR_PWRGD signal, which indicates that the voltage regulator power is operating at a stable

voltage level. The system manufacturer should use this signal on the system electronics to control

power inputs and to gate PWROK to the PIIX4E/M South Bridge. Table 22 provides the detailed

definitions and sequences of the voltage signals.

The following list includes additional specifications and clarifications of the power sequence

timing and Figure 6 provides an illustration.

1. The VR_ON signal may only be asserted to a logical high by a digital signal after V_DC ≥

7.5V, V_5 ≥ 4.5V, and V_3 ≥ 3.0V.

Table 22. Volt age Signal Definitions and Sequences

Signal Source Definitions and Sequences

V_DC System Electronics

V_DC is required to be between 7.5V and 21.0V DC and is driven by

the system electronics’ power supply. V_DC powers the Pentium III

processor mobile mo dule DC-to-DC converter for the processor core

and I/O voltages.

The mobile module cannot be hot inserte d or removed while

V_DC is powered on.

V_5 System Electronics V_5 is supplied by the system electronics for the voltage regulator.

V_3 System Electronics V_3 is supplied by the system electronics for the 82443BX and powers

the mobile module’s linear regulators for generating the V_CLK and

V_CPUPU voltage rails. It stays on during suspend.

V_3S System Electronics V_3S is supplied by the system electronics, and V_3S is shut off

during suspend.

VR_ON System Electronics

VR_ON is a 3.3-V signal that enables the voltage regulator circuit.

When driven active high, the voltage regulator circuit is activated. The

signal driving VR_ON should be a digital signal with a rise and fall time

of less than or equal to 1 µS. (VIL (max)= 0.4V, VIH (min)= 3.0V.)

V_CORE Module A result of VR_ON being asserted, V_CORE is an output of the DC-

DC regulator on the mobile module and is driven to the core voltage of

the processor .

VR_PWRGD Module

Upon sampling the voltage level of V_CORE (minus tolerances for

ripple), VR_PWRGD is driven active high. If VR_PWRGD is not

sampled active within 1 second of the assertion of VR_ON, then the

system electronics should deasser t VR_ON. After V_CO RE is

stabilized, VR_PWRGD will assert to logic high (3.3V). This signal

must not be pulled up by the system electronics. VR_PWRGD should

be "logically ANDed" with V_3S to generate the PIIX4E/M input signal,

PWROK. The system electronics should monitor VR_PWRGD to verify

that it is asserted high prior to the active high assertion of PIIX4E/M

PWROK.

V_CPUPU Module V_CPUPU is 1.5V. The system electronics uses this voltage to power

the PIIX4E/M-to-proces sor interface circuit ry.

V_CLK Module V_CLK is 2.5V. The system electronics uses this voltage to power the

HCLK[0:1] drivers for the processor clock.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 33

2. The Rise Time and Fall Time of VR_ON must be less than or equal to 1.0 µS.

3. VR_ON has its VIL (max ) = +0.4V and VIH (min) = +3.0V.

4. The VR_PWRGD will get asserted to logi c high (3.3V) after V_ CORE is stabilized and V_DC

reaches 7.5V. This signal should not and can not be pulled up by the system electronics.

5. In the power-on process, Intel recommends to raise the higher voltage power plane first

(V_DC), followed by the lower power planes (V_5, V_3), and finally assert VR_ON after

above voltage levels are met on all rails. For powering off, follow the reverse process, i.e.

VR_ON gets deasserted, followed by the lower power planes, and finally the higher power

planes.

6. VR_ON must monotonically rise through its VIL to VIH and fal l t hrough it s V IH to VIL points.

The sign of slope can not change between VIL and VIH in rising and VIH and VIL in falling.

7. VR_ON must provide an instantaneous in-rush current to the mo bile mo dule with the

following values as listed in Table 23.

8. VR_ON Valid-Low Time specifies how long VR_ON needs to be low for a valid off, before

VR_ON can be turned back on again. In going from a valid on to off and then back on, the

following conditions must be met to prevent damage to the OEM syst em or the mobile

module:

•VR_ON must be low for 1.0 mS.

•The original voltage level req uirements for turn-on must be met before assertio n of

VR_ON (i.e. V_DC ≥ 7.5V, V_5 ≥ 4.5V, and V_3 ≥ 3.0V ).

Table 23. VR_ON In-rush Current

Instan taneous DC Operating

Maximum 41.0 mA 0.1 µA

Typical 0.2 mA 0.0 µA

Pentium III Processor Mobile Module MMC-2

34 Datasheet 245304-004

Figure 6. Power Sequence Timing

5.3.3 Power Planes: Bulk Capacitance Requirements

The placement of sufficient bulk capacitance on the system electronics board is critical to the

operation of the mobile mo dule and to ens ure tha t the sys tem des ign can accommo date fu tu re high

frequency modules. Intel has pro vided the maximum possible bulk capacitance on the mobile

module. However, in order to achieve proper filtering and in-rush current protection, it is

imperative that add itional filtering be provided on the system electronics board. Table 24 details

the bulk capacitance requirements for the system electronics.

Note: Observe the voltage rating requirement for the capacitors on each respective voltage rail.

NOTES:

1. PWROK on I/O board should be active on when VR_PWRGD is active and V_3S is good.

2. CPU_RST from I/O board should be active for a minimum of 6.0 mS after PWROK is active and PLL_STP# and CPU_STP# are inactive.

Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4E/M.

3. This is the 5V power supplied to the MMC-2 connector. This should be the first 5.0-V plane to power up. Stays on du ring suspend.

4. V_DC >= 7.5V, V_5>=4.5V, V_3S>=3.0V.

5. VR_PWRGD is specified active by the module regulator within less than or equal to 6.0-mS maximum after the assertion of VR_ON.

6. V_CPUPU and V_CLK are generated on the mobile module.

V_CPUPU

V_CLK

NOTE 6

VR_PWRGD

V_DC

V_3

V_5

V_3S

VR_ON NOTE 4

0 MS MIN

NOTE 3

0 MS MIN

NOTE 5 0 MS MIN

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 35

Table 24 details the bulk capacitance requirements for the system electronics.

Table 24. Bulk Capacitance Requirements

NOTES:

1. Placement of above capacitance requirements should be located near the connector.

2. V_CLK filtering should be located next to the system clock synthesizer.

3. The Ripple current specification depends on the V_DC input for the mobile module. See Figure 7 below.

4. If Tantalum* Capacitors are used, a 50% voltage derating practice must be observed. For example, a 5.0-V

rail requires a 10.0-V rated capacitor.

5. In order to reduce ESR, Intel recommends the use of multiple bulk capacitors rather than a single large

capacitor.

6. Intel strongly recommends that system manufacturers pay close attention to capacitor design considerations.

Specifically, the "Capacitance vs. Temperature De-rating Curve," "Capacitance vs. Applied DC Voltage De-

rating Curve," and the "Capacitance vs. Frequency De-rating Curve." Some capacitor dielectrics are

particularly susceptible to these conditions, for example Y5V ceramic capacitors.

7. Specifications labeled N/A are not available.

Power

Plane

Bulk Capacitance Requirements High Frequency Capacitance

Requirements Notes

Total

Capacitance ESR

Max RMS Ripple

Current

V_DC 100.0 µF 20.0 mΩ 3.0A~ 5.0A 0.1 µF, 0.01 µF Not es 1,3,4,5,6

V_5 100.0 µF 100.0 mΩ1.0A 0.1 µF, 0.01 µF Notes 1,4,5,6

V_3 470.0 µF 100.0 mΩ1.0A 0.1 µF, 0.01 µF Notes 1,4,5,6

V_3S 100.0 µF 100.0 mΩN/A 0.1 µF 0.01 µF Notes 1,4,5,6

VCC_AGP 22.0 µF 100.0 mΩ1.0A 0.1 µF, 0.01 µF Notes 1,4,5,6

V_CPUPU 2.2 µF N/A N/A 8200.0 pF Notes 1,5,6,7

V_CLK 10. 0 µF N/A N/A 8200.0 pF Notes 1,2,5,6,7

Pentium III Processor Mobile Module MMC-2

36 Datasheet 245304-004

Figure 7 shows the dependence of V_DC ripple current on V_DC.

Figure 7. V_DC Ripple Current

5.3.4 System Power Supply Protection Guidelines

5.3.4.1 DC Power System Protection

The recommended DC Power System Protection consists of the following:

•A DC Power Supply capable of delivering 7.5V to 21.0V to the mobile module

•An Overcurrent Protection circu it providing a mean s to limit the maximum current available to

the system

•A Slew Rate Control circuit providing a controlled voltage slew rate at turn on, which provides

protection for compo nents sensitive to fast voltag e rise times

•An Undervoltage Lockout circuit to protect against potentially damaging high currents, which

might be encountered if the DC Power Supply voltage is too low

•An Overvoltage Lockout circuit providing protection from potentially damaging high DC

Power Supply voltages

• Bulk Decoupling Capacitors prov iding filtering and a res ervoir of ener gy that can give a faster

transient response than the power supply

V_DC I nput Ri ppl e Curr ent vs. V_DC Vol t age

5.32

5.09

4.86

4.64

4.45

4.28

4.12

3.98

3.85

3.73

3.62

3.52

3.43

3.35

3.27

3.19

3.12

0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

5.50

6.00

7 8 9 101112131415161718192021

V_DC(V)

Input Rippl e Current ( A )

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 37

Figure 8. V_DC Power System Protection Block Diagram

5.3.4.2 V_DC Power Supply

The power supply must be able to deliver 7.5V to 21.0V to the mobile module, measured at the

mobile mod ule .

5.3.4.3 Overcurrent Protection

The overcurrent protection circuit provides a way to limit current drawn by the mobile module.

Under normal op erating cond itio ns, I_DC s hou ld no t be ex pected to exceed 3.0A at V_ DC = 7 .5V.

To allow for component variations and margining issues, a reasonable I_DC current limit would be

6.0A.

V_DC Power

Supply

(See Table 19)

Overcurrent

Protection

(See Section 5.3.4.3)

Undervoltage

Lockout

(See Section 5.3.4.6)

Overvoltage

Lockout

(Se e S ect ion 5.3. 4.7)

Slew Ra te

Control

(See Section 5.3.4.5)

Bulk

Decoupling

Capacitors

Module

Pentium III Processor Mobile Module MMC-2

38 Datasheet 245304-004

Figure 9. Overcurrent Protection Circuit

At the other end of the V_DC input range, the current will be somewhat less. At 14.0V, for

example, the corresponding power could be produced with only 3.0A. In this example, a

comparator, U1A, will be used to sense when V_DC is over 14.0V and will shif t the current limit

from 6.0A to 3.0A.

•Let I_DC(limit)= 6.0A

•Let I_DC(limit2)= 3.0A

•Let b(Q1)= 100

•Let R1=5.0 mΩ= 0.005Ω

•Let R12= 100.0Ω

•Let R13= 100.0Ω

•Let V(R14)≈ 1.8V

•Let I(R20)≈ 100.0 µA

•Let C36= 2.0K

Slew Rate ControlOver Current Protection

R33

R36

R35 V_DC

U1A

C18

2.5V

2N7000

Si4435DY

V_DC

U1B

2N2222A

LM4040

Power Supply

R4 R16

R14

R12

R13

R20

NOTE

: U1B must be able to operate with inputs near the V_DC

rail. Consider the LMC6762.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 39

Figure 10. Current Shift Model

5.3.4.4 Current Limit Shift Point

Comparator U1A should switch when the non-inverting input is equal to the 2.5-V reference on the

inverting input, or when the voltage applied to V_DC is equal to the selected switch point and the

voltage dropped across R36 is 2.5V. This drop should occur when V_DC= 14.0V.

Equation 1.

(The nearest standard 1% value is 9.01 kΩ.)

Comparator U1A will pull its output low when V_DC falls below 14.0V. This drop will effectively

put R33 in parallel with R14.

When power is initial ly applied to the circuit, C18 charges up to 2.5V through R20. This slowly

rising vol tage is applied to the ba se of the cu rrent so urce, Q1. The volt age on R 14 is ap proximat ely

2.5V minus th e base- emi tter drop of abo ut 0.7 V (at 25°C): V(R14) ≈ 1.8V. Q1 is a 2N2222A with a

moderate β of about 100. Therefore, the current through R13 is approximately equal to the current

through R14.

The charging of C18, provides a small increment of delay as U1 will no t allow R4 to pull up the

Gate of M3 until Q1 has pulled the non-inverting input of U1 down slig htly.

The voltage developed across R1 is a function of the load.

Equation 2.

V(R1)= I_DC*R1

U1A +in

V_DC

R36

R35

R35 V_DC Vref

()

Vref

R36

R35 14 2.5

()

2.5

2000

Pentium III Processor Mobile Module MMC-2

40 Datasheet 245304-004

If the maximum I_DC expected is 3.0A, consider setting the I_DC Current Limit at 6.0A. If the

Current Sense resistor, R1, is selected to be 5.0 mΩ (0.0 05Ω), the maximum voltage developed

across this resistor can be calculated. See below.

Consider now the case where V_DC is above 14.0V.

Equation 3.

I_DC(limit)*Rsense= 3.0A*5E-3= 15.0 mV)

The Offset voltage applied to the inverting input of the comparator, U1B, should then be 15.0 mV.

If R13 is selected to be 100.0Ω, the current can then be calculated as shown in Equation 4 below.

Equation 4.

Ioffse t= 15. 0 mV/10 0Ω= 150.0 µA

Note: For a successful design, the input offset of the comparator must be considered. One option is that

the design offset is at least ten times greater than the device offsets.

The value of R14 can now be calculated as shown in Equation 5 belo w.

Equation 5.

R14= 1.8V/150.0 µA= 12. 0 kΩ

(The nearest 1% value is 12.1K.)

Consider now the case when V_DC drops below 14.0V and the current limits sh if t to 6. 0A.

Equation 6.

I_DC(limit)*Rsense= 6.0A*5E-3= 30.0 mV

The Offset vo ltage applied to the inverting inpu t of the comp arator, U1B, should then be 30 mV. If

R13 is selected to be 100Ω, the current can then be calculated as shown in Equation 7 below.

Equation 7.

Ioffse t= 30. 0 mV/10 0Ω= 300.0 µA

The value of parallel combination of R14 and R33 can now be calculated as shown in Equation 8

below.

Equation 8.

Rcombo= 1.8V/3 00.0 µA= 6.0 kΩ

R14 is a 12.0-K resist or. If R33 is also a 12.0-K resistor, the parallel combination will b e 6.0 K.

In R20, the LM4040-2.5 has a very wide operating current range from 60.0 µA to 15.0 µA. In order

to provide the Current Source Base drive you will need Equation 9.

Equation 9.

Ibase≈ Ic/b= 300.0 µA/100= 3.0 µA

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 41

If selected for I (R20), 100 µA would be adequ ate for th e Reference and Curren t Source B ase drive.

Since both of these currents must be satisfied at the low-power supply margin, a V_DC of 7.5V

will be assumed.

Equation 10.

R20 = (V_DC-Vref)/I(R20) = (7.5-2.50)/100.0 µA= 50.0 kΩ

(To allow for component tolerances, 51.0 kΩ is recommended.)

5.3.4.5 Slew Rate Control

The Slew Rate Control regulates the rate that the power supply voltage is appl ied to the system.

•Let the Threshold voltage of M1, Vt = -1.0V

•Let M1 VGS(sat) = -2.4V, also denoted as Vsat

•Let R16 = 100.0 kΩ

•Let t _delay = 500.0 µS

•Let Ctotal = The sum or the Bulk capacitors + the sum of the module capacitors = 5 X 22.0 µF

+ 2 X 4.7 µF= 119.4 µF

M1 is a low RDS(on) P-C hann el MOSFET such as the Siliconix* Si4435 D Y. When the power

supply voltage is applied and increased to a value that exceeds the Lockout value, (7.5V will be

used in this example), the Undervoltage Lockout circuit, allo ws R4 to pull up the gate of M3 to

start a turn-on sequence. M3 pulls its drain toward ground, forcing current to flow through R2. M1

will not start to source any current until after t_delay , with t_delay defined as shown in Equation 11

and Equation 12 below.

Equation 11.

Equation 12.

The publis hed mi nimu m t hres ho ld of the Si443 5D Y i s a VGS of -1.0 V, i.e. C9 must charge to 1 .0V

before M1 starts to turn on. The delay, t_delay, is the time requ ired to charge C9 to 1.0V.

Assuming a negligible voltage drop across M3 , when M3 is ON, the voltage on the Gate of M1,

VG, with respect to ground, is the voltage developed across R2: VG≡ V(R2). If a minimum steady-

state bias on M1 is -4.5V, this will be the voltage dropped across R16. At the low end of the V_DC

margin, i.e. 7.5V, then V G can be derived from Equation 13 below.

Equation 13.

VG = V_DC+VGS = 7.5V- 4.5V = 3.0V (with respect to ground)

t_delay R2 C9

.ln 1 Vt

V_DC Vg

Vgs R16

R16 R2

V_DC

Pentium III Processor Mobile Module MMC-2

42 Datasheet 245304-004

Equation 14.

(The nearest standard 1% value is 66.5 kΩ. The example will continue with R2= 66.5 kΩ.)

Rearranging Equation 8 to solve for C9 yields the following result, as shown in Equati on 15.

Equation 15.

Now a value for C9 can be calculated. See Equation 16 below.

Equation 16.

C 9= 0.354 µF

(A close standard value of 0.33 µF will yield a t_delay of 466.0 µS.)

The ramp-up time, t_ramp, is defined as shown in Equation 17 be low.

Equation 17.

If M1 has a VGS(sat) of -2.4V, then see Equation 18 below.

Equation 18.

t_ramp = 948.8 µS

The maximum current during the power-up ramp is shown in Equation 19 below.

Equation 19.

If the total capacitance, Ctotal on the V_DC bus, is 119.4 µF, then see Equation 20 below.

Equation 20.

Imax = 0.994A

From the values assumed and calculated, t_delay = 466.0 µS, t_ramp = 949.0 µS, and Imax = 944

mA.

R2 Vg R16

V_DC Vg ,R2 66.67 k Ω=

C9 t_delay

R2 ln 1 Vt

V_DC Vg

t_ramp R2 C9

.ln 1 Vsat

Vgs

.t_delay

≈

Imax Ctotal tv

dCtotal V_DC

t_ramp

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 43

5.3.4.6 Undervoltage Lockout

The circuit below shows the Undervoltage Lockout portion of the V_DC Supply circuit. This

circuit protects and locks out the applied voltage to the mobile module to prevent an accidental

turn-on at low V_DC supply voltages.

Warning: A low voltage applied to the mobil e module could result in destructiv e current levels.

Figure 11. Undervoltage Lockout

The output of the LM339 comparator is an open-collector and is low when the applied voltage at

V_DC is less than 7.5V, wh ich holds the Gate of M3 low. Consequently, the Slew Rate Controller

is not allowed to turn on. The 2.5-V reference, Vref, voltage is de rived fr om D7 in Figure 9. When

the non-inverting input of the comparator exceeds Vref, 2.5V, the comparator trips and allows its

output to go to a High Z state. The Gate of M3 can then be pulled up by R4, starting the controlled

Power-up Slew.

The model in Figure 12 will be used to calculate the Underv olt age Lockout trip p oint.

Undervoltage Lockout

V_DC_A

M3 Gate

Vref

2.5V

V_DC

LM339

R25

R18

R17

Let V_DC_UVlock=7.5V

Let R17=10 k

Ω

Let R25=1 mΩ

Let VCEsat= 0.3V

Let V ref=2.5 V

Pentium III Processor Mobile Module MMC-2

44 Datasheet 245304-004

Figure 12. Undervoltage Lockout Model

VCEsat is the saturation voltage of the comparator output transistor.

The comparator trip point voltage can be calculated with Equat ion 21.

Equation 21.

If power to the mobile module is to be held off until V_DC exceeds 7.5V, Equation 21 can be

rearranged to solve for R18.

Equation 22.

A va lue for R1 8 can be det ermined by plugging th ese values into Equation 23.

Equation 23.

R18 = 11.0 kΩ

(4.99 kΩ is a standard 1% resistor value, which would provide lockout below 7.532V.)

5.3.4.7 Overvoltage Lockout

The mobile module operates with a maximum input voltage of 21.0V. This circuit can be set to lock

out the input voltage if it exceeds the desired input.

Unde r voltage Lockout Model

VCEsat

2.5V

V_DC

R25 R18

R17

V_DC_UVlock Vref Vref

R18

Vref VCEsat

R25 R17

R18 VrefR17

.R25

R25 V_DC_UVlock Vref()

.R17 Vref VCEsat()

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 45

Figure 13. Overvoltage Lockout

The LM339 comparator is an open-collector output and is pulled low when the applied voltage at

V_DC is too high, thus disabling the Slew-rate circuit.

The model in Figure 14 below will be used for component calculations.

Figure 14. Overvoltage Lockout Model

Assume that the desired V_DC Overvoltage Lockout is 21.0V. Using Equation 24, the input to the

non-inverting input of the OV Lockout comparator can be calculated with the following equations.

Overvoltage Lockout

M3 Gate

V_DC_A

2.5V

V_DC

LM339

R27

R23

R24

R26

Vref

Let R4=100KΩ

Let R24=100K

Let R26=1MΩ

Let R27=1KΩ

Overvoltage Lockout Model

Vinv

R23

R24

V_DC

Vref

Vnoninv

V_DC_A

R27

R26

Pentium III Processor Mobile Module MMC-2

46 Datasheet 245304-004

Equation 24.

Equation 25.

Vnoninv= 2.517V

Equation 26.

The output of the OV Lockout comparator will become active and pull down when the inverting

input becomes greater th an the 2.517V in put on the non-inverting input. Equa tion 26 can be

rearranged to solve for R23.

Equation 27.

The OV Lockout comparator trip point is defined by Vinv = Vnoninv = 2.517V. Equation 28

provides a so lution for R23.

Equation 28.

R23= 13.618 kΩ

(The nearest standard 1% value is 13.7 kΩ.)

If V_DC exceeds 6.0V, the voltage on the OV Lockout comparator inverting input will exceed

2.517V causing the comparator to trip, pulli ng its o ut put lo w and di sabling the Power Skew

Control circuit which, in turn, will disconnect V_DC from the mobile module.

Vnoninv Vref R27 V_DC_OVlock Vref

()

R4 R26 R27

Vinv V_DC_OVlockR23

()

R23 R24

R23 R24Vinv

V_DC_OVlock Vinv

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 47

Figure 15. Recommended Power Supply Protection Circ uit for the System Electr onics

Figure 16. Simulation of V_DC Voltage Skew

Under

Voltage Lockout

Over Voltag e Loc kou t

Input Bulk Decoup ling Ca pacit ors MMO Processor M odule

Over Cu rrent Protection Slew Rate Control

27uF 4.7uF

4.7uF

27uF27uF

2.5V

V_DC

LM339

2N7000

Si4435DY

V_DC

LM339

2N2222A

LM339

C18

LM4040

C Adaptor

0.3 1M 0.3

0.3

0.30.3

0.3

R25

R27

R23

R24

R26

R18

R17

R4 R16

R14

R33

R12

R13

R36

R35

R20

Com p o ne nts valu es ass umed and calcu lated

R1 5mΩR20 20 kΩ, ± 5%

R2 5.62 kΩ, ± 1% R23 71.5 kΩ, ± 1%

R4 100 kΩ, ± 1% R24 100 kΩ, ± 1%

R12 100Ω, ± 1% R25 1M, ± 5%

R13 100Ω, ± 1% R26 1M, ± 5%

R14 1 2.1 kΩ, ± 1% R27 1 kΩ, ± 1%

R16 100 kΩ, ± 1% R33 12.1 kΩ, ± 1%

R17 10 kΩ, ± 1 % R3 5 9.1 kΩ, ± 1%

R18 11 kΩ, ± 1% R36 2 kΩ, ± 1%

C9 0.33 µF

C18 0.1 µF

Pentium III Processor Mobile Module MMC-2

48 Datasheet 245304-004

5.4 A ctive Thermal Feedback

5.5 Thermal Sensor Configuration Register

The configuration register of the thermal sensor controls the operating mode (Auto Convert vs.

Standby) of the device. Since the processor temperature varies dynamically during normal

operation, Auto Convert mod e s hou ld be u sed ex clusiv ely to mo nitor pro cessor temp erature. Table

26 shows the format of the configuration register. If the RUN/STOP bit is low, then the thermal

sensor enters Auto Convert mode. If the RUN/STOP bit is s et high , then the thermal sensor

immediately stops converting and enters the Standby mode. The thermal sensor will still perform

temperature conversions in Standby mode when it receives a one-shot command. However, the

result of a one-shot command during Auto Convert mode is not guaranteed. Intel does not

recommend using the one-shot comm and to monitor temp erature when the pro cessor is active, only

Auto Convert mode should be used. The thermal sensor can be configured in various interface

modes for tem peratu r e sampling. Intel recommends interf acing th e thermal sensor using Interrupt

mode. For more detailed inform ation regarding interface methods, please see the Intel Mobile

Module Thermal Diode Temperature Sensor Application Note available through your Intel Field

Representative.

NOTE: All RFU bits should be written as “0” and read as “don’t care” for programming purposes.

Table 25. Thermal Sensor SMBus Address

Function SMBus Address

Thermal Sensor 1001 110

Table 26. Thermal Sensor Configuration Register

Bit Name Reset State Function

7 MSB MASK 0 Masks SMBALERT# when high

6 RUN/STOP 0 Standby mode control bit. If low, the device enters Auto Convert

mode. If high, the device immediately stops converting and enters

Standby mode where the one-shot command can be performed.

5-0 R FU 0 Reser ved for future use

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 49

6.0 Mechanical Specification

This section provides the physical dimensions of the Pentium III processor mobi le modu le.

6.1 Mo dule Dim ensions

Figure 17 shows the board dimensions and the connector orientation.

Figure 17. Board Dimensions and MMC-2 Connector Orientation

6.1.1 Pin 1 Location of the MMC-2 Connector

Figure 18 shows the location of pin 1 of the 400-pin connector.

Module Mechanical X-Y-Z Dimensions and Thermal

Attach Points

Unless otherwise specified:

Tolerances

Angles ± 0.5°

.X ± 0.2

.XX ± 0.15

.XXX ± 0.075

* All Dimensions are in mm

Pentium III Processor Mobile Module MMC-2

50 Datasheet 245304-004

Figure 18. Board Dimensions and MMC-2 Connector—Pin 1 Orientation

6.1.2 Printed Circuit Board

Figure 19 shows the Pentium III processor mobile module associated minimum and maximum

thickness of the prin ted circuit board (PCB). The range of PCB thickness allows for different PCB

technologies to be used with curre n t and futu r e Intel m obile m odules.

Note: The system manufacturer must ensure that the mechanical restraining method and/or system-level

EMI contacts are able to support this range of PCB for comp atibility with future Intel mobile

modules.

Figure 19. Printed Circuit Board Thickness

Min: 0.90 mm

Max: 1.10 mm

Pri nted Circui t Board

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 51

6.1.3 Height Restrictions

Figure 20 shows the mechanical stack-up and the associated component clearance requirements.

This is the module keep-out zone and should not be entered. The system manufacturer establishes

board-to-board clearance between the module and the system electronics by selecting one of three

mating connectors available in heights of approximately 4 mm, 6 mm, and 8 mm. The three sizes

provide flexibility in choos in g the sy stem electronics components between the two boards.

Information on these connectors can be obtained from your Intel sales representative.

Figure 20. Keep-out Zone

6.2 Thermal Transfer Plate

The thermal transfer plates (TTP) provide heat dissipation on the mob ile Pentium III processor and

the 82443BX. The TTP ma y vary on different generations of Intel mobile module s. The TT P

provides the thermal attach point, where a system manufacturer can transfer heat through the

notebook system using a heat pipe, a heat spreader plate, or a thermal solution. Attachment

dimensions for the thermal interface block to the TTP are provided in Figure 21, Figure 22, and

Figure 23. The TTP on the mobile module is designed to be a high efficiency spreader. To fully

take advantage of the mobile module therm al design and optimize the s ystem thermal perf ormance,

the contact area (Ac) needs to be a minimum of 30 mm x 30 mm. While it crucial to maximize the

contact area, it is equ ally impo rtant to en sure tha t the co ntact ar ea an d/or the m obile modu le is fr ee

from warpage in an assembled configuration.

Warning: If warpage occurs, the thermal resistance of the mobile module could be adversely affected.

When attaching a mating b lock to either TTP, Intel recommends that a thermal elastomer be used as

an interface material. This material reduces the thermal resistance. The OEM thermal interface

block should be secured to the CPU TTP with M2 screws using a maximum torque of 1.5 Kg*cm

to 2.0 Kg*cm (equivalent to 0.147 N*m to.197 N*m). The thread length of the M2 screws should

Note 3

NOTES:

1. All values are nominal unless otherwise specified.

2. 3D CAD model (PRO/E Native) Available upon

request.

3. These dimensions have changed.

Pentium III Processor Mobile Module MMC-2

52 Datasheet 245304-004

be 2.25-mm gageable thread (2.25-mm minimum to 2.80-mm maximum). The mobile module is

designed to ensur e that the th ermal resi stance between the processor die cen ter and a po int dire ctly

above on the TTP surface is ≤ to 0.35° C/W, under the following set of conditions.

•RTTP-a = TTP (center point) to ambient = ~2.4° C/W

•Ac = Contact area centered between the two TTP attach points = 30 mm x 30 mm.

Figure 21. 82443BX Thermal Transfer Plate (Reference Only)

Figure 22. 82443BX Thermal Transfer Plate Detail

Rivets for PCB Mounting

BX TTP

1.000 ± 0.89

3.150

1.050

6.280

3.569

NOTE: All tolerances a re ± 0.015 mm unless otherwise noted.

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 53

Figure 23. CPU Thermal Transfer Plate (Reference Only)

6.3 Module Physical Support

6.3.1 Module Mounting Requirements

Three mounting holes are available for securing the module to the system base or the system

electronics. See Figure 17 for mounting hole locations. These hole locations and board edge

clearances will remain fixed for all Intel mobile modules. All three mounting holes should be used

to ensure long term mechanical reliability and EMI integrity of the system.

The board edge clearance includes a 0.762-m m (0.030-in ches ) wide EMI containment ring arou nd

the perimeter of the mobile module. This ring is on each layer of the PCB and is grounded. The

hole patterns also have a plated surrounding ring to use a metal standoff for EMI shielding

purposes. Standoffs should be used to provide support for the installed mobile module. However,

the warpage of the baseboard can vary and should be calculated into the final dimensions of the

standoffs used. All calculations can be made with the Intel MMC-2 Standoff/Receptacle Height

Spreadsheet. Information on this spreadsheet can be obtained from your local Intel Field

Representative.

Figure 24 shows the st ando ff su ppo rt hol e det ai ls , th e board edge clearance, and the dimens i ons of

the EMI containment ring. No components are placed on the board in the keep-out area.

Pentium III Processor Mobile Module MMC-2

54 Datasheet 245304-004

Figure 24. Standoff Holes, Board Edge Clearance, and EMI Containme nt Ring

6.3.2 Module Weight

The Pentium III processor mobile module weighs approximately 56 grams.

Hole deta il, 3 place s

0.762 mm width of EMI containment ring

1.27+/- 0.19 mm board edge to EMI ring

2.54+/-0.19 mm keep-out area

3.81+/-0.19 mm board edge to hole centerline

3.81 +/- 0.1 9 mm

4.45 mm diameter groun ded ring

+ 0.050 mm

- 0. 025 mm

hole diameter

2.41 3 mm

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 55

7.0 Thermal Specification

7.1 Thermal Desi gn Power

The power handling capability of the system thermal solution may be reduced to less than the

recommended typical Thermal Design Power (T DP) as s hown in Table 27 with the implementation

of firmware/software control or "throttling” that reduces the CPU power consumption and

dissipation. The typical TDP is the typical power dissipation under normal operating conditions at

nominal V_CO RE (CPU power supply) w hile executing the worst case powe r instru ction mix. This

includes the power dissipated by all of the relevant components. During all operating

environments, the processor junction temperature, TJ, must be within the specified range of 0° C to

100 ° C.

Table 27. Thermal Design Power Specification

NOTES:

1. During all operating environments, the processor temperature, Tj, must be within the special range of 0 °C to

100°C.

2. TDPModule is a thermal-solution design reference point for thermal solution readiness for total module power.

Symbol Parameter Typical

450 MHz Typical

500 MHz Notes

TDP Module Module Thermal Design Power 14.1W 15.0W Module = core + 82443BX +

voltage regulator

Pentium III Processor Mobile Module MMC-2

56 Datasheet 245304-004

8.0 Labeling Information

Intel mobile modules are tracked in two ways. The first is by the product tracking code (P TC). Intel

uses the PTC label to determine the assembly level of the module. Figure 25 shows where the PTC

can be found on the module. The PTC contains 13 characters and provides the following

information.

Example: PML50002001AA

Key: AABCCCDDEEEFFF

Definition:

AA - Processor Module = PM

B- Pentium

III processor mobile module = L

CCC - Speed Identity = 450, 500

DD - Cache Size = 02 (256K)

EEE - Notifiable Design Revision (Start at 001)

FF - Notifiable Processor Revision (Start at AA)

Note: For other Intel mobile modules, the second field (B) is defined as:

Pentium II Processor Mobile Module (MMC-1) = D

Pentium II Processor Mobile Module (MMC-2) = E

Pentium II Processor Mobile Module With On-die Cache (MMC-1) = F

Pentium II Processor Mobile Module With On-die Cache (MMC-2) = G

Celeron Processor Mobile Module (MMC-1) = H

Celeron Processor Mobile Module (MMC-2) = I

Pentium III Processor Mobile Module MMC-2

245304-004 Datasheet 57

Figure 25. Product Tracking Code

The second tracking method is by an OEM generated so ftw a re utility. Four strapping resistors

located on module determine its production level. If connected and terminated properly, up to 16

module-revision levels can be determined. An OEM generated software utility can then read these

ID bits w ith CPU IDs and st epping IDs t o provi de a comple te module manufactur ing revis ion level .

For current PTC and module ID bit information, please refer to the latest Intel mobile module

product change notification (PCN) letter, which can be obtained from your local Intel Field

Representative.

Secondary Side of the Module

Intel Serial Number Intel Assembly Identification

Product Tracking Code

ISYWW6666 PBA XXXXXX-XXX

XXXXXXXXXXXXX

Pentium III Processor Mobile Module MMC-2

58 Datasheet 245304-004

9.0 Environmental Standards

The environmental standards are defined in Table 28.

Table 28. Environmental Standards

Parameter Condition Specification

Temperature Cycle Non-operating

Operating -40 °C to 85 °C

0 °C to 55 °C

Humidity Unbiased 85% relative humidity at 55°C

Voltage V_5

V_3 5.0V ± 5%

3.3V ± 5%

Shock

Non-operating

Unpackaged

Packaged

Half Sine, 2G, 11 mS

Trapezoidal, 50G, 11 mS

Inclined impact at 5.7 feet/S

Half Sine, 2 mS at 36 inches simulated free fall

Vibration Unpackaged

Packaged

5 Hz to 500 Hz, 2.2-gRMS random

10 Hz to 500 Hz, 1.0 gRMS

11,800 impacts 2 Hz to 5 Hz (low frequency)

ESD Damage Human Body Model Non-powered test of the mobile module only for non-

catastrophic failure. The module is tested at 2 kV and then

inserted in a system for functional test.