ATSAM3U2EA-AU - ATMEL - Datasheet.Directory

NOTE: This is a summary document.

The complete document is available on

the Atmel website at www.atmel.com.

Features

•Core

– ARM® Cortex®-M3 revision 2.0 running at up to 96 MHz

– Memory Protection Unit (MPU)

–Thumb

®-2 instruction set

•Memories

– From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator,

dual bank

– From 16 to 48 Kbytes embedded SRAM with dual banks

– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines

– Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash

controller with 4 Kbytes RAM buffer and ECC

•System

– Embedded voltage regulator for single supply operation

– POR, BOD and Watchdog for safe reset

– Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768

kHz for RTC or device clock.

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default

Frequency for fast device startup

– Slow Clock Internal RC oscillator as permanent clock for device clock in low power

mode

– One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device

– Up to 17 peripheral DMA (PDC) channels and 4-channel central DMA

•Low Power Modes

– Sleep and Backup modes, down to 2.5 µA in Backup mode

– Backup domain: VDDBU pin, RTC, 32 backup registers

– Ultra low power RTC: 0.6 µA

•Peripherals

– USB 2.0 Device: 480 Mbps, 4-kbyte FIFO, up to 7 bidirectional Endpoints,

dedicated DMA

– Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester support) and one

UART

– Up to 2 TWI (I2C compatible), 1 SPI, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC)

– 3-Channel 16-bit Timer/Counter (TC) for capture, compare and PWM

– 4-channel 16-bit PWM (PWMC)

– 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features

– 8-channel 12-bit 1MSPS ADC with differential input mode and programmable gain

stage, 8-channel 10-bit ADC

•I/O

– Up to 96 I/O lines with external interrupt capability (edge or level sensitivity),

debouncing, glitch filtering and on-die Series Resistor Termination

– Three 32-bit Parallel Input/Outputs (PIO)

•Packages

– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm

– 100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm

– 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm

– 144-ball TFBGA, 10 x 10 mm, pitch 0.8 mm

AT91SAM

ARM-based

Flash MCU

SAM3U Series

Summary

6430FS–ATARM–10-Feb-12

SAM3U Series

1. SAM3U Description

Atmel's SAM3U series is a member of a family of Flash microcontrollers based on the high per-

formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 96 MHz

and features up to 256 Kbytes of Flash and up to 52 Kbytes of SRAM. The peripheral set

includes a High Speed USB Device port with embedded transceiver, a High Speed MCI for

SDIO/SD/MMC, an External Bus Interface with NAND Flash controller, up to 4xUSARTs

(SAM3U1C/2C/4C have 3), up to 2xTWIs (SAM3U1C/2C/4C have 1), up to 5xSPIs

SAM3U1C/2C/4C have 4), as well as 4xPWM timers, 3xgeneral purpose 16-bit timers, an RTC,

a 12-bit ADC and a 10-bit ADC.

The SAM3U architecture is specifically designed to sustain high speed data transfers. It includes

a multi-layer bus matrix as well as multiple SRAM banks, PDC and DMA channels that enable it

to run tasks in parallel and maximize data throughput.

It can operate from 1.62V to 3.6V and comes in 100-pin and 144-pin LQFP and BGA packages.

The SAM3U device is particularly well suited for USB applications: data loggers, PC peripherals

and any high speed bridge (USB to SDIO, USB to SPI, USB to External Bus Interface).

1.1 Configuration Summary

The SAM3U series differ in memory sizes, package and features list. Table 1-1 summarizes the

configurations of the six devices.

Note: 1. The SRAM size takes into account the 4-Kbyte RAM buffer of the NAND Flash Controller (NFC) which can be used by the

core if not used by the NFC.

Table 1-1. Configuration Summary

Device Flash

Flash

Organization SRAM

Number

of PIOs

Number

USARTs

Number

of TWI

FWUP,

SHDN

pins

External Bus

Interface

HSMCI

data

size Package ADC

SAM3U4E 2x128

Kbytes dual plane 52

Kbytes 96 4 2 Yes

8 or 16 bits,

4 chip selects,

24-bit address

8 bits LQFP144

BGA144

2 (8+ 8

channels)

SAM3U2E 128

Kbytes single plane 36

Kbytes 96 4 2 Yes

8 or 16 bits,

4 chip selects

24-bit address

8 bits LQFP144

BGA144

2 (8+ 8

channels)

SAM3U1E 64

Kbytes single plane 20

Kbytes 96 4 2 Yes

8 or 16 bits,

4 chip selects,

24-bit address

8 bits LQFP144

BGA144

2 (8+ 8

channels)

SAM3U4C 2 x 128

Kbytes dual plane 52

Kbytes 57 3 1 FWUP

8 bits,

2 chip selects,

8-bit address

4 bits LQFP100

BGA100

2 (4+ 4

channels)

SAM3U2C 128

Kbytes single plane 36

Kbytes 57 3 1 FWUP

8 bits,

2 chip selects, 8-

bit address

4 bits LQFP100

BGA100

2 (4+ 4

channels)

SAM3U1C 64

Kbytes single plane 20

Kbytes 57 3 1 FWUP

8 bits

2 chip selects,

8-bit address

4 bits LQFP100

BGA100

2 (4+ 4

channels)

6430FS–ATARM–10-Feb-12

SAM3U Series

2. SAM3U Block Diagram

Figure 2-1. 144-pin SAM3U4/2/1E Block Diagram

D0-D15

A0/NBS0

A2-A20

NCS0

NCS1

NRD

NWR0/NWE

NWR1/NBS1

APB

SHDN

FWUP

NANDOE,

NANDWE

SLAVE

MASTER

A23

NWAIT

EBI

Static

Memory

Controller

NAND Flash

Controller

& ECC

NCS2

NCS3

HSMCI

TWI0

TWI1

USART0

USART1

USART2

USART3

PWM

TC0

TC1

TC2

SSC

DMA

USB

Device

8-channel

12-bit ADC

10-bit ADC

DA0-DA7

CDA

TWCK0-TWCK1

CTS0-CTS3

RTSO-RTS3

SCK0-SCK3

RDX0-RDX3

TXD0-TXD3

NPCS0-NPCS3

SPCK

MOSI

MISO

PWMH0-PWMH3

TCLK0-TCLK2

TIOA0-TIOA2

TIOB0-TIOB2

ADTRG-AD12BTRG

AD0-AD7

ANA

VBG

DFSDP

DFSDM

DHSDP

DHSDM

VDDUTMII

In-Circuit Emulator

TDI

TDO/TRACESWO

TMS/SWDIO

TCK/SWCLK

JTAGSEL

I/D

A21/

NANDALE

A22/

NANDCLE

DCD0

DTR0

RI0

PDC

5-layer AHB Bus Matrix

SPI

MPU DMA

PDC

DSR0

PDC PDC

Voltage

Regulator

VDDIN

VDDOUT

TWD0-TWD1

PWML0-PWML3

NANDRDY

NAND Flash

SRAM

(4KBytes)

ADVREF-AD12BVREF

AD12B0-AD12B7

Flash

Unique

Identifier

UART

URXD

UTXD

PDC

PLLA

TST

PCK0

-PCK2

System Controller

VDDBU

XIN

NRST

PMC

UPLL

XOUT

WDT

RTT

OSC

32K

XIN32

XOUT32

SUPC

RSTC

GPBREG

OSC

3-20 M

PIOA

PIOC

PIOB

POR

RTC

RC 32K

BOD

VDDCORE

VDDUTMI

RC Osc.

12/8/4 M

ERASE

NRSTB

Cortex-M3 Processor

Fmax 96 MHz

SysTick Counter

JTAG & Serial Wire HS UTMI

Transceiver

Peripheral

DMA

Controller

Peripheral

Bridge

ROM

16 KBytes

4-Channel

DMA

SRAM0

32 KBytes

16 KBytes

8 KBytes

FLASH

2x128 KBytes

1x128 KBytes

1x64 KBytes

SRAM1

16 KBytes

6430FS–ATARM–10-Feb-12

SAM3U Series

Figure 2-2. 100-pin SAM3U4/2/1C Block Diagram

D0-D7

A2-A7

NCS0

NCS1

NRD

NWE

APB

SHDN

FWUP

NANDOE,

NANDWE

SLAVE

MASTER

EBI

Static

Memory

Controller

NAND Flash

Controller

& ECC

HSMCI

TWI USART0

USART1

USART2

PWM

TC0

TC1

TC2

SSC

Peripheral

DMA

Controller

Peripheral

Bridge

ROM

16 KBytes

4-Channel

DMA

USB

Device

4-channel

12-bit ADC

10-bit ADC

DA0-DA3

CDA

TWCK0

CTS0-CTS2

RTSO-RTS2

SCK0-SCK2

RDX0-RDX2

TXD0-TXD2

NPCS0-NPCS3

SPCK

MOSI

MISO

PWMH0-PWMH3

TCLK0-TCLK2

TIOA0-TIOA2

TIOB0-TIOB2

ADTRG-AD12BTRG

AD0-AD3

VDDANA

VBG

DFSDP

DFSDM

SRAM0

32 KBytes

16 KBytes

8 KBytes

DHSDP

DHSDM

VDDUTMII

In-Circuit Emulator

TDI

TDO/TRACESWO

TMS/SWDIO

TCK/SWCLK

JTAGSEL

I/D

DCD0

DTR0

RI0

PDC

5-layer AHB Bus Matrix

SPI

MPU DMA

PDC

DSR0

FLASH

2x128 KBytes

1x128 KBytes

1x64 KBytes

SRAM1

16 KBytes

PDC PDC

Voltage

Regulator

VDDIN

VDDOUT

TWD0

PWML0-PWML3

NANDRDY

NAND Flash

SRAM

(4KBytes)

ADVREF-AD12BVREF

AD12B0-AD12B3

Flash

Unique

Identifier

UART

URXD

UTXD

PDC

PLLA

TST

PCK0

-PCK2

System Controller

VDDBU

XIN

NRST

PMC

UPLL

XOUT

WDT

RTT

OSC

32K

XIN32

XOUT32

SUPC

RSTC

GPBREG

OSC

3-20 M

PIOA PIOB

POR

RTC

RC 32K

BOD

VDDCORE

VDDUTMI

RC Osc.

12/8/4 M

ERASE

NRSTB

Cortex-M3 Processor

Fmax 96 MHz

SysTick Counter

JTAG & Serial Wire HS UTMI

Transceiver

NANDCLE

NANDALE

6430FS–ATARM–10-Feb-12

SAM3U Series

3. Signal Description

Table 3-1 gives details on the signal names classified by peripheral.

Table 3-1. Signal Description List

Signal Name Function Type

Active

Level

Voltag e

Reference Comments

Power Supplies

VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V

VDDIN Voltage Regulator Input Power 1.8V to 3.6V

VDDOUT Voltage Regulator Output Power 1.8V

VDDUTMII USB UTMI+ Interface Power Supply Power 3.0V to 3.6V

GNDUTMII USB UTMI+ Interface Ground Ground

VDDBU Backup I/O Lines Power Supply Power 1.62V to 3.6V

GNDBU Backup Ground Ground

VDDPLL

PLL A, UPLL and OSC 3-20 MHz Power Supply

Power 1.62 V to 1.95V

GNDPLL PLL A, UPLL and OSC 3-20 MHz Ground Ground

VDDANA ADC Analog Power Supply Power 2.0V to 3.6V

GNDANA ADC Analog Ground Ground

VDDCORE Core, Memories and Peripherals Chip Power

Supply Power 1.62V to 1.95V

GND Ground Ground

Clocks, Oscillators and PLLs

XIN Main Oscillator Input Input VDDPLL

XOUT Main Oscillator Output Output

XIN32 Slow Clock Oscillator Input Input VDDBU

XOUT32 Slow Clock Oscillator Output Output

VBG Bias Voltage Reference Analog

PCK0 - PCK2 Programmable Clock Output Output VDDIO

Shutdown, Wakeup Logic

SHDN Shut-Down Control Output VDDBU

push/pull

0: The device is in

backup mode

1: The device is running

(not in backup mode)

FWUP Force Wake-Up Input Input Low Needs external pull-up

Serial Wire/JTAG Debug Port (SWJ-DP)

TCK/SWCLK Test Clock/Serial Wire Clock Input

VDDIO

No pull-up resistor

TDI Test Data In Input No pull-up resistor

TDO/TRACESWO Test Data Out/Trace Asynchronous Data Out Output(4)

TMS/SWDIO Test Mode Select/Serial Wire Input/Output Input No pull-up resistor

JTAGSEL JTAG Selection Input High VDDBU Internal permanent

pull-down

6430FS–ATARM–10-Feb-12

SAM3U Series

Flash Memory

ERASE Flash and NVM Configuration Bits Erase

Command

Input High VDDBU Internal permanent 15K

pulldown

Reset/Test

NRST Microcontroller Reset I/O Low VDDIO Internal permanent

pullup

NRSTB Asynchronous Microcontroller Reset Input Low

VDDBU

Internal permanent

pullup

TST Test Select Input Internal permanent

pulldown

Universal Asynchronous Receiver Transceiver - UART

URXD UART Receive Data Input

UTXD UART Transmit Data Output

PIO Controller - PIOA - PIOB - PIOC

PA0 - PA31 Parallel IO Controller A I/O

VDDIO

•Schmitt Trigger (1)

Reset State:

•PIO Input

•Internal pullup enabled

PB0 - PB31 Parallel IO Controller B I/O

•Schmitt Trigger (2)

Reset State:

•PIO Input

•Internal pullup enabled

PC0 - PC31 Parallel IO Controller C I/O

•Schmitt Trigger(3)

Reset State:

•PIO Input

•Internal pullup enabled

External Bus Interface

D0 - D15 Data Bus I/O

A0 - A23 Address Bus Output

NWAIT External Wait Signal Input Low

Static Memory Controller - SMC

NCS0 - NCS3 Chip Select Lines Output Low

NWR0 - NWR1 Write Signal Output Low

NRD Read Signal Output Low

NWE Write Enable Output Low

NBS0 - NBS1 Byte Mask Signal Output Low

NAND Flash Controller - NFC

NANDOE NAND Flash Output Enable Output Low

NANDWE NAND Flash Write Enable Output Low

NANDRDY NAND Ready Input

Table 3-1. Signal Description List (Continued)

Signal Name Function Type

Active

Level

Voltag e

Reference Comments

6430FS–ATARM–10-Feb-12

SAM3U Series

High Speed Multimedia Card Interface - HSMCI

CK Multimedia Card Clock I/O

CDA Multimedia Card Slot A Command I/O

DA0 - DA7 Multimedia Card Slot A Data I/O

Universal Synchronous Asynchronous Receiver Transmitter - USARTx

SCKx USARTx Serial Clock I/O

TXDx USARTx Transmit Data I/O

RXDx USARTx Receive Data Input

RTSx USARTx Request To Send Output

CTSx USARTx Clear To Send Input

DTR0 USART0 Data Terminal Ready I/O

DSR0 USART0 Data Set Ready Input

DCD0 USART0 Data Carrier Detect Input

RI0 USART0 Ring Indicator Input

Synchronous Serial Controller - SSC

TD SSC Transmit Data Output

RD SSC Receive Data Input

TK SSC Transmit Clock I/O

RK SSC Receive Clock I/O

TF SSC Transmit Frame Sync I/O

RF SSC Receive Frame Sync I/O

Timer/Counter - TC

TCLKx TC Channel x External Clock Input Input

TIOAx TC Channel x I/O Line A I/O

TIOBx TC Channel x I/O Line B I/O

Pulse Width Modulation Controller- PWMC

PWMHx PWM Waveform Output High for channel x Output

PWMLx

PWM Waveform Output Low for channel x

Output

only output in

complementary mode

when dead time

insertion is enabled

PWMFI0-2 PWM Fault Input Input

Serial Peripheral Interface - SPI

MISO Master In Slave Out I/O

MOSI Master Out Slave In I/O

SPCK SPI Serial Clock I/O

NPCS0 SPI Peripheral Chip Select 0 I/O Low

NPCS1 - NPCS3 SPI Peripheral Chip Select Output Low

Table 3-1. Signal Description List (Continued)

Signal Name Function Type

Active

Level

Voltag e

Reference Comments

6430FS–ATARM–10-Feb-12

SAM3U Series

Notes: 1. PIOA: Schmitt Trigger on all except PA14 on 100 and 144 packages.

2. PIOB: Schmitt Trigger on all except PB9 to PB16, PB25 to PB31 on 100 and 144 packages.

3. PIOC: Schmitt Trigger on all except PC20 to PC27 on 144 package.

4. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus an external pull-up (100 kΩ) must be

added to avoid current consumption due to floating input.

3.1 Design Considerations

In order to facilitate schematic capture when using a SAM3U design, Atmel provides a “Sche-

matics Checklist” Application note.

Please visit http://www.atmel.com/products/AT91/ for additional documentation.

Two-Wire Interface - TWI

TWDx TWIx Two-wire Serial Data I/O

TWCKx TWIx Two-wire Serial Clock I/O

12-bit Analog-to-Digital Converter - ADC12B

AD12Bx Analog Inputs Analog

AD12BTRG ADC Trigger Input

AD12BVREF ADC Reference Analog

10-bit Analog-to-Digital Converter - ADC

ADx Analog Inputs Analog

ADTRG ADC Trigger Input

ADVREF ADC Reference Analog

Fast Flash Programming Interface - FFPI

PGMEN0-PGMEN2 Programming Enabling Input

VDDIO

PGMM0-PGMM3 Programming Mode Input

PGMD0-PGMD15 Programming Data I/O

PGMRDY Programming Ready Output High

PGMNVALID Data Direction Output Low

PGMNOE Programming Read Input Low

PGMCK Programming Clock Input

PGMNCMD Programming Command Input Low

USB High Speed Device - UDPHS

DFSDM USB Device Full Speed Data - Analog

VDDUTMII

DFSDP USB Device Full Speed Data + Analog

DHSDM USB Device High Speed Data - Analog

DHSDP USB Device High Speed Data + Analog

Table 3-1. Signal Description List (Continued)

Signal Name Function Type

Active

Level

Voltag e

Reference Comments

6430FS–ATARM–10-Feb-12

SAM3U Series

4. Package and Pinout

The SAM3U4/2/1E is available in 144-lead LQFP and 144-ball TFBGA packages.

The SAM3U4/2/1C is available in 100-lead LQFP and 100-ball TFBGA packages.

4.1 SAM3U4/2/1E Package and Pinout

4.1.1 144-ball TFBGA Package Outline

The 144-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its

dimensions are 10 x 10 x 1.4 mm.

Figure 4-1. Orientation of the 144-ball TFBGA Package

4.1.2 144-lead LQFP Package Outline

Figure 4-2. Orientation of the 144-lead LQFP Package

TOP VIEW

BALL A1

ABCDEF GHJ KL M

109

108

144

6430FS–ATARM–10-Feb-12

SAM3U Series

4.1.3 144-lead LQFP Pinout

Table 4-1. 144-pin SAM3U4/2/1E Pinout

1 TDI 37 DHSDP 73 VDDANA 109 PA0/PGMNCMD

2 VDDOUT 38 DHSDM 74 ADVREF 110 PC0

3 VDDIN 39 VBG 75 GNDANA 111 PA1/PGMRDY

4TDO/TRACESWO 40 VDDUTMI 76 AD12BVREF 112 PC1

5 PB31 41 DFSDM 77 PA22/PGMD14 113 PA2/PGMNOE

6 PB30 42 DFSDP 78 PA30 114 PC2

7TMS/SWDIO 43 GNDUTMI 79 PB3 115 PA3/PGMNVALID

8 PB29 44 VDDCORE 80 PB4 116 PC3

9TCK/SWCLK 45 PA28 81 PC15 117 PA4/PGMM0

10 PB28 46 PA29 82 PC16 118 PC4

11 NRST 47 PC22 83 PC17 119 PA5/PGMM1

12 PB27 48 PA31 84 PC18 120 PC5

13 PB26 49 PC23 85 VDDIO 121 PA6/PGMM2

14 PB25 50 VDDCORE 86 VDDCORE 122 PC6

15 PB24 51 VDDIO 87 PA13/PGMD5 123 PA7/PGMM3

16 VDDCORE 52 GND 88 PA14/PGMD6 124 PC7

17 VDDIO 53 PB0 89 PC10 125 VDDCORE

18 GND 54 PC24 90 GND 126 GND

19 PB23 55 PB1 91 PA15/PGMD7 127 VDDIO

20 PB22 56 PC25 92 PC11 128 PA8/PGMD0

21 PB21 57 PB2 93 PA16/PGMD8 129 PC8

22 PC21 58 PC26 94 PC12 130 PA9/PGMD1

23 PB20 59 PB11 95 PA17/PGMD9 131 PC9

24 PB19 60 GND 96 PB16 132 PA10/PGMD2

25 PB18 61 PB12 97 PB15 133 PA11/PGMD3

26 PB17 62 PB13 98 PC13 134 PA12/PGMD4

27 VDDCORE 63 PC27 99 PA18/PGMD10 135 FWUP

28 PC14 64 PA27 100 PA19/PGMD11 136 SHDN

29 PB14 65 PB5 101 PA20/PGMD12 137 ERASE

30 PB10 66 PB6 102 PA21/PGMD13 138 TST

31 PB9 67 PB7 103 PA23/PGMD15 139 VDDBU

32 PC19 68 PB8 104 VDDIO 140 GNDBU

33 GNDPLL 69 PC28 105 PA24 141 NRSTB

34 VDDPLL 70 PC29 106 PA25 142 JTAGSEL

35 XOUT 71 PC30 107 PA26 143 XOUT32

36 XIN 72 PC31 108 PC20 144 XIN32

6430FS–ATARM–10-Feb-12

SAM3U Series

4.1.4 144-ball TFBGA Pinout

Table 4-2. 144-ball SAM3U4/2/1E Pinout

A1 VBG D1 DFSDM G1 PB0 K1 PB7

A2 VDDUTMI D2 DHSDM G2 PC26 K2 PC31

A3 PB9 D3 GNDPLL G3 PB2 K3 PC29

A4 PB10 D4 PC14 G4 PC25 K4 PB3

A5 PB19 D5 PB21 G5 PB1 K5 PB4

A6 PC21 D6 PB23 G6 GND K6 PA14/PGMD6

A7 PB26 D7 PB24 G7 GND K7 PA16/PGMD8

A8 TCK/SWCLK D8 PB28 G8 VDDCORE K8 PA18/PGMD10

A9 PB30 D9 TDI G9 PC4 K9 PC20

A10 TDO/TRACESWO D10 VDDBU G10 PA6/PGMM2 K10 PA1/PGMRDY

A11 XIN32 D11 PA10/PGMD2 G11 PA7/PGMM3 K11 PC1

A12 XOUT32 D12 PA11/PGMD3 G12 PC6 K12 PC2

B1 VDDCORE E1 PC22 H1 PC24 L1 PC30

B2 GNDUTMI E2 PA28 H2 PC27 L2 ADVREF

B3 XOUT E3 PC19 H3 PA27 L3 AD12BVREF

B4 PB14 E4 VDDCORE H4 PB12 L4 PA22/PGMD14

B5 PB17 E5 GND H5 PB11 L5 PC17

B6 PB22 E6 VDDIO H6 GND L6 PC10

B7 PB25 E7 GNDBU H7 VDDCORE L7 PC12

B8 PB29 E8 NRST H8 PB16 L8 PA19/PGMD11

B9 VDDIN E9 PB31 H9 PB15 L9 PA23/PGMD15

B10 JTAGSEL E10 PA12/PGMD4 H10 PC3 L10 PA0/PGMNCMD

B11 ERASE E11 PA8/PGMD0 H11 PA5/PGMM1 L11 PA26

B12 SHDN E12 PC8 H12 PC5 L12 PC0

C1 DFSDP F1 PA31 J1 PB5 M1 VDDANA

C2 DHSDP F2 PA29 J2 PB6 M2 GNDANA

C3 XIN F3 PC23 J3 PC28 M3 PA30

C4 VDDPLL F4 VDDCORE J4 PB8 M4 PC15

C5 PB18 F5 VDDIO J5 PB13 M5 PC16

C6 PB20 F6 GND J6 VDDIO M6 PC18

C7 PB27 F7 GND J7 PA13/PGMD5 M7 PA15/PGMD7

C8 TMS/SWDIO F8 VDDIO J8 PA17/PGMD9 M8 PC11

C9 VDDOUT F9 PC9 J9 PC13 M9 PA20/PGMD12

C10 NRSTB F10 PA9/PGMD1 J10 PA2/PGMNOE M10 PA21/PGMD13

C11 TST F11 VDDCORE J11 PA3/PGMNVALID M11 PA24

C12 FWUP F12 PC7 J12 PA4/PGMM0 M12 PA25

6430FS–ATARM–10-Feb-12

SAM3U Series

4.2 SAM3U4/2/1C Package and Pinout

4.2.1 100-lead LQFP Package Outline

Figure 4-3. Orientation of the 100-lead LQFP Package

4.2.2 100-ball TFBGA Package Outline

Figure 4-4. Orientation of the 100-ball TFBGA Package

100

2 3 4 5 6 7 8 9 10

TOP VIEW

6430FS–ATARM–10-Feb-12

SAM3U Series

4.2.3 100-lead LQFP Pinout

Table 4-3. 100-pin SAM3U4/2/1C1 Pinout

1 VDDANA 26 PA0/PGMNCMD 51 TDI 76 DHSDP

2 ADVREF 27 PA1/PGMRDY 52 VDDOUT 77 DHSDM

3GNDANA 28PA2/PGMNOE 53 VDDIN 78 VBG

4 AD12BVREF 29 PA3/PGMNVALID 54 TDO/TRACESWO 79 VDDUTMI

5PA22/PGMD14 30 PA4/PGMM0 55 TMS/SWDIO 80 DFSDM

6 PA30 31 PA5/PGMM1 56 TCK/SWCLK 81 DFSDP

7 PB3 32 PA6/PGMM2 57 NRST 82 GNDUTMI

8 PB4 33 PA7/PGMM3 58 PB24 83 VDDCORE

9 VDDCORE 34 VDDCORE 59 VDDCORE 84 PA28

10 PA13/PGMD5 35 GND 60 VDDIO 85 PA29

11 PA14/PGMD6 36 VDDIO 61 GND 86 PA31

12 PA15/PGMD7 37 PA8/PGMD0 62 PB23 87 VDDCORE

13 PA16/PGMD8 38 PA9/PGMD1 63 PB22 88 VDDIO

14 PA17/PGMD9 39 PA10/PGMD2 64 PB21 89 GND

15 PB16 40 PA11/PGMD3 65 PB20 90 PB0

16 PB15 41 PA12/PGMD4 66 PB19 91 PB1

17 PA18/PGMD10 42 FWUP 67 PB18 92 PB2

18 PA19/PGMD11 43 ERASE 68 PB17 93 PB11

19 PA20/PGMD12 44 TST 69 PB14 94 PB12

20 PA21/PGMD13 45 VDDBU 70 PB10 95 PB13

21 PA23/PGMD15 46 GNDBU 71 PB9 96 PA27

22 VDDIO 47 NRSTB 72 GNDPLL 97 PB5

23 PA24 48 JTAGSEL 73 VDDPLL 98 PB6

24 PA25 49 XOUT32 74 XOUT 99 PB7

25 PA26 50 XIN32 75 XIN 100 PB8

6430FS–ATARM–10-Feb-12

SAM3U Series

4.2.4 100-ball TFBGA Pinout

Table 4-4. 100-ball SAM3U4/2/1C Pinout

A1 VBG C6 PB22 F1 PB1 H6 PA15/PGMD7

A2 XIN C7 TMS/SWDIO F2 PB12 H7 PA18/PGMD10

A3 XOUT C8 NRSTB F3 VDDIO H8 PA24

A4 PB17 C9 JTAGSEL F4 PA31 H9 PA1/PGMRDY

A5 PB21 C10 VDDBU F5 VDDIO H10 PA2/PGMNOE

A6 PB23 D1 DFSDM F6 GND J1 PB6

A7 TCK/SWCLK D2 DHSDM F7 PB16 J2 PB8

A8 VDDIN D3 VDDPLL F8 PA6/PGMM2 J3 ADVREF

A9 VDDOUT D4 VDDCORE F9 VDDCORE J4 PA30

A10 XIN32 D5 PB20 F10 PA7/PGMM3 J5 PB3

B1 VDDCORE D6 ERASE G1 PB11 J6 PA16/PGMD8

B2 GNDUTMI D7 TST G2 PB2 J7 PA19/PGMD11

B3 VDDUTMI D8 FWUP G3 PB0 J8 PA21/PGMD13

B4 PB10 D9 PA11/PGMD3 G4 PB13 J9 PA26

B5 PB18 D10 PA12/PGMD4 G5 VDDCORE J10 PA0/PGMNCMD

B6 PB24 E1 PA29 G6 GND K1 PB7

B7 NRST E2 GND G7 PB15 K2 VDDANA

B8 TDO/TRACESWO E3 PA28 G8 PA3/PGMNVALID K3 GNDANA

B9 TDI E4 PB9 G9 PA5/PGMM1 K4 AD12BVREF

B10 XOUT32 E5 GNDBU G10 PA4/PGMM0 K5 PB4

C1 DFSDP E6 VDDIO H1 VDDCORE K6 PA14/PGMD6

C2 DHSDP E7 VDDCORE H2 PB5 K7 PA17/PGMD9

C3 GNDPLL E8 PA10/PGMD2 H3 PA27 K8 PA20/PGMD12

C4 PB14 E9 PA9/PGMD1 H4 PA22/PGMD14 K9 PA23/PGMD15

C5 PB19 E10 PA8/PGMD0 H5 PA13/PGMD5 K10 PA25

6430FS–ATARM–10-Feb-12

SAM3U Series

5. Power Considerations

5.1 Power Supplies

The SAM3U product has several types of power supply pins:

• VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage

ranges from 1.62V to 1.95V.

• VDDIO pins: Power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V.

• VDDIN pin: Powers the Voltage regulator

• VDDOUT pin: It is the output of the voltage regulator.

• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage

ranges from 1.62V to 3.6V. VDDBU must be supplied before or at the same time than VDDIO

and VDDCORE.

• VDDPLL pin: Powers the PLL A, UPLL and 3-20 MHz Oscillator; voltage ranges from 1.62V

to 1.95V.

• VDDUTMI pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDANA pin: Powers the ADC cells; voltage ranges from 2.0V to 3.6V.

Ground pins GND are common to VDDCORE and VDDIO pins power supplies.

Separated ground pins are provided for VDDBU, VDDPLL, VDDUTMI and VDDANA. These

ground pins are respectively GNDBU, GNDPLL, GNDUTMI and GNDANA.

5.2 Voltage Regulator

The SAM3U embeds a voltage regulator that is managed by the Supply Controller.

This internal regulator is intended to supply the internal core of SAM3U but can be used to sup-

ply other parts in the application. It features two different operating modes:

• In Normal mode, the voltage regulator consumes less than 700 µA static current and draws

150 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current

depending on the required load current. In Wait Mode or when the output current is low,

quiescent current is only 7µA.

• In Shutdown mode, the voltage regulator consumes less than 1 µA while its output is driven

internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal

mode is inferior to 400 µs.

For adequate input and output power supply decoupling/bypassing, refer to “Voltage Regulator”

in the “Electrical Characteristics” section of the product datasheet.

5.3 Typical Powering Schematics

The SAM3U supports a 1.8V-3.6V single supply mode. The internal regulator input connected to

the source and its output feed VDDCORE. Figure 5-1, Figure 5-2, Figure 5-3 show the power

schematics.

6430FS–ATARM–10-Feb-12

SAM3U Series

Figure 5-1. Single Supply

Note: Restrictions

With Main Supply < 2.0 V, USB and ADC are not usable.

With Main Supply ≥ 2.4V and < 3V, USB is not usable.

With Main Supply ≥ 3V, all peripherals are usable.

VDDIN

Voltage

Regulator

VDDOUT

Main Supply (1.62V-3.6V)

VDDCORE

VDDBU

VDDUTMI

VDDIO

VDDANA

VDDPLL

6430FS–ATARM–10-Feb-12

SAM3U Series

Figure 5-2. Core Externally Supplied

Note: Restrictions

With Main Supply < 2.0 V, USB and ADC are not usable.

With Main Supply ≥ 2.4V and < 3V, USB is not usable.

With Main Supply ≥ 3V, all peripherals are usable.

VDDIN

Voltage

Regulator

VDDOUT

Main Supply (1.62V-3.6V)

VDDCORE

VDDCORE Supply (1.62V-1.95V)

VDDBU

VDDIO

VDDANA

VDDUTMI

VDDPLL

6430FS–ATARM–10-Feb-12

SAM3U Series

Figure 5-3. Backup Batteries Used

Note: Restrictions

With Main Supply < 2.0 V, USB and ADC are not usable.

With Main Supply ≥ 2.4V and < 3V, USB is not usable.

With Main Supply ≥ 3V, all peripherals are usable.

VDDIN

Voltage

Regulator

VDDOUT

Main Supply (1.62V-3.6V)

VDDCORE

Backup Batteries VDDBU

VDDIO

VDDANA

VDDUTMI

VDDPLL

FWUP

SHDN