DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC General Description The DS4422 and DS4424 contain two or four I2C programmable current DACs that are each capable of sinking and sourcing current up to 200A. Each DAC output has 127 sink and 127 source settings that are programmed using the I2C interface. The current DAC outputs power up in a high-impedance state. Full-Scale Current 50A to 200A Full-Scale Range for Each DAC Determined by External Resistors 127 Settings Each for Sink and Source Modes I2C-Compatible Serial Interface Applications Two Address Pins Allow Four Devices on Same I2C Bus Power-Supply Adjustment Power-Supply Margining Adjustable Current Sink or Source Low Cost Small Package (14-Pin, 3mm x 3mm TDFN) Ordering Information -40C to +85C Temperature Range OUTPUTS TEMP RANGE PINPACKAGE DS4422N+ 2 -40C to +85C 14 TDFN-EP DS4422N+T&R 2 -40C to +85C 14 TDFN-EP DS4424N+ 4 -40C to +85C 14 TDFN-EP DS4424N+T&R 4 -40C to +85C 14 TDFN-EP PART Benefits and Features Two (DS4422) or Four (DS4424) Current DACs 2.7V to 5.5V Operating Range Pin Configuration appears at end of data sheet. +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. EP = Exposed pad. Typical Operating Circuit VCC VOUT0 VOUT1 RPU RPU SDA SCL A1 A0 GND DS4422/ DS4424 OUT0 OUT1 FS0 RFS0 19-4744; Rev 2; 9/17 OUT VCC FS1 RFS1 DC-DC CONVERTER OUT R0A FB DC-DC CONVERTER R1A FB R0B R1B DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Absolute Maximum Ratings Voltage Range on VCC, SDA, and SCL Relative to Ground............................................-0.5V to +6.0V Voltage Range on A0, A1, FS0, FS1, FS2, FS3, OUT0, OUT1, OUT2, and OUT3 Relative to Ground................ -0.5V to (VCC + 0.5V) (Not to exceed 6.0V.) Operating Temperature Range............................ -40C to +85C Storage Temperature Range............................. -55C to +125C Soldering Temperature.......................... Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (TA = -40C to +85C.) PARAMETER SYMBOL Supply Voltage VCC Input Logic 1 (SDA, SCL, A0, A1) VIH Input Logic 0 (SDA, SCL, A0, A1) VIL Full-Scale Resistor Values CONDITIONS MIN (Note 1) TYP MAX 2.7 5.5 0.7 x VCC -0.3 RFS0, RFS1, (Note 2) RFS2, RFS3 UNITS V VCC + 0.3 V 0.3 x VCC V 40 160 k MAX UNITS DC Electrical Characteristics (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL CONDITIONS Supply Current ICC VCC = 5.5V (Note 3) Input Leakage (SDA, SCL) IIL VCC = 5.5V Output Leakage (SDA) IL Output Current Low (SDA) IOL RFS Voltage VRFS I/O Capacitance CI/O MIN TYP DS4422 250 DS4424 250 VOL = 0.4V 3 VOL = 0.6V 6 A 1 A 1 A mA 0.976 V 10 pF Output Current Source Characteristics (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL Output Voltage for Sinking Current VOUT:SINK Output Voltage for Sourcing Current Full-Scale Sink Output Current Full-Scale Source Output Current CONDITIONS (Note 4) VOUT:SOURCE (Note 4) IOUT:SINK (Notes 1, 4) IOUT:SOURCE (Notes 1, 4) Output Current Full-Scale Accuracy IOUT:FS +25C, VCC = 3.3V; using 0.1% RFS resistor (Note 2), VOUT0 = VOUT1 = 1.2V Output Current Temperature Coefficient IOUT:TC (Note 5) www.maximintegrated.com MIN MAX UNITS 0.5 TYP 3.5 V 0 VCC 0.75 V 50 200 A -200 -50 A 6 % 75 ppm/C Maxim Integrated 2 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Output Current Source Characteristics (continued) (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL CONDITIONS MIN TYP Output Current Variation Due to Power-Supply Change DC source 0.32 DC sink 0.42 Output Current Variation Due to Output-Voltage Change DC source, VOUT measure at 1.2V 0.16 DC sink, VOUT measure at 1.2V 0.16 Output Leakage Current at Zero Current Setting IZERO MAX UNITS %/V %/V -1 +1 A Output Current Differential Linearity DNL (Notes 6, 7) -0.5 +0.5 LSB Output Current Integral Linearity INL (Notes 7, 8) -1 +1 LSB MAX UNITS 400 kHz AC Electrical Characteristics (VCC = +2.7V to +5.5V, TA = -40C to +85C.) PARAMETER SYMBOL CONDITIONS MIN TYP SCL Clock Frequency fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 s Hold Time (Repeated) START Condition tHD:STA 0.6 s tLOW 1.3 s Low Period of SCL High Period of SCL (Note 9) 0 tHIGH 0.6 Data Hold Time tDH:DAT 0 Data Setup Time tSU:DAT 100 START Setup Time tSU:STA SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: s 0.9 ns 0.6 s tR (Note 10) 20 + 0.1CB 300 tF (Note 10) 20 + 0.1CB 300 tSU:STO CB 0.6 (Note 10) s ns ns s 400 pF All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative. Input resistors (RFS) must be between the speciifed values to ensure the device meets its accuracy and linearity specifications. Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS). The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications. Temperature drift excludes drift caused by external resistor. Differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. The expected incremental increase is the full-scale range divided by 127. Guaranteed by design. Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. The expected value is a straight line between the zero and the full-scale values proportional to the setting. Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. CB--total capacitance of one bus line in pF. www.maximintegrated.com Maxim Integrated 3 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Typical Operating Characteristics (TA = +25C, unless otherwise noted.) 2.5 3.0 3.5 4.0 4.5 5.0 100 DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0, FS1, FS2, OR FS3 50 0 5.5 -40 -20 toc01 250 200 150 100 50 0 0 1 2 3 50 0 25 50 75 100 125 50 DS4422/4 toc03 +25C TO -40C 0 -50 +25C TO +85C -100 -150 -200 -250 FOR THE 50A TO 200A CURRENT SINK RANGE 25 0 SETTING (DEC) 0.50 50 75 100 125 SETTING (DEC) DIFFERENTIAL LINEARITY 1.0 FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE 0.8 0.6 0.4 0.25 DNL (LSB) INL (LSB) +25C TO +85C -50 FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE 0.75 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE COEFFICIENT vs. SETTING (SINK) +25C TO -40C 0 0 TEMPERATURE COEFFICIENT vs. SETTING (SOURCE) INTEGRAL LINEARITY 1.00 -250 80 VOUT (V) 100 VOUT (V) 0 -0.25 0.2 0 -0.2 -0.4 -0.50 -0.6 -0.75 -1.00 60 FOR THE 50A TO 200A CURRENT SOURCE RANGE 150 -100 4 40 DS4422/4 toc07 IOUT (A) 200 TEMPERATURE COEFFICIENT (C/ppm) 38.75K Load 20 -225 TEMPERATURE (C) SUPPLY VOLTAGE (V) VOLTCO (SINK) 0 -200 DS4422/4 toc06 50 VCC = 3.3V VCC = 2.7V DS4422/4 toc08 DOES NOT INCLUDE CURRENT DRAWN BY RESISTORS CONNECTED TO FS0, FS1, FS2, OR FS3 150 40k LOAD ON FS0, FS1, FS2, AND FS3 -175 IOUT (A) 100 200 TEMPERATURE COEFFICIENT (C/ppm) 150 VCC = 5.0V VOLTCO (SOURCE) -150 DS4422/4 toc02 DS4422/4 toc01 200 0 250 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 250 SUPPLY CURRENT vs. TEMPERATURE DS4422/4 toc05 SUPPLY CURRENT vs. SUPPLY VOLTAGE -0.8 0 25 50 75 SETTING (DEC) www.maximintegrated.com 100 125 -1.0 0 25 50 75 100 125 SETTING (DEC) Maxim Integrated 4 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Pin Description PIN NAME FUNCTION DS4424 DS4422 1 1 SDA I2C Serial Data. Input/output for I2C data. 2 2 SCL I2C Serial Clock. Input for I2C clock. 3 3 GND Ground 4 -- FS3 5 -- FS2 6 6 FS1 7 7 FS0 8 8 OUT0 10 10 OUT1 12 -- OUT2 14 -- OUT3 9, 11 9, 11 A0, A1 13 13 VCC Power Supply -- 4, 5, 12, 14 N.C. No Connection -- -- EP Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (The DS4422 has only two inputs: FS0 and FS1.) Current Output. Sinks or sources the current determined by the I2C interface and the resistance connected to FSx. (The DS4422 has only two outputs: OUT0 and OUT1.) Address Select Inputs. Determines the I2C slave address by connecting VCC or GND. See the Detailed Description section for the available device addresses. Exposed Pad. Connect to GND or leave unconnected. Block Diagram SDA SCL A1 VCC A0 I2C-COMPATIBLE SERIAL INTERFACE DS4422/DS4424 VCC F8h SOURCE OR SINK MODE CURRENT DAC0 GND FS0 RFS0 127 POSITIONS EACH FOR SINK AND SOURCE MODE OUT0 FBh FAh F9h CURRENT DAC1 FS1 RFS1 CURRENT DAC3 CURRENT DAC2 OUT1 FS2 RFS2 OUT2 FS3 RFS3 OUT3 DS4424 ONLY www.maximintegrated.com Maxim Integrated 5 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Detailed Description The DS4422/DS4424 contain two or four I2C adjustable current sources that are each capable of sinking and sourcing current. Each output (OUT0, OUT1, OUT2, and OUT3) has 127 sink and 127 source settings that can be controlled by the I2C interface. The full-scale ranges and corresponding step sizes of the outputs are determined by external resistors, connected to pins FS0, FS1, FS2, and FS3, that can adjust the output current over a 4:1 range. Pins OUT2, OUT3, FS2, and FS3 are only available on the DS4424. I2C Slave Address The DS4422/DS4424 respond to one of four I2C slave addresses determined by the two address inputs, A0 and A1. The address inputs should be connected to either VCC or ground. Table 1 lists the slave addresses determined by the address input combinations. Table 1. Slave Addresses The formula to determine RFS (connected to the FSx pins) to attain the desired full-scale current range is: Equation 1: VRFS = R FS x127 16 xI FS Where IFS is the desired full-scale current value, VRFS is the RFS voltage (see the DC Electrical Characteristics table), and RFS is the external resistor value. A1 A0 SLAVE ADDRESS (HEX) GND GND 20h GND VCC 60h VCC GND A0h VCC VCC E0h Memory Organization To control the DS4422/DS4424's current sources, write to the memory addresses listed in Table 2. Table 2. Memory Addresses To calculate the output current value (IOUT) based on the corresponding DAC value (see Table 1 for corresponding memory addresses), use equation 2. MEMORY ADDRESS (HEX) CURRENT SOURCE F8h OUT0 Equation 2: I OUT = DAC Value(dec) xI FS 127 On power-up the DS4422/DS4424 output zero current. This is done to prevent them from sinking or sourcing an incorrect amount of current before the system host controller has had a chance to modify the device's setting. As a source for biasing instrumentation or other circuits, the DS4422/DS4424 provide a simple and inexpensive current source with an I2C interface for control. The adjustable full-scale range allows the application to get the most out of its 7-bit sink or source resolution. When used in adjustable power-supply applications (see Typical Operating Circuit), the DS4422/DS4424 do not affect the initial power-up voltage of the supply because they default to providing zero output current on power-up. As the devices source or sink current into the feedbackvoltage node, they change the amount of output voltage required by the regulator to reach its steadystate operating point. Using the external resistor, RFS, to set the output current range, the DS4422/DS4424 provide some flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined. www.maximintegrated.com F9h OUT1 FAh* OUT2* FBh* OUT3* *Only for DS4424. The format of each output control register is given by: MSB LSB S D6 D5 D4 D3 D2 D1 D0 Where: BIT S DX NAME POWER-ON DEFAULT FUNCTION Determines if DAC sources or Sign Bit sinks current. For sink S = 0; for source S = 1. Data 7-Bit Data Controlling DAC Output. Setting 0000000b outputs zero current regardless of the state of the sign bit. 0b 0000000b Maxim Integrated 6 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Example: RFS0 = 80k and register 0xF8h is written to a value of 0xAAh. Calculate the output current. IFS = (0.976V/80k) x (127/16) = 96.838A The MSB of the output register is 1, so the output is sourcing the value corresponding to position 2Ah (42 decimal). The magnitude of the output current is equal to: 96.838A x (42/127) = 32.025A I2C Serial Interface Description I2C Definitions The following terminology is commonly used to describe I2C data transfers: I2C Slave Address: The slave address of the DS4422/ DS4424 is determined by the state of the A0 and A1 pins (see Table 1). Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is the master to initiate a new data transfer Transitioning SDA from high to low while high generates a START condition. See applicable timing. generated by with a slave. SCL remains Figure 1 for STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 1 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup and hold time requirements (Figure 1). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 1) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a SDA tBUF tLOW tHD:STA tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START tHD:DAT REPEATED START tSU:STO NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 1. I2C Timing Diagram www.maximintegrated.com Maxim Integrated 7 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC TYPICAL I2C WRITE TRANSACTION MSB START A1 A0 1 0 0 0 0 LSB MSB R/W SLAVE b7 ACK READ/ WRITE SLAVE ADDRESS* LSB b6 b5 b4 b3 b2 b1 b0 SLAVE ACK MSB b7 LSB b6 b5 REGISTER/MEMORY ADDRESS b4 b3 b2 b1 b0 SLAVE ACK STOP DATA *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1. EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED) A) SINGLE BYTE WRITE -WRITE REGISTER F9h TO 00h 20h F9h START 0 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 SLAVE 0 0 0 0 0 0 0 0 SLAVE ACK ACK ACK 20h F8h B) SINGLE BYTE READ START 0 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE -READ REGISTER F8h ACK ACK STOP 21h DATA REPEATED 0 0 1 0 0 0 0 1 SLAVE START ACK MASTER NACK STOP Figure 2. I2C Communication Examples NACK by transmitting a one during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 2). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave will return control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4422/DS4424 slave www.maximintegrated.com address is determined by the state of the A0 and A1 address pins. Table 1 describes the addresses corresponding to the state of A0 and A1. When the R/W bit is 0 (such as in A0h), the master is indicating that it will write data to the slave. If R/W = 1 (A1h in this case), the master is indicating that it wants to read from the slave. If an incorrect slave address is written, the DS4422/DS4424 assume the master is communicating with another I2C device and ignore the communication until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication Writing to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations. Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. Maxim Integrated 8 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC VCC VOUT* = 2.0V 4.7k 4.7k OUT VCC SDA SCL A1 A0 DS4422/ DS4424 OUT0 DC-DC CONVERTER I0A R0A = 4.00k FB VFB* = 0.8V I0B GND R0B= 2.67k FS0 RFS0 = 80k IOUT0 *VOUT AND VFB VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH VOUT AND VRFS OF THE DS4422/DS4424. Figure 3. Example Application Circuit Applications Information Example Calculations for an Adjustable Power Supply In this example, the Typical Operating Circuit is used as a base to create Figure 3, a DC-DC output voltage of 2.0V with 20% margin. The adjustable power supply has a DC-DC converter output voltage, VOUT, of 2.0V and a DC-DC converter feedback voltage, VFB, of 0.8V. To determine the relationship of R0A and R0B, start with the equation: = VFB R 0B x VOUT R 0A + R 0B Substituting VFB = 0.8V and VOUT = 2.0V, the relationship between R0A and R0B is determined to be: R0A 1.5 x R0B IOUT0 is chosen to be 100A (midrange source/sink current for the DS4422/DS4424). Summing the currents into the feedback node produces the following: IOUT0 = IR0B - IR0A Where: V I R0B = FB R 0B www.maximintegrated.com And: V - VFB I R0A = OUT R 0A To create a 20% margin in the supply voltage, the value of VOUT is set to 2.4V. With these values in place, R0B is calculated to be 2.67k, and R0A is calculated to be 4.00k. The current DAC in this configuration allows the output voltage to be moved linearly from 1.6V to 2.4V using 127 settings. This corresponds to a resolution of 6.3mV/step. VCC Decoupling To achieve the best results when using the DS4422/ DS4424, decouple the power supply with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surfacemount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. Power Rail Considerations Given that the absolute maximum rating for the OUT pins is VCC + 0.5V, it is recommended that the DS4424 power rail be brought up before or at the same time as the power rail of the source it is controlling. Maxim Integrated 9 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Pin Configuration Package Information TOP VIEW 1 14 + SDA OUT3 (N.C.) SCL 2 13 VCC GND 3 12 OUT2 (N.C.) FS3 (N.C.) 4 11 A1 FS2 (N.C.) 5 FS1 6 FS0 7 DS4422/ DS4424 *EP 10 OUT1 9 A0 8 OUT0 For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 14 TDFN-EP T1433+2 21-0137 ( ) INDICATES DS4422 ONLY. *EXPOSED PAD www.maximintegrated.com Maxim Integrated 10 DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source Current DAC Revision History REVISION NUMBER REVISION DATE 0 3/08 Initial release. -- 1 7/09 Added the Power Rail Considerations section. 9 2 9/17 Replaced TOC04 in Typical Operating Characteristics section 4 DESCRIPTION PAGES CHANGED For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2017 Maxim Integrated Products, Inc. 11