General Description
The DS4422 and DS4424 contain two or four I2C
programmable current DACs that are each capable of
sinking and sourcing current up to 200μA. Each DAC
output has 127 sink and 127 source settings that are
programmed using the I2C interface. The current DAC
outputs power up in a high-impedance state.
Applications
●Power-Supply Adjustment
●Power-Supply Margining
●Adjustable Current Sink or Source
Benets and Features
●Two (DS4422) or Four (DS4424) Current DACs
● Full-Scale Current 50μA to 200μA
● Full-Scale Range for Each DAC Determined by
External Resistors
● 127 Settings Each for Sink and Source Modes
●I2C-Compatible Serial Interface
●Two Address Pins Allow Four Devices on Same
I2C Bus
●Low Cost
● Small Package (14-Pin, 3mm x 3mm TDFN)
●-40°C to +85°C Temperature Range
● 2.7V to 5.5V Operating Range
19-4744; Rev 2; 9/17
Pin Configuration appears at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
EP = Exposed pad.
PART OUTPUTS TEMP RANGE PIN-
PACKAGE
DS4422N+ 2 -40°C to +85°C 14 TDFN-EP
DS4422N+T&R 2 -40°C to +85°C 14 TDFN-EP
DS4424N+ 4 -40°C to +85°C 14 TDFN-EP
DS4424N+T&R 4 -40°C to +85°C 14 TDFN-EP
DC-DC
CONVERTER
FB
OUT
SDA
SCL
A0
A1 OUT0
OUT1
GND
RFS0 RFS1
RPU
RPU VCC
VCC VOUT0
FS0 FS1
R0B
R0A DC-DC
CONVERTER
FB
OUT
VOUT1
R1B
R1A
DS4422/
DS4424
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
Typical Operating Circuit
Ordering Information
Voltage Range on VCC, SDA, and SCL
Relative to Ground............................................-0.5V to +6.0V
Voltage Range on A0, A1, FS0, FS1, FS2, FS3,
OUT0, OUT1, OUT2, and OUT3 Relative to
Ground ...............-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.)
Operating Temperature Range ........................... -40°C to +85°C
Storage Temperature Range ............................ -55°C to +125°C
Soldering Temperature ......................... Refer to the IPC/JEDEC
J-STD-020 Specification.
(TA = -40°C to +85°C.)
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC (Note 1) 2.7 5.5 V
Input Logic 1 (SDA, SCL, A0, A1) VIH 0.7 x VCC VCC + 0.3 V
Input Logic 0 (SDA, SCL, A0, A1) VIL -0.3 0.3 x VCC V
Full-Scale Resistor Values RFS0, RFS1,
RFS2, RFS3 (Note 2) 40 160 kΩ
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current ICC VCC = 5.5V
(Note 3)
DS4422 250 µA
DS4424 250
Input Leakage (SDA, SCL) IIL VCC = 5.5V 1 µA
Output Leakage (SDA) IL1 µA
Output Current Low (SDA) IOL VOL = 0.4V 3mA
VOL = 0.6V 6
RFS Voltage VRFS 0.976 V
I/O Capacitance CI/O 10 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Voltage for Sinking Current VOUT:SINK (Note 4) 0.5 3.5 V
Output Voltage for Sourcing
Current
VOUT:SOURCE
(Note 4) 0VCC -
0.75 V
Full-Scale Sink Output Current IOUT:SINK (Notes 1, 4) 50 200 µA
Full-Scale Source Output Current
IOUT:SOURCE
(Notes 1, 4) -200 -50 µA
Output Current Full-Scale
Accuracy IOUT:FS +25°C, VCC = 3.3V; using 0.1% RFS resistor
(Note 2), VOUT0 = VOUT1 = 1.2V ±6 %
Output Current Temperature
Coefcient IOUT:TC (Note 5) ±75 ppm/°C
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended Operating Conditions
DC Electrical Characteristics
Output Current Source Characteristics
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Input resistors (RFS) must be between the speciifed values to ensure the device meets its accuracy and linearity
specifications.
Note 3: Supply current specified with all outputs set to zero current setting. A0 and A1 are connected to GND. SDA and SCL are
connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS).
Note 4: The output-voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to posi-
tion and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Note 7: Guaranteed by design.
Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 10: CB—total capacitance of one bus line in pF.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 9) 0 400 kHz
Bus Free Time Between STOP
and START Conditions tBUF 1.3 µs
Hold Time (Repeated) START
Condition tHD:STA 0.6 µs
Low Period of SCL tLOW 1.3 µs
High Period of SCL tHIGH 0.6 µs
Data Hold Time tDH:DAT 00.9 µs
Data Setup Time tSU:DAT 100 ns
START Setup Time tSU:STA 0.6 µs
SDA and SCL Rise Time tR(Note 10) 20 + 0.1CB300 ns
SDA and SCL Fall Time tF(Note 10) 20 + 0.1CB300 ns
STOP Setup Time tSU:STO 0.6 µs
SDA and SCL Capacitive Loading CB(Note 10) 400 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Current Variation Due to
Power-Supply Change
DC source 0.32 %/V
DC sink 0.42
Output Current Variation Due to
Output-Voltage Change
DC source, VOUT measure at 1.2V 0.16 %/V
DC sink, VOUT measure at 1.2V 0.16
Output Leakage Current at Zero
Current Setting IZERO -1 +1 µA
Output Current Differential
Linearity DNL (Notes 6, 7) -0.5 +0.5 LSB
Output Current Integral Linearity INL (Notes 7, 8) -1 +1 LSB
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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AC Electrical Characteristics
Output Current Source Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
DS4422/4 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
806040200-20
50
100
150
200
250
0
-40
VCC = 5.0V
VCC = 2.7V
VCC = 3.3V
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0, FS1, FS2,
OR FS3
VOLTCO (SOURCE)
DS4422/4 toc03
VOUT (V)
IOUT (µA)
4.54.03.53.02.52.01.51.00.5
-225
-200
-175
-150
-250
0 5.0
40kΩ LOAD ON FS0, FS1, FS2, AND FS3
0
50
100
150
200
250
0 1 2 3 4
IOUT (µA)
VOUT (V)
VOLTCO (SINK)
toc01
38.75KΩLoad
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
DS4422/4 toc05
SETTING (DEC)
TEMPERATURE COEFFICIENT (°C/ppm)
125100755025
-50
0
50
100
150
200
-100
0
+25°C TO -40°C
+25°C TO +85°C
FOR THE 50µA TO 200µA CURRENT SOURCE
RANGE
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
DS4422/4 toc06
SETTING (DEC)
TEMPERATURE COEFFICIENT (°C/ppm)
125100755025
-200
-150
-100
-50
0
50
-250
0
+25°C TO -40°C
+25°C TO +85°C
FOR THE 50µA TO 200µA CURRENT SINK
RANGE
INTEGRAL LINEARITY
DS4422/4 toc07
SETTING (DEC)
INL (LSB)
12510025 50 75
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0
FOR THE 50µA TO 200µA CURRENT SOURCE
AND SINK RANGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DS4422/4 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
5.04.54.03.53.0
50
100
150
200
250
0
2.5 5.5
DOES NOT INCLUDE CURRENT DRAWN BY
RESISTORS CONNECTED TO FS0, FS1, FS2,
OR FS3
DIFFERENTIAL LINEARITY
DS4422/4 toc08
SETTING (DEC)
DNL (LSB)
125100755025
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0
FOR THE 50µA TO 200µA CURRENT SOURCE
AND SINK RANGE
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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Typical Operating Characteristics
PIN NAME FUNCTION
DS4424 DS4422
1 1 SDA I2C Serial Data. Input/output for I2C data.
2 2 SCL I2C Serial Clock. Input for I2C clock.
3 3 GND Ground
4 — FS3
Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale
current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (The DS4422 has only
two inputs: FS0 and FS1.)
5 — FS2
6 6 FS1
7 7 FS0
8 8 OUT0
Current Output. Sinks or sources the current determined by the I2C interface and the
resistance connected to FSx. (The DS4422 has only two outputs: OUT0 and OUT1.)
10 10 OUT1
12 — OUT2
14 — OUT3
9, 11 9, 11 A0, A1 Address Select Inputs. Determines the I2C slave address by connecting VCC or GND.
See the Detailed Description section for the available device addresses.
13 13 VCC Power Supply
—4, 5, 12,
14 N.C. No Connection
— — EP Exposed Pad. Connect to GND or leave unconnected.
VCC
VCC
RFS0 RFS1 RFS2 RFS3
SDA SCL A1 A0
GND
FS0 FS1
OUT1OUT0
CURRENT
DAC0
F8h F9h
SOURCE OR
SINK MODE
FS2
OUT2
FS3
OUT3
CURRENT
DAC3
127 POSITIONS
EACH FOR SINK
AND SOURCE
MODE
FAh FBh
CURRENT
DAC1
CURRENT
DAC2
I2C-COMPATIBLE
SERIAL INTERFACE
DS4422/DS4424
DS4424 ONLY
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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Pin Description
Block Diagram
Detailed Description
The DS4422/DS4424 contain two or four I2C adjustable
current sources that are each capable of sinking and
sourcing current. Each output (OUT0, OUT1, OUT2, and
OUT3) has 127 sink and 127 source settings that can be
controlled by the I2C interface. The full-scale ranges and
corresponding step sizes of the outputs are determined
by external resistors, connected to pins FS0, FS1, FS2,
and FS3, that can adjust the output current over a 4:1
range. Pins OUT2, OUT3, FS2, and FS3 are only avail-
able on the DS4424.
The formula to determine RFS (connected to the FSx
pins) to attain the desired full-scale current range is:
Equation 1:
RFS
FS FS
V
R 127
16 I
= ×
×
Where IFS is the desired full-scale current value, VRFS
is the RFS voltage (see the DC Electrical Characteristics
table), and RFS is the external resistor value.
To calculate the output current value (IOUT) based on the
corresponding DAC value (see Table 1 for corresponding
memory addresses), use equation 2.
Equation 2:
OUT FS
DACValue(dec)
II
12 7
= ×
On power-up the DS4422/DS4424 output zero current.
This is done to prevent them from sinking or sourcing an
incorrect amount of current before the system host con-
troller has had a chance to modify the device’s setting.
As a source for biasing instrumentation or other circuits,
the DS4422/DS4424 provide a simple and inexpensive
current source with an I2C interface for control. The
adjustable full-scale range allows the application to get
the most out of its 7-bit sink or source resolution.
When used in adjustable power-supply applications (see
Typical Operating Circuit), the DS4422/DS4424 do not
affect the initial power-up voltage of the supply because
they default to providing zero output current on power-up.
As the devices source or sink current into the feedback-
voltage node, they change the amount of output voltage
required by the regulator to reach its steadystate oper-
ating point. Using the external resistor, RFS, to set the
output current range, the DS4422/DS4424 provide some
flexibility for adjusting the impedances of the feedback
network or the range over which the power supply can be
controlled or margined.
I2C Slave Address
The DS4422/DS4424 respond to one of four I2C slave
addresses determined by the two address inputs, A0 and
A1. The address inputs should be connected to either
VCC or ground. Table 1 lists the slave addresses deter-
mined by the address input combinations.
Memory Organization
To control the DS4422/DS4424’s current sources, write to
the memory addresses listed in Table 2.
The format of each output control register is given by:
Where:
*Only for DS4424.
Table 1. Slave Addresses
Table 2. Memory Addresses
A1 A0 SLAVE ADDRESS
(HEX)
GND GND 20h
GND VCC 60h
VCC GND A0h
VCC VCC E0h
MEMORY ADDRESS
(HEX) CURRENT SOURCE
F8h OUT0
F9h OUT1
FAh* OUT2*
FBh* OUT3*
MSB LSB
S D6D5D4D3D2D1D0
BIT NAME FUNCTION POWER-ON
DEFAULT
S Sign Bit
Determines if DAC sources or
sinks current. For sink
S = 0; for source S = 1.
0b
DXData
7-Bit Data Controlling DAC
Output. Setting 0000000b
outputs zero current regardless
of the state of the sign bit.
0000000b
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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Example: RFS0 = 80kΩ and register 0xF8h is written to a
value of 0xAAh. Calculate the output current.
IFS = (0.976V/80kΩ) x (127/16) = 96.838μA
The MSB of the output register is 1, so the output is sourc-
ing the value corresponding to position 2Ah (42 decimal).
The magnitude of the output current is equal to:
96.838μA x (42/127) = 32.025μA
I2C Serial Interface Description
I2C Denitions
The following terminology is commonly used to describe
I2C data transfers:
I2C Slave Address: The slave address of the DS4422/
DS4424 is determined by the state of the A0 and A1 pins
(see Table 1).
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data at
the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 1 for
applicable timing.
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates a
STOP condition. See Figure 1 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeated
START condition is issued identically to a normal START
condition. See Figure 1 for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL, plus the
setup and hold time requirements (Figure 1). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 1) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse and
the data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL clock
pulses, including when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the ninth bit. A device performs a
Figure 1. I2C Timing Diagram
SDA
SCL
tHD:STA
tLOW
tHIGH
tRtF
tBUF
tHD:DAT
tSU:DAT REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
START
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
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NACK by transmitting a one during the ninth bit. Timing
for the ACK and NACK is identical to all other bit writes
(Figure 2). An ACK is the acknowledgment that the device
is properly receiving data. A NACK is used to terminate a
read sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant
bit first) plus a 1-bit acknowledgement from the slave to
the master. The 8 bits transmitted by the master are done
according to the bit-write definition, and the acknowledge-
ment is read using the bit-read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information that
are transferred (most significant bit first) from the slave
to the master are read by the master using the bit-read
definition above, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminated
communication so the slave will return control of SDA to
the master.
Slave Address Byte: Each slave on the I2C bus responds
to a slave address byte sent immediately following a
START condition. The slave address byte contains the
slave address in the most significant 7 bits and the R/W
bit in the least significant bit. The DS4422/DS4424 slave
address is determined by the state of the A0 and A1
address pins. Table 1 describes the addresses corre-
sponding to the state of A0 and A1.
When the R/W bit is 0 (such as in A0h), the master is indi-
cating that it will write data to the slave. If R/W = 1 (A1h
in this case), the master is indicating that it wants to read
from the slave. If an incorrect slave address is written, the
DS4422/DS4424 assume the master is communicating
with another I2C device and ignore the communication
until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data. The
memory address is always the second byte transmitted
during a write operation following the slave address byte.
I2C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
Figure 2. I2C Communication Examples
SLAVE
ADDRESS*
START
START
A1 A0 1 0 0 0 0 R/WSLAVE
ACK
SLAVE
ACK
SLAVE
ACK
MSB LSB MSB LSB MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
READ/
WRITE
REGISTER/MEMORY ADDRESS
b7 b6 b5 b4 b3 b2 b1 b0
DATA
STOP
SINGLE BYTE WRITE
-WRITE REGISTER
F9h TO 00h
SINGLE BYTE READ
-READ REGISTER F8h START REPEATED
START
21h
MASTER
NACK STOP
00100000 11111 000
F8h
00100 001
00100000 11111 001
20h F9h
STOP
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED)
TYPICAL I2C WRITE TRANSACTION
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
00000 000
20h
A)
B)
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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Applications Information
Example Calculations
for an Adjustable Power Supply
In this example, the Typical Operating Circuit is used as
a base to create Figure 3, a DC-DC output voltage of
2.0V with ±20% margin. The adjustable power supply
has a DC-DC converter output voltage, VOUT, of 2.0V
and a DC-DC converter feedback voltage, VFB, of 0.8V.
To determine the relationship of R0A and R0B, start with
the equation:
0B
FB OUT
+
0A 0B
R
VV
RR
= ×
Substituting VFB = 0.8V and VOUT = 2.0V, the relationship
between R0A and R0B is determined to be:
R0A ≈ 1.5 x R0B
IOUT0 is chosen to be 100μA (midrange source/sink cur-
rent for the DS4422/DS4424). Summing the currents into
the feedback node produces the following:
IOUT0 = IR0B - IR0A
Where:
FB
R0B
0B
V
IR
=
And:
OUT FB
R0A 0A
VV
IR
−
=
To create a 20% margin in the supply voltage, the value
of VOUT is set to 2.4V. With these values in place, R0B
is calculated to be 2.67kΩ, and R0A is calculated to be
4.00kΩ. The current DAC in this configuration allows the
output voltage to be moved linearly from 1.6V to 2.4V
using 127 settings. This corresponds to a resolution of
6.3mV/step.
VCC Decoupling
To achieve the best results when using the DS4422/
DS4424, decouple the power supply with a 0.01μF or
0.1μF capacitor. Use a high-quality ceramic surfacemount
capacitor if possible. Surface-mount components mini-
mize lead inductance, which improves performance, and
ceramic capacitors tend to have adequate high-frequency
response for decoupling applications.
Power Rail Considerations
Given that the absolute maximum rating for the OUT pins
is VCC + 0.5V, it is recommended that the DS4424 power
rail be brought up before or at the same time as the power
rail of the source it is controlling.
Figure 3. Example Application Circuit
DC-DC
CONVERTER
FB
OUT
SDA
SCL
A0
A1 OUT0
GND
*VOUT AND VFB VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH VOUT AND VRFS OF THE DS4422/DS4424.
RFS0 = 80kΩ
4.7kΩ4.7kΩVCC
VCC
VOUT* = 2.0V
VFB* = 0.8V
FS0
R0B= 2.67kΩ
R0A = 4.00kΩ
DS4422/
DS4424
I0A
I0B
IOUT0
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
14 TDFN-EP T1433+2 21-0137
TOP VIEW
2
4
5
13
11
10
VCC
A1
OUT1
SCL
FS3 (N.C.)
FS2 (N.C.)
( ) INDICATES DS4422 ONLY.
*EXPOSED PAD
*EP
1
+
14 OUT3 (N.C.)
OUT2 (N.C.)
SDA
312
GND
69A0FS1
78OUT0FS0
DS4422/
DS4424
DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
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Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Pin Conguration
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 3/08 Initial release. —
17/09 Added the Power Rail Considerations section. 9
29/17 Replaced TOC04 in Typical Operating Characteristics section 4
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are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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DS4422/DS4424 Two-/Four-Channel, I2C, 7-Bit Sink/Source
Current DAC
© 2017 Maxim Integrated Products, Inc.
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11
Revision History
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