www.ti.com
FEATURESGENERALDESCRIPTION
PINCONNECTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
28−Pin DIP Module
(TOP VIEW)
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
32k×8NONVOLATILESRAM(5V,3.3V)
•DataRetentionforatleast10YearsWithoutTheCMOSbq4011/Y/LYisanonvolatile262,144-bit
PowerstaticRAMorganizedas32,768wordsby8bits.The
integralcontrolcircuitryandlithiumenergysource
•AutomaticWrite-ProtectionDuringprovidereliablenonvolatilitycoupledwiththe
Power-up/Power-downCyclesunlimitedwritecyclesofstandardSRAM.
•ConventionalSRAMOperation,IncludingThecontrolcircuitryconstantlymonitorsthesingle
UnlimitedWriteCyclessupplyforanout-of-tolerancecondition.WhenVCC
•InternalIsolationofBatterybeforePowerfallsoutoftolerance,theSRAMisunconditionally
Applicationwrite-protectedtopreventaninadvertentwrite
•5-Vor3.3-VOperationoperation.
•IndustryStandard28-PinDIPPinoutAtthistimetheintegralenergysourceisswitchedon
tosustainthememoryuntilafterVCCreturnsvalid.
Thebq4011/Y/LYusesextremelylowstandby
currentCMOSSRAMs,coupledwithsmalllithium
coincellstoprovidenonvolatilitywithoutlong
write-cycletimesandthewrite-cyclelimitations
associatedwithEEPROM.
Thebq4011/Y/LYrequiresnoexternalcircuitryandis
compatiblewiththeindustry-standard256-kbSRAM
pinout.
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.Copyright©1999–2007,TexasInstrumentsIncorporated
ProductsconformtospecificationsperthetermsoftheTexas
Instrumentsstandardwarranty.Productionprocessingdoesnot
necessarilyincludetestingofallparameters.
Not Recommended For New Designs
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DEVICEINFORMATION
FUNCTIONALDESCRIPTION
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
Table1.TERMINALFUNCTIONS
TERMINALI/ODESCRIPTION
NAMENUMBER
A010I
A19I
A28I
A37I
A46I
A55I
A64I
A73IAddressinputs
A825I
A924I
A1021I
A1123I
A122I
A1326I
A141I
CE 20IChip-enableinput
DQ011I/O
DQ112I/O
DQ213I/O
DQ315I/ODatainput/output
DQ416I/O
DQ517I/O
DQ618I/O
DQ719I/O
OE22IOutputenableinput
VCC28ISupplyvoltageinput
VSS14-Ground
WE27IWriteenableinput
Whenpowerisvalid,thebq4011/Y/LYoperatesasastandardCMOSSRAM.Duringpower-downandpower-up
cycles,thebq4011/Y/LYactsasanonvolatilememory,automaticallyprotectingandpreservingthememory
contents.
Power-down/power-upcontrolcircuitryconstantlymonitorstheVCCsupplyforapower-fail-detectthresholdVPFD.
Thebq4011monitorsforVPFD=4.62Vtypicalforusein5-Vsystemswith5%supplytolerance.Thebq4011Y
monitorsforVPFD=4.37Vtypicalforusein5-Vsystemswith10%supplytolerance.Thebq4011LYmonitorsfor
VPFD=2.90V(typ)forusein3.3-Vsystems.
WhenVCCfallsbelowtheVPFDthreshold,theSRAMautomaticallywrite-protectsthedata.Alloutputsbecome
highimpedance,andallinputsaretreatedasdon'tcare.Ifavalidaccessisinprocessatthetimeofpower-fail
detection,thememorycyclecontinuestocompletion.IfthememorycyclefailstoterminatewithintimetWPT,
write-protectiontakesplace.
AsVCCfallspastVPFDandapproachesVSO,thecontrolcircuitryswitchestotheinternallithiumbackupsupply,
whichprovidesdataretentionuntilvalidVCCisapplied.
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BLOCKDIAGRAM
32 k × 8
SRAM
Block
OE
WE
A0- A14
DQ0- DQ7
Power-Fail
Control
Power CECON
CE VCC
+
Lithium
Cell
UDG-06075
DIP MODULE
bq4011/Y/LY
MA PACKAGE
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
WhenVCCreturnstoalevelabovetheinternalbackupcellvoltage,thesupplyisswitchedbacktoVCC.AfterVCC
rampsabovetheVPFDthreshold,write-protectioncontinuesforatimetCER(120msmaximumin5-Vsystem,
85msmaximumin3.3-Vsystem)toallowforprocessorstabilization.Normalmemoryoperationmayresume
afterthistime.
Theinternalcoincellsusedbythebq4011/Y/LYhaveanextremelylongshelflifeandprovidedataretentionfor
morethan10yearsintheabsenceofsystempower.
AsshippedfromTI,theintegrallithiumcellsoftheMT-typemoduleareelectricallyisolatedfromthememory.
(Self-dischargeinthisconditionisapproximately0.5%peryear.)FollowingthefirstapplicationofVCC,this
isolationisbroken,andthelithiumbackupprovidesdataretentiononsubsequentpower-downs.
TRUTHTABLE
MODECEWE OE I/OOPERATIONPOWER
NotselectedHXXHigh-ZStandby
OutputdisableLHHHigh-ZActive
ReadLHLDOUTActive
WriteLLXDINActive
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bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
ORDERINGINFORMATION
Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthedatasheet,orsee
theTIwebsiteatwww.ti.com.
SELECTIONGUIDE
MAXIMUMNEGATIVESUPPLYNOMINALINPUTTEMPERATURE
DEVICENUMBERACCESSTOLERANCEVOLTAGE(°C)
TIME(ns)(%)VCC(V)
bq4011MA-7070
bq4011MA-150150-5
bq4011MA-200200
bq4011YMA-70700to70
bq4011YMA-1001005
bq4011YMA-150150
bq4011YMA-200200-10
bq4011YMA-70N70
bq4011YMA-150N150-40to85
bq4011LYMA-70N703.3
PARTNUMBERING
INPUTNEGATIVE
PRODUCTMEMORYSPEEDTEMPERATURE
VOLTAGESUPPLYPACKAGE
LINEDENSITY(ns)°C
(V)TOLERANCE(%)
bq4011LYMA70N
10=8k×8Blank=5Blank=5%MA=DIP70Blank=Commercial
11=32k×8L=3.3Y=10%85(0to70)
13=128k×8100
14=256k×8120N=Industrial
15=512k×8150(-40to85)
16=1024k×8200
17=2048k×8
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ABSOLUTEMAXIMUMRATINGS(1)
RECOMMENDEDOPERATINGCONDITIONS(TA=TOPR)
DCELECTRICALCHARACTERISTICS
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
PARAMETERCONDITIONVALUEUNIT
bq4011Y–0.3to7.0
VCCDCvoltageappliedonVCCrelativetoVSSbq4011–0.3to7.0V
bq4011LY–0.3to6.0
bq4011Y–0.3to7.0
DCvoltageappliedonanypinexcluding
VTVVT≤VCC+0.3Vbq4011–0.3to7.0V
VCCrelativetoVSSbq4011LY–0.3to(VCC+0.3)
Commercial0to70
TOPROperatingtemperatureIndustrial–40to85
Commercial–10to70
TSTGStoragetemperatureIndustrial–40to85°C
Commercial–10to70
TBIASTemperatureunderbiasIndustrial–40to85
TSOLDERSolderingtemperatureFor10seconds260
(1)PermanentdevicedamagemayoccurifAbsoluteMaximumRatingsareexceeded.Functionaloperationshouldbelimitedtothe
RecommendedDCOperatingConditionsdetailedinthisdatasheet.Exposuretoconditionsbeyondtheoperationallimitsforextended
periodsoftimemayaffectdevicereliability.
MINTYP(1)MAXUNIT
bq4011Y4.505.005.50
VCCSupplyvoltagebq40114.755.005.50
bq4011LY3.003.303.60V
VSSSupplyvoltage000
VILLow-levelinputvoltage–0.30.8
VIHHigh-levelInputvoltage2.2VCC+0.3
(1)TypicalvaluesindicateoperationatTA=25°C.
TA=TOPR,VCC(min)≤VCC≤VCC(max)
PARAMETERTESTCONDITIONSMINTYP(1)MAXUNIT
ILIInputleakagecurrentVIN=VSStoVCC±1µA
ILOOutputleakagecurrentCE=VIHorOE=VIHorWE=VIL±1
VOHOutputhighvoltageIOH=–1.0mA2.4V
VOLOutputlowvoltageIOL=2.1mA0.4
ISB1StandbysupplycurrentCE=VIH12µA
CE≥VCC–0.2V,0V≤VIN≤0.2V,ISB2Standbysupplycurrent0.11mA
orVIN≥VCC–0.2
bq401150
Minimumcycle,duty=100%,
ICCOperatingsupplycurrentbq4011YmA
CE=VIL,II/O=0mA
bq4011LY30
bq40114.554.624.75
VPFDPower-fail-detectvoltagebq4011Y4.304.374.50
bq4011LY2.852.902.95V
bq40113
VSOSupplyswitch-overvoltagebq4011Y3
bq4011LY2.9
(1)TypicalvaluesindicateoperationatTA=25°C,VCC=5.0VorVCC=3.3V.
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CAPACITANCE(TA=25°C,f=1MHz,VCC=5.0VorVCC=3.3V)
ACTESTCONDITIONS
100 pF1 kW
1.9 kW
+ 5 V
DOUT
5 pF1 kW
1.9 kW
+ 5 V
DOUT
30 pF1.4 kW
1.2 kW
+ 3.3 V
DOUT
5 pF1.4 kW
1.2 kW
+ 3.3 V
DOUT
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
PARAMETER(1)TESTCONDITIONSMINTYPMAXUNIT
CI/OInput/outputcapacitanceOutputvoltage=0V8pF
CINInputcapacitanceInputvoltage=0V10
(1)Ensuredbydesign.Notproductiontested.
TESTCONDITIONS
PARAMETER5V3.3V
Inputpulselevels0Vto3.0V0VtoVCC
Inputriseandfalltimes5ns5ns
Inputandoutputtimingreferencelevels1.5V(unlessotherwisespecified)50%
Outputload(includingscopeandjig)SeeFigure1andFigure2SeeFigure3andFigure4
Figure1.5-VOutputLoadAFigure2.5-VOutputLoadB
Figure3.3.3-VOutputLoadAFigure4.3.3-VOutputLoadB
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Previous Data Valid Data Valid
Address
DOUT
tRC
tAA
tOH
High−Z High−Z
CE
DOUT
tRC
tACE
tCLZ tCHZ
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
Table2.READCYCLE(TA=TOPR,VCC(min)≤VCC≤VCC(max))
-70-100-150-200
PARAMETERTESTCONDITIONSUNIT
MINMAXMINMAXMINMAXMINMAX
tRCReadcycletime70100150200
tAAAddressaccesstime70100150200
tACEChipenableaccesstimeOutputloadA70100150200
tOEOutputenabletooutputvalid35507090
tCLZChipenabletooutputinlowZ5555ns
tOLZOutputenabletooutputinlowZ0000
OutputloadB
tCHZChipdisabletooutputinhighZ025025025025
tOHZOutputdisabletooutputinhighZ025025025025
tOHOutputholdfromaddresschangeOutputloadA10101010
(1)WEisheldhighforareadcycle.(2)Deviceiscontinuouslyselected:CE=OE=VIL.
Figure5.ReadCycleNo.1(AddressAccess)(1)(2)
(1)WEisheldhighforareadcycle.(2)Deviceiscontinuouslyselected:CE=OE=VIL.
(3)AddressisvalidpriortoorcoincidentwithCEtransitionlow.
Figure6.ReadCycleNo.2(CEAccess)(1)(2)(3)
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Address
Data−In Valid
High−Z
DOUT Data Undefined (1)
tWZ tOW
tDW tDH1
tWP
tAS
tCW
tAW tWR1
tWC
DIN
WE
CE
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
Table3.WRITECYCLE(TA=TOPR,VCC(min)≤VCC≤VCC(max))
-70-100-150-200
PARAMETERTESTCONDITIONSUNIT
MINMAXMINMAXMINMAXMINMAX
tWCWritecycletime70100150200
tCWChipenabletoendofwriteSee(1)6590100150
tAWAddressvalidtoendofwriteSee(1)658090150
Measuredfromaddressvalidto
tASAddresssetuptime0000
beginningofwrite.(2)
Measuredfrombeginningofwriteto
tWPWritepulsewidth557590130
endofwrite.(1)
MeasuredfromWEgoinghightoendtWR1Writerecoverytime(writecycle1)5555
ofwritecycle.(3)
ns
MeasuredfromCEgoinghightoend
tWR2Writerecoverytime(writecycle2)15151515
ofwritecycle.(3)
Measuredtofirstlow-to-hightransition
tDWDatavalidtoendofwrite30405070
ofeitherCEorWE.
MeasuredfromWEgoinghightoendtDH1Dataholdtime(writecycle1)0000
ofwritecycle.(4)
MeasuredfromCEgoinghightoend
tDH2Dataholdtime(writecycle2)0000
ofwritecycle.(4)
tWZWriteenbledtooutputinhighZI/Opinsareinoutputstate.(5)025030050070
tOWOutputactivefromendofwrite5555
I/Opinsareinoutputstate.(5)
(1)AwriteendsattheearliertransitionofCEgoinghighandWEgoinghigh.
(2)AwriteoccursduringtheoverlapofalowCEandalowWE.AwritebeginsatthelatertransitionofCEgoinglowandWEgoinglow.
(3)EithertWR1ortWR2mustbemet.
(4)EithertDH1ortDH2mustbemet.
(5)IfCEgoeslowsimultaneouslywithWEgoingloworafterWEgoinglow,theoutputsremaininhigh-impedancestate.
(1)CEorWEmustbehighduringaddresstransition.
(2)BecauseI/Omaybeactive(OElow)duringthisperiod,datainputsignalsofoppositepolaritytotheoutputsmustnot
beapplied.
(3)IfOEishigh,theI/Opinsremaininastateofhighimpedance.
Figure8.WriteCycleNo.1(WE-Controlled)(1)(2)(3)
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Address
High−Z
Data−in Valid
DOUT Data Undefined (1)
tWZ
tDW tDH2
tWP
DIN
WE
CE
tWR2
tAS
tAW
tCW
tWC
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
(1)CEorWEmustbehighduringaddresstransition.
(2)BecauseI/Omaybeactive(OElow)duringthisperiod,datainputsignalsofoppositepolaritytotheoutputsmustnot
beapplied.
(3)IfOEishigh,theI/Opinsremaininastateofhighimpedance.
(4)EithertWR1ortWR2mustbemet.
(5)EithertDH1ortDH2mustbemet.
Figure9.WriteCycleNo.2(CE-Controlled)(1)(2)(3)(4)(5)
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VCC tPF
tFS tDR
tCER
tPU
tWPT
VPFD VPFD
4.75 V
4.25 V
VSO VSO
CE
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
Table4.5-VPOWER-DOWN/POWER-UP(TA=TOPR)
PARAMETERTESTCONDITIONSMINTYP(1)MAXUNIT
tPFVCCslew,4.75to4.25V300µs
tFSVCCslew,4.25toVSO10µs
tPUVCCslew,VSOtoVPFD(max.)0µs
TimeduringwhichSRAMiswrite-protectedafter
tCERChipenablerecoverytime4080120ms
VCCpassesVPFDonpower-up.
tDRData-retentiontimeinabsenceofVCCTA=25°C(2)10years
DelayafterVCCslewsdownpastVPFDbeforeSRAM
tWPTWrite-protecttime40100150µs
iswriteprotected.
(1)TypicalvaluesindicateoperationatTA=25°C,VCC=5V.
(2)BatteriesaredisconnectedfromcircuituntilafterVCCisappliedforthefirsttime.tDRistheaccumulatedtimeinabsenceofpower
beginningwhenpowerisfirstappliedtothedevice.
Figure10.5-VPower-Down/Power-UpTiming
11
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3.0 V
VCC
VPFD(max)
VSO VSO
CE
VPFD
tF
tDR
tCER
tR
bq4011/Y/LY
SLUS118A–MAY1999–REVISEDMAY2007
Table5.3.3-VPOWER-DOWN/POWER-UP(TA=TOPR)
PARAMETERTESTCONDITIONSMINTYP(1)MAXUNIT
tFVCCslew,3Vto0V300µs
tRVCCslew,VSOtoVPFD(max)100
TimeduringwhichSRAMiswrite-protectedafter
tCERChipenablerecoverytime1085ms
VCCpassesVPFDonpower-up.
tDRData-retentiontimeinabsenceofVCCTA=25°C(2)10years
(1)TypicalvaluesindicateoperationatTA=25°C,VCC=3.3V.
(2)BatteriesaredisconnectedfromcircuituntilafterVCCisappliedforthefirsttime.Dataretentiontime(tDR)istheaccumulatedtimein
absenceofpowerbeginningwhenpowerisfirstappliedtothedevice.
Figure11.3.3-VPower-Down/Power-UpTiming
CAUTION:
Negativeundershootsbelowtheabsolutemaximumratingof-0.3Vin
battery-backupmodemayaffectdataintegrity.
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PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
BQ4011LYMA-70N NRND DIP MODULE MA 28 12 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011MA-100 NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011MA-150 NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011YMA-100 NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011YMA-150 NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011YMA-200 NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011YMA-70 NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
BQ4011YMA-70N NRND DIP MODULE MA 28 14 Pb-Free (RoHS) Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MPDI061 – MAY 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MA (R-PDIP-T**) PLASTIC DUAL-IN-LINE
28 PINS SHOWN
0.110
0.150
0.023
0.013
0.375
0.630
0.740
0.740
1.500
Max.
E
G
L
e
D/28 PIN
D/12 PIN
C
B
0.710
0.090
0.120
0.590
1.470
0.710
0.017 –
Dimension
A1
A0.015
Min.
Inches
2.79
3.81
16.00
0.58
18.80
18.80
0.33
38.10
18.03
2.29
3.05
14.99
–
0.43
18.03
37.34
Millimeters
Max.
9.53
Min.
0.38
A1
4201975/A 03/01
1.670
D/32 PIN 1.700 42.42 43.18
2.070
D/40 PIN 2.100 52.58 53.34
0.075
S0.110 1.91 2.79
0.365 9.27
0.008 0.20
0.105
S/12 PIN 0.130 2.67 3.30
e
A
C
S
L
G
B
E
D
NOTES: A. All linear dimensions are in inches (mm).
B. This drawing is subject to change without notice.
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