2
PIN NAMES
DEVICE OPERATION
The UT67164 has four control inputs called Enable 1 (E1),
Enable 2 (E2), Write Enable (W), and Output Enable (G); 13
address inputs, A(12:0); and eight bidirectional data lines,
DQ(7:0). E1 and E2 are device enable inputs that control device
selection, active, and standby modes. Asserting both E1 and E2
enables the device, causes IDD to rise to its active value, and
decodes the 13 address inputs to select one of 8,192 words in
the memory. W controls read and write operations. During a read
cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min), E1 less than VIL
(max), and E2 greater than VIH (min) defines a read cycle. Read
access time is measured from the latter of device enable, Output
Enable, or valid address to valid data output.
Read Cycle 1, the Address Access read in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified tAVQV is satisfied. Outputs remain
active throughout the entire cycle. As long as device enable and
output enable are active, the address inputs may change at a rate
equal to the minimum read cycle time (tAVAV ).
Figure 3b shows Read Cycle 2, the Chip Enable-controlled
Access. For this cycle, G remains asserted, W remains
deasserted, and the addresses remain stable for the entire cycle.
After the specified tETQV is satisfied, the eight-bit word
addressed by A(12:0) is accessed and appears at the data outputs
DQ(7:0).
Figure 3c shows Read Cycle 3, the Output Enable-controlled
Access. For this cycle, E1 and E2 are asserted, W is deasserted,
and the addresses are stable before G is enabled. Read access
time is tGLQV unless tAVQV or tETQV have not been satisfied.
A(12:0) Address WWrite
DQ(7:0) Data Input/Output GOutput Enable
E1 Enable 1 VDD Power
E21Enable 2 VSS Ground
128
227
326
425
524
623
722
821
920
10 19
11 18
12 17
13 16
14 15
Figure 2. SRAM Pinout
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
VDD
W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
GWE1 E2 I/O Mode Mode
X1 X X 03-state Standby
X X 1X3-state Standby
X001Data in Write
11013-state Read2
0101Data out Read