| FAIRCHILD eer pepe SEMICONDUCTOR 74AC174 + 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip- flops. Features lB loc reduced by 50% Hi Outputs source/sink 24 mA November 1988 Revised January 1999 @ ACT174 has TTL-compatible inputs Ordering Code: Order Number | Package Number Package Description 74AC1748C M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body 74AC1748J M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.8mm Wide 74AC174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT1748C M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT1748J M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.8mm Wide 74ACT174MTG MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Logic Symbols Litt Do D, Dy Dy Dy Dy rcPr Opve % & OQ Q Os ITT ttl IEEE/IEC MR cP Dg D, De Ds Dy Ds, FACT is a trademark of Fairchild Semiconductor Corporation. Q% Q Q Os Q Qs, Connection Diagram Pin Assignment for DIP and SOIC _ YY wR 1 161Voo Q42 15,05 Do-43 14;D, d-44 13}D, as 12a, Do46 11}D; Q-7 10F-05 GND-48 9f-cCP Pin Descriptions Pin Names Description Do-Ds Data Inputs cP Clock Pulse Input MR Master Reset Input Qo-Qs5, Outputs 1999 Fairchild Semiconductor Corporation DS009935.prf www.fairchildsemi.com yesoy Ja1SeW YM dojg-dij4 odAL-q X9H PZLLOVPZ * PLLOWPL74AC174 - 74ACT174 Functional Description Truth Table The AC/ACT174 consists of six edge-triggered D-type flip- flops with individual D inputs and Q outputs. The Clock Inputs Output (CP) and Master Reset (MR) are common to all flip-flops. MR cp D Q Each D input's state is transferred to the corresponding flip- flop's output following the LOW-to-HIGH Clock (CP) transi- L x x L tion. A LOW input to the Master Reset (MR) will force all H LY H H outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for applications where the true output H z~ L L only is required and the Clock and Master Reset are com- 4 L x Q mon to all storage elements. H = HIGH Voltage Level L = LOW Voltage Level ~~ = LOW-to-HIGH Transition X = Immaterial Logic Diagram m cp Os Dg Ds Dy D, Do I I lJ I l Qs, % Qs, Q Q Q Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. No www.fairchildsemi.comAbsolute Maximum Ratingsinote 1) Supply Voltage (Vcc) DC Input Diode Current (I),) Vv, =-0.5V Vi=Veco + 0.5V DC Input Voltage (V)) DC Output Diode Current (lox) Vo =-0.5V V=Voco + 0.5V DC Output Voltage (Vo) DC Output Source or Sink Current (lo) DC Vee or Ground Current per Output Pin (leg or lenp) Storage Temperature (Tstq) Junction Temperature (Ty) PDIP 0.5V to +7.0V -20 mA +20 mA -0.5V to Vec +0.5V -20 mA +20 mA -0.5V to V ce + 0.5V +50 mA +50 mA -65C to +150C 140C DC Electrical Characteristics for AC Recommended Operating Conditions Supply Voltage (Vcc) AC ACT Input Voltage (Vj) Output Voltage (Vo) Operating Temperature (Ta) Minimum Input Edge Rate (AV/At) AC Devices Vin from 30% to 70% of Veco Veco @ 3.3, 4.5V, 5.5V Minimum Input Edge Rate (AV/At) ACT Devices Vin from 0.8V to 2.0V Voc @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 2.0V to 6.0V 4.5V to 5.5V OV to Voc OV to Voc 40C to +85C 125 mV/ns 125 mV/ns Symbol Parameter Veco Ty, = +25C Ta =40C to +85C Units Conditions (V) Typ Guaranteed Limits Vin Minimum High Level 3.0 1.5 2.1 2.1 Vout =0.1V Input Voltage 4.5 2.25 3.15 3.15 v or Voc 0.1V 5.5 2.75 3.85 3.85 Vit Maximum Low Level 3.0 1.5 0.9 0.9 Vout =0.1V Input Voltage 4.5 2.25 1.35 1.35 v or Veg 0.1V 5.5 2.75 1.65 1.65 Vou Minimum High Level 3.0 2.99 29 29 lout = 50 pA Output Voltage 45 4.49 44 44 Vv 5.5 5.49 5.4 5.4 Vin = Vit or Vin 3.0 2.56 2.46 lon =12 mA 45 3.86 3.76 Vv lo =-24 mA 5.5 4.86 4.76 lou = 24 mA (Note 2) VoL Maximum Low Level 3.0 0.002 0.1 0.1 lout = 50 pA Output Voltage 45 0.001 0.1 0.1 Vv 5.5 0.001 0.1 0.1 Vin = Vit or Vin 3.0 0.36 0.44 lol =12 mA 45 0.36 0.44 Vv lo, = 24 mA 5.5 0.36 0.44 lot = 24 mA(Note 2) lI Maximum Input 5.5 +0.1 +1.0 pA Vi=Veco (Note 4) Leakage Current or GND Top | Minimum Dynamic 5.5 75 mA |Vop = 1.65V Max lou Output Current (Note 3) 55 75 mA Voup = 3.85V Min loc Maximum Quiescent 5.5 4.0 40.0 pA Vin=Vec (Note 4) Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: |, and Ig @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V Vg. www.fairchildsemi.com PLILLOVbZ * PLZLOWPL74AC174 - 74ACT174 DC Electrical Characteristics for ACT Symbol Parameter Veco Ta =+25C Ta =40C to +85C Units oe Conditions (V) Typ Guaranteed Limits Vin Minimum High Level 45 1.5 2.0 2.0 Vv Vout = 0.1V Input Voltage 5.5 1.5 2.0 2.0 or Veg 0.1V VIL Maximum Low Level 4.5 1.5 0.8 0.8 v Vout = 0.1V Input Voltage 5.5 1.5 0.8 0.8 or Veg 0.1V Vou Minimum High Level 45 449 44 44 Vv lout =-50 pA Output Voltage 5.5 5.49 5.4 5.4 Vin = Vit or Vin 45 3.86 3.76 Vv loy =-24 mA 5.5 4.86 4.76 loy =-24 mA (Note 5) Voi Maximum Low Level 4.5 0.001 0.1 0.1 v lout = 50 pA Output Voltage 5.5 0.001 0.1 0.1 Vin = Vit or Vin 45 0.36 0.44 Vv lo. = 24 mA 5.5 0.36 0.44 lo. = 24 mA (Note 5) In Maximum Input 5.5 +0.1 +1.0 pA Vi = Veco, GND Leakage Current loot Maximum 5.5 0.6 1.5 mA Vi=Veo-2.1V Ioc/Input lotp Minimum Dynamic 5.5 75 mA Vo_p = 1.65V Max loup Output Current (Note 6) 5.5 75 mA Voup = 3.85V Min loc Maximum Quiescent 5.5 4.0 40.0 pA Vin=Vec Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Ta =+28C Ty, =40C to +85C Vec A A Symbol Parameter (vy) C1 = 50 pF C1 =50 pF Units (Note 7) Min Typ Max Min Max fmax Maximum Clock 3.3 90 100 70 MHz Frequency 5.0 100 125 100 teLH Propagation Delay 3.3 2.0 9.0 11.5 1.5 12.5 ns CP toQ, 5.0 1.5 6.0 8.5 1.0 9.5 tPHL Propagation Delay 3.3 2.0 8.5 11.0 1.5 12.0 ns CP toQ, 5.0 1.5 6.0 8.0 1.0 9.0 tPHL Propagation Delay 3.3 2.5 9.0 11.5 2.0 12.5 ns MR toQ, 5.0 15 7.0 9.0 15 10.5 Note 7: Voltage Range 3.3 is 3.3V +0.3V Voltage Range 5.0 is 5.0V +0.5V www.fairchildsemi.com 4AC Operating Requirements for AC Ta = +28C Ta =40C to +85C Symbol Parameter we C_ = 50 pF C_ = 50 pF Units (Note 8) Typ Guaranteed Minimum tg Setup Time, HIGH or LOW 3.3 2.5 65 7.0 ns D, to CP 5.0 2.0 5.0 5.5 ty Hold Time, HIGH or LOW 3.3 1.0 3.0 3.0 ns D, to CP 5.0 0.5 3.0 3.0 tw MR Pulse Width, LOW 3.3 1.0 5.5 7.0 ns 5.0 1.0 5.0 5.0 tw CP Pulse Width 3.3 1.0 5.5 7.0 ns 5.0 1.0 5.0 5.0 trec Recovery Time 3.3 0 2.5 2.5 ns MR to CP 5.0 0 2.0 2.0 Note 8: Voltage Range 3.3 is 3.3V 10.3V Voltage Range 5.0 is 5.0V +0.5V AC Electrical Characteristics for ACT Vee Ta =+28C Ta =40C to +85C Symbol Parameter (Vv) C1 = 50 pF Ci = 50 pF Units (Note 9) Min Typ Max Min Max fmax Maximum Clock 5.0 165 200 140 MHz Frequency teLH Propagation Delay 5.0 1.5 7.0 10.5 1.5 11.5 ns CP toQ, tPHL Propagation Delay 5.0 1.5 7.0 10.5 1.5 11.5 ns CP toQ, tPHL Propagation Delay 5.0 1.5 6.5 9.5 1.5 11.0 ns MR to Q, Note 9: Voltage Range 5.0 is 5.0V +0.5V AC Operating Requirements for ACT Vee Ta =+28C Ta =40C to +85C Symbol Parameter (V) C1 = 50 pF C= 50 pF Units (Note 10) Typ Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 0.5 1.5 1.5 ns D, to CP ty Hold Time, HIGH or LOW 5.0 1.0 2.0 2.0 ns D, to CP tw MR Pulse Width, LOW 5.0 1.5 3.0 3.5 ns tw CP Pulse Width, HIGH OR LOW 5.0 1.5 3.0 3.5 ns trec Recovery Time 5.0 -1.0 0.5 0.5 ns MR to CP Note 10: Voltage Range 5.0 is 5.0V +0.5V Capacitance Symbol Parameter Typ Units Conditions Cn Input Capacitance 4.5 pF Voc = OPEN Cpp Power Dissipation Capacitance 85.0 pF Voc = 5.0V www.fairchildsemi.com PLILLOVbZ * PLZLOWPL74AC174 - 74ACT174 0.150-0.157 (3.B103.968) o.0w-o020 10.254 0.508) [" 7 0,008 0.010 {0.203-0.254) TYP ALL LEADS 6.008 (0.102) ALL LEAD TIPS. J 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body FBRARRBA Physical DimensiONS inches (millimeters) unless otherwise noted 0.386 0.394 igao410.0) | 16 % 1413 12 1 110 Q 0.280.244 30: (5.791 6.198) TYP > Oe a LEAD NOt 1 2 3 4 5 6 7 68 IDENT ond MAX (0.254) 0.053~0.069 (1.346 1.753) 0.004 0.010 B MAX TYP 40.102 0.254) ALL LEADS Tl 7 a =H. SEATING oF A PLANE | 0.014 Ata 0.060 0.014 ~0.020 D016 0.050 2.050 _>| TYP Tone 1270; (0.356) (1.270) 10.356 0.508) : TYP TYP ALL LEADS 0.008 ei To.203) YP via ev Package Number M16A 0.295-0.319 (7.5-8.1) 0.205-0.213 (5.2-5.4) | POGEREEE 16-Lead Small Outline Package (SOP), EIAJ TYPE Il, 5.3mm Wide Package Number M16D 0.394-0.402 0.71 0.006-0.010 (10.0-10.2) (ay? Vaasa sy TP | [ \ 0.067-0.083 tt iy rir li Pieri / G.7-2.1) o-8 TYP { Q|0.006 (0.15) eee - SEATING tO 0.049 _ PLANE 0.000-0.010 (Ggsy TYP) (0-9.25) 0.016-0.031 9.014-0.020 1, ag > ~(0.4-0.8) TYP {0.35-0.50) M16D (REV B) www.fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted (Continued) U4 Tr Tu te ia g 4440.1 1 - 1.78 [She FER) 0.654 _- Loz ALL LEAL TIP: LAND PATTERN RECOMMENDATION cEE DETAIL & ALL LEAD TIPS La MAY poeta _ i 0 = SRSA, C LL | osoenos - ~NF _ O9-20 7 Vo a _ 7 12.00' TOF 2 BOTTOM PU, le- PULSE __| NOTES i _ oe + A, CONFORMS TO JEDEC PEGISTPATION MO-1S3 VAPIATION AE. ms as Lf - PEF NOTE 6, DATED 7/93 i Cc _ B, DIMENSIONS ARE IN MILLIMETER? vi C, DIMENSION? ARE EXCLUSIVE OF BUPP3. MOLD FLASH, O.ckO, AND TIE BAR EXTRUSION: Lan DETAIL A SEATING PLANE 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com PLILLOVbZ * PLZLOWPL74AC174 + 74ACT174 Hex D-Type Flip-Flop with Master Reset Physical DimensiONS inches (millimeters) unless otherwise noted (Continued) 0.740 - 0,780 0.090 18.80 19.81 ies ( ) >| (2.286) Ei INDEX AREA 0.250 0.010 (6.350 0.254) PIN NO. 1 PIN NO. 1 went LY 2] By 4! BD) 6) ZI IDENT OPTION 01 OPTION 02 0.0865 0.130 0,005 (0-130 0.005_ 0.060 4 TYP 0,300 - 0.320 (1.651) \ (3.302 0.127) =| [- Crsaa) TYP [> oprionaL 7 (7.620 = 8.128) { 0.145 = 0.200 ! | (3.683-5.080) + | | f f 95? 5 0.008- 0.016 90 4 TYP open TYP (0508) win 4 0.280 {0.203 - 0.406) 0.125 = 0.150 0.030 40.015 (7.112) (175 =3.810) im (0.762 0.381) MIN 0.014 = 0.023 0.1000.010 +0.040 (0.356-0.584) +| (2.54020.254) (0.325915 Wp 0.050 0.010 TP NIE (REV F) (1.2700.254) (8.255 ot) TYP 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild coes not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairctild reserves the right at any time without notice to change said circuitry and spedifications.