REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD8110/AD8111
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
260 MHz, 16 8 Buffered
Video Crosspoint Switches
FEATURES
16 8 High-Speed Nonblocking Switch Arrays
AD8110: G = +1
AD8111: G = +2
Serial or Parallel Switch Array Control
Serial Data Out Allows “Daisy Chaining” of Multiple
Crosspoints to Create Larger Switch Arrays
Pin-Compatible with AD8108/AD8109 8 8 Switch
Arrays
For a 16 16 Array See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers, AD8110 (G = +1),
AD8111 (G = +2)
Drives 150 V Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02% Differential Gain Error (RL = 150 V)
0.028 Differential Phase Error (RL = 150 V)
Excellent AC Performance
260 MHz –3 dB Bandwidth
500 V/ms Slew Rate
Low Power of 50 mA
Low All Hostile Crosstalk of –78 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead LQFP Package (12 mm 12 mm)
APPLICATIONS
Routing of High-Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
FUNCTIONAL BLOCK DIAGRAM
AD8110/AD8111
SWITCH
MATRIX
OUTPUT
BUFFER
G = +1,
G = +2
40
40
128
40-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
PARALLEL LATCH
DECODE
8 5:16 DECODERS
8
CLK
DATA IN
UPDATE
CE
RESET
16 INPUTS
A0
DATA
OUT
8 OUTPUTS
SET INDIVIDUAL
OR RESET ALL
OUTPUTS
TO "OFF"
A1
A2
SER/PAR D0 D1 D2 D3
ENABLE/DISABLE
D4
PRODUCT DESCRIPTION
The AD8110 and AD8111 are high-speed 16 × 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 260 MHz, and channel switch times of less than
25 ns with 1% settling. With –78 dB of crosstalk and –97 dB
isolation (@ 5 MHz), the AD8110/AD8111 are useful in many
high-speed applications. The differential gain and differential
phase of better than 0.02% and 0.02° respectively, along with
0.1 dB flatness out to 60 MHz, make the AD8110/AD8111
ideal for video signal switching.
The AD8110 and AD8111 include eight independent output
buffers that can be placed into a high impedance state for paral-
leling crosspoint outputs so that off channels do not load the
output bus. The AD8110 has a gain of +1, while the AD8111
offers a gain of +2. They operate on voltage supplies of ±5 V
while consuming only 50 mA of idle current. The channel
switching is performed via a serial digital control (which can
accommodate “daisy chaining” of several devices) or via a parallel
control, allowing updating of an individual output without repro-
gramming the entire array.
The AD8110/AD8111 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
REV. A
–2–
AD8110/AD8111–SPECIFICATIONS
(VS = ⴞ5 V, TA = +25ⴗC, RL = 1 k⍀ unless otherwise noted.)
AD8110/AD8111
Parameter Conditions Min Typ Max Unit Reference
DYNAMIC PERFORMANCE
–3 dB Bandwidth 200 mV p-p, R
L
= 150 Ω300/190 390/260 MHz TPC 1, 7
2 V p-p, R
L
= 150 Ω150 MHz TPC 1, 7
Propagation Delay 2 V p-p, R
L
= 150 Ω5ns
Slew Rate 2 V Step, R
L
= 150 Ω500 V/µs
Settling Time 0.1%, 2 V Step, R
L
= 150 Ω40 ns TPC 6, 12
Gain Flatness 0.05 dB, 200 mV p-p, R
L
= 150 Ω60/40 MHz TPC 1, 7
0.05 dB, 2 V p-p, R
L
= 150 Ω65/40 MHz TPC 1, 7
0.1 dB, 200 mV p-p, R
L
= 150 Ω80/57 MHz TPC 1, 7
0.1 dB, 2 V p-p, R
L
= 150 Ω70/57 MHz TPC 1, 7
NOISE/DISTORTION PERFORMANCE
Differential Gain Error NTSC or PAL, R
L
= 1 kΩ0.01 %
NTSC or PAL, R
L
=150 Ω0.02 %
Differential Phase Error NTSC or PAL, R
L
= 1 kΩ0.01 Degrees
NTSC or PAL, R
L
= 150 Ω0.02 Degrees
Crosstalk, All Hostile f = 5 MHz 78/85 dB TPC 2, 8
f = 10 MHz 70/80 dB TPC 2, 8
Off Isolation, Input-Output f = 10 MHz, R
L
=150 Ω, One Channel 93/99 dB TPC 17, 23
Input Voltage Noise 0.01 MHz to 50 MHz 15 nV/
√
Hz TPC 14, 20
DC PERFORMANCE
Gain Error R
L
= 1 kΩ0.04/0.1 0.07/0.5 %
R
L
= 150 Ω0.15/0.25 %
Gain Matching No Load, Channel-Channel 0.02/1.0 %
R
L
= 1 kΩ, Channel-Channel 0.09/1.0 %
Gain Temperature Coefficient 0.5/8 ppm/°C
OUTPUT CHARACTERISTICS
Output Impedance DC, Enabled 0.2 Ω18, 24
Disabled 10/0.001 MΩ15, 21
Output Disable Capacitance Disabled 2 pF
Output Leakage Current Disabled, AD8110 Only 1/NA µA
Output Voltage Range No Load ±2.5 ±3V
Output Current 20 40 mA
Short Circuit Current 65 mA
INPUT CHARACTERISTICS
Input Offset Voltage Worst Case (All Configurations) 5 20 mV 29, 35
Temperature Coefficient 12 µV/°C 30, 36
Input Voltage Range ±2.5/±1.25 ±3/±1.5 V
Input Capacitance Any Switch Configuration 2.5 pF
Input Resistance 1 10 MΩ
Input Bias Current Per Output Selected 2 5 µA
SWITCHING CHARACTERISTICS
Enable On Time 60 ns
Switching Time, 2 V Step 50% UPDATE to 1% Settling 25 ns
Switching Transient (Glitch) Measured at Output 20/30 mV p-p 16, 22
POWER SUPPLIES
Supply Current AVCC, Outputs Enabled, No Load 38 mA
AVCC, Outputs Disabled 15 mA
AVEE, Outputs Enabled, No Load 38 mA
AVEE, Outputs Disabled 15 mA
DVCC 11 mA
Supply Voltage Range ±4.5 to ±5.5 V
PSRR f = 100 kHz 75/78 dB 13, 19
f = 1 MHz –55/–58 dB
OPERATING TEMPERATURE RANGE
Temperature Range Operating (Still Air) –40 to +85 °C
θ
JA
Operating (Still Air) 48 °C/W
Specifications subject to change without notice.
REV. A
AD8110/AD8111
–3–
TIMING CHARACTERISTICS (Serial)
Limit
Parameter Symbol Min Typ Max Unit
Serial Data Setup Time t
1
20 ns
CLK Pulsewidth t
2
100 ns
Serial Data Hold Time t
3
20 ns
CLK Pulse Separation, Serial Mode t
4
100 ns
CLK to UPDATE Delay t
5
0ns
UPDATE Pulsewidth t
6
50 ns
CLK to DATA OUT Valid, Serial Mode t
7
180 ns
Propagation Delay, UPDATE to Switch On or Off – 8 ns
Data Load Time, CLK = 5 MHz, Serial Mode – 8 µs
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
1
0
1
0
1 = LATCHED
0 = TRANSPARENT
DATA OUT
CLK
DATA IN OUT7 (D4) OUT7 (D3) OUT00 (D0)
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
2
t
4
t
1
t
3
t
7
t
5
t
6
UPDATE
Figure 1. Timing Diagram, Serial Mode
Table I. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, DATA IN, CLK, DATA IN, CLK, DATA IN, CLK, DATA IN,
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min
REV. A
AD8110/AD8111
–4–
TIMING CHARACTERISTICS (Parallel)
Limit
Parameter Symbol Min Max Unit
Data Setup Time t
1
20 ns
CLK Pulsewidth t
2
100 ns
Data Hold Time t
3
20 ns
CLK Pulse Separation t
4
100 ns
CLK to UPDATE Delay t
5
0ns
UPDATE Pulsewidth t
6
50 ns
Propagation Delay, UPDATE to Switch On or Off – 8 ns
CLK, UPDATE Rise and Fall Times – 100 ns
RESET Time – 200 ns
t5t6
t4
t2
t1t3
1
0
1
0
1 = LATCHED
CLK
D0–D4
A0–A2
0 = TRANSPARENT
UPDATE
Figure 2. Timing Diagram, Parallel Mode
Table II. Logic Levels
V
IH
V
IL
V
OH
V
OL
I
IH
I
IL
I
OH
I
OL
RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR RESET, SER/PAR
CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2, CLK, D0, D1, D2,
D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2 D3, D4, A0, A1, A2
CE, UPDATE CE, UPDATE DATA OUT DATA OUT CE, UPDATE CE, UPDATE DATA OUT DATA OUT
2.0 V min 0.8 V max 2.7 V min 0.5 V max 20 µA max –400 µA min –400 µA max 3.0 mA min
REV. A
AD8110/AD8111
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8110/AD8111 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V
Internal Power Dissipation
2
AD8110/AD8111 80-Lead Plastic LQFP (ST) . . . . . 2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
S
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T
A
= 25°C):
80-lead plastic LQFP (ST): θ
JA
= 48°C/W.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8110/AD8111 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
While the AD8110/AD8111 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
AMBIENT TEMPERATURE – ⴗC
5.0
MAXIMUM POWER DISSIPATION – Watts
4.0
0
–50 80–40 –30 –20 –10 0 10 20 30 40 50 60 70
3.0
2.0
1.0
TJ = 150ⴗC
90
Figure 3. Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8110AST –40°C to +85°C 80-Lead Plastic LQFP (12 mm × 12 mm) ST-80A
AD8111AST –40°C to +85°C 80-Lead Plastic LQFP (12 mm × 12 mm) ST-80A
AD8110-EB Evaluation Board
AD8111-EB Evaluation Board
REV. A
AD8110/AD8111
–6–
Table III. Operation Truth Table
SER/
CE UPDATE CLK DATA IN DATA OUT RESET PAR Operation/Comment
1 X X X X X X No change in logic.
01 fData
i
Data
i-40
1 0 The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 40
clocks later.
01 fD0 . . . D4, NA in Parallel 1 1 The data on the parallel data lines, D0–D4, are
A0...A2 Mode loaded into the 40-bit serial shift register loca-
tion addressed by A0–A2.
0 0 X X X 1 X Data in the 40-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
X X X X X 0 X Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D
CLK
Q
3 TO 8 DECODER
A0
A1
A2
CLK
CE
UPDATE
8
128
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
RESET
(OUTPUT ENABLE)
OUT0 EN
DATA
OUT
PARALLEL
DATA
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
D1
D2
D3
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
DQ
CLK
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D
LE
QCLR
OUT7
EN
OUTPUT ENABLE
SWITCH MATRIX
S
D1
Q
D0
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
DQ
CLK
S
D1
Q
D0
D4
DECODE
D
LE
QCLR
OUT0
EN
D
LE
OUT0
B0
Q
D
LE
Q
OUT0
B1
D
LE
Q
OUT0
B2
D
LE
Q
OUT0
B3
D
LE
OUT1
B0
Q
D
LE
QCLR
OUT6
EN
D
LE
OUT7
B0
Q
D
LE
OUT7
B1
Q
D
LE
OUT7
B2
Q
DQ
CLK
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT7
B3
Q
S
D1
Q
D0
Figure 4. Logic Diagram
REV. A
AD8110/AD8111
–7–
PIN FUNCTION DESCRIPTIONS
Pin Name Pin Numbers Pin Description
INxx 66, 68, 70, 72, 74, 76, 78, Analog Inputs; xx = Channel Numbers 00 Through 15.
1, 3, 5, 7, 9, 11, 13, 15, 64
DATA IN 57 Serial Data Input, TTL Compatible.
CLK 58 Clock, TTL Compatible. Falling Edge Triggered.
DATA OUT 59 Serial Data Out, TTL Compatible.
UPDATE 56 Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “High.”
RESET 61 Disable Outputs, Active “Low.”
CE 60 Chip Enable, Enable “Low.” Must be “low” to clock in and latch data.
SER/PAR 55 Selects Serial Data Mode, “Low” or Parallel Data Mode, “High.” Must be connected.
OUTyy 41, 38, 35, 32, 29, 26, 23, 20 Analog Outputs yy = Channel Numbers 00 Through 07.
AGND 2, 4, 6, 8, 10, 12, 14, 16, 46 Analog Ground for Inputs and Switch Matrix.
65, 67, 69, 71, 73, 75, 77
DVCC 63, 79 5 V for Digital Circuitry.
DGND 62, 80 Ground for Digital Circuitry.
AVEE 17, 45 –5 V for Inputs and Switch Matrix.
AVCC 18, 44 +5 V for Inputs and Switch Matrix.
AGNDxx 42, 39, 36, 33, 30, 27, 24, 21 Ground for Output Amp, xx = Output Channel Numbers 00 Through 07. Must be connected.
AVCCxx/yy 43, 37, 31, 25, 22, 19 +5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
AVEExx/yy 40, 34, 28, 22 –5 V for Output Amplifier that is shared by Channel Numbers xx and yy. Must be connected.
A0 54 Parallel Data Input, TTL Compatible (Output Select LSB).
A1 53 Parallel Data Input, TTL Compatible (Output Select).
A2 52 Parallel Data Input, TTL Compatible (Output Select MSB).
D0 51 Parallel Data Input, TTL Compatible (Input Select LSB).
D1 50 Parallel Data Input, TTL Compatible (Input Select).
D2 49 Parallel Data Input, TTL Compatible (Input Select).
D3 48 Parallel Data Input, TTL Compatible (Input Select MSB).
D4 47 Parallel Data Input, TTL Compatible (Output Enable).
ESD
ESD
INPUT
VCC
AVEE
ESD
ESD
OUTPUT
VCC
AVEE
1k
(AD8111 ONLY)
ESD
ESD
RESET
VCC
20k
DGND
ESD
ESD
INPUT
VCC
DGND
ESD
ESD
OUTPUT
VCC
2k
DGND
Figure 5. I/O Schematics
a. Analog Input b. Analog Output c.
Reset
Input
d. Logic Input e. Logic Output
REV. A
AD8110/AD8111
–8–
PIN CONFIGURATION
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
56
57
58
59
54
55
52
53
50
51
60
45
46
47
48
43
44
42
49
41
5
4
3
2
7
6
9
8
1
11
10
16
15
14
13
18
17
20
19
12
PIN 1
IDENTIFIER
TOP VIEW
(PINS DOWN)
0.5mm LEAD PITCH
AD8110/AD8111
16 8
80L LQFP
(12mm 12mm)
40
39
38
37
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
36
DGND
DVCC
IN07
AGND
IN06
AGND
IN05
AGND
IN04
AGND
IN03
AGND
IN02
AGND
IN01
AGND
IN00
DVCC
DGND
RESET
AGND07
AVEE06/07
OUT06
AGND06
AVCC05/06
OUT05
AGND05
AVEE04/05
OUT04
AGND04
AVCC03/04
OUT03
AGND03
AVEE02/03
OUT02
AGND02
AVCC01/02
OUT01
AGND01
CE
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
A0
A1
A2
D0
D1
D2
D3
D4
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00
IN08
AGND
IN09
AGND
IN10
AGND
IN11
AGND
IN12
AGND
IN13
AGND
IN14
AGND
IN15
AGND
AVEE
AVCC
AVCC07
OUT07
AVEE00/01
REV. A –9–
Typical Performance Characteristics–AD8110/AD8111
FREQUENCY – Hz
GAIN – dB
–2
1
0
–1
–3
100k 1M 1G10M 100M
FLATNESS – dB
0.2
0.1
0
–0.1
–0.2
–0.3
GAIN
FLATNESS
2
3
0.3
4
5
200mV p-p
2V p-p
RL = 150
TPC 1. AD8110 Frequency Response
FREQUENCY – MHz
CROSSTALK – dB
–30
–40
–100
0.3 1 20010 100
–50
–60
–70
–80
–90
ADJACENT
ALL HOSTILE
RL = 1k
TPC 2. AD8110 Crosstalk vs. Frequency
FREQUENCY – Hz
DISTORTION – dB
100k 1M 100M10M
–100
–40
–50
–60
–70
–80
–90
2ND HARMONIC
3RD HARMONIC
R
L
= 150
V
OUT
= 2V p-p
TPC 3. AD8110 Distortion vs. Frequency
50
25
0
25
50
25ns/DIV
25mV/DIV
RL = 150
TPC 4. AD8110 Step Response, 100 mV Step
1
0.5
0
0.5
1
25ns/DIV
0.5V/DIV
R
L
= 150
TPC 5. AD8110 Step Response, 2 V Step
2V STEP
R
L
= 150
0 10 20304050607080
10ns/DIV
0.1%/DIV
TPC 6. AD8110 Settling Time
REV. A
AD8110/AD8111
–10–
FREQUENCY – Hz
GAIN – dB
–2
1
0
–1
–3
100k 1M 1G10M 100M
FLATNESS – dB
0.4
0.2
0
–0.2
–0.4
2
3
0.6
GAIN
FLATNESS
–0.6
0.8
200mV p-p
2V p-p
–0.8
4
5
TPC 7. AD8111 Frequency Response
FREQUENCY – MHz
CROSSTALK – dB
–20
–30
–90
0.3 1 20010 100
–40
–50
–60
–70
–80
–100
–110
RL = 1k
ADJACENT
ALL HOSTILE
TPC 8. AD8111 Crosstalk vs. Frequency
FREQUENCY Hz
DISTORTION dB
30
40
100
100k 1M 100M10M
50
60
70
80
90
2ND HARMONIC
3RD HARMONIC
R
L
= 150
V
OUT
= 2V p-p
TPC 9. AD8111 Distortion vs. Frequency
50
25
0
25
50
25ns/DIV
25mV/DIV
TPC 10. AD8111 Step Response, 100 mV Step
1
0.5
0
0.5
1
25ns/DIV
500mV/DIV
TPC 11. AD8111 Step Response, 2 V Step
2V STEP RTO
R
L
= 150
0 10 20304050607080
10ns/DIV
0.1%/DIV
TPC 12. AD8111 Settling Time
REV. A
AD8110/AD8111
–11–
FREQUENCY Hz
POWER SUPPLY REJECTION dB
30
40
10k 100k 10M1M
50
60
70
80
90
R
L
= 150
TPC 13. AD8110 PSRR vs. Frequency
FREQUENCY Hz
100
56.3
10 1k 10M
100k
31.6
17.
8
10
5.63
3.16
100 10k 1M
nV/ Hz
TPC 14. AD8110 Voltage Noise vs. Frequency
FREQUENCY MHz
OUTPUT IMPEDANCE
1M
0.1 1 50010
100k
10k
1k
100
100
TPC 15. AD8110 Output Impedance, Disabled
UPDATE INPUT
TYPICAL VIDEO OUT (RTO)
5
4
3
2
1
0
10
–10
0
50ns/DIV
10mV/DIV 1V/DIV
SWITCHING BETWEEN
TWO INPUTS
TPC 16. AD8110 Switching Transient (Glitch)
FREQUENCY – Hz
OFF ISOLATION – dB
100k 1M 500M10M 100M
VIN = 2V p-p
RL = 150
–50
–60
–70
–80
–90
–100
–110
–120
–130
TPC 17. AD8110 Off Isolation, Input-Output
10,000
1000
100
10
1
0.1
FREQUENCY – Hz
OUTPUT IMPEDANCE –
100k 1M 500M10M 100M
TPC 18. AD8110 Output Impedance, Enabled
REV. A
AD8110/AD8111
–12–
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB RTI
10k 100k 1M 10M
–30
–40
–50
–60
–70
–80
R
L
= 150
TPC 19. AD8111 PSRR vs. Frequency
FREQUENCY Hz
100
56.3
10 1k 10M
100k
31.6
17.8
10
5.63
3.16
100 10k 1M
nV/ Hz
TPC 20. AD8111 Voltage Noise vs. Frequency
FREQUENCY MHz
OUTPUT IMPEDANCE
100k
0.1 1 50010
10k
1k
100
10
100
TPC 21. AD8111 Output Impedance, Disabled
1V/DIV
UPDATE INPUT
TYPICAL VIDEO OUT (RTO)
10mV/DIV
5
4
3
2
1
0
10
0
–10
50ns/DIV
SWITCHING BETWEEN
TWO INPUTS
TPC 22. AD8111 Switching Transient (Glitch)
FREQUENCY – Hz
OFF ISOLATION – dB
100k 1M 500M10M 100M
–60
–80
–100
–120
–130
–110
–90
–70
–50
V
OUT
= 2V p-p
R
L
= 150
–40
`
TPC 23. AD8111 Off Isolation, Input-Output
FREQUENCY Hz
OUTPUT IMPEDANCE
1k
100k 1M 500M10M
100
10
1
0.1
100M
TPC 24. AD8111 Output Impedance, Enabled
REV. A
AD8110/AD8111
–13–
INPUT IMPEDANCE –
1M
100k
10k
1k
100
10M
30k 100k 1M 10M 100M 500M
FREQUENCY – Hz
TPC 25. AD8110 Input Impedance vs. Frequency
FREQUENCY – Hz
GAIN – dB
14
12
–4
0.1M 1M 10M 100M 1G
10
8
0
6
4
2
–2
18pF = 7.7dB
12pF = 4.5dB
3G
VIN = 200mV p-p
RL = 150
TPC 26. AD8110 Frequency Response vs. Capacitive Load
FREQUENCY – Hz
FLATNESS – dB
0.7
0.6
–0.2
0.1M 1M 10M 100M 1G
0.5
0.4
0
0.3
0.2
0.1
–0.1
V
IN
= 200mV p-p
R
L
= 150
C
L
= 18pF
C
L
= 12pF
3G
TPC 27. AD8110 Flatness vs. Capacitive Load
V
OUT
UPDATE
INPUT 1 AT +1V
INPUT 0 AT –1V
1
0
–1
5
0
50ns/DIV
2V/DIV 1V/DIV
TPC 28. AD8110 Switching Time
OFFSET VOLTAGE – Volts
FREQUENCY
260
60
–0.020 –0.010 0.000 0.010
240
180
160
120
80
220
200
140
100
40
20
0
0.020
TPC 29. AD8110 Offset Voltage Distribution
TEMPERATURE – C
V
OS
– mV
2.0
–2.0
–60 –40 100–20 0 20 40 60 80
1.5
0
–0.5
–1.0
–1.5
1.0
0.5
TPC 30. AD8110 Offset Voltage vs. Temperature
(Normalized at 25
°
C)
REV. A
AD8110/AD8111
–14–
FREQUENCY – Hz
INPUT IMPEDANCE –
30k 1M 500M10M 100M
1M
100k
10k
1k
100
100k
10M
TPC 31. AD8111 Input Impedance vs. Frequency
GAIN – dB
12
10
–6
8
6
–2
4
2
0
–4
FREQUENCY – Hz
0.1M 1M 10M 100M 1G 3G
18pF
12pF
TPC 32. AD8111 Frequency Response vs. Capacitive Load
GAIN – dB
0.7
0.6
–0.1
0.5
0.4
0
0.3
0.2
0.1
–0.2
–0.3
FREQUENCY – Hz
0.1M 1M 10M 100M 1G 3G
12pF
18pF
VIN = 100mV
RL = 150
TPC 33. AD8111 Flatness vs. Capacitive Load
V
OUT
UPDATE
INPUT 1 AT +1V
INPUT 0 AT –1V
1
0
–1
5
0
50ns/DIV
2V/DIV 1V/DIV
TPC 34. AD8111 Switching Time
OFFSET VOLTAGE – Volts
FREQUENCY
120
480
360
320
240
160
440
400
280
200
80
40
0
–0.020 0.020–0.010 0.000 0.010
TPC 35. AD8111 Offset Voltage Distribution (RTI)
TEMPERATURE – C
V
OS
– mV
2.0
–2.0
–60 –40 100–20 0 20 40 60 80
1.5
0
–0.5
–1.0
–1.5
1.0
0.5
TPC 36. AD8111 Offset Voltage Drift vs. Temperature
(Normalized at 25
°
C)
REV. A
AD8110/AD8111
–15–
THEORY OF OPERATION
The AD8110 (G = +1) and AD8111 (G = +2) share a common
core architecture consisting of an array of 128 transconductance
(gm) input stages organized as eight 16:1 multiplexers with a
common, 16-line analog input bus. Each multiplexer is basically
a folded-cascode high-speed voltage feedback amplifier with 16
input stages. The input stages are NPN differential pairs whose
differential current outputs are combined at the output stage,
which contains the high impedance node, compensation and a
complementary emitter follower output buffer. In the AD8110,
the output of each multiplexer is fed directly back to the inverting
inputs of its 16 gm stages. In the AD8111, the feedback network
is a voltage divider consisting of two equal resistors.
This switched-gm architecture results in a low power crosspoint
switch that is able to directly drive a back terminated video load
(150 Ω) with low distortion (differential gain and differential
phase errors are better than 0.02% and 0.02°, respectively). This
design also achieves high input resistance and low input capaci-
tance without the signal degradation and power dissipation of
additional input buffers. However, the small input bias current at
any input will increase almost linearly with the number of out-
puts programmed to that input.
The output disable feature of these crosspoints allows larger
switch matrices to be built simply by busing together the outputs
of multiple 16 × 8 ICs. However, while the disabled output imped-
ance of the AD8110 is very high (10 MΩ), that of the AD8111
is limited by the resistive feedback network (which has a nominal
total resistance of 1 kΩ) that appears in parallel with the disabled
output. If the outputs of multiple AD8111s are connected through
separate back termination resistors, the loading due to these
finite output impedances will lower the effective back termination
impedance of the overall matrix. This problem is eliminated if
the outputs of multiple AD8111s are connected directly and
share a single back termination resistor for each output of the
overall matrix. This configuration increases the capacitive loading
of the disabled AD8111 on the output of the enabled AD8111.
APPLICATIONS
The AD8110/AD8111 have two options for changing the
programming of the crosspoint matrix. In the first option, a serial
word of 40 bits can be provided that will update the entire matrix
each time. The second option allows for changing a single
output’s programming via a parallel interface. The serial option
requires fewer signals, but requires more time (clock cycles) for
changing the programming, while the parallel programming tech-
nique requires more signals, but can change a single output at a
time and requires fewer clock cycles to complete programming.
Serial Programming
The serial programming mode uses the device pins CE, CLK,
DATA IN, UPDATE, and SER/PAR. The first step is to assert
a LOW on SER/PAR in order to enable the serial programming
mode. CE for the chip must be LOW to allow data to be clocked
into the device. The CE signal can be used to address an indi-
vidual device when devices are connected in parallel.
The UPDATE signal should be HIGH during the time that data
is shifted into the device’s serial port. Although the data will still
shift in when UPDATE is LOW, the transparent, asynchronous
latches will allow the shifting data to reach the matrix. This will
cause the matrix to try to update to every intermediate state as
defined by the shifting data.
The data at DATA IN is clocked in at every down edge of CLK.
A total of 40 data bits must be shifted in to complete the program-
ming. For each of the eight outputs, there are four bits (D0–D3)
that determine the source of its input followed, by one bit (D4)
that determines the enabled state of the output. If D4 is LOW
(output disabled) the four associated bits (D0–D3) do not matter,
because no input will be switched to that output.
The most significant output address data is shifted in first, then
following in sequence until the least significant output address
data is shifted in. At this point UPDATE can be taken LOW,
which will cause the programming of the device according to the
data that was just shifted in. The UPDATE registers are asyn-
chronous and when UPDATE is LOW (and CE is LOW), they
are transparent.
If more than one AD8110/AD8111 device is to be serially pro-
grammed in a system, the DATA OUT signal from one device
can be connected to the DATA IN of the next device to form a
serial chain. All of the CLK, CE, UPDATE and SER/PAR pins
should be connected in parallel and operated as described above.
The serial data is input to the DATA IN pin of the first device
of the chain, and it will ripple on through to the last. Therefore,
the data for the last device in the chain should come at the begin-
ning of the programming sequence. The length of the programming
sequence will be 40 times the number of devices in the chain.
Parallel Programming
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the
matrix. In fact, parallel programming allows the modification
of a single output at a time. Since this takes only one CLK/
UPDATE cycle, significant time savings can be realized by
using parallel programming.
One important consideration in using parallel programming is
that the RESET signal does not reset all registers in the AD8110/
AD8111. When taken low, the RESET signal will only set each
output to the disabled state. This is helpful during power-up to
ensure that two parallel outputs will not be active at the same time.
After initial power-up, the internal registers in the device will
generally have random data, even though the RESET signal
was asserted. If parallel programming is used to program one
output, that output will be properly programmed, but the rest
of the device will have a random program state depending
on the internal register content at power-up. Therefore, when
using parallel programming, it is essential that all outputs be
programmed to a desired state after power-up.
REV. A
AD8110/AD8111
–16–
This will ensure that the programming matrix is always in a
known state. From then on, parallel programming can be used
to modify a single output or more at a time.
In a similar fashion, if both CE and UPDATE are taken LOW
after initial power-up, the random power-up data in the shift
register will be programmed into the matrix. Therefore, in order to
prevent the crosspoint from being programmed into an unknown
state do not apply low logic levels to both CE and UPDATE after
power is initially applied. Programming the full shift register one
time to a desired state by either serial or parallel programming
after initial power-up will eliminate the possibility of program-
ming the matrix to an unknown state.
To change an output’s programming via parallel programming,
SER/PAR and UPDATE should be taken HIGH and CE should
be taken LOW. The CLK signal should be in the HIGH state.
The address of the output that is to be programmed should be
put on A0–A2. The first four data bits (D0–D3) should contain the
information that identifies the input that is programmed to the
output that is addressed. The fourth data bit (D4) will determine
the enabled state of the output. If D4 is LOW (output disabled),
the data on D0–D3 does not matter.
After the desired address and data signals have been established,
they can be latched into the shift register by a HIGH-to-LOW
transition of the CLK signal. The matrix will not be programmed,
however, until the UPDATE signal is taken low. Thus, it is
possible to latch in new data for several or all of the outputs first
via successive negative transitions of CLK while UPDATE is
held high, and then have all the new data take effect when
UPDATE goes LOW. This technique should be used when
programming the device for the first time after power-up when
using parallel programming.
POWER-ON RESET
When powering up the AD8110/AD8111 it is usually desirable
to have the outputs come up in the disabled state. The RESET
pin, when taken LOW will cause all outputs to be in the dis-
abled state. However, the RESET signal does not reset all registers
in the AD8110/AD8111. This is important when operating in
the parallel programming mode. Please refer to that section for
information about programming internal registers after power-
up. Serial programming will program the entire matrix each
time, so no special considerations apply.
Since the data in the shift register is random after power-up, it
should not be used to program the matrix or else the matrix can
enter unknown states. To prevent this, do not apply logic low signals
to both CE and UPDATE initially after power-up. The shift register
should first be loaded with the desired data, and then UPDATE
can be taken LOW to program the device.
The RESET pin has a 20 kΩ pull-up resistor to DVDD that can
be used to create a simple power-up reset circuit. A capacitor
from RESET to ground will hold RESET LOW for some time
while the rest of the device stabilizes. The LOW condition will
cause all the outputs to be disabled. The capacitor will then
charge through the pull-up resistor to the HIGH state; thus
allowing full programming capability of the device.
GAIN SELECTION
The 16 × 8 crosspoints come in two versions depending on the
desired gain of the analog circuit paths. The AD8110 device is
unity gain and can be used for analog logic switching and other
applications where unity gain is desired. The AD8110 can also
be used for the input and interior sections of larger crosspoint
arrays where termination of output signals is not usually used.
The AD8110 outputs have a very high impedance when their
outputs are disabled.
For devices that will be used to drive a terminated cable with its
outputs, the AD8111 can be used. This device has a built-in
gain of two that eliminates the need for a gain-of-two buffer to
drive a video line. Because of the presence of the feedback network
in these devices, the disabled output impedance is about 1 kΩ.
If external amplifiers are used to provide a gain = +2, Analog
Devices’ AD8079 provides a fixed G = +2 function.
CREATING LARGER CROSSPOINT ARRAYS
The AD8110/AD8111 are high-density building blocks for
creating crosspoint arrays of dimensions larger than 16 × 8.
Various features such as output disable, chip enable, and gain-
of-one- and-two options are useful for creating larger arrays.
For very large arrays, they can be used along with the AD8116,
a 16 × 16 video crosspoint device. In addition, when required
for customizing a crosspoint array size, they can be used with
the AD8108 and AD8109, a pair (unity gain and gain-of-two)
of 8 × 8 video crosspoint switches.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.
The 16 × 8 architecture of the AD8110/AD8111 contains 128
“points,” which is a factor of 32 greater than a 4 × 1 crosspoint.
The PC board area and power consumption savings are readily
apparent when compared to using these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the avail-
ability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than
this minimum. These systems have connectivity available on a
statistical basis that is determined when designing the overall system.
REV. A
AD8110/AD8111
–17–
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to
“wire-OR” the outputs together in the vertical direction. The
meaning of horizontal and vertical can best be understood by
looking at a diagram. Figure 6 illustrates this concept for a 32 × 8
crosspoint array.
AD8110
OR
AD8111
16
16
RTERM
IN 00–15
AD8110
OR
AD8111
16
16
RTERM
IN 16–31
8
8
Figure 6. A 32
×
8 Crosspoint Array Using Two AD8110s
or Two AD8111s
The inputs are each uniquely assigned to each of the 32 inputs
of the two devices and terminated appropriately. The outputs
are wire-ORed together in pairs. The output from only one of a
wired OR pair should be enabled at any given time. The device
programming software must be properly written to cause this
to happen.
At some point, the number of outputs that are wire-ORed becomes
too great to maintain system performance. This will vary according
to which system specifications are most important. It will also depend
on whether the matrix consists of AD8110s or AD8111s. The
output disabled impedance of the AD8110 is much higher than
that of the AD8111, so its disabled parasitics will have a smaller
effect on the one output that is enabled. For example, a 128 × 8
crosspoint can be created with eight AD8110/AD8111s. This
design will have 128 separate inputs and have the corresponding
outputs of each device wire-ORed together in groups of eight.
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-ORed together. Figure 7
shows a block diagram of a system using eight AD8110s and
two AD8111s to create a nonblocking, gain-of-two, 128 × 8
crosspoint that restricts the wire-ORing at the output to only
four outputs. These devices are the AD8110, which has a higher
disabled output impedance than the AD8111.
Additionally, by using the lower four outputs from each of the
two Rank 2 AD8111s, a blocking 128 × 16 crosspoint array can
be realized. There are, however, some drawbacks to this tech-
nique. The offset voltages of the various cascaded devices will
accumulate and the bandwidth limitations of the devices will
compound. In addition, the extra devices will consume more
current and take up more board space. Once again, the overall
system design specifications will determine how to make the
various tradeoffs.
16
R
TERM
IN 00–15
4
4
IN 16–31
IN 32–47
IN 48–63
IN 64–79
IN 80–95
IN 96–111
IN 112–127
4
4
4
4
RANK 2
16:8 NONBLOCKING
(16:16 BLOCKING)
RANK 1
(8 x AD8110)
128:16
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
AD8111
AD8110
AD8110
AD8110
AD8110
AD8110
AD8110
AD8110
AD8110
4
1k
4
1k
4
1k
4
1k
AD8111
OUT 00 – 07
NONBLOCKING
ADDITIONAL
8 OUTPUTS
(SUBJECT
TO BLOCKING)
Figure 7. A Gain-of-Two 128
×
8 Nonblocking Crosspoint Array (128
×
16 Blocking)
REV. A
AD8110/AD8111
–18–
Multichannel Video
The excellent video specifications of the AD8110/AD8111 make
them ideal candidates for creating composite video crosspoint
switches. These can be made quite dense by taking advantage
of the AD8110/AD8111’s high level of integration and the fact
that composite video requires only one crosspoint channel per
system video channel. There are, however, other video formats
that can be routed with the AD8110/AD8111 requiring more
than one crosspoint channel per video channel.
Some systems use twisted-pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
that operates in noisy environments or where common-mode volt-
ages are present between transmitting and receiving equipment.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero common-
mode signal. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8110/AD8111, eight differen-
tial video channels can be assigned to the 16 inputs and four to
the outputs. This will effectively form an 8 × 4 differential cross-
point switch.
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8110/AD8111
and the requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
commonly being used in systems such as satellite TV, digital
cable boxes and higher quality VCRs, is called S-video or Y/C
video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color (chromi-
nance, chroma or C) on a second channel.
Since S-video also uses two separate circuits for one video chan-
nel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differential
video system. Aside from the nature of the video format, other
aspects of these two systems will be the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R-Y, B-Y format, sometimes called YUV
format. These three-circuit, video standards are referred to as
component analog video.
The component video standards require three crosspoint chan-
nels per video channel to handle the switching function. In a
fashion similar to the two-circuit video formats, the inputs and
outputs are assigned in groups of three and the appropriate logic
programming is performed to route the video signals.
CROSSTALK
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.
When there are many signals in proximity in a system, as will
undoubtedly be the case in a system that uses the AD8110/
AD8111, the crosstalk issues can be quite complex. A good
understanding of the nature of crosstalk and some definition of
terms is required in order to specify a system that uses one or
more AD8110/AD8111s.
Types of Crosstalk
Crosstalk can be propagated by means of any of three meth-
ods. These fall into the categories of electric field, magnetic
field and sharing of common impedances. This section will explain
these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propa-
gates across a stray capacitance (e.g., free space) and couples
with the receiver and induces a voltage. This voltage is an
unwanted crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that circulate
around the currents. These magnetic fields will then generate
voltages in any other conductors whose paths they link. The undes-
ired induced voltages in these other channels are crosstalk signals.
The channels that crosstalk can be said to have a mutual inductance
that couples signals from one channel to another.
The power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various chan-
nels. When a current from one channel flows in one of these
paths, a voltage that is developed across the impedance becomes
an input crosstalk signal for other channels that share the com-
mon impedance.
All these sources of crosstalk are vector quantities, so the magnitudes
cannot be simply added together to obtain the total crosstalk. In
fact, there are conditions where driving additional circuits in paral-
lel in a given configuration can actually reduce the crosstalk.
Areas of Crosstalk
For a practical AD8110/AD8111 circuit, it is required that it be
mounted to some sort of circuit board in order to connect it to
power supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an evalu-
ation board) that adds minimum crosstalk to the intrinsic device.
This, however, raises the issue that a system’s crosstalk is a
combination of the intrinsic crosstalk of the devices in addition
to the circuit board to which they are mounted. It is important
to try to separate these two areas of crosstalk when attempting
to minimize its effect.
In addition, crosstalk can occur among the inputs to a cross-
point and among the outputs. It can also occur from input to
output. Techniques will be discussed for diagnosing which part
of a system is contributing to crosstalk.
REV. A
AD8110/AD8111
–19–
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by:
XT Asel s Atest s=
() ()
()
20 10
log /
where s = jw is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected channel
and Atest(s) is the amplitude of the test signal. It can be seen
that crosstalk is a function of frequency, but not a function of
the magnitude of the test signal (to first order). In addition, the
crosstalk signal will have a phase relative to the test signal asso-
ciated with it.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magni-
tude and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can become
extremely large. For example, in the case of the 16 ⫻ 8 matrix of
the AD8110/AD8111, we can examine the number of crosstalk
terms that can be considered for a single channel, say IN00 input.
IN00 is programmed to connect to one of the AD8110/AD8111
outputs where the measurement can be made.
We can first measure the crosstalk terms associated with driving
a test signal into each of the other 15 inputs one at a time. We
can then measure the crosstalk terms associated with driving a
parallel test signal into all 15 other inputs taken two at a time in
all possible combinations; and then three at a time, etc., until,
finally, there is only one way to drive a test signal into all 15
other inputs.
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar
crosstalk matrix can be proposed for every other input. In addition,
if the possible combinations and permutations for connecting
inputs to the other (not used for measurement) outputs are
taken into consideration, the numbers rather quickly grow to
astronomical proportions. If a larger crosspoint array of multiple
AD8110/AD8111s is constructed, the numbers grow larger still.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One common
method is to measure “all hostile” crosstalk. Su˘s term means
that the crosstalk to the selected channel is measured, while all
other system channels are driven in parallel. In general, this will
yield the worst crosstalk number, but this is not always the case
due to the vector nature of the crosstalk signal.
Other useful crosstalk measurements are those created by one
nearest neighbor or by the two nearest neighbors on either side.
These crosstalk measurements will generally be higher than
those of more distant channels, so they can serve as a worst-case
measure for any other one-channel or two-channel crosstalk
measurements.
Input and Output Crosstalk
The flexible programming capability of the AD8110/AD8111
can be used to diagnose whether crosstalk is occurring more on
the input side or the output side. Some examples are illustrative.
A given input channel (IN07 in the middle for this example) can
be programmed to drive OUT03. The input to IN07 is just
terminated to ground (via 50 or 75 Ω) and no signal is applied.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), with all
other outputs except OUT03 disabled. Since grounded IN07 is
programmed to drive OUT03, there should be no signal present.
Any signal that is present can be attributed to the other 15 hostile
input signals, because no other outputs are driven. (They are all
disabled.) Thus, this method measures the all-hostile input
contribution to crosstalk into IN07. Of course, the method
can be used for other input channels and combinations of
hostile inputs.
For output crosstalk measurement, a single input channel (IN00
for example) is driven and all outputs other than a given output
(IN03 in the middle) are programmed to connect to IN00.
OUT03 is programmed to connect to IN15 (far away from
IN00), which is terminated to ground. Thus OUT03 should not
have a signal present since it is listening to a quiet input. Any
signal measured at the OUT03 can be attributed to the output
crosstalk of the other seven hostile outputs. Again, this method
can be modified to measure other channels and other crosspoint
matrix combinations.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced crosstalk.
However, significant current can flow through the input termi-
nation resistors and the loops that drive them. Thus, the PC board
on the input side can contribute to magnetically coupled crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk will be given by:
XT R C s
SM
=
()
×
[]
20 10
log
where R
S
is the source resistance, C
M
is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
From the equation it can be observed that this crosstalk mechanism
has a high-pass nature; it can also be minimized by reducing the
coupling capacitance of the input circuits and lowering the output
impedance of the drivers. If the input is driven from a 75 Ω terminated
cable, the input crosstalk can be reduced by buffering this signal with
a low output impedance buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8110/AD8111 is specified with
excellent differential gain and phase when driving a standard
150 Ω video load, the crosstalk will be higher than the minimum
obtainable due to the high output currents. These currents will
induce crosstalk via the mutual inductance of the output pins
and bond wires of the AD8110/AD8111.
REV. A
AD8110/AD8111
–20–
From a circuit standpoint, this output crosstalk mechanism
looks like a transformer with a mutual inductance between the
windings that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by:
XT Mxy s R
L
=×
()
20
10
log /
where Mxy is the mutual inductance of output x to output y,
and R
L
is the load resistance on the measured output. This
crosstalk mechanism can be minimized by keeping the mutual
inductance low and increasing R
L
. The mutual inductance can
be kept low by increasing the spacing of the conductors and
minimizing their parallel length.
PCB Layout
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing, and
supply bypassing.
The packaging of the AD8110/AD8111 is designed to help keep
the crosstalk to a minimum. Each input is separated from each
other input by an analog ground pin. All of these AGNDs should
be directly connected to the ground plane of the circuit board.
These ground pins provide shielding, low impedance return
paths and physical separation for the inputs. All of these help to
reduce crosstalk.
Each output is separated from its two neighboring outputs by an
analog ground pin in addition to an analog supply pin of one
polarity or the other. Each of these analog supply pins provides
power to the output stages of only the two nearest outputs. These
supply pins and analog grounds provide shielding, physical
separation and a low impedance supply for the outputs. Individual
bypassing of each of these supply pins with a 0.01 µF chip capaci-
tor directly to the ground plane minimizes high frequency output
crosstalk via the mechanism of sharing common impedances.
Each output also has an on-chip compensation capacitor that is
individually tied to the nearby analog ground pins AGND00
through AGND07. This technique reduces crosstalk by prevent-
ing the currents that flow in these paths from sharing a common
impedance on the IC and in the package pins. These AGNDxx
signals should all be directly connected to the ground plane.
The input and output signals will have minimum crosstalk if
they are located between ground planes on layers above and
below, and separated by ground in between. Vias should be
located as close to the IC as possible to carry the inputs and
outputs to the inner layer. The only place the input and output
signals surface is at the input termination resistors and the out-
put series back termination resistors. These signals should also
be separated, to the extent possible, as soon as they emerge from
the IC package.
Evaluation Board
A four-layer evaluation board is available for the AD8110/AD8111.
The exact same board and external components are used for
each device. The only difference is the device itself, which offers
a selection of a gain of unity or gain of two through the analog
channels. This board has been carefully laid out and tested to
demonstrate the specified high-speed performance of the device.
Figure 9 shows the schematic of the evaluation board. Figure 10
shows the component side silk-screen. The layouts of the board’s
four layers are given in:
Component Layer—Figure 11
Signal Routing Layer—Figure 12
Power Layer—Figure 13
Bottom Layer—Figure 14
The evaluation board package includes the following:
•
Fully populated board with BNC-type connectors.
•
Windows
®
based software for controlling the board from a PC
via the printer port.
•
Custom cable to connect evaluation board to PC.
•
Disk containing Gerber files of board layout.
Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Stripline techniques are used
to achieve a characteristic impedance on the signal input and
output lines also of 75 Ω. Figure 8 shows a cross-section of one
of the input or output tracks along with the arrangement of the
PCB layers. It should be noted that unused regions of the four
layers are filled up with ground planes. As a result, the input
and output traces, in addition to having controlled impedances,
are well shielded.
w = 0.008"
(0.2mm)
a = 0.008"
(0.2mm)
b = 0.024"
(0.6mm)
h = 0.011325"
(0.288mm)
t = 0.00135" (0.0343mm)
TOP LAYER
SIGNAL LAYER
POWER LAYER
BOTTOM LAYER
Figure 8. Cross Section of Input and Output Traces
The board has 24 BNC type connectors: 16 inputs and 8 outputs.
The connectors are arranged in a crescent around the device. As
can be seen from Figure 12, this results in all 16 input signal
traces and all eight signal output traces having the same length.
This is useful in tests such as All-Hostile Crosstalk where the
phase relationship and delay between signals needs to be
maintained from input to output.
Windows is a registered trademark of Microsoft Corporation
REV. A
AD8110/AD8111
–21–
65
64
75
INPUT 00 INPUT 00
AGND
75
AVEE
41
40
0.01F
39
67
66
75
INPUT 01 INPUT 01
AGND
69
68
75
INPUT 02 INPUT 02
AGND
71
70
75
INPUT 03 INPUT 03
AGND
73
72
75
INPUT 04 INPUT 04
AGND
75
74
75
INPUT 05 INPUT 05
AGND
77
76
75
INPUT 06 INPUT 06
AGND
78
75
INPUT 07 INPUT 07
2
1
75
INPUT 08 INPUT 08
AGND
4
3
75
INPUT 09 INPUT 09
AGND
6
5
75
INPUT 10 INPUT 10
AGND
8
7
75
INPUT 11 INPUT 11
AGND
10
9
75
INPUT 12 INPUT 12
AGND
12
11
75
INPUT 13 INPUT 13
AGND
14
13
75
INPUT 14 INPUT 14
AGND
16
15
75
INPUT 15 INPUT 15
AGND
59 DATA OUT
59 DATA IN
80 DGND
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
RESET
DGND
CE
CLK
UPDATE
SER/PAR
A0
A1
A2
D0
D1
D2
D3
D4
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
P2-5
P2-4
P2-2
P2-3
P2-1
P2-6
P2-5
P2-4
62 61 60 58 56 55 54 53 52 51 50 49 48 47
SERIAL MODE
JUMP
R25
20k
DVCC
46
42
75
AVCC
38
37
0.01F
36
75
AVEE
35
34
0.01F
33
75
AVCC
32
31
0.01F
30
75
AVEE
29
28
0.01F
27
75
AVCC
26
25
0.01F
24
75
AVEE
23
22
0.01F
21
75
20
AGND
AGND
OUTPUT 00
AVEE
AGND
OUTPUT 01
AVCC
AGND
OUTPUT 02
AVEE
AGND
OUTPUT 03
AVCC
AGND
OUTPUT 04
AVEE
AGND
OUTPUT 05
AVCC
AGND
OUTPUT 06
AVEE
AGND
OUTPUT 07
AVCC
19
0.01F
AVCC
AVCC
18
0.01F
AVCC
AVEE
17
0.01F
AVEE
0.01F
45
AVEE
AVEE
0.01F
44
AVCC
AVCC
0.01F
43
AVCC
AVCC
0.01F
63
DVCC
0.01F
79
DVCC
AD8110/AD8111
DVCC DGND NCAVEE AGND AVCCNC
P1-1
CR1
CR2
+
+
+
P1-2 P1-3 P1-4 P1-5 P1-6 P1-7
0.1F10F
0.1F10F
0.1F10F
DVCC DVCC
Figure 9. Evaluation Board Schematic
REV. A
AD8110/AD8111
–22–
Figure 10. Component Side Silkscreen
Figure 11. Board Layout (Component Side)
REV. A
AD8110/AD8111
–23–
Figure 12. Board Layout (Signal Layer)
Figure 13. Board Layout (Power Plane)
REV. A
AD8110/AD8111
–24–
The three power supply pins AVCC, DVCC, and AVEE should
be connected to good quality, low noise, ±5 V supplies. Where
the same ±5 V power supplies are used for analog and digital,
separate cables should be run for the power supply to the evalu-
ation board’s analog and digital power supply pins.
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 µF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 µF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10 µF capacitor should be used to decouple power supplies as
they come on to the board.
Controlling the Evaluation Board from a PC
The evaluation board includes Windows-based control software
and a custom cable that connects the board’s digital interface to
the printer port of the PC. The wiring of this cable is shown in
Figure 15. The software requires Windows 3.1 or later to oper-
ate. To install the software, insert the disk labeled “Disk #1 of
2'' in the PC and run the file called SETUP.EXE. Additional
installation instructions will be given on-screen. Before begin-
ning installation, it is important to terminate any other Windows
applications that are running.
When you launch the crosspoint control software, you will be
asked to select the printer port you are using. Most modern PCs
have only one printer port, usually called LPT1. However some
laptop computers use the PRN port.
RESET
CLK
DATA IN
DGND
CE
UPDATE
MOLEX 0.100" CENTER
CRIMP TERMINAL HOUSING
1
6
D-SUB 25 PIN (MALE)
14 1
25 13
EVALUATION BOARD PC
2
3
4
5
6
25
3
1
4
5
2
6
SIGNAL
CE
RESET
UPDATE
DATA IN
CLK
DGND
MOLEX
TERMINAL HOUSING
D-SUB-25
Figure 15. Evaluation Board-PC Connection Cable
Figure 14. Board Layout (Bottom Layer)
REV. A
AD8110/AD8111
–25–
Figure 16 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 16 × 8 on-screen array.
Each time a button is clicked on, the software automatically
sends and latches the required 40-bit data stream to the evaluation
board. An output can be turned off by clicking the appropriate
button in the Off column. To turn off all outputs, click on RESET.
The software offers volatile and nonvolatile storage of configura-
tions. For volatile storage, up to two configurations can be stored
and recalled using the Memory 1 and Memory 2 Buffers. These
function in an identical fashion to the memory on a pocket
calculator. For nonvolatile storage of a configuration, the Save
Setup and Load Setup functions can be used. This stores the
configuration as a data file on disk.
Overshoot on PC Printer Ports’ Data Lines
The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder-side of the evaluation board to
allow this capacitor to be soldered into place. Depending upon
the overshoot from the printer port, this capacitor may need to
be as large as 0.01 µF.
Figure 16. Evaluation Board Control Panel
REV. A
AD8110/AD8111
–26–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead Plastic LQFP
(ST-80A)
SEATING
PLANE
0.063 (1.60)
MAX
0.030 (0.75)
0.020 (0.50)
0.003 (0.08)
MAX
0.057 (1.45)
0.053 (1.35)
0.006 (0.15)
0.002 (0.05) 0.011 (0.27)
0.007 (0.17)
0.559 (14.20)
0.543 (13.80)
0.476 (12.10)
0.469 (11.90)
0.476 (12.10)
0.469 (11.90)
0.559 (14.20)
0.543 (13.80)
TOP VIEW
(PINS DOWN)
1
20
21
41
40
60
6180
0.020 (0.50)
BSC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. A
AD8110/AD8111
–27–
Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A.
Universal change in nomenclature from MQFP to LQFP
Comment added to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REV. A
–28–
C01069–0–2/02(A)
PRINTED IN U.S.A.
