Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.6
FUJITSU SEMICONDUCTOR
DATA SHEET
DS704-00001-2v0-E
FUJITSU SEMICONDUCTOR CONFIDENTIAL r2.0
16-bit Proprietary Microcontroller
F2MC-16FX MB96670 Series
MB96F673R/A, MB96F675R/A
DESCRIPTION
MB96670 series is based on FUJITSU’s advanced F2MC-16FX architecture (16-bit with instruction
pipeline for RISC-like performance). The CPU uses the same instruction set as the established F2MC-16LX
family thus allowing for easy migration of F2MC-16LX Software to the new F2MC-16FX products.
F2MC-16FX product improvements compared to the previous generation include significantly improved
performance - even at the same operation frequency, reduced power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a
minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power
is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree
allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website.
The website contains information useful for customers.
http://edevice.fujitsu.com/micom/en-support/
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
FEATURES
• Technology
0.18µm CMOS
• CPU
• F2MC-16FX CPU
• Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers)
• 8-byte instruction queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• System clock
• On-chip PLL clock multiplier (×1 to ×8, ×1 when PLL stop)
• 4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator depends on Q-factor)
• Up to 8MHz external clock for devices with fast clock input feature
• 32.768kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog
• Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of peripherals
• The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a
Power or External reset
• Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes)
• On-chip voltage regulator
Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power
consumption
• Low voltage detection function
Reset is generated when supply voltage falls below programmable reference voltage
• Code Security
Protects Flash Memory content from unintended read-out
• DMA
Automatic transfer function independent of CPU, can be assigned freely to resources
• Interrupts
• Fast Interrupt processing
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• CAN
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1Mbps
• 32 message objects
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
• USART
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Extended support for LIN-Protocol to reduce interrupt load
• I2C
• Up to 400kbps
• Master and Slave functionality, 7-bit and 10-bit addressing
• A/D converter
• SAR-type
• 8/10-bit resolution
• Signals interrupt on conversion end, single conversion mode, continuous conversion mode,
stop conversion mode, activation by software, external trigger, reload timers and PPGs
• Range Comparator Function
• Scan Disable Function
• ADC Pulse Detection Function
• Source Clock Timers
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
• Hardware Watchdog Timer
• Hardware watchdog timer is active after reset
• Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
• Reload Timers
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
• Free-Running Timers
• Signals an interrupt on overflow
• Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of peripheral clock frequency
• Input Capture Units
• 16-bit wide
• Signals an interrupt upon external event
• Rising edge, Falling edge or Both (rising & falling) edges sensitive
• Programmable Pulse Generator
• 16-bit down counter, cycle and duty setting registers
• Can be used as 2 × 8-bit PPG
• Interrupt at trigger, counter borrow and/or duty match
• PWM operation and one-shot operation
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer
underflow as clock input
• Can be triggered by software or reload timer
• Can trigger ADC conversion
• Timing point capture
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
• Stepping Motor Controller
• Stepping Motor Controller with integrated high current output drivers
• Four high current outputs for each channel
• Two synchronized 8/10-bit PWMs per channel
• Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock
• Dedicated power supply for high current output drivers
• LCD Controller
• LCD controller with up to 4COM × 24SEG
• Internal or external voltage generation
• Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
• Fixed 1/3 bias
• Programmable frame period
• Clock source selectable from four options (main clock, peripheral clock, subclock or RC oscillator clock)
• Internal divider resistors or external divider resistors
• On-chip data memory for display
• LCD display can be operated in Timer Mode
• Blank display: selectable
• All SEG, COM and V pins can be switched between general and specialized purposes
• Sound Generator
• 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
• PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock
• Real Time Clock
• Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz)
• Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
• External Interrupts
• Edge or Level sensitive
• Interrupt mask bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Non Maskable Interrupt
• Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block
• Once enabled, can not be disabled other than by reset
• High or Low level sensitive
• Pin shared with external interrupt 0
• I/O Ports
• Most of the external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
• Bit-wise programmable input enable
• One input level per GPIO-pin (either Automotive or CMOS hysteresis)
• Bit-wise programmable pull-up resistor
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
• Built-in On Chip Debugger (OCD)
• One-wire debug tool interface
• Break function:
- Hardware break: 6 points (shared with code event)
- Software break: 4096 points
• Event function
- Code event: 6 points (shared with hardware break)
- Data event: 6 points
- Event sequencer: 2 levels + reset
• Execution time measurement function
• Trace function: 42 branches
• Security function
• Flash Memory
• Dual operation flash allowing reading of one Flash bank while programming or erasing the other bank
• Command sequencer for automatic execution of programming algorithm and for supporting DMA for
programming of the Flash Memory
• Supports automatic programming, Embedded Algorithm
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the automatic algorithm
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase or write
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
PRODUCT LINEUP
Features
MB96670
Remark
Product Type
Flash Memory Product
Subclock
Subclock can be set by software
Dual Operation Flash Memory
RAM
-
64.5KB + 32KB 4KB MB96F673R, MB96F673A
Product Options
R: MCU with CAN
A: MCU without CAN
128.5KB + 32KB 4KB MB96F675R, MB96F675A
Package
LQFP-64
FPT-64P-M23/M24
DMA
2ch
USART
2ch
LIN-USART 0/1
with automatic LIN-Header
transmission/reception
Yes (onl y 1ch) LIN-USART 0
with 16 byte RX- and
TX-FIFO
No
I2C
1ch
I2C 0
8/10-bit A/D Converter
12ch
AN 8/9/12/13/16 to 23
with Data Buffer
No
with Range Comparator
Yes
with Scan Disable
Yes
with ADC Pulse Detection
Yes
16-bit Reload Timer ( R LT )
3ch
RLT 1/2/6
16-bit Free-Running Timer (FRT)
2ch
FRT 0/1
16-bit Input Capture Unit (ICU)
4ch
(2 channels for LIN-USART)
ICU 0/1/4/5
ICU 0/1 for LIN-USART
8/16-bit Programmable Pulse Generator
(PPG)
4ch (16-bit) / 8ch (8-bit) PPG 0 to 3
with Timing point capture
Yes
with Start delay
No
with Ramp
No
CAN Interface 1ch
CAN 0
32 Message Buffers
Stepping Motor Controller (SMC)
2ch
SMC 0/1
External Interrupts (INT)
7ch
INT 0 to 4/6/7
Non-Maskable Interrupt (NMI)
1ch
Sound Generator (SG)
1ch
SG 0
LCD Controller 4COM × 24SEG
COM 0 to 3
SEG 3 to 6/8 to 11/
19 to 21/23/30/36 to
39/42/45 to 47/54 to 56
Real Time Clock (RTC)
1ch
I/O Ports
48 (Dual clock mode)
50 (Single clock mode)
Clock Calibration Unit (CAL)
1ch
Clock Output Function
2ch
Low Voltage Detection Function Yes
Low voltage detection
function can be
disabled by software
Hardware Watchdog Timer
Yes
On-chip RC-oscillator
Yes
On-chip Debugger
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the general I/O port according to your function use.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
BLOCK DIAGRAM
DMA
Controller Boot ROM
Peripheral
Bus Bridge
Peripheral
Bus Bridge
16FX Core Bus (CLKB)
Watchdog RAM Voltage
Regulator
Vcc
Vss
C
16FX
CPU
Clock &
Mode Controller
Flash
Memory A
Peripheral Bus 2 (CLKP2)
Peripheral Bus 1 (CLKP1)
X0, X1
X0A, X1A
RSTX
MD
CKOTX0
CKOT0_R, CKOT1
OCD
DEBUG I/F
Interrupt
Controller
NMI
SDA0
SCL0
AVcc
AVss
AVRH
AN12, AN13
ADTG
AN16 to AN23
IN4_R, IN5_R
INT0 to INT4
INT1_R, INT2_R
INT6, INT7
COM0 to COM3
SEG3 to SEG6, SEG8 to SEG11
SEG19 to SEG21, SEG23
SEG30,SEG36 to SEG39
SEG42,SEG45 to SEG47
SEG54 to SEG56
V0 to V3
IN0_R, IN1, IN1_R
TIN1, TIN1_R, TIN2_R
TOT1, TOT1_R, TOT2_R
I
2
C
1ch
8/10-bit ADC
12ch
I/O Timer 0
FRT 0
ICU 0/1
16-bit
Reload Timer
1/2/6
3ch
I/O Timer 1
FRT 1
ICU 4/5
External
Interrupt
7ch
LCD
controller/
driver
4COM24SEG
CAN
Interface
1ch
Sound
Generator
1ch
TX0
RX0
SGO0
SGA0
USART
2ch
Real Time
Clock
PPG
4ch (16-bit) /
8ch (8-bit)
Stepping
Motor
Controller
2ch
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
PPG0_R, PPG1_R, PPG2_R, PPG3
TTG1
PPG0_B, PPG1_B, PPG2_B, PPG3_B
PWM1M0, PWM1M1
PWM1P0, PWM1P1
PWM2M0, PWM2M1
PWM2P0, PWM2P1
DVcc
DVss
WOT_R
AN8, AN9
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
PIN ASSIGNMENT
(Top view)
LQFP-64
49 32
P04_4 / PPG3 / SDA0*
2
P12_1 / SEG5 / TIN1_R / PPG0_B
P12_2 / SEG6 / TOT1_R / PPG1_B
50 31
P13_6 / SCK0 / CKOTX0 / SEG47*
1
P12_4 / SEG8
51 30
P13_5 / SOT0 / ADTG / INT7 / SEG46
P12_5 / SEG9 / TIN2_R / PPG2_B
52 29
P13_4 / SIN0 / INT6 / SEG45*
1
P12_6 / SEG10 / TOT2_R / PPG3_B
53 28
P08_7 / PWM2M1 / AN23
P12_7 / SEG11 / INT1_R
54 27
P08_6 / PWM2P1 / AN22
P01_1 / SEG21 / CKOT1
55 26
P08_5 / PWM1M1 / AN21
P01_3 / SEG23
56 25
P08_4 / PWM1P1 / AN20
P03_0 / SEG36 / V0
57 24
DVss
P03_1 / SEG37 / V1
58 23
DVcc
P03_2 / SEG38 / V2
59 22
P08_3 / PWM2M0 / AN19
P03_3 / SEG39 / V3
60 21
P08_2 / PWM2P0 / AN18
P03_4 / RX0 / INT4*
1
61 20
P08_1 / PWM1M0 / AN17
P03_5 / TX0
62 19
P08_0 / PWM1P0 / AN16
P03_6 / INT0 / NMI
63 18
P05_5 / AN13
Vcc
64 17
P05_4 / AN12 / INT2_R / WOT_R
P12_0 / SEG4 / IN1_R
48
1
Vss
P11_3 / COM3 / PPG2_R
47
2
C
P11_2 / COM2 / PPG1_R
46
3
P03_7 / INT1 / SIN1*
1
P11_1 / COM1 / PPG0_R
45
4
P13_0 / INT2 / SOT1
P11_0 / COM0
44
5
P13_1 / INT3 / SCK1 / SEG42*
1
P11_7 / SEG3 / IN0_R
43
6
P00_7 / SEG19 / SGO0
RSTX
42
7
P01_0 / SEG20 / SGA0
P04_1 / X1A*
3
41
8
P02_2 / SEG30 / CKOT0_R
P04_0 / X0A*
3
40
9
P06_5 / IN1 / SEG54 / TTG1
Vss
39
10
P06_6 / TIN1 / SEG55 / IN4_R
X1
38
11
P06_7 / TOT1 / SEG56 / IN5_R
X0
37
12
P05_0 / AN8
MD
36
13
P05_1 / AN9
P17_0
35
14
AVcc
DEBUG I/F
34
15
AVRH
P04_5 / SCL0*
2
33
16
AVss
(FPT-64P-M23/M24)
*1: CMOS input level only
*2: CMOS input level only for I2C
*3: Please set ROM Configuration Block (RCB) to use the subclock.
Other than those above, general-purpose pins have only Automotive input level.
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
PIN DESCRIPTION
Pin name
Feature
Description
ADTG ADC A/D converter trigger input pin
ANn
ADC
A/D converter channel n input pin
AV c c
Supply
Analog circuits power supply pin
AV R H
ADC
A/D converter high reference voltage input pin
AV s s
Supply
Analog circuits power supply pin
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock Output function
Clock Output function n output pin
CKOTn_R Clock Output function Relocated Clock Output function n output pin
CKOTXn Clock Output function Clock Output function n inverted output pin
COMn LCD LCD Common driver pin
DEBUG I/F OCD On Chip Debugger input/output pin
DVcc
Supply
SMC pins power supply
DVss
Supply
SMC pins power supply
INn
ICU
Input Capture Unit n input pin
INn_R
ICU
Relocated Input Capture Unit n input pin
INTn
External Interrupt
External Interrupt n input pin
INTn_R
External Interrupt
Relocated External Interrupt n input pin
MD Core Input pin for specifying the operating mode
NMI External Interrupt Non-Maskable Interrupt input pin
Pnn_m GPIO General purpose I/O pin
PPGn PPG Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_R PPG
Relocated Programmable Pulse Generator n output pin
(16bit/8bit)
PPGn_B
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PWMn SMC SMC PWM high current output pin
RSTX Core Reset input pin
RXn CAN CAN interface n RX input pin
SCKn USART USART n serial clock input/output pin
SCLn
I2C
I2C interface n clock I/O input/output pin
SDAn
I2C
I2C interface n serial data I/O input/output pin
SEGn
LCD
LCD Segment driver pin
SGAn
Sound Generator
Sound Generator amplitude output pin
SGOn
Sound Generator
Sound Generator sound/tone output pin
SINn
USART
USART n serial data input pin
SOTn USART USART n serial data output pin
TINn Reload Timer Reload Timer n event input pin
TINn_R Reload Timer Relocated Reload Timer n event input pin
TOTn Reload Timer Reload Timer n output pin
TOTn_R Reload Timer Relocated Reload Timer n output pin
TTGn PPG Programmable Pulse Generator n trigger input pin
TXn CAN CAN interface n TX output pin
Vn
LCD
LCD voltage reference pin
Vcc
Supply
Power supply pin
Vss
Supply
Power supply pin
WOT_R
RTC
Relocated Real Time clock output pin
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
Pin name
Feature
Description
X0 Clock Oscillator input pin
X0A Clock Subclock Oscillator input pin
X1 Clock Oscillator output pin
X1A Clock Subclock Oscillator output pin
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
PIN CIRCUIT TYPE
Pin no. I/O circuit type* Pin name
1 Supply Vss
2 F C
3 M P03_7 / INT1 / SIN1
4 H P13_0 / INT2 / SOT1
5 P P13_1 / INT3 / SCK1 / SEG42
6 J P00_7 / SEG19 / SGO0
7 J P01_0 / SEG20 / SGA0
8 J P02_2 / SEG30 / CKOT0_R
9 J P06_5 / IN1 / SEG54 / TTG1
10 J P06_6 / TIN1 / SEG55 / IN4_R
11 J P06_7 / TOT1 / SEG56 / IN5_R
12 K P05_0 / AN8
13 K P05_1 / AN9
14 Supply AV c c
15 G AV R H
16 Supply AV s s
17 K P05_4 / AN12 / INT2_R / WOT_R
18 K P05_5 / AN13
19 R P08_0 / PWM1P0 / AN16
20 R P08_1 / PWM1M0 / AN17
21 R P08_2 / PWM2P0 / AN18
22 R P08_3 / PWM2M0 / AN19
23 Supply DVcc
24 Supply DVss
25 R P08_4 / PWM1P1 / AN20
26 R P08_5 / PWM1M1 / AN21
27 R P08_6 / PWM2P1 / AN22
28 R P08_7 / PWM2M1 / AN23
29 P P13_4 / SIN0 / INT6 / SEG45
30 J P13_5 / SOT0 / ADTG / INT7 / SEG46
31 P P13_6 / SCK0 / CKOTX0 / SEG47
32 N P04_4 / PPG3 / SDA0
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
*: See “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
Pin no. I/O circuit type* Pin name
33 N P04_5 / SCL0
34 O DEBUG I/F
35 H P17_0
36 C MD
37 A X0
38 A X1
39 Supply Vss
40 B P04_0 / X0A
41 B P04_1 / X1A
42 C RSTX
43 J P11_7 / SEG3 / IN0_R
44 J P11_0 / COM0
45 J P11_1 / COM1 / PPG0_R
46 J P11_2 / COM2 / PPG1_R
47 J P11_3 / COM3 / PPG2_R
48 J P12_0 / SEG4 / IN1_R
49 J P12_1 / SEG5 / TIN1_R / PPG0_B
50 J P12_2 / SEG6 / TOT1_R / PPG1_B
51 J P12_4 / SEG8
52 J P12_5 / SEG9 / TIN2_R / PPG2_B
53 J P12_6 / SEG10 / TOT2_R / PPG3_B
54 J P12_7 / SEG11 / INT1_R
55 J P01_1 / SEG21 / CKOT1
56 J P01_3 / SEG23
57 L P03_0 / SEG36 / V0
58 L P03_1 / SEG37 / V1
59 L P03_2 / SEG38 / V2
60 L P03_3 / SEG39 / V3
61 M P03_4 / RX0 / INT4
62 H P03_5 / TX0
63 H P03_6 / INT0 / NMI
64 Supply Vcc
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
I/O CIRCUIT TYPE
Ty p e
Circuit
Remarks
A
R
FCI
X out
0
1
X1
X0
FCI or Osc disable
High-speed oscillation circuit:
• Programmable between
oscillation mode (external
crystal or resonator connected
to X0/X1 pins) and Fast
external Clock Input (FCI)
mode (external clock
connected to X0 pin)
• Feedback resistor = approx.
1.0MΩ
• The amplitude: 1.8V±0.15V
to operate by the internal
supply voltage
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
Ty p e
Circuit
Remarks
B
R
FCI
X out
0
1
Pout
R
Nout
Automotive input
FCI or Osc disable
Standby
control
for input
shutdown
Standby
control
for input
shutdown
Automotive input
X1A
X0A
R
P-ch P-ch
N-ch
Pull-up control
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Low-speed oscillation circuit
shared with GPIO functionality:
• Feedback resistor = approx.
5.0MΩ
• GPIO functionality selectable
(CMOS level output (IOL =
4mA, IOH = -4mA),
Automotive input with input
shutdown function and
programmable pull-up
resistor)
C
R
Hysteresis
inputs
CMOS hysteresis input pin
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
Ty p e
Circuit
Remarks
F
P-ch
N-ch
Power supply input protection
circuit
G
P-ch
N-ch
• A/D converter ref+ (AVRH)
power supply input pin with
protection circuit
• Without protection circuit
against VCC for pins AVRH
H
Standby control
for input shutdown Automotive input
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up
resistor
J
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
SEG or COMoutput
Automotive input
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up
resistor
• SEG or COM output
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
Ty p e
Circuit
Remarks
K
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Analog input
Automotive input
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up
resistor
• Analog input
L
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Vn input or SEG output
Automotive input
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• Automotive input with input
shutdown function
• Programmable pull-up
resistor
• Vn input or SEG output
M
Standby control
for input shutdown
Hysteresis input
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis input with
input shutdown function
• Programmable pull-up
resistor
17
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
Ty p e
Circuit
Remarks
N
Standby control
for input shutdown
Hysteresis input
R
Pull-up control
Pout
Nout*
P-ch P-ch
N-ch
• CMOS level output
(IOL = 3mA, IOH = -3mA)
• CMOS hysteresis input with
input shutdown function
• Programmable pull-up
resistor
*: N-channel transistor has slew
rate control according to I2C
spec, irrespective of usage.
O
Standby control
for input shutdown TTL input
R
Nout
N-ch
• Open-drain I/O
• Output 25mA, Vcc = 2.7V
• TTL input
P
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
SEG or COMoutput
Hysteresis input
• CMOS level output
(IOL = 4mA, IOH = -4mA)
• CMOS hysteresis inputs with
input shutdown function
• Programmable pull-up
resistor
• SEG or COM output
18
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
Ty p e
Circuit
Remarks
R
Standby control
for input shutdown
R
Pull-up control
Pull-down control
Pout
Nout
P-ch P-ch
N-ch
N-ch
Analog input
Automotive input
• CMOS level output
(programmable IOL = 4mA,
IOH = -4mA and IOL = 30mA,
IOH = -30mA)
• Automotive input with input
shutdown function
• Programmable pull-up /
pull-down resistor
• Analog input
19
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
MEMORY MAP
FF:FFFF
H
DE:0000
H
DD:FFFF
H
10:0000
H
0F:C000
H
0E:9000
H
01:0000
H
00:8000
H
RAMSTART0*
2
00:0C00
H
00:0380
H
00:0180
H
00:0100
H
00:00F0
H
00:0000
H
GPR*
3
DMA
Reserved
Peripheral
Reserved
USER ROM*1
Reserved
Boot-ROM
Peripheral
ROM/RAM
MIRROR
Internal RAM
bank0
Peripheral
Reserved
*1: For details about USER ROM area, see “USER ROM MEMORY MAP FOR FLASH DEVICES”
on the following pages.
*2: For RAMSTART addresses, see the table on the next page.
*3: Unused GPR banks can be used as RAM area.
GPR: General-Purpose Register
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
20
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
RA MSTA RT A D DRESSES
Devices
Bank 0
RAM size
RAMSTART0
MB96F673
MB96F675
4KB 00:7200H
21
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
US ER ROM MEMORY MAP FOR FLASH DEV ICES
MB96F673
CPU mode
address
Flash memory
mode address
FF:FFFF
H
FF:0000
H
3F:FFFF
H
3F:0000
H
SA39 - 64KB SA39 - 64KB
FE:FFFF
H
FE:0000
H
3E:FFFF
H
3E:0000
H
SA38 - 64KB
FD:FFFF
H
DF:A000
H
DF:9FFF
H
DF:8000
H
1F:9FFF
H
1F:8000
H
SA4 - 8KB
DF:7FFF
H
DF:6000
H
1F:7FFF
H
1F:6000
H
SA3 - 8KB
DF:5FFF
H
DF:4000
H
1F:5FFF
H
1F:4000
H
SA2 - 8KB
DF:3FFF
H
DF:2000
H
1F:3FFF
H
1F:2000
H
SA1 - 8KB
SA4 - 8KB
SA3 - 8KB
SA2 - 8KB
SA1 - 8KB
DF:1FFF
H
DF:0000
H
1F:1FFF
H
1F:0000
H
SAS - 512B* SAS - 512B*
Bank A of Flash A
DE:FFFF
H
DE:0000
H
Reserved Reserved
Reserved
Reserved
Bank B of Flash A
Flash size
64.5KB + 32KB
Flash size
128.5KB + 32KB
Bank A of Flash A
MB96F675
*: Physical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH.
SAS can not be used for E2PROM emulation.
22
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
MB96670
Pin Number USART Number Normal Function
29
USART0
SIN0
30 SOT0
31 SCK0
3
USART1
SIN1
4 SOT1
5 SCK1
23
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
INTERRUPT VECTOR TABLE
Vector
number
Offset in
vector table Vector name Cleared by
DMA
Index in
ICR to
program
Description
0 3FCH CALLV0 No - CALLV instruction
1
3F8H
CALLV1
No
-
CALLV instruction
2
3F4H
CALLV2
No
-
CALLV instruction
3 3F0
H
CALLV3 No - CALLV instruction
4
3ECH
CALLV4
No
-
CALLV instruction
5
3E8H
CALLV5
No
-
CALLV instruction
6 3E4
H
CALLV6 No - CALLV instruction
7
3E0H
CALLV7
No
-
CALLV instruction
8
3DCH
RESET
No
-
Reset vector
9
3D8H
INT9
No
-
INT9 instruction
10 3D4H EXCEPTION No - Undefined instruction execution
11
3D0H
NMI
No
-
Non-Maskable Interrupt
12
3CCH
D LY
No
12
Delayed Interrupt
13 3C8
H
RC_TIMER No 13 RC Clock Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16 3BC
H
LV D I No 16 Low Voltage Detector
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
EXTINT1
Yes
18
External Interrupt 1
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
-
-
22
Reserved
23 3A0
H
EXTINT6 Yes 23 External Interrupt 6
24
39CH
EXTINT7
Yes
24
External Interrupt 7
25
398H
-
-
25
Reserved
26 394
H
- - 26 Reserved
27
390H
-
-
27
Reserved
28
38CH
-
-
28
Reserved
29
388H
-
-
29
Reserved
30
384H
-
-
30
Reserved
31
380H
-
-
31
Reserved
32
37CH
-
-
32
Reserved
33 378
H
CAN0 No 33 CAN Controller 0
34
374H
-
-
34
Reserved
35
370H
-
-
35
Reserved
36 36C
H
- - 36 Reserved
37
368H
-
-
37
Reserved
38
364H
PPG0
Yes
38
Programmable Pulse Generator 0
39
360H
PPG1
Yes
39
Programmable Pulse Generator 1
40
35CH
PPG2
Yes
40
Programmable Pulse Generator 2
24
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
Vector
number
Offset in
vector table Vector name Cleared by
DMA
Index in
ICR to
program
Description
41 358
H
PPG3 Yes 41 Programmable Pulse Generator 3
42
354H
-
-
42
Reserved
43
350H
-
-
43
Reserved
44
34CH
-
-
44
Reserved
45 348H - - 45 Reserved
46
344H
-
-
46
Reserved
47
340H
-
-
47
Reserved
48 33C
H
- - 48 Reserved
49
338H
-
-
49
Reserved
50
334H
-
-
50
Reserved
51 330
H
- - 51 Reserved
52
32CH
-
-
52
Reserved
53
328H
-
-
53
Reserved
54
324H
-
-
54
Reserved
55
320H
-
-
55
Reserved
56
31CH
-
-
56
Reserved
57
318H
-
-
57
Reserved
58 314
H
- - 58 Reserved
59
310H
R LT 1
Yes
59
Reload Timer 1
60
30CH
R LT 2
Yes
60
Reload Timer 2
61 308
H
- - 61 Reserved
62
304H
-
-
62
Reserved
63
300H
-
-
63
Reserved
64
2FCH
R LT 6
Yes
64
Reload Timer 6
65
2F8H
ICU0
Yes
65
Input Capture Unit 0
66
2F4H
ICU1
Yes
66
Input Capture Unit 1
67
2F0H
-
-
67
Reserved
68 2EC
H
- - 68 Reserved
69
2E8H
ICU4
Yes
69
Input Capture Unit 4
70
2E4H
ICU5
Yes
70
Input Capture Unit 5
71 2E0
H
- - 71 Reserved
72
2DCH
-
-
72
Reserved
73
2D8H
-
-
73
Reserved
74
2D4H
-
-
74
Reserved
75
2D0H
-
-
75
Reserved
76
2CCH
-
-
76
Reserved
77
2C8H
-
-
77
Reserved
78 2C4
H
- - 78 Reserved
79
2C0H
-
-
79
Reserved
80
2BCH
-
-
80
Reserved
25
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
Vector
number
Offset in
vector table Vector name Cleared by
DMA
Index in
ICR to
program
Description
81 2B8
H
- - 81 Reserved
82
2B4H
-
-
82
Reserved
83
2B0H
-
-
83
Reserved
84
2ACH
-
-
84
Reserved
85 2A8H - - 85 Reserved
86
2A4H
-
-
86
Reserved
87
2A0H
-
-
87
Reserved
88 29C
H
- - 88 Reserved
89
298H
FRT0
Yes
89
Free-Running Timer 0
90
294H
FRT1
Yes
90
Free-Running Timer 1
91 290
H
- - 91 Reserved
92
28CH
-
-
92
Reserved
93
288H
RTC0
No
93
Real Time Clock
94
284H
CAL0
No
94
Clock Calibration Unit
95
280H
SG0
No
95
Sound Generator 0
96
27CH
IIC0
Yes
96
I2C interface 0
97
278H
-
-
97
Reserved
98 274
H
ADC0 Yes 98 A/D Converter 0
99
270H
-
-
99
Reserved
100
26CH
-
-
100
Reserved
101 268
H
LINR0 Yes 101 LIN USART 0 RX
102
264H
LINT0
Yes
102
LIN USART 0 TX
103
260H
LINR1
Yes
103
LIN USART 1 RX
104
25CH
LINT1
Yes
104
LIN USART 1 TX
105
258H
-
-
105
Reserved
106
254H
-
-
106
Reserved
107
250H
-
-
107
Reserved
108 24C
H
- - 108 Reserved
109
248H
-
-
109
Reserved
110
244H
-
-
110
Reserved
111 240
H
- - 111 Reserved
112
23CH
-
-
112
Reserved
113
238H
-
-
113
Reserved
114
234H
-
-
114
Reserved
115
230H
-
-
115
Reserved
116
22CH
-
-
116
Reserved
117
228H
-
-
117
Reserved
118 224
H
- - 118 Reserved
119
220H
-
-
119
Reserved
120
21CH
-
-
120
Reserved
26
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
Vector
number
Offset in
vector table Vector name Cleared by
DMA
Index in
ICR to
program
Description
121 218
H
- - 121 Reserved
122
214H
-
-
122
Reserved
123
210H
-
-
123
Reserved
124
20CH
-
-
124
Reserved
125 208H - - 125 Reserved
126
204H
-
-
126
Reserved
127
200H
-
-
127
Reserved
128 1FC
H
- - 128 Reserved
129
1F8H
-
-
129
Reserved
130
1F4H
-
-
130
Reserved
131 1F0
H
- - 131 Reserved
132
1ECH
-
-
132
Reserved
133
1E8H
FLASHA
Yes
133
Flash memory A interrupt
134
1E4H
-
-
134
Reserved
135
1E0H
-
-
135
Reserved
136
1DCH
-
-
136
Reserved
137
1D8H
-
-
137
Reserved
138 1D4
H
- - 138 Reserved
139
1D0H
ADCRC0
No
139
A/D Converter 0 - Range Comparator
140
1CCH
ADCPD0
No
140
A/D Converter 0 - Pulse detection
141 1C8
H
- - 141 Reserved
142
1C4H
-
-
142
Reserved
143
1C0H
-
-
143
Reserved
27
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 Ser ies
DS704-00001-2v0-E
HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-1Ea
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FUJITSU SEMICONDUCTOR CONFIDENTIAL
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DS704-00001-2v0-E
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications
(computers, office automation and other office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat
resistance during soldering, you should only mount under FUJITSU SEMICONDUCTOR's recommended
conditions. For detailed information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended
mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results
in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised to
mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.
29
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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DS704-00001-2v0-E
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly
moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in
their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
30
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special
environmental conditions should consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
31
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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HANDLING DEVICES
Special care is required for the following whe n handling the device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Notes on PLL clock mode operation
• Power supply pins (Vcc/Vss)
• Crystal oscillator and ceramic resonator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on Power-on
• Stabilization of power supply voltage
• SMC power supply pins
• Serial communication
• Mode Pin (MD)
1. Latch-up preventio n
CMOS IC chips may suffer latch-up under the following conditions:
- A voltage higher than VCC or lower than VSS is applied to an input or output pin.
- A voltage higher than the rated voltage is applied between Vcc pins and Vss pins.
- T h e AV CC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors
which should be more than 2kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must
be connected as follows:
(1) Single phase external clock for Main oscillator
When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open.
And supply 1.8V power to the external clock.
X0
X1
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(2) Single phase external clock for Sub oscillator
When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and
X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO.
(3) Opposite phase external clock
When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has
the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V.
X0
X1
4. Notes on PLL clock mode operation
If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external
clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this
operation, however, cannot be guaranteed.
5 . Power supply pins (Vcc/Vss)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is
more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed
operating range.
Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance.
The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs.
Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1µF
between Vcc and Vss pins as close as possible to Vcc and Vss pins.
6. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass
capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic
resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of
other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A
pins with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
7. Turn on sequence of pow er supply to A/D c onverter and ana log inputs
It is required to turn the A/D converter power supply (AVCC, AVRH) and analog inputs (ANn) on after turning
the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In
this case, AVRH must not exceed AV CC . Input voltage for ports shared with analog input ports also must not
exceed AV CC (turning the analog and digital power supplies simultaneously on or off is acceptable).
8. Pin ha ndli ng when no t using the A/D converter
If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC =
VCC , AV SS = AVRH = VSS.
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9. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply
on should be slower than 50µs from 0.2V to 2.7V.
10. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the VCC power supply
voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization
guidelines, the power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak
value) in the commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage
and the transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply
switching.
11. SMC power supply pins
All DVcc /DVss pins must be set to the same level as the Vcc /Vss pins.
Note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, VCC
must always be powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
12. Serial co mmunication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13. Mode Pin (MD)
Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to
noise, lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and
provide a low-impedance connection.
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E LECTRI C AL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol Condition
Rating
Unit Remarks
Min
Max
Power supply
voltage*
1
VCC - VSS - 0.3 VSS + 6.0 V
Analog power
supply voltage*
1
AV CC - VSS - 0.3 VSS + 6.0 V VCC = AV CC*2
Analog reference
voltage*
1
AV R H - VSS - 0.3 VSS + 6.0 V
AV
CC
≥ AV R H ,
AVRH ≥ AV SS
SMC Power
supply*
1
DVCC - VSS - 0.3 VSS + 6.0 V VCC = AV CC= DVCC
*2
LCD power supply
voltage*
1
V0 to V3 - VSS - 0.3 VSS + 6.0 V
V0 to V3 must not
exceed VCC
Input voltage*1
VI
-
VSS - 0.3
VSS + 6.0
V
VI ≤ (D)VCC + 0.3V*3
Output voltage*1
VO
-
VSS - 0.3
VSS + 6.0
V
VO ≤ (D)VCC + 0.3V*3
Maximum Clamp
Current
ICLAMP - -4.0 +4.0 mA
Applicable to general
purpose I/O pins *
4
Total Maximum
Clamp Current
Σ|ICLAMP| - - 16 mA
Applicable to general
purpose I/O pins *
4
"L" level maximum
output current
IOL
-
-
15
mA
Normal port
IOLSMC
TA= -40°C
-
52
mA
High current port
TA= +25°C
-
39
mA
TA= +85°C
-
32
mA
TA= +105°C
-
30
mA
"L" level average
output current
IOLAV
-
-
4
mA
Normal port
IOLAVSMC
TA= -40°C
-
40
mA
High current port
TA= +25°C
-
30
mA
TA= +85°C
-
25
mA
TA= +105°C
-
23
mA
"L" level maximum
overall output
current
ΣIOL
-
-
34
mA
Normal port
ΣIOLSMC - - 180 mA High current port
"L" level average
overall output
current
ΣIOLAV
-
-
17
mA
Normal port
ΣIOLAVSMC - - 90 mA High current port
"H" level maximum
output current
IOH
-
-
-15
mA
Normal port
IOHSMC
TA= -40°C
-
-52
mA
High current port
TA= +25°C
-
-39
mA
TA= +85°C
-
-32
mA
TA= +105°C
-
-30
mA
"H" level average
output current
IOHAV
-
-
-4
mA
Normal port
IOHAVSMC
TA= -40°C
-
-40
mA
High current port
TA= +25°C
-
-30
mA
TA= +85°C
-
-25
mA
TA= +105°C
-
-23
mA
"H" level maximum
overall output
current
ΣIOH
-
-
-34
mA
Normal port
ΣIOHSMC - - -180 mA High current port
"H" level average
overall output
current
ΣIOHAV
-
-
-17
mA
Normal port
ΣIOHAVSMC - - -90 mA High current port
Power
consumption*
5
PD TA= +105°C - 281*6 mW
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Parameter Symbol Condition
Rating
Unit Remarks
Min
Max
Operating ambient
temperature
TA - -40 +105 °C
Storage temperature
TSTG
-
-55
+150
°C
*1: This parameter is based on VSS = AV SS = DVSS = 0 V.
*2: AVCC and VCC and DVCC must be set to the same voltage. It is required that AVCC does not exceed VCC,
DVCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the
maximum current to/from an input is limited by some means with external components, the ICLAMP rating
supersedes the VI rating. Input/Output voltages of high current ports depend on DVCC. Input/Output voltages
of standard ports depend on VCC.
*4: • Applicable to all general purpose I/O pins (Pnn_m).
• Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the Power reset.
• The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative
clamping current (4mA). For protection against positive input voltages, use an external clamping diode
which limits the input voltage to maximum 6.0V.
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• Sample recommended circuits:
V
CC
R
+B input (0V to 16V)
Limiting
resistance
Protective diode
P-ch
N-ch
*5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL × IOL + VOH × IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC × (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC.
*6: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
(VSS = AV SS = DVSS = 0V)
Parameter Symbol
Value
Unit Remarks
Min
Ty p
Max
Power supply
voltage
V
CC
,
AV CC,
DVCC
2.7
-
5.5
V
2.0 - 5.5 V Maintains RAM data in stop mode
Smoothing
capacitor at C pin CS 0.5 1.0 to 3.9 4.7 µF
1.0µF (Allowance within ± 50%)
3.9µF (Allowance within ± 20%)
Please use the ceramic capacitor or the
capacitor of the frequency response of
this level.
The smoothing capacitor at VCC must
use the one of a capacity value that is
larger than CS.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
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3. DC Characteristics
(1) Current Rating
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
current in Run
modes*1
ICCPLL
Vcc
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32MHz
Flash 0 wait
(CLKRC and CLKSC
stopped)
- 25 - mA TA = +25°C
- - 34 mA TA = +105°C
ICCMAIN
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
Flash 0 wait
(CLKPLL, CLKSC and
CLKRC stopped)
- 3.5 - mA TA = +25°C
- - 7.5 mA TA = +105°C
ICCRCH
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = CLKRC =
2MHz
Flash 0 wait
(CLKMC, CLKPLL and
CLKSC stopped)
- 1.7 - mA TA = +25°C
- - 5.5 mA TA = +105°C
ICCRCL
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = CLKRC =
100kHz
Flash 0 wait
(CLKMC, CLKPLL and
CLKSC stopped)
- 0.15 - mA TA = +25°C
- - 3.2 mA TA = +105°C
ICCSUB
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
Flash 0 wait
(CLKMC, CLKPLL and
CLKRC stopped)
- 0.1 - mA TA = +25°C
- - 3 mA TA = +105°C
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Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
current in
Sleep modes*1
ICCSPLL
Vcc
PLL Sleep mode with
CLKS1/2 = CLKP1/2 =
32MHz
(CLKRC and CLKSC
stopped)
- 6.5 - mA TA = +25°C
- - 13 mA TA = +105°C
ICCSMAIN
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC
and CLKSC stopped)
- 0.9 - mA TA = +25°C
- - 4 mA TA = +105°C
ICCSRCH
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL
and CLKSC stopped)
- 0.5 - mA TA = +25°C
- - 3.5 mA TA = +105°C
ICCSRCL
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
CLKRC = 100kHz
(CLKMC, CLKPLL
and CLKSC stopped)
- 0.06 - mA TA = +25°C
- - 2.7 mA TA = +105°C
ICCSSUB
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz,
(CLKMC, CLKPLL
and CLKRC stopped)
- 0.04 - mA TA = +25°C
- - 2.5 mA TA = +105°C
Power supply
current in
Timer
modes*2
ICCTPLL
PLL Timer mode with
CLKPLL = 32MHz
(CLKRC and CLKSC
stopped)
- 1800 2245 µA TA = +25°C
- - 3140 µA TA = +105°C
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC
and CLKSC stopped)
- 285 325 µA TA = +25°C
- - 1055 µA TA = +105°C
ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKMC
and CLKSC stopped)
- 160 210 µA TA = +25°C
- - 970 µA TA = +105°C
ICCTRCL
RC Timer mode with
CLKRC = 100kHz
(CLKPLL, CLKMC
and CLKSC stopped)
- 30 70 µA TA = +25°C
- - 820 µA TA = +105°C
ICCTSUB
Sub Timer mode with
CLKSC = 32kHz
(CLKMC, CLKPLL
and CLKRC stopped)
- 25 55 µA TA = +25°C
- - 800 µA TA = +105°C
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Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Power supply
current in Stop
mode
*3
ICCH
Vcc
-
- 20 55 µA TA = +25°C
- - 800 µA TA = +105°C
Flash Power
Down current
ICCFLASHPD - - 36 70 µA
Power supply
current
for active Low
Voltage
detector*
4
ICCLVD Low voltage
detector enabled
- 5 - µA TA = +25°C
- - 12.5 µA TA = +105°C
Flash Write/
Erase current*5 ICCFLASH - - 12.5 - mA T
A
= +25°C
- - 20 mA TA = +105°C
*1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and
a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator
control circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On
Chip Debugger" part is not included. Power supply current in Run mode does not include Flash Write / Erase
current.
*2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a
32kHz external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not
included.
*3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
*4: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
*5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
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(2) Pin Characteristics
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter
Symbol
Pin
name
Conditions
Value
Unit
Remarks
Min
Typ
Max
"H" level
input
voltage
VIH
Port inputs
Pnn_m
-
V
CC
× 0.7
-
V
CC
+ 0.3
V
CMOS Hysteresis
input
-
V
CC
× 0.8
-
V
CC
+ 0.3
V
AUTOMOTIVE
Hysteresis input
VIHX0S X0
External clock in
"Fast Clock Input mode"
VD
× 0.8
- VD V VD=1.8V±0.15V
VIHX0AS X0A
External clock in
"Oscillation mode"
V
CC
× 0.8
-
V
CC
+ 0.3
V
VIHR RSTX -
V
CC
× 0.8
-
V
CC
+ 0.3
V
CMOS Hysteresis
input
VIHM MD -
V
CC
- 0.3
-
V
CC
+ 0.3
V
CMOS Hysteresis
input
VIHD
DEBUG
I/F
- 2.0 -
V
CC
+ 0.3
V TTL Input
"L" level
input
voltage
VIL
Port
inputs
Pnn_m
-
V
SS
- 0.3
-
V
CC
× 0.3
V
CMOS Hysteresis
input
-
V
SS
- 0.3
-
V
CC
× 0.5
V
AUTOMOTIVE
Hysteresis input
VILX0S X0
External clock in "Fast
Clock Input mode"
VSS -
VD
× 0.2
V VD=1.8V±0.15V
VILX0AS X0A
External clock in
"Oscillation mode"
V
SS
- 0.3
-
V
CC
× 0.2
V
VILR RSTX -
V
SS
- 0.3
-
V
CC
× 0.2
V
CMOS Hysteresis
input
VILM MD -
V
SS
- 0.3
-
V
SS
+ 0.3
V
CMOS Hysteresis
input
VILD
DEBUG
I/F
-
V
SS
- 0.3
- 0.8 V TTL Input
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Parameter
Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
"H" level
output
voltage
VOH4 4mA
type
4.5V ≤ (D)V
CC
≤ 5.5V
IOH = -4mA
(D)VCC
- 0.5 - (D)VCC V
2.7V ≤ (D)V
CC
< 4.5V
IOH = -1.5mA
VOH30
High
Drive
type*
4.5V ≤ DV
CC
≤ 5.5V
IOH = -52mA
DVCC
- 0.5 - DVCC V
TA = -40°C
2.7V ≤ DV
CC
< 4.5V
IOH = -18mA
4.5V ≤ DV
CC
≤ 5.5V
IOH = -39mA
TA = +25°C
2.7V ≤ DV
CC
< 4.5V
IOH = -16mA
4.5V ≤ DV
CC
≤ 5.5V
IOH = -32mA
TA = +85°C
2.7V ≤ DV
CC
< 4.5V
IOH = -14.5mA
4.5V ≤ DV
CC
≤ 5.5V
IOH = -30mA
TA = +105°C
2.7V ≤ DV
CC
< 4.5V
IOH = -14mA
VOH3 3mA
type
4.5V ≤ V
CC
≤ 5.5V
IOH = -3mA
VCC
- 0.5 - VCC V
2.7V ≤ V
CC
< 4.5V
IOH = -1.5mA
"L" level
output
voltage
VOL4 4mA
type
4.5V ≤ (D)V
CC
≤ 5.5V
IOL = +4mA
- - 0.4 V
2.7V ≤ (D)V
CC
< 4.5V
IOL = +1.7mA
VOL30
High
Drive
type*
4.5V ≤ DV
CC
≤ 5.5V
IOL = +52mA
- - 0.5 V
TA = -40°C
2.7V ≤ DV
CC
< 4.5V
IOL = +22mA
4.5V ≤ DV
CC
≤ 5.5V
IOL = +39mA
TA = +25°C
2.7V ≤ DV
CC
< 4.5V
IOL = +18mA
4.5V ≤ DV
CC
≤ 5.5V
IOL = +32mA
TA = +85°C
2.7V ≤ DV
CC
< 4.5V
IOL = +14mA
4.5V ≤ DV
CC
≤ 5.5V
IOL = +30mA
TA = +105°C
2.7V ≤ DV
CC
< 4.5V
IOL = +13.5mA
VOL3
3mA
type
2.7V ≤ V
CC
< 5.5V
IOL = +3mA
- - 0.4 V
VOLD
DEBUG
I/F
V
CC
= 2.7V
IOL = +25mA
0 - 0.25 V
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Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Input leak
current IIL
Pnn_m
VSS < VI < VCC
AVSS < VI <
AVCC, AVRH
- 1 - + 1 µA
Single port pin
except high
current output
I/O for SMC
P08_m
DVSS < VI < DVCC
AVSS < VI <
AV
CC
, AVRH
- 3 - + 3 µA
Total LCD
leak
current
Σ|IILCD| All SEG/
COM pin VCC = 5.0V - 0.5 10 µA
Maximum
leakage
current of all
LCD pins
Internal
LCD
divide
resistance
RLCD
Between
V3 and V2,
V2 and V1,
V1 and V0
VCC = 5.0V 6.25 12.5 25 kΩ
Pull-up
resistance
value
RPU Pnn_m VCC = 5.0V ±10% 25 50 100 kΩ
Pull-down
resistance
value
RDOWN P08_m VCC = 5.0V ±10% 25 50 100 kΩ
Input
capacitance CIN
Other than
C,
Vcc,
Vss,
DVcc
DVss,
AVcc,
AVss,
AV R H ,
P08_m
- - 5 15 pF
P08_m - - 15 30 pF
*: In the case of driving stepping motor directly or high current outputs, set "1" to the bit in the Port High Drive
Register (PHDRnn:HDx="1").
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4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = AV CC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Value
Unit Remarks
Min
Typ
Max
Input frequency fC X0,
X1
4 - 8 MHz
When using a crystal
oscillator, PLL off
- - 8 MHz
When using an opposite
phase external
clock, PLL off
4 - 8 MHz
When using a crystal
oscillator or opposite
phase external clock,
PLL on
Input frequency fFCI X0
- - 8 MHz
When using a single
phase external
clock in “Fast Clock
Input mode”, PLL off
4 - 8 MHz
When using a single
phase external
clock in “Fast Clock
Input mode”, PLL on
Input clock cycle tCYLH - 125 - - ns
Input clock pulse
width
PWH,
PWL - 55 - - ns
The amplitude changes by resistance, capacity which added outside or the difference of the device.
t
CYLH
Reference value:
1.8V±0.15V
X0,X1
When using the crystal oscillator
V
IHX0S
V
IHX0S
V
IHX0S
t
CYLH
X0
P
WH
V
ILX0S
P
WL
V
ILX0S
When using the external clock
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(2) Sub Clock Input Characteristics
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Ty p
Max
Input frequency fCL
X0A,
X1A
- - 32.768 - kHz
When using an
oscillation circuit
- - - 100 kHz
When using an
opposite phase
external clock
X0A - - - 50 kHz
When using a
single phase
external clock
Input clock cycle tCYLL - - 10 - - µs
Input clock pulse
width - - PWH/tCYLL,
P
WL
/t
CYLL
30 - 70 %
tCYLL
VCC
X0A,X1A
When using the crystal oscillator
V
IHX0AS
V
IHX0AS
V
IHX0AS
t
CYLL
X0A
P
WH
V
ILX0AS
P
WL
V
ILX0AS
When using the external clock
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(3) Built-in RC Oscillation Characteristics
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Value
Unit Remarks
Min
Typ
Max
Clock frequency fRC
50 100 200 kHz
When using slow frequency of
RC oscillator
1 2 4 MHz
When using fast frequency of
RC oscillator
RC clock stabilization
time tRCSTAB
80 160 320 µs
When using slow frequency of
RC oscillator
(16 RC clock cycles)
64 128 256 µs
When using fast frequency of
RC oscillator
(256 RC clock cycles)
(4) Internal Clock Timing
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Value
Unit
Min
Max
Internal System clock frequency
(CLKS1 and CLKS2) fCLKS1, fCLKS2 - 54 MHz
Internal CPU clock frequency (CLKB),
Internal peripheral clock frequency (CLKP1) fCLKB, fCLKP1 - 32 MHz
Internal peripheral clock frequency (CLKP2) fCLKP2 - 32 MHz
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(5) Operating Conditions of PLL
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Value
Unit Remarks
Min
Typ
Max
PLL oscillation stabilization wait time tLOCK 1 - 4 ms For CLKMC = 4MHz
PLL input clock frequency f
PLLI
4 - 8 MHz
PLL oscillation clock frequency fCLKVCO 56 - 108 MHz
Permitted VCO output
frequency of PLL
(CLKVCO)
PLL phase jitter tPSKEW -5 - +5 ns For CLKMC (PLL input
clock) ≥ 4MHz
PLL output
Deviation time from the ideal clock is assured per cycle out of 20,000 cycles.
Ideal clock
Slow
t1
t1
t2 t3 tn-1
tn-1
tn
tn
t2 t3
Fast
Deviation
time
(6) Reset Input
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol Pin name
Value
Unit
Min
Max
Reset input time tRSTL RSTX 10 - µs
Rejection of reset input time 1 - µs
RSTX
0.2V
CC
0.2V
CC
t
RSTL
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(7) Power-on Reset Timing
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol Pin name
Value
Unit
Min
Typ
Max
Power on rise time
tR
Vcc
0.05
-
30
ms
Power off time tOFF Vcc 1 - - ms
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below.
0.2V
2.7V
t
R
t
OFF
0.2V 0.2V
It is required that rises in voltage
have a slope of 50 mV/ms or less.
2.7V
5.0V
0V
V
CC
V
CC
V
SS
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(8) USART Timing
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C, CL=50pF)
Parameter Symbol
Pin
name
Conditions
4.5V ≤ VCC < 5.5V
2.7V ≤ VCC < 4.5V
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKn
Internal shift
clock mode
4tCLKP1
-
4tCLKP1
-
ns
SCK ↓ → SOT delay time tSLOVI
SCKn,
SOTn
- 20 + 20 - 30 + 30 ns
SOT → SCK ↑ delay time tOVSHI
SCKn,
SOTn
N
×
tCLKP1
– 20
*
- N
×
tCLKP1
– 30
*
- ns
SIN → SCK ↑ setup time tIVSHI
SCKn,
SINn
tCLKP1
+ 45
- tCLKP1
+ 55
- ns
SCK ↑ → SIN hold time tSHIXI
SCKn,
SINn
0 - 0 - ns
Serial clock "L" pulse width tSLSH SCKn
External shift
clock mode
tCLKP1
+ 10
- tCLKP1
+ 10
- ns
Serial clock "H" pulse width tSHSL SCKn tCLKP1
+ 10
- tCLKP1
+ 10
- ns
SCK ↓ → SOT delay time tSLOVE
SCKn,
SOTn
- 2tCLKP1
+ 45
- 2tCLKP1
+ 55
ns
SIN → SCK ↑ setup time tIVSHE
SCKn,
SINn
t
CLKP1
/2
+ 10
-
t
CLKP1
/2
+ 10
- ns
SCK ↑ → SIN hold time tSHIXE
SCKn,
SINn
tCLKP1
+ 10
- tCLKP1
+ 10
- ns
SCK fall time
tF
SCKn
-
20
-
20
ns
SCK rise time
tR
SCKn
-
20
-
20
ns
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by
some parameters. These parameters are shown in “MB96600 series HARDWARE MANUAL”.
• tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKn and SOTn_R is not guaranteed.
*: Parameter N depends on tSCYC and can be calculated as follows:
• If tSCYC = 2 × k × tCLKP1, then N = k, where k is an integer > 2
• If tSCYC = (2 × k + 1) × tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
tSCYC N
4 × tCLKP1 2
5 × tCLKP1, 6 × tCLKP1 3
7 × tCLKP1, 8 × tCLKP1 4
... ...
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tSCYC
VOL VOL
VOH
VOH
VIH VIH
VIL
VIL
tSLOVI
tIVSHI tSHIXI
VOL
SCK
SOT
SIN
Internal shift clock mode
tOVSHI
tSLSH
V
IH
V
IH
V
IH
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
OL
V
OH
t
SLOVE
t
R
t
SHIXE
t
IVSHE
t
F
SCK
SOT
SIN
tSHSL
External shift clock mode
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(9) External Input Timing
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol Pin name
Value
Unit Remarks
Min
Max
Input pulse width tINH,
tINL
Pnn_m
2tCLKP1 +200
(tCLKP1=
1/fCLKP1)*
- ns
General Purpose I/O
ADTG
A/D Converter trigger
input
TINn, TINn_R
Reload Timer
TTGn
PPG trigger input
INn, INn_R
Input Capture
INTn, INTn_R
200 - ns
External Interrupt
NMI
Non-Maskable
Interrupt
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
V
IH
V
IL
t
INL
t
INH
V
IL
External input timing V
IH
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(10) I2C Timing
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol Conditions Typical mode
High-speed
mode*
4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
CL = 50pF,
R = (Vp/IOL)*1
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
tHDSTA 4.0 - 0.6 - µs
SCL clock "L" width
tLOW
4.7
-
1.3
-
µs
SCL clock "H" width
tHIGH
4.0
-
0.6
-
µs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA 4.7 - 0.6 - µs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT 0 3.45*2 0 0.9*3 µs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT 250 - 100 - ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO 4.0 - 0.6 - µs
Bus free time between
"STOP condition" and
"START condition"
tBUS 4.7 - 1.3 - µs
Pulse width of spikes which
will be suppressed by input
noise filter
tSP - 0 (1-1.5) ×
tCLKP1*5 0 (1-1.5) ×
tCLKP1*5 ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250ns".
*4: For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz.
*5: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time.
SDA
SCL
t
HDSTA
t
LOW
t
HDDAT
t
SUDAT
t
HIGH
t
SUSTA
t
HDSTA
t
SP
t
BUS
t
SUSTO
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5. A/D Converter
(1) Electrical Characteristics for the A/D Converter
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Value
Unit Remarks
Min
Typ
Max
Resolution
-
-
-
-
10
bit
Total error - - - 3.0 - + 3.0 LSB
Nonlinearity error - - - 2.5 - + 2.5 LSB
Differential
Nonlinearity error
- - - 1.9 - + 1.9 LSB
Zero transition
voltage VOT ANn Typ - 20 AV SS
+ 0.5LSB Typ + 20 mV
Full scale transition
voltage
VFST ANn Typ - 20
AV R H
- 1.5LSB
Typ + 20 mV
Compare time* - -
1.0
-
5.0
µs
4.5V ≤ ΑVCC ≤ 5.5V
2.2
-
8.0
µs
2.7V ≤ ΑVCC < 4.5V
Sampling time* - -
0.5
-
-
µs
4.5V ≤ ΑVCC ≤ 5.5V
1.2
-
-
µs
2.7V ≤ ΑVCC < 4.5V
Power supply
current
IA
AV CC
-
2.0
3.1
mA
A/D Converter active
IAH - - 3.3 µA
A/D Converter not
operated
Reference power
supply current
(between AVRH
and AV SS )
IR
AV R H
- 520 810 µA A/D Converter active
IRH - - 1.0 µA
A/D Converter not
operated
Analog input
capacity CVIN
AN8, 9, 12,
13
- - 15.5 pF Normal outputs
AN16 to 23
-
-
17.4
pF
High current outputs
Analog impedance RVIN ANn
-
-
1450
Ω
4.5V ≤ AV CC ≤ 5.5V
-
-
2700
Ω
2.7V ≤ AV CC < 4.5V
Analog port input
current (during
conversion)
IAIN
AN8, 9, 12,
13
- 1.0 - + 1.0 µA AV SS < VAIN <
AVCC, AVRH
AN16 to 23
- 3.0
-
+ 3.0
µA
Analog input
voltage
VAIN ANn AV SS - AV R H V
Reference voltage
range
- AV R H
AV
CC
- 0.1
- AV CC V
Variation between
channels
- ANn - - 4.0 LSB
*: Time for each channel.
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(2) Accuracy and Setting of the A/D Converter Sampling Time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the
internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling
time (Tsamp) depends on the external driving impedance Rext, the board capacitance of the A/D converter
input pin Cext and the AVCC voltage level. The following replacement model can be used for the calculation:
Sampling switch
(During sampling:ON)
CVIN
RVIN
Analog
input
MCU
Rext
Cext
Source Comparator
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Analog input capacity (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
The following approximation formula for the replacement model above can be used:
Tsamp = 7.62 × (Rext × Cext + (Rext + RVIN) × CVIN)
• Do not select a sampling time below the absolute minimum permitted value.
(0.5µs for 4.5V ≤ AVCC ≤ 5.5V, 1.2µs for 2.7V ≤ AVCC < 4.5V)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1µF to the analog input pin.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin
input leakage current IIL (static current before the sampling switch) or the analog input leakage
current IAIN (total leakage current of pin input and comparator during sampling). The effect of the
pin input leakage current IIL cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVSS| becomes smaller.
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(3) Definition of A/D Converter Terms
• Resolution : Analog variation that is recognized by an A/D converter.
• Nonlinearity error : Deviation of the actual conversion characteristics from a straight line that connects
the zero transition point (0b0000000000 ←→ 0b0000000001) to the full-scale
transition point (0b1111111110 ←→ 0b1111111111).
• Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to
change the output code by 1LSB.
• Total error : Difference between the actual value and the theoretical value. The total error
includes zero transition error, full-scale transition error and nonlinearity error.
• Zero transition voltage: Input voltage which results in the minimum conversion value.
• Full scale transition voltage: Input voltage which results in the maximum conversion value.
Nonlinearity error Differential nonlinearity error
Digital output
Digital output
Actual conversion
characteristics Actual conversion
characteristics
Ideal characteristics
Actual conversion
characteristics
Actual conversion characteristics
Ideal characteristics
Analog inputAnalog input
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
AVSS AVRH AVSS AVRH
0x(N-2)
0x(N-1)
0x(N+1)
0xN
{1 LSB(N-1) + VOT}
VNT
(Actually-measured
value)
VFST
(Actually-
measured
value)
VOT (Actually-measured value)
VNT
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
Nonlinearity error of digital output N =
VNT - {1LSB × (N - 1) + VOT}
[LSB]
1LSB
Differential nonlinearity error of digital output N =
V(N + 1) T - VNT
- 1 [LSB]
1LSB
1LSB =
VFST - VOT
1022
N : A/D converter digital output value.
VOT : Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0x3FE to 0x3FF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
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Total error
Digital output
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
Analog input
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
AVSS AVRH
1.5 LSB
0.5 LSB
V
NT
(Actually-measured value)
{1 LSB (N-1) + 0.5 LSB}
1LSB (Ideal value) =
AVRH - AVSS
[V]
1024
Total error of digital output N =
VNT - {1LSB × (N - 1) + 0.5LSB}
1LSB
N : A/D converter digital output value.
VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT (Ideal value) = AVSS + 0.5LSB[V]
VFST (Ideal value) = AVRH - 1.5LSB[V]
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6. High Current Output Slew Rate
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol
Pin
name
Conditions
Value
Unit Remarks
Min
Typ
Max
Output rise/fall
time
tR30,
tF30 P08_m
Outputs
driving
strength set to
"30mA"
15 - 75 ns CL=85pF
V
H
V
H
Voltage
Time
V
L
V
L
V
H
=V
OL30
+0.9 × (V
OH30
-V
OL30
)
V
L
=V
OL30
+0.1 × (V
OH30
-V
OL30
)
t
R30
t
F30
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7. Low Voltage Detection Function Characteristics
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Symbol Conditions
Value
Unit
Min
Typ
Max
Detected voltage*1
VDL0
CILCR:LVL = 0000B
2.70
2.90
3.10
V
VDL1
CILCR:LVL = 0001B
2.79
3.00
3.21
V
VDL2
CILCR:LVL = 0010B
2.98
3.20
3.42
V
VDL3
CILCR:LVL = 0011B
3.26
3.50
3.74
V
VDL4
CILCR:LVL = 0100B
3.45
3.70
3.95
V
VDL5
CILCR:LVL = 0111B
3.73
4.00
4.27
V
VDL6
CILCR:LVL = 1001B
3.91
4.20
4.49
V
Power supply voltage
change rate*2 dV/dt - - 0.004 - + 0.004 V/µs
Hysteresis width VHYS CILCR:LVHYS=0 - - 50 mV
CILCR:LVHYS=1 80 100 120 mV
Stabilization time TLVDSTAB - - - 75 µs
Detection delay time
td
-
-
-
30
µs
*1: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a
possibility that the low voltage detection will occur or stop after the power supply voltage passes the
detection range.
*2: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation
of the power supply voltage within the limits of the change ration of power supply voltage.
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Time
Vcc
VDLX min
Voltage
VDLX max
dV
dt
Detected Voltage
Time
Vcc
td
Voltage
td
V
HYS
dV
dt
Internal Reset
Release Voltage
Normal Operation
Low Voltage Reset Assertion Power Reset Extension Time
RCR:LVDE
···Low voltage detection
function enable
Low voltage detection
function disable
Stabilization time
T
LVDSTAB
Low voltage detection
function enable···
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8. Flash Memory Write/Erase Characteristics
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
Parameter Conditions
Value
Unit Remarks
Min
Typ
Max
Sector erase time
Large Sector
-
-
1.6
7.5
s
Includes write time
prior to internal erase.
Small Sector
-
-
0.4
2.1
s
Security Sector
-
-
0.31
1.65
s
Word (16-bit) write time - - 25 400 µs
Not including
system-level overhead
time.
Chip erase time - - 5.11 25.05 s
Includes write time
prior to internal erase.
Note: While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the
application system where the external power (VCC) might be shut down while writing or erasing, be sure
to turn the power off by using a low voltage detection function.
To put it concrete, change the external power in the range of change ration of power supply voltage
(-0.004V/µs to +0.004V/µs) after the external power falls below the detection voltage (VDLX)*1.
Write/Erase cycles and data hold time
Write/Erase cycles
(cycle)
Data hold time
(year)
1,000
20 *2
10,000
10 *2
100,000
5 *2
*1: See "7. Low Voltage Detection Function Characteristics".
*2: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
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EXAMPLE CHARACTERISTICS
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
• MB96F675
0.01
0.10
1.00
10.00
100.00
-50 0 50 100 150
I
CC
[mA]
T
A
[ºC]
Run Mode
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
RC clock (100kHz)
Sub osc. (32kHz)
(V
CC
= 5.5V)
0.001
0.010
0.100
1.000
10.000
100.000
-50 0 50 100 150
I
CC
[mA]
T
A
[ºC]
Sleep Mode
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
RC clock (100kHz)
Sub osc. (32kHz)
(V
CC
= 5.5V)
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• MB96F675
0.001
0.010
0.100
1.000
10.000
-50 0 50 100 150
I
CC
[mA]
T
A
[ºC]
Timer Mode
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
RC clock (100kHz)
Sub osc. (32kHz)
(V
CC
= 5.5V)
0.001
0.010
0.100
1.000
-50 0 50 100 150
I
CC
[mA]
T
A
[ºC]
Stop Mode
(V
CC
= 5.5V)
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• Used setting
Mode
Selected Source
Clock
Clock/Regulator and FLASH Settings
Run mode
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz
Main osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz
RC clock fast
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz
RC clock slow
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz
Sleep mode
PLL
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
Main osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
RC clock fast
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
RC clock slow
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
Timer mode
PLL
CLKMC = 4MHz, CLKPLL = 32MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
Main osc.
CLKMC = 4MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock fast
CLKMC = 2MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock slow
CLKMC = 100kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Sub osc.
CLKMC = 32 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Stop mode
stopped
(All clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
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ORDERING INFORMATION
MCU with CAN controller
Part number
Flash memory
Package*
MB96F673RBPMC-GSE1
Flash A
(96.5KB)
64-pin plastic LQFP
(FPT-64P-M23)
MB96F673RBPMC-GSE2
MB96F673RBPMC1-GSE1
64-pin plastic LQFP
(FPT-64P-M24)
MB96F673RBPMC1-GSE2
MB96F675RBPMC-GSE1
Flash A
(160.5KB)
64-pin plastic LQFP
(FPT-64P-M23)
MB96F675RBPMC-GSE2
MB96F675RBPMC1-GSE1
64-pin plastic LQFP
(FPT-64P-M24)
MB96F675RBPMC1-GSE2
*: For details about package, see "PACKAGE DIMENSION".
MCU without CAN controller
Part number
Flash memory
Package*
MB96F673ABPMC-GSE1
Flash A
(96.5KB)
64-pin plastic LQFP
(FPT-64P-M23)
MB96F673ABPMC-GSE2
MB96F673ABPMC1-GSE1
64-pin plastic LQFP
(FPT-64P-M24)
MB96F673ABPMC1-GSE2
MB96F675ABPMC-GSE1
Flash A
(160.5KB)
64-pin plastic LQFP
(FPT-64P-M23)
MB96F675ABPMC-GSE2
MB96F675ABPMC1-GSE1
64-pin plastic LQFP
(FPT-64P-M24)
MB96F675ABPMC1-GSE2
*: For details about package, see "PACKAGE DIMENSION".
65
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PACKAGE DIMENSION
64-pin plastic LQFP Lead pitch 0.65 mm
Package width ×
package length 12.0 × 12.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.47 g
Code
(Reference)P-LQFP64-12 ×12-0.65
64-pin plastic LQFP
(FPT-64P-M23)
(FPT-64P-M23)
C2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4
0.65(.026)
0.10(.004)
116
17
3249
64
3348
*12.00±0.10(.472± .004)SQ
14.00±0.20(.551± .008)SQ
INDEX
0.32±0.05
(.013± .002)
M
0.13(.005)
0.145±0.055
(.006± .002)
"A"
.059–.004
+.008
–0.10
+0.20
1.50
0~8°
0.25(.010)
(Mounting height)
0.50±0.20
(.020± .008)
0.60±0.15
(.024± .006)
0.10± 0.10
(.004± .004)
Details of "A" part
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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64-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 10.0 × 10.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.32 g
Code
(Reference)P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
(FPT-64P-M24)
LEAD No.
Details of "A" part
0.25(.010)
(Stand off)
0.10±0.10
0.60±0.15
(.024±.006)
0.50±0.20
(.020±.008)
1.50+0.20
–0.10
+.008
–.004
.059
0°~8°
"A"
0.08(.003)
0.145±0.055
(.006±.002)
0.08(.003)
M
(.008±.002)
0.20±0.05
0.50(.020)
12.00±0.20(.472±.008)SQ
INDEX
49
64
3348
17
32
161
2005-2010 FUJITSU SEMICONDUCTOR LIMITED F64036S-c-1-3
C
(Mounting height)
*10.00±0.10(.394±.004)SQ
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
(.004±.004)
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
67
FUJITSU SEMICONDUCTOR CONFIDENTIAL
MB96670 S er ies
DS704-00001-2v0-E
MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
4
FEATURES
Changed the description of “LCD Controller”
On-chip drivers for internal divider resistors or external divider
resistors
→
Internal divider resistors or external divider resistors
Changed the description of “External Interrupts”
Interrupt mask and pending bit per channel
→
Interrupt mask bit per channel
9
PIN DESCRIPTION
Deleted Pin name
WOT
27 to
30
HANDLING PRECAUTIONS
Added a section
33
HANDLING DEVICES
Changed the description in “11. SMC power supply pins”
To avoid this, VCC must always be powered on before DVCC.
→
To avoid this, VCC must always be powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
35
ELECTRICAL
CHARACTERISTICS
1. Absolute Maximum Ratings
Changed the annotation *2
It is required that AVCC does not exceed VCC and that the
voltage at the analog inputs does not exceed AVCC when the
power is switched on.
→
It is required that AVCC does not exceed VCC, DVCC and that the
voltage at the analog inputs does not exceed AVCC when the
power is switched on.
39
3. DC Characteristics
(1) Current Rating
Changed the Conditions for I
CCSRCH
CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 2MHz,
→
CLKS1/2 = CLKP1/2 = CLKRC = 2MHz,
Changed the Conditions for I
CCSRCL
CLKS1/2 = CLKB = CLKP1/2 = CLKRC = 100kHz
→
CLKS1/2 = CLKP1/2 = CLKRC = 100kHz
Changed the Conditions for I
CCTPLL
PLL Timer mode with CLKP1 = 32MHz
→
PLL Timer mode with CLKPLL = 32MHz
Changed the Value of “Power supply current in Timer modes”
ICCTPLL
Typ: 2480μA → 1800μA (TA = +25°C)
Max: 2710μA → 2245μA (TA = +25°C)
Max: 3955μA → 3140μA (TA = +105°C)
Changed the Conditions for I
CCTRCL
RC Timer mode with CLKRC = 100kHz,
SMCR:LPMSS = 0 (CLKPLL, CLKMC and CLKSC stopped)
→
RC Timer mode with CLKRC = 100kHz
(CLKPLL, CLKMC and CLKSC stopped)
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Page
Section
Change Results
40
ELECTRICAL
CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
Changed the annotation *2
Power supply for "On Chip Debugger" part is not included.
Power supply current in Run mode does not include
Flash Write / Erase current.
→
The current for "On Chip Debugger" part is not included.
Added the description to annotation *2, *3
When Flash is not in Power-down / reset mode, ICCFLASHPD must
be added to the Power supply current.
52
4. AC Characteristics
(10) I
2
C timing
Added parameter, “Noise filter” and an annotation *5 for it
Added tSP to the figure
54
5. A/D Converter
(2) Accuracy and Setting of the
A/D Converter Sampling Time
Deleted the unit “[Min]” from approximation formula of
Sampling time
57
6. High Current Output Slew
Rate
Changed the condition
(VCC = AV CC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS =
AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
→
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V,
TA = - 40°C to + 105°C)
60
8. Flash Memory Write/Erase
Characteristics
Changed the condition
(VCC = AV CC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS =
AV SS = DVSS = 0 V, T A = - 40°C to + 105°C)
→
(VCC = AV CC = DVCC = 2.7V to 5.5V, VSS = AV SS = DVSS = 0 V,
TA = - 40°C to + 105°C)
Changed the Note
While the Flash memory is written, shutdown of the external
power (VCC) is prohibited. In the application system where the
external power (VCC) might be shut down while writing, be sure
to turn the power off by using an external voltage detector.
→
While the Flash memory is written or erased, shutdown of the
external power (VCC) is prohibited. In the application system
where the external power (VCC) might be shut down while
writing or erasing, be sure to turn the power off by using a low
voltage detection function.
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MB96670 Ser ies
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FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further inform ati on please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fujitsu.com/kr/fsk/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road,
Pudong District, Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR")
reserves the right to make changes to the information contained in this document without notice. Please contact your
FUJITSU SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented
solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU
SEMICONDUCTOR disclaims any and all warranties of any kind, whether express or implied, related to such
information, including, without limitation, quality, accuracy, performance, proper operation of the device or
non-
infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR device based on
such information, you must assume any responsibility or liability arising out of or in connection with such information or
any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any damages whatsoever arising
out of or in connection with such information or any use thereof.
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strued as granting or conferring any right under any patents, copyrights, or
any other intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express
or implied. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual
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thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other
loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass
transport control system, medical life support system and military application), or (2) for use requiring extremely high
level of reliability (including, without limitation, submersible repeater and artificial satellite). FUJITSU
SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages arising out of or in
connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs
and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures
into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and
other abnormal operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade
Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are
responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and
technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Edited: Sales Promotion Department
