VNP20N07
"OMNIFET":
FULLY AUTOPROTECTED POWER MOSFET
March 2004
123
TO-220
B LOCK DI AG RAM
TYPE Vclamp RDS(on) Ilim
VNP20N07 70 V 0.05 Ω20 A
■LINE AR CURRENT LI MIT A TION
■THE RMAL SHUT DO W N
■SHORT C IRCUIT PROTECTION
■INTEGRATED CLAMP
■LOW CURRE NT DRA WN F RO M I NP UT PIN
■DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN
■ESD PROTECTION
■DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
■COMPATIBLE WITH STANDARD POWER
MOSFET
■ST AN DARD TO -220 PAC KAG E
D ESCRIP T ION
The VNP20N07 is a monolithic device made
using STMicroelectronics VIPower Technology,
intended for replacement of standard power
MOSFETS in DC to 50 KHz applications.
Built-in thermal shut-down, linear current limi-
tation and overvoltage clamp protect the chip
in harsh enviroments.
Fault feedback can be detected by monitoring th e
voltage at the input pin.
1/11
ABSOLUTE MAXIMUM RATING
Symbol Parameter Value Unit
VDS Drain-source Voltage (Vin = 0) Internally Clamped V
Vin Input Voltage 18 V
IDDrain Current Internally Limited A
IRReverse DC Output Current -28 A
Vesd Electrostatic Discharge (C= 100 pF, R=1.5 KΩ) 2000 V
Ptot Total Dissipation at Tc = 25 oC83W
T
j
Operating Junction Temperature Internally Limited oC
TcCase Operating Temperature Internally Limited oC
Tstg Storage Temperature -55 to 150 oC
THERMAL DATA
Rthj-case
Rthj-amb Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max 1.5
62.5
oC/W
oC/W
ELE CT RICAL CHAR ACT ERIST I CS (Tcase = 25 oC unless otherwise specif ied)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCLAMP Drain-source Clamp
Voltage ID = 200 mA Vin = 0 607080 V
V
CLTH Drain-source Clamp
Threshold Voltage ID = 2 mA Vin = 0 55 V
VINCL Input-Source Reverse
Clamp Voltage Iin = -1 mA -1 -0.3 V
IDSS Zero Input Voltage
Drain Current (Vin = 0) VDS = 13 V Vin = 0
VDS = 25 V Vin = 0 50
200 µA
µA
IISS Supply Current from
Input Pin VDS = 0 V Vin = 10 V 250 500 µA
ON (∗)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VIN(th) Input Threshold
Voltage VDS = Vin ID + Iin = 1 mA 0.8 3 V
RDS(on) Static Drain-source On
Resistance Vin = 10 V ID = 10 A
Vin = 5 V ID = 10 A 0.05
0.07 Ω
Ω
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (∗) Forward
Transconductance VDS = 13 V ID = 10 A 13 17 S
Coss Output Capacitance V DS = 13 V f = 1 MHz Vin = 0 500 800 pF
VNP20N07
2/11
ELE CT RICAL CHAR ACT ERIST I CS (continued)
SWI T CHING (∗∗)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
VDD = 15 V Id = 10 A
Vgen = 10 V Rgen = 10 Ω
(see figure 3)
90
240
430
150
180
400
800
300
ns
ns
ns
ns
td(on)
tr
td(off)
tf
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
VDD = 15 V Id = 10 A
Vgen = 10 V Rgen = 1000 Ω
(see figure 3)
800
1.5
6
3.5
1200
2.2
10
5.5
ns
µs
µs
µs
(di/dt)on Turn-on Current Slope VDD = 15 V ID = 10 A
Vin = 10 V Rgen = 10 Ω60 A/µs
QiTotal Input Charge VDD = 12 V ID = 10 A Vin = 10 V 60 nC
SOUR CE DRAI N DIO DE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VSD (∗) Forward On Voltage ISD = 10 A Vin = 0 1.6 V
trr(∗∗)
Qrr(∗∗)
IRRM(∗∗)
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
ISD = 10 A di/dt = 100 A/µs
VDD = 30 V Tj = 25 oC
(see test circuit, figure 5)
165
0.55
6.5
ns
µC
A
PROTECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Ilim Drain Current Limit Vin = 10 V VDS = 13 V
Vin = 5 V VDS = 13 V 14
14 20
20 28
28 A
A
tdlim(∗∗) Step Response
Current Limit Vin = 10 V
Vin = 5 V 29
70 60
140 µs
µs
Tjsh(∗∗) Overtemperature
Shutdown 150 oC
Tjrs(∗∗) Overtemperature Reset 135 oC
Igf(∗∗) Fault Sink Current Vin = 10 V
Vin = 5 V 50
20 mA
mA
Eas(∗∗) Single Pulse
Avalanche Energy starting Tj = 25 oC VDD = 20 V
Vin = 10 V Rgen = 1 KΩ L = 10 mH 0.95 J
(∗) P ulsed: P ulse duration = 300 µs, duty cy cle 1.5 %
(∗∗) Parameters guarant eed by des ign/c haracterizat i on
VNP20N07
3/11
During normal operation, the Input pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC to 50 KHz. The only difference
from the user’s standpoint is that a small DC
current (Iiss) flows into the Input pin in order to
supply the i nternal circuitry .
The device integrat es:
-OVERVOLTAGE CLAMP PROTECTION:
internally set at 70V, along with the rugged
avalanche characteristics of the Power
MOSFET stage give this device unrivalled
ruggedness and energy handling capability.
This feature is mainly important when driving
inductive loads.
-LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current Id to Ilim whatever the Input
pin voltage. When the current limiter is active,
the device operates in the linear region, so
power dissipation may exceed the capability of
the heatsink. Both case and junction
temperatures increase, and if this phase lasts
long enough, junction temperature may reach
the overtemperat ure thres hold Tjsh.
-OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing
the chip temperature and are not dependent on
the input voltage. The location of the sensing
element on the chip in the power stage area
ensures fast , accurate detection of the junction
temperature. Overtemperature cutout occurs at
minimum 150oC. The device is automatically
restarted when the chip temperature falls
below 135oC.
-STATUS FEEDBACK: In the case of an
overtemperature fault condition, a Status
Feedback is provided through the Input pin.
The internal protection circuit disconnects the
input from the gate and connects it instead to
ground via an equivalent resistance of 100 Ω.
The failure can be detected by monitoring the
voltage at the Input pin, which will be close to
ground potential.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit (with a small increas e in RDS(on)).
PROTECTION FEATURES
VNP20N07
4/11
Thermal Impedance
Out put Charact eris tics
St atic Drain-S ource On Resist ance vs I nput
Voltage
Derating Curve
Transconductance
Static Drain-Sourc e On Resistance
VNP20N07
5/11
St atic Drain-Sourc e On Resistance
Capacitance Variations
N ormalized On Resist ance vs Temperat ure
Input Charge vs Input V oltage
Normalized Input T hres hold Voltage vs
Temperature
Normalized O n Resist ance vs Temperature
VNP20N07
6/11
Turn-on Current Slope
Turn-off Drain-Source Voltage Slope
Switching Time Resis tive Load
Turn- on Current Slope
Turn- off Drain-Source Voltage Slope
Switching Time Resistive Load
VNP20N07
7/11
Switching Time Resis tive Load
St ep Response Current Limit
Cur rent Limit v s Junction Temperat ur e
Sourc e Drain Diode Forward Charac teris tic s
VNP20N07
8/11
Fig. 2: Unclamped Inductiv e Wav eform s
Fig. 3: Switching Times Test Circuit s Fo r
R esistive Load Fig. 4: Input Charge T est Cir cuit
Fig. 1: Unclamped Induct ive Load Test Circ uits
Fig. 5: Test Circuit For Inductive Load Switching
And Di ode Recovery Times Fig. 6: Waveforms
VNP20N07
9/11
10/11
VNP20N07
DIM. mm.
MIN. TYP MAX.
A 4.40 4.60
b 0.61 0.88
b1 1.15 1.70
c 0.49 0.70
D 15.25 15.75
E 10 10.40
e 2.40 2.70
e1 4.95 5.15
F 1.23 1.32
H1 6.20 6.60
J1 2.40 2.72
L13 14
L1 3.50 3.93
L20 16.40
L30 28.90
∅P 3.75 3.85
Q 2.65 2.95
Pa ckage Weight 1.9 G r. (T yp .)
TO-220 ME CHANI CAL DATA
11/11
VNP20N07
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