CYONS2100 ADVANCE OvationONSTM II Wired Gaming Laser Navigation System on Chip Features Description Programmable Blocks Highly integrated mouse-on-a-chip with programmable PSoC(R) MCU 32K Byte Flash memory 2K Byte SRAM memory Internal 24, 12, or 6 MHz main oscillator Internal 32 kHz low speed oscillator 16 bit data report enables high speed and high resolution Tracking Performance Continuously variable resolution: 400 to 3200 cpi independent of speed High speed with high accuracy tracking Speed up to 75 in/s Acceleration up to 30G The CYONS2100 is the version that is designed for high performance gaming applications. Enabled by the Cypress 0.13 micron mixed signal process technology, the device integrates the OptiCheck sensor with full speed USB into a single silicon chip that enables seamless communication between sensor and MCU/Full Speed USB. The sensor provides the best translation of hand motion into true gaming motion on PC. Peripheral interface Integrated full speed USB for wired applications SPI master for interface to external functions Up to 28 general purpose IO pins 2 I C This highly integrated solution is programmable. It provides mouse suppliers the ease of use to design a single PCB system and customize their product. With the VCSEL integrated in the same package, designers do not need to calibrate the laser power during the manufacturing process. This greatly increases production throughput and reduces manufacturing costs. Power Internal power system enables operation from 5V USB or 2.7 to 3.6V external supply Self adjusting power saving modes On-Chip Laser Vertical Cavity Surface Emitting Laser (VCSEL) integrated within the sensor package No calibration or alignment needed ESD immunity: 2000V (human body model) Wavelength: 850 nm Typ (840 nm min, 870 nm max) Class 1 Safety: built in TUC compliant eye safety fault tolerant laser drive circuitry The innovative technology of OvationONSTM II provides high precision, high speed motion tracking, and low power consumption. Designers can select from a family of integration options, ranging from low power to high performance, to target different types of wired and wireless design applications. The CYONS2100 is a member of Cypress Semiconductor's second generation laser navigation SoC family of products. Powered by the high speed and high precision OptiCheckTM technology, along with the world leading PSoC technology, this family integrates the sensor, USB, and MCU functions into one chip. Bundled with the Vertical Cavity Surface Emitting Laser (VCSEL) into one package, the combination forms the market's first true Mouse-on-a-Chip solution. The CYONS2100 solutions have a small form factor. Along with the lens, each package forms a complete and compact laser tracking system. This data sheet describes the detailed technology capabilities of the CYONS2100. Figure 1. CYONS2100/CYONSLENS2000 (2-Piece System) Snap On Lens Molded Optic: Self aligning snap on molded lens 6 mm distance between the PCB and tracking surface Cypress Semiconductor Corporation Document Number: 001-44046 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 5, 2008 [+] Feedback CYONS2100 ADVANCE OvationONS II Family Performance Table Parameter CYONS2000 CYONS2001 Variable resolution CYONS2100 CYONS2101 CYONS2110 Unit 400, 800, 1600 400, 800, 1600 400-3200 400-3200 400-3200 cpi Maximum speed 30 30 75 75 75 in/s Maximum acceleration 20 20 30 30 30 G Integrated MCU Yes Yes Yes Yes Yes CapSense No No No No 26 inputs Flash 16K 16K 32K 32K 32K Byte SRAM 2K 2K 2K 2K 2K Byte Full speed USB 4 wire SPI up to 28 GPIOs 4 wire SPI up to 28 GPIOs Full speed USB 4 wire SPI up to 28 GPIO 4 wire SPI up to 28 GPIOs Full speed USB 4 wire SPI up to 28 GPIOs NA 0.8 - 3.6 NA 0.8 to 3.6 0.8 to 3.6 V 4.25 to 5.25 NA 4.25 to 5.25 NA 4.25 to 5.25 V 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 2.7 - 3.6 V 1 1 1 1 1 count Interfaces Battery supply voltage USB supply voltage External supply voltage Zero motion OvationONS II Family Applications Wired and wireless laser mice Gaming, graphic design, desktop, and mobile mice Optical trackballs Battery powered devices Motion sensing applications OvationONS II Family Functional Description The OvationONS II family is a two-piece laser navigation system on chip (SoC) kit containing the integrated IC package and the molded lens. The 2 kV ESD rated IC package integrates the VCSEL and laser sensor SoC. Depending on the product selected, the SoC includes a microcontroller unit (MCU), Flash, SRAM, internal oscillator, CapSense system, battery boost regulator, power regulator, and full speed USB. The molded lens collimates the VCSEL beam and images the light scattered from the tracking surface on to the sensor portion of the laser detector. The lens has features for registration to the package and easily snaps on to the PC board. At the heart of the system is the OptiCheck laser navigation engine. It supports all functions required for tracking, including laser power control, resolution control, and self-adjusting power reduction, which reduces power consumption when motion stops. The laser output power is pre-calibrated to meet the eye safety requirements of IEC 60825 Class 1. The navigation engine is accessed and controlled by an integrated PSoC-based MCU. The interface between the two blocks is through a system bus and a collection of navigation Document Number: 001-44046 Rev. *A engine interrupts. Full details are available in the Technical Reference Manual. In addition to controlling the navigation engine, the PSoC MCU also serves as the main application processor. Based on Cypress's M8C architecture, the PSoC supports a rich instruction set, multiple processor speeds, flexible general purpose IOs (GPIOs). Its internal oscillator requires no external crystal. On-chip Flash and RAM enable entire navigation systems to be implemented with the single SoC. The OvationONS II Family supports a wide range of powering options. Internal regulators minimize the need for external circuitry. Depending on the product selected, the device can be powered from USB's 5V supply, from a single battery, from dual batteries, or from an external supply. The configuration and use of the power blocks are controlled with the integrated PSoC. Wired sensors include integrated full speed USB. As with the navigation engine and power system, the USB block is controlled by the integrated PSoC. All sensors support a 4-wire SPI interface. A typical use of the SPI interface is to provide access to a radio for wireless applications. The CYONS2110 device also supports CapSense functions, enabling additional features and differentiation in end products. All features of the OvationONS II family are configured using Cypress's PSoC DesignerTM software, enabling fast application development and time to market. The OvationONS II family block diagram is shown in Figure 2. It shows a true System-on-a-Chip solution that enables design cycle reductions along with savings on manufacturing, PCB area, and component inventory management. The packaged solution delivers a fully integrated system that demonstrates tracking performance with efficient power consumption. Page 2 of 33 [+] Feedback CYONS2100 ADVANCE Figure 2. Block Diagram OptiCheckTM Navigation System Lift Detection DSP Resolution Control 3.3V Regulator Boost Regulator Battery Filter Power Control POWER BUS f VCSEL Laser Control Ovation II Power System Port 3 Port 2 Port 1 Port 0 1.8V Analog Regulator PSoC Core Regulator PSoC CORE SYSTEM BUS Global Analog Interconnect SRAM Supervisory ROM (SROM) Interrupt Controller Flash Nonvolatile Memory Sleep and Watchdog CPU Core (M8C) 32 kHz Internal Low Speed Oscillator (ILO) 6/12/24 MHz Internal Main Oscillator (IMO) Multiple Clock Sources SYSTEM BUS Full Speed USB Internal Voltage References POR and LVD System Resets SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks I2C Slave ADC CapSense System SYSTEM RESOURCES NOTE: Shaded blocks indicate optional functions - Refer to OvationONSTM II Family Performance Table for details Pin Descriptions This section describes, lists, and illustrates the CYONS2100 device pins and pinout configurations. The CYONS2100 is available in a 42-pin QFN package. Table 1. CYONS2100 Pin Descriptions Pin[1] Name Digital Analog Description 1 XRES I Active high external reset with internal pull down 2 DVSS Power 3 DNU 4 DVSS Power Power Digital ground 5 DVDD Power Power Digital supply voltage and regulated output (see page 10) 6 VREGD Power Power Digital VREG 7 AVDD Power Power Analog supply voltage 8 VREGA Power Power Analog VREG 9 P2[7] IO I Power Digital ground Do not use GPIO 10 P1[5] IOHR I SPI MISO, GPIO 11 P1[3] IOHR I SPI CLK, GPIO 12 P2[3] IO I GPIO 13 P2[5] IO I GPIO Document Number: 001-44046 Rev. *A Page 3 of 33 [+] Feedback CYONS2100 ADVANCE Table 1. CYONS2100 Pin Descriptions (continued) Pin[1] Name Digital Analog Description 14 P1[7] IOHR I SPI SS, GPIO 15 P1[1] IOHR I SPI MOSI, ISSP CLK(1), GPIO 16 P3[3] IOHR I HCLK (OCD high speed clock output), GPIO 17 P1[0] IO I ISSP DATA(1), GPIO 18 P3[5] IO I CCLK (OCD CPU clock output), GPIO 19 P1[6] IOHR I GPIO 20 P1[2] IOHR I GPIO 21 P2[2] IO I GPIO 22 P3[7] IO I OCDOE (OCD mode direction pin), GPIO 23 P3[1] IO I OCDO (OCD odd data output), GPIO 24 OCDE OCD OCD 25 AVSS Power Power OCDE (OCD even data output) 26 P2[1] IO I GPIO 27 P2[0] IO I GPIO 28 P1[4] IOHR I EXT CLK, GPIO 29 P2[4] IO I GPIO 30 DVSS Power Power 31 P2[6] IO I GPIO 32 P0[0] IO I GPIO 33 P0[2] IO I GPIO 34 P0[4] IO I GPIO 35 P0[6] IO I GPIO 36 P0[1] IO I GPIO 37 P0[3] IO I GPIO 38 P0[5] IO I GPIO 39 P0[7] IO I GPIO 40 D- IO USB data 41 D+ IO USB data Analog ground Digital ground 42 VDD5V Power Power 5V power CP DVSS Power Power Center pad must be connected to digital ground Legend: I=Input; O=Output; H=5 mA High Output Drive, R=Regulated Output, OCD=On-Chip Debug Note 1. These are the ISSP pins, which are not High Z at POR (Power On Reset) Document Number: 001-44046 Rev. *A Page 4 of 33 [+] Feedback CYONS2100 ADVANCE AI, P0[5] AI, P0[3] AI, P0[1] AI, P0[6] 38 37 35 34 33 32 31 30 29 28 27 26 25 24 23 CYONS2100 QFN Flexible on-chip memory 32K flash program storage 50,000 erase and write cycles 2K bytes SRAM data storage Partial flash updates Flexible protection modes In-System Serial Programming (ISSP) Full speed USB (12 Mbps) Eight unidirectional endpoints One bidirectional control endpoint USB 2.0 Compliant Dedicated 512 byte buffer Internal 3.3V output regulator 14 15 16 17 18 19 20 21 22 AI, SPI SS, P1[7] AI, SPI MOSI, ISSP CLK, P1[1] AI, HCLK, P3[3] AI, ISSP DATA, P1[0] AI, CCLK, P3[5] AI, P1[6] AI, P1[2] AI, OCDOE, P3[7] Complete development tools Free development tool (PSoC Designer) Full featured In-Circuit Emulator and programmer Full speed emulation Complex breakpoint structure 128K trace memory Document Number: 001-44046 Rev. *A AI, P0[4] AI, P0[2] AI, P0[0] AI, P2[6] DVSS AI, P2[4] AI, EXT CLK, P1[4] AI, P2[0] AI, P2[1] AVSS OCDE AI, OCDO, P3[1] Precision programmable clocking Internal 5.0% 6, 12, or 24 MHz main oscillator Internal low speed oscillator at 32 kHz for watchdog and sleep Support for optional external 32 kHz crystal 0.25% accuracy for USB with no external crystal Programmable pin configurations 25 mA sink current on all GPIO Pull Up, High-Z, Open Drain drive modes on all GPIO CMOS drive mode on ports 0 and 1 Up to 28 analog inputs on GPIO Configurable inputs on all GPIO Selectable, regulated Digital IO on port 1 3.0V, 20 mA total port 1 source current 5 mA source current mode on ports 0 and 1 Hot swap capable Versatile analog mux Common internal analog bus Simultaneous connection of IO combinations High PSRR comparator Low dropout voltage regulator for the analog array Additional system resources SPI Master and SPI Slave * Configurable between 46.9 kHz and 3 MHz Three 16-bit timers Watchdog and Sleep timers Internal voltage reference Integrated supervisory circuit Analog to digital converter 2 I C Slave Features Powerful Harvard Architecture processor M8C processor speed up to 24 MHz Low power at high speed Interrupt controller Operating temperature range: +5C to +45C AI, P2[2] 12 13 AI, P2[3] AI, P2[5] 10 11 AI, SPI CLK, P1[3] (Top View) Microcontroller System 36 AI, P0[7] 39 40 VDD5V D+ D41 1 2 3 4 5 6 7 8 9 AI, SPI MISO, P1[5] XRES DVSS DNU DVSS DVDD VREGD AVDD VREGA AI, P2[7] 42 Figure 3. Pin Diagram Page 5 of 33 [+] Feedback ADVANCE PSoC Functional Overview Cypress's Programmable System-on-Chip (PSoC) Mixed-Signal Arrays combine dynamic, configurable analog and digital blocks and an 8-bit MCU on a single chip, replacing multiple discrete components while delivering advanced flexibility and functionality. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture enables the creation of customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The architecture for this device family, as illustrated in Figure 2 on page 3, contains: the core, the navigation sensor, the power system, and the system resources (including a full speed USB port). A common, versatile bus enables connection between IO and the analog system. A GPIO, which provides access to the MCU and analog mux, is also included. The PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. The PSoC core encompasses SRAM for data storage, an interrupt controller, Sleep and Watchdog timers, an IMO (Internal Main Oscillator), and an ILO (Internal Low Speed Oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4 MIPS, 8-bit Harvard architecture microprocessor. System resources provide additional capability, such as configurable USB and SPI master-slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. The Analog Multiplexer System The analog mux bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. Analog signals may be routed to an internal analog-to-digital converter. Other multiplexer applications include: Chip-wide mux that enables analog input from any IO pin Crosspoint connection between any IO pin combinations Additional System Resources System resources, some previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The following statements describe the merits of each system resource: CYONS2100 The SPI master/slave module Provides communication over three or four wires Runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). An I2C slave module Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal reference provides an absolute reference for capacitive sensing. Getting Started The quickest path to understanding the Laser Sensor and PSoC silicon is to read this data sheet and use the PSoC Designer Integrated Development Environment (IDE). Reference Design Kits Reference design kits are available from Cypress. Contact your sales representative for information. Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, and advanced analog. Go to http://www.cypress.com/techtrain. Application Notes A long list of application notes assist you in every aspect of your design effort. To view the PSoC application notes, go to http://www.cypress.com and select Application Notes under the Documentation list located in the top right of the web page. Application notes are sorted by date by default. Development Tools PSoC Designer is a Microsoft Windows(R) based integrated development environment for the Programmable System-on-ChipTM (PSoC) devices. The PSoC Designer IDE and application runs on the Windows NT(R) 4.0, Windows 2000, Windows Millennium (Me), Windows XP, or Windows VistaTM operating systems. (Refer to PSoC Designer Functional Flow diagram in Figure 4 on page 7.) PSoC Designer helps the customer select an operating configuration for the USB, navigation, and power modules, write application code, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator (ICE), in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high level C language compiler developed specifically for the devices in the family. Document Number: 001-44046 Rev. *A Page 6 of 33 [+] Feedback ADVANCE Figure 4. PSoC Designer Subsystems CYONS2100 Application Editor In the Application Editor, edit the C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler The macro assembler enables the assembly code to merge seamlessly with C code. The link libraries automatically use absolute addressing or compile in relative mode, and link with other software modules to get absolute addressing. C Language Compiler A C language compiler supporting the CYONS2100 family of devices is available. Even if you have never worked in the C language before, the product quickly enables you to create complete C programs for the CYONS2100 family devices. The embedded, optimizing C compiler provides all the features of C tailored to the CYONS2100 architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, enabling the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands enable the designer to PSoC Designer Software Subsystems Device Editor The device editor subsystem enables the selection of different onboard analog and digital components, called user modules, using the CYONS2100 device blocks. Examples of user modules are timers, SPI, and so on. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration enables changing configurations at run time. PSoC Designer sets up power on initialization tables for selected CYONS2100 block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of CYONS2100 block configurations at run time. PSoC Designer can print a configuration sheet for a supplied project configuration for use during application programming in conjunction with the device data sheet. After the framework is generated, the user adds application specific code to complete the framework. It is also possible to change the selected components and regenerate the framework. Document Number: 001-44046 Rev. *A Read the program Read and write data memory Read and write IO registers Read and write CPU registers Set and clear breakpoints Provide program run, halt, and step control The debugger also enables the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator (ICE) A low cost, high functionality ICE is available for development support. This hardware can program single devices. Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, can implement a wide variety of user-selectable functions. Each Page 7 of 33 [+] Feedback CYONS2100 ADVANCE block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware and the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer IDE provides a library of prebuilt, pretested hardware peripheral functions, called user modules. User modules simplify selecting and implementing peripheral devices and come in analog, digital, and mixed signal varieties. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that enable you to tailor its precise configuration to your particular application. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt. Figure 5. User Module and Source Code Development Flows Device Editor Generate Application Application Editor Project Manager The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You must pick and place the user modules that you need for the project. The tool automatically builds signal chains by connecting user modules to the default IO pins or as required. At this stage, you can also configure the clock source connections and enter parameter values directly or by selecting values from drop down menus. When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Source Code Generator User Module Selection Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager The next step is to write your main program, and any subroutines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that enables you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep style" patterns. A single mouse click invokes the Build Manager. It employs a professional strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single step, run-to-breakpoint and watch variable features, the Debugger provides a large trace buffer and enables you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Document Number: 001-44046 Rev. *A Page 8 of 33 [+] Feedback CYONS2100 ADVANCE Document Conventions Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. Acronyms Used Table 2 lists the acronyms used in this document. Units of Measure The units of measure in Table 3 lists the abbreviations used to measure the devices. Table 2. Acronyms Acronym Description Acronym Description AC Alternating Current IO Input/output API Application Programming Interface LSb Least-significant Bit CPU Central Processing Unit LVD Low Voltage Detect DC Direct Current MSb Most-significant Bit GPIO General Purpose IO POR Power On Reset GUI Graphical User Interface PPOR Precision Power On Reset ICE In-circuit Emulator PSoC(R) Programmable System-on-chipTM ILO Internal Low Speed Oscillator SLIMO Slow IMO IMO Internal Main Oscillator SRAM Static Random Access Memory . Table 3. Units of Measure This table lists the units of measure used in this section Symbol Unit of Measure Symbol Unit of Measure C degree Celsius W microwatt dB decibel mA milliampere fF femtofarad ms millisecond Hz hertz mV millivolt KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolt k kilohm W ohm MHz megahertz pA picoampere M megaohm pF picofarad A microampere pp peak-to-peak F microfarad ppm parts per million H microhenry ps picosecond s microsecond sps samples per second V microvolts s sigma: one standard deviation Vrms microvolts root-mean-square V volt Document Number: 001-44046 Rev. *A Page 9 of 33 [+] Feedback CYONS2100 ADVANCE Power Supply Connections Figure 6. Power Connections CYONS2100 VDD5V 42 4.25 - 5.25 V 3.3V Regulator External 3.3V Supply, 15 mA max 10 nH 10 uF 10 uF DVDD 5 AVDD 7 USB IO Regulator VREGD 6 VREGA 8 Digital GND Analog GND 4 30 DVSS DVSS 3V Digital Circuitry 2 1.8V Digital Circuitry DVSS Analog GND 3V Analog Circuitry AVSS 25 1.8V Analog Circuitry Digital GND 1.8V PSoC Core Regulator 1.8V Analog Regulator Analog GND Digital GND Digital GND Digital GND Overview Using USB Power The CYONS2100 incorporates a powerful and flexible powering system. It can be powered from one of two sources: a 5V supply (typically from the USB VBUS line) or an external 3.3V supply. Additionally, the CYONS2100's internal regulators can supply current to external devices. This section describes the capabilities and usage of the power system. Refer to Figure 6 for a block diagram of the CYONS2100's power system. For most USB applications, the device is powered from the USB VBUS signal. In this case, the 5V VBUS signal should be connected directly to the CYONS2100's VDD5V pin. Understanding DVDD DVDD is a unique pin because it can serve as either an input or an output. When the device is powered from USB (using the 3.3V Regulator), DVDD acts as an output, providing a 3.3V voltage that can be used to power AVDD, VREGD, VREGA, and external parts. When the device is powered from an external 3.3V supply, DVDD acts as an input only. AVDD, VREGA, and VREGD Using External Power The CYONS2100 can also be powered from an external source. In this case, the external 3.3V source should connect to DVDD, and VDD5V should be left unconnected. Filtering and Grounding For all designs, it is important to provide proper grounding and proper isolation between the analog and digital power supplies. The analog and digital grounds should be isolated, except for a single connection point that is placed very close to the device. On the supply side, an L-C filter should be placed between AVDD and DVDD, as shown in the figure. As with DVDD, these signals power the internal circuitry of the device. Unlike DVDD, these are always inputs. They should be connected as shown in the figure. Document Number: 001-44046 Rev. *A Page 10 of 33 [+] Feedback S DP DM GND GND_SHIELD AGND 0.1 uF AVCC AGND 0.1 uF DVCC Zero C4 1M 1 nF 0.1 uF VCC_5V Sensor Decoupling Caps 1 2 3 4 5 10 uF + DVCC 10 nH VCC Filter 22 22 + 10 uF AGND + AVCC DMINUS DPLUS 10 uF Z-WHEEL1 Z-WHEEL2 LF_SW RT_SW CTR_SW 27 26 21 12 29 13 31 9 32 36 33 37 34 38 35 39 1 22 18 16 24 23 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 AGND DD+ ISSP DATA, P1_0 SPI_MOSI, ISSP CLK, P1_1 P1_2 SPI_CLK, P1_3 EXT_CLK, P1_4 SPI MISO, P1_5 P1_6 SPI SS, P1_7 BATT_MON BOOST_GND CYONS2100 XRES OCDOE, P3_7 CCLK, P3_5 HCLK, P3_3 OCDE OCDO, P3_1 U2 CP 43 1 2 3 4 5 7 AVDD AVSS W G R B SHLD 8 VREGA VCC_5V DVCC DVCC 5 DVDD 25 Vbus D+/SDATA D-/SCLK GND AVCC 42 VDD5V VCC_5V 6 VREGD DVSS 30 Document Number: 001-44046 Rev. *A 1206 USB Interface 40 41 17 15 20 11 28 10 19 14 4 2 1 2 2 2 3 Z-WHEEL2 COM GND1 GND2 ENCODER QB QA Z WHEEL SW PUSHBUTTON 1 SW PUSHBUTTON Z-WHEEL1 DMINUS DPLUS 2 SW PUSHBUTTON 1 4 5 1 CTR_SW RT_SW LF_SW Mouse Button Switches ADVANCE CYONS2100 Wired Mouse Application Example The drawing below shows an implementation of a wired mouse. For complete details, refer to the CY4631 Reference Design Kit. Figure 7. Wired Mouse Page 11 of 33 [+] Feedback CYONS2100 ADVANCE Electrical Specifications This section presents the DC and AC electrical specifications of the CYONS2100 device. For the most up-to-date electrical specifications, confirm that you have the most recent data sheet by going to http://www.cypress.com. Absolute Maximum Ratings Parameter Min Storage Temperature -40 Operating Temperature -15 Typ Lead Solder Temperature Max Unit 85 C Case temperature 55 C Case temperature 260 C 10 seconds Supply Voltage, DVDD, AVDD, VREGA, and VREGD relative to DVSS) V Supply Voltage, VDD5V relative to DVSS V ESD (Electric Static Discharge) IO Voltage relative to DVSS -0.5 2 kV All pins, HBM MIL 883 method 3015 DVDD + 0.5 V GPIO ports 0, 2, and 3 GPIO port 1 IO Voltage relative to DVSS 5.5 V Latchup Current 100 mA +50 mA Max Unit C Maximum current into any GPIO pin Conditions -25 Operating Conditions Parameter Min Typ Operating Temperature 5 45 Power Supply Voltage VDD5V DVDD, AVDD, VREGD VREGA 4.35 2.7 1.71 5.25 3.6 3.6 Power Supply Rise Time 100 Conditions V s Supply Noise--AVDD (sinusoidal) 25 mV p-p 10 kHz-50 MHz Supply Noise--VDD, DVDD (sinusoidal) 100 mV p-p 10 kHz-50 MHz Distance from PCB to Tracking Surface 5.80 PCB Thickness 1.54 Document Number: 001-44046 Rev. *A 6 6.20 mm See Figure 17 on page 26 1.79 mm See Figure 17 on page 26 Page 12 of 33 [+] Feedback CYONS2100 ADVANCE Power Consumption Introduction As described earlier, the CYONS2100 has a highly advanced power system, which can be used to develop very low power applications. This section describes and specifies the power consumption performance of the device. Enabling Low-Power Modes In some cases, designers may want to develop "always-on" applications, with no power-saving modes and consequently no wakeup latency in performance. In other applications, conserving power is crucial, and power-saving modes are a firm requirement. The CYONS2100 enables low-power modes to be enabled or disabled in firmware, either through register writes or through the application programming interface in Cypress's PSoC Designer development software. The remainder of this section applies to applications requiring power-saving modes. Operating Modes From a power consumption standpoint, there are three operating modes to consider: Tracking mode: In this mode, the device is actively tracking on a surface. It is the highest power mode of the device. The current consumption is slightly dependent on speed and surface. The current, however, is independent of resolution. Inactive mode: In this mode, the device is in its lowest power state. In inactive mode, the device cannot sense motion, but a timer is running. The timer can generate an interrupt that can wake the rest of the device and start tracking motion. Sleep modes: In sleep modes, the device self-transitions between tracking mode and inactive mode. The typical use of sleep modes is when the device is at rest, but might still be moved. In Sleep modes, the CYONS2100 stays in inactive mode for a fixed time, then wakes up and checks for motion. If motion is detected, the device fully wakes up and begins tracking. If no motion is detected, the device can go back to Sleep mode. Power Management Through Sleep Mode Control with four sets of sleep mode settings, enabling four levels of sleep. By controlling the parameters of these four sleep modes, the designer can tailor the solution to make appropriate tradeoffs between power consumption and wakeup latency. The transition between sleep modes is under the control of the CYONS2100's DSP; no firmware needs to be written to manage the transition between modes. Each of the four available sleep modes is defined by three parameters. These parameters are defined as registers that can be controlled by firmware, either through direct register writes or by using the NAV User Module in PSoC Designer. Sleep time: This is the amount of time that the device is in its low-power inactive state. Motion threshold: This is the amount of motion that is required to bring the device out of sleep. Sleep mode time: This is the amount of time that the device stays in a particular sleep mode before transitioning to the next lowest sleep mode. Longer sleep times save power but have higher wakeup latency. Figure 8 shows the flowchart for a particular sleep mode, showing how the three parameters affect behavior. Calculating Power for Sleep Mode The power consumption in sleep mode can be found by using a duty cycle calculation. The sleep mode current is determined by the tracking mode current, the inactive current, the time required to check for motion (typically 2.3 ms), and the time between check-for-motion events. The expected current consumption is given by the formula I TRACK x 2.3 + I INACT x T SLEEP I SLEEP = ----------------------------------------------------------------------------------2.3 + T SLEEP where ISLEEP is the sleep current, ITRACK is the tracking current, IINACT is the inactive current, and TSLEEP is the time (in ms) in the low power state. As an example, if the tracking current is 7.0 mA, the inactive current is 30 A and the sleep time is 100 ms, then the expected sleep current is 0.19 mA. Power management for the CYONS2100 consists of setting the parameters that define the sleep modes. The device is equipped Document Number: 001-44046 Rev. *A Page 13 of 33 [+] Feedback CYONS2100 ADVANCE Figure 8. Sleep Mode Flowchart Power Consumption Specifications Table 5 provides the current consumption values for the CYONS2100. In general, there are two components to total current consumption. The first is the total current drawn by the DVDD, AVDD, VREGA, and VREGD pins. The second is the current drawn by the internal regulator that drives these pins. For externally powered designs, no internal regulator is active, and no additional current is present. For designs powered by the VDD5V pin, the 5V-to-3V regulator is active, and the current consumption of this block, specified in Table 4. Power Consumption Specifications Symbol Description Table 5, must be included in the total. Also, the USB block is run directly from this regulator, so USB-based designs should include the additional current. Sleep current is achieved by activating power-saving modes through firmware. Doing so enables the sleep mode progressions described earlier, and also causes the laser and detector circuitry to turn on and off as needed to minimize power. For the CYONS2100, low-power operation is only needed to support USB Suspend. Reference code for this is available in the CY4631 Wired Mouse Reference Design Kit. If sleep modes are not activated, the device current stays at tracking current levels, even when the device is not sensing motion. Conditions Min Typ Max Units ITRACK Tracking current into DVDD, 3.6V, 45C, 10 inch/second, 24 MHz IMO, 6 MHz CPU AVDD, VREGD, VREGA clock, power-saving modes enabled, white surface, USB active 9 mA ITRACK2 High performance tracking current into DVDD, AVDD,VREGD, VREGA 3.6V, 45C, 10 inch/second, 24 MHz IMO, 24 MHz CPU clock, power-saving modes disabled, white surface, USB active 17 mA IINACT Inactive current into DVDD, AVDD, VREGD, VREGA 3.6V, 45C, 24 MHz IMO, 6 MHz CPU clock, powersaving modes enabled, white surface 30 ISLEEP Sleep current into DVDD, AVDD, VREGD, VREGA 3.6V, 45C, 24 MHz IMO, 6 MHz CPU clock, powersaving modes enabled, white surface ISB Shutdown current, all blocks 3.6V, 25C off into DVDD, AVDD, VREGD, VREGA 12 IREG5V 5V-to-3V regulator current consumption 250 Document Number: 001-44046 Rev. *A VDD5V = 5.25V s A See previous section A 300 A Page 14 of 33 [+] Feedback CYONS2100 ADVANCE DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage range of 2.7V to 3.6V at the DVDD pin, and over the temperature range 5C TA 45C. Typical parameters apply to 3.3V at 25C and are for design guidance only. Table 5. 2.7V to 3.6V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units RPU Pull up Resistor 4 5.6 8 k VOH1 High Output Voltage Port 2 or 3 Pins IOH < 10 A, maximum of 10 mA source current in all IOs. DVDD 0.2 - - V VOH2 High Output Voltage Port 2 or 3 Pins IOH = 1 mA, maximum of 20 mA source current in all IOs. DVDD 0.9 - - V VOH3 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH < 10 A, maximum of 10 mA source current in all IOs. DVDD 0.2 - - V VOH4 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 5 mA, maximum of 20 mA source current in all IOs. DVDD 0.9 - - V VOH5 High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out IOH < 10 A, DVDD > 3.1V, maximum of 4 IOs all sourcing 5 mA. 2.85 3.00 3.30 V VOH6 High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out IOH = 5 mA, DVDD > 3.1V, maximum of 20 mA source current in all IOs. 2.20 - - V VOH7 High Output Voltage IOH < 10 A, DVDD > 2.7V, maximum Port 1 Pins with LDO Enabled for 2.5V of 20 mA source current in all IOs. Out 2.35 2.50 2.75 V VOH8 High Output Voltage IOH = 2 mA, DVDD > 2.7V, maximum Port 1 Pins with LDO Enabled for 2.5V of 20 mA source current in all IOs. Out 1.90 - - V VOH9 High Output Voltage IOH < 10 A, DVDD > 2.7V, maximum Port 1 Pins with LDO Enabled for 1.8V of 20 mA source current in all IOs. Out 1.60 1.80 2.10 V VOH10 High Output Voltage IOH = 1 mA, DVDD > 2.7V, maximum Port 1 Pins with LDO Enabled for 1.8V of 20 mA source current in all IOs. Out 1.20 - - V VOL Low Output Voltage - - 0.75 V 0.80 V IOL = 25 mA, DVDD > 3.3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). VIL Input Low Voltage - - VIH Input High Voltage 2.00 - VH Input Hysteresis Voltage IIL Input Leakage (Absolute Value) CPIN Pin Capacitance Document Number: 001-44046 Rev. *A V - 80 - mV Gross tested to 1 A. - 0.5 1 A 25oC. 0.5 1.7 8 pF Temp = Page 15 of 33 [+] Feedback CYONS2100 ADVANCE DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 6. DC Analog Mux Bus Specifications Min Typ Max Unit RSW Parameter Switch Resistance to Common Analog Bus Pin voltage < 1.8V Description Conditions - - 800 RVDD Resistance of Initialization Switch to DVSS Pin voltage < 1.8V - - 800 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 7. DC Low Power Comparator Specifications Parameter Description Min Typ Max Unit 0.0 - 1.8 V LPC supply current - 10 40 A LPC voltage offset - 2.5 30 mV VLPC Low Power Comparator (LPC) common mode ILPC VOSLPC Conditions Maximum voltage limited to DVDD. DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 8. DC POR and LVD Specifications Parameter Description VPPOR0 VPPOR1 VPPOR2 VPPOR3 DVDD Value for PPOR Trip PORLEV[1:0] = 00b, HPOR = 0 PORLEV[1:0] = 00b, HPOR = 1 PORLEV[1:0] = 01b, HPOR = 1 PORLEV[1:0] = 10b, HPOR = 1 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b Conditions DVDD must be greater than or equal to 1.71V during startup, reset from the XRES pin, or reset from watchdog. Min Typ Max Unit 1.61 1.66 2.36 2.60 2.82 1.71 2.40 2.65 2.95 V V V V 2.45 2.71 2.92 3.02 3.13 1.90 1.80 2.51 2.78 2.99 3.09 3.20 2.32 1.84 V V V V V V V - 2.40[2] 2.64[3] 2.85[4] 2.95 3.06 1.84 1.75[5] Notes 2. Always greater than 50 mV above VPPOR1 voltage for falling supply. 3. Always greater than 50 mV above VPPOR2 voltage for falling supply. 4. Always greater than 50 mV above VPPOR3 voltage for falling supply. 5. Always greater than 50 mV above VPPOR0 voltage for falling supply. Document Number: 001-44046 Rev. *A Page 16 of 33 [+] Feedback CYONS2100 ADVANCE DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. The CYONS2100 must be properly powered for Flash programming, with DVDD, AVDD, VREGD and VREGA all held within the specified range. A suitable option for in-circuit programming USB designs is to apply 5V to the VDD5V pin, and use the internal regulator to drive DVDD, AVDD, VREGD, and VREGA. This enables direct connection to Cypress's CY3210-Miniprog. For in-circuit programming of externally-powered designs, the designer must include provisions for supplying DVDD, AVDD, VREGD, and VREGA externally. Table 9. DC Programming Specifications Parameter Description Conditions VIW applied to DVDD, AVDD, VREGD and VREGA Min Typ Max Unit 2.7 - 3.6 V - 5 25 mA VIW Supply Voltage for Flash Write Operations IDDP Supply Current During Programming or Verify VILP Input Low Voltage During Programming or Verify See "DC General Purpose IO Specifications" on page 15. - - VIL V VIHP Input High Voltage During Programming or Verify See "DC General Purpose IO Specifications" on page 15. VIH - - V IILP Input Current when Applying Driving internal pull down resistor. Vilp to P1[0] or P1[1] During Programming or Verify - - 0.2 mA IIHP Input Current when Applying Driving internal pull down resistor. Vihp to P1[0] or P1[1] During Programming or Verify - - 1.5 mA VOLP Output Low Voltage During Programming or Verify - - Vss + 0.75 V VOHP Output High Voltage During "DC General Purpose IO SpecificaProgramming or Verify tions" on page 15. For DVDD > 3V use the value with IOH = 5 mA. VOH - Vdd V FlashENPB Flash Write Endurance Erase/write cycles by block. 50,000 - - Cycles FlashDR Flash Data Retention Following maximum flash write cycles. 8 20 - Years DC Characteristics - USB Interface Table 10. DC USB Characteristics Symbol Description Min Typ Max Units USB D+ pull up resistance With idle bus 0.900 TBD 1.575 k Rusba USB D+ pull up resistance While receiving traffic 1.425 TBD 3.090 k Vohusb Static Output High 2.8 TBD 3.6 V TBD 0.3 V Rusbi Conditions Volusb Static Output Low Vdi Differential Input Sensitivity 0.2 Vcm Differential Input Common Mode Range TBD TBD TBD V Vse Single Ended Receiver Threshold 0.8 TBD 2.0 V Cin Transceiver Capacitance TBD 50 pF Iio Hi-Z State Data Line Leakage On D+ or D- line TBD TBD TBD uA Rps2 PS/2 Pull-up resistance 3 TBD 7 k Rext External USB Series Resistor In series with each USB pin 21.78 22 22.22 Document Number: 001-44046 Rev. *A TBD V Page 17 of 33 [+] Feedback CYONS2100 ADVANCE AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. AC Chip Level Specifications Parameter Description Min Typ Max Unit FMAX Maximum Operating Frequency[6] 24 FCPU Maximum Processing Frequency[7] 13 F32K1 Internal Low Speed Oscillator Frequency 19 32 50 kHz 22.8 24 25.2 MHz 11.4 12 12.6 MHz FIMO24 Internal Main Oscillator Stability for 24 MHz 5% FIMO12 Internal Main Oscillator Stability for 12 MHz[8] [8] MHz[8] MHz MHz FIMO6 Internal Main Oscillator Stability for 6 5.7 6.0 6.3 MHz DCIMO Duty Cycle of IMO 40 50 60 % TRAMP Supply Ramp Time 0 - - TXRST External Reset Pulse Width at Power Up 1 TXRST2 External Reset Pulse Width after Power Up 10 TMOT Motion delay from reset to valid tracking data s ms s 30 ms AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. AC GPIO Specs Parameter Description Min Typ Max Units Strong Mode, Port 1 Conditions 0 - 12 MHz Rise time, ports 0 -1 Strong mode, CLOAD = 50pF, DVDD = 3.0 - 3.6 10 50 ns Rise time, ports 0 -1, low supply Strong mode, CLOAD = 50pF, DVDD = 2.7 - 3.0 70 ns FGPIO GPIO Operating Freq TRISE_01 TRISE_01_L TRISE_LDO_3 Rise time, port 1, 3V LDO enabled Strong mode, CLOAD = 50pF, DVDD > 3.1V TRISE_LDO_2.5 Rise time, port 1, 2.5 LDO enabled Strong mode, CLOAD = 50pF, DVDD > 2.7V TRISE_LDO_1.8 Rise time, port 1, 1.8 LDO enabled Strong mode, CLOAD = 50pF, DVDD > 2.7V 100 ns TRISE_23 Rise time, ports 2 - 3 Strong mode, CLOAD = 50pF, DVDD = 2.7 - 3.6 15 80 ns TFALL Fall time, all ports Strong mode, CLOAD = 50pF, DVDD = 3.0 - 3.6 10 50 ns TFALL_L Fall time, all ports, low supply Strong mode, CLOAD = 50pF, DVDD = 2.7 - 3.0 10 70 ns TFALL_LDO_3 Fall time, port 1, 3V LDO enabled Strong mode, CLOAD = 50pF, DVDD > 3.1V 50 ns TFALL_LDO_2.5 Fall time, port 1, 2.5 LDO enabled Strong mode, CLOAD = 50pF, DVDD > 2.7V 70 ns TFALL_LDO_1.8 Fall time, port 1, 1.8 LDO enabled Strong mode, CLOAD = 50pF, DVDD > 2.7V 80 ns 10 50 ns 70 ns Notes 6. Vdd = 3.0V and TJ = 85C, digital clocking functions. 7. Vdd = 3.0V and TJ = 85C, CPU speed. 8. Trimmed for 3.3V operation using factory trim values. Document Number: 001-44046 Rev. *A Page 18 of 33 [+] Feedback CYONS2100 ADVANCE AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. AC External Clock Specifications Parameter Description Min Typ Max Unit FOSCEXT Frequency 0.750 - 25.2 MHz - High Period 20.6 - 5300 ns - Low Period 20.6 - - ns - Power Up IMO to Switch 150 - - s AC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. AC Analog Mux Bus Specifications Parameter FSW Description Switch Rate Conditions Pin voltage < 1.8V Min Typ Max Unit - - 6.3 MHz AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. AC Programming Specifications Symbol Description Conditions Min Typ Max Units TRSCLK Rise Time of SCLK 1 - 20 ns TFSCLK Fall Time of SCLK 1 - 20 ns TSSCLK Data Set up Time to Falling Edge of SCLK 40 - - ns THSCLK Data Hold Time from Falling Edge of SCLK 40 - - ns FSCLK Frequency of SCLK 0 - 8 MHz - - 18 ms - - 25 ms - - 85 ns TERASEB Flash Erase Time (Block) TWRITE Flash Block Write Time TDSCLK2 Data Out Delay from Falling Edge of SCLK Document Number: 001-44046 Rev. *A 3.0 DVDD 3.6 Page 19 of 33 [+] Feedback CYONS2100 ADVANCE AC SPI Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. AC SPI Master Specifications Parameter Description [9] fSCLK SCK Frequency tSETUP MISO to SCK Setup Time tHOLD SCLK to MISO Hold Time tOUT_SU MOSI to SCK Setup Time tOUT_H SCK to MOSI Hold Time Min Typ Max Unit - - FIMO/2 MHz 150 ns -100 ns 200 -100 ns ns Table 17. AC SPI Slave Specifications Max Unit fSCLK Parameter SCK Frequency[9] Description Min Typ 12 MHz tLOW Minimum SCK Low Width 50 ns tHIGH Minimum SCK High Width 50 ns tSETUP MOSI to SCK Setup Time 25 ns tHOLD SCK to MOSI Hold Time 25 ns tOUT_H SCK to MISO Hold Time tSS_MISO SPI_SS to MISO Valid 100 ns tSCLK_MISO SCK to MISO Valid 140 ns tSS_HIGH Minimum SPI_SS High Width 35 ns tSS_CLK Time from SPI_SS Low to First SCK 20 ns tCLK_SS Time from Last SCK to SPI_SS High 25 ns 35 ns Note 9. Clock frequency is half of clock input to SPI block. Document Number: 001-44046 Rev. *A Page 20 of 33 [+] Feedback CYONS2100 ADVANCE Figure 9. SPI Master Timing Diagram, Modes 0 and 2 SPI Master, modes 0 & 2 1/fSCLK SCLK (mode 0) tFALL tRISE SCLK (mode 2) tSETUP MISO (input) tHOLD LSb MSb tOUT_SU MOSI (output) tOUT_H LSb MSb Figure 10. SPI Master Timing Diagram, Modes 1 and 3 SPI Master, modes 1 & 3 1/fSCLK SCLK (mode 1) tRISE tFALL SCLK (mode 3) tSETUP MISO (input) tHOLD LSb MSb tOUT_SU MOSI (output) Document Number: 001-44046 Rev. *A tOUT_H MSb LSb Page 21 of 33 [+] Feedback CYONS2100 ADVANCE Figure 11. SPI Slave Timing Diagram, Modes 0 and 2 SPI Slave, modes 0 & 2 tSS_CLK tCLK_SS tSS_HIGH /SS 1/fSCLK tLOW tHIGH SCLK (mode 0) tRISE tFALL SCLK (mode 2) tOUT_H tSS_MISO MISO (output) tSETUP tHOLD MOSI (input) MSb LSb Figure 12. SPI Slave Timing Diagram, Modes 1 and 3 SPI Slave, modes 1 & 3 tSS_CLK tCLK_SS /SS 1/fSCLK tHIGH tLOW SCLK (mode 1) tFALL tRISE SCLK (mode 3) tOUT_H tSCLK_MISO tSS_MISO MISO (output) MSb tSETUP MOSI (input) Document Number: 001-44046 Rev. *A LSb tHOLD MSb LSb Page 22 of 33 [+] Feedback CYONS2100 ADVANCE AC Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC Low Power Comparator Specifications Symbol TLPC Description Conditions Min Typ Comparator Response Time, 50 mV 50 mV overdrive does not include Overdrive offset voltage. Max Units 100 ns AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. AC Characteristics of the I2C SDA and SCL Pins Symbol Description Standard Mode Conditions FSCLI2C SCL Clock Frequency THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C THIGHI2C Min Max Fast Mode Min Max Units 0 100 0 400 kHz 4.0 - 0.6 - s LOW Period of the SCL Clock 4.7 - 1.3 - s HIGH Period of the SCL Clock 4.0 - 0.6 - s TSUSTAI2C Setup Time for a Repeated START Condition 4.7 - 0.6 - s THDDATI2C Data Hold Time 0 - 0 - s TSUDATI2C Data Setup Time 250 - 100[10] - ns TSUSTOI2C Setup Time for STOP Condition 4.0 - 0.6 - s TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 - 1.3 - s TSPI2C Pulse Width of spikes are suppressed by the input filter. - - 0 50 ns Figure 13. Timing for Fast and Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Note 10. Output clock frequency is half of input clock rate. Document Number: 001-44046 Rev. *A Page 23 of 33 [+] Feedback CYONS2100 ADVANCE AC USB Specifications S Table 20. AC Characteristics - USB Data Timing Specifications Symbol Tdrate Description Full speed data rate Conditions Average bit rate Min Typ Max Units 12-0.25% 12 12 + 0.25 MHz Tdjr1 Receiver data jitter tolerance To next transition -8 TBD 8 ns Tdjr2 Receiver data jitter tolerance To pair transition -5 TBD 5 ns Tudj1 Driver differential jitter To next transition -3.5 TBD 3.5 ns Tudj2 Driver differential jitter To pair transition -4.0 TBD 4.0 ns Tfdeop Source jitter for differential transition To SE0 transition -2 TBD 5 ns Tfeopt Source SE0 interval of EOP 160 TBD 175 ns Tfeopr Receiver SE0 interval of EOP 82 TBD Tfst Width of SE0 interval during differential transition ns TBD 14 ns Min Typ Max Units 4 TBD 20 ns Table 21. AC Characteristics - USB Driver Symbol Description Conditions Tr Transition rise time 50 pF Tf Transition fall time 50 pF TR Rise/fall time matching 0.8V - 2.5V Vcrs Output signal crossover voltage Document Number: 001-44046 Rev. *A 4 TBD 20 ns 90.00 TBD 111.11 % 1.3 TBD 2.0 V Page 24 of 33 [+] Feedback ADVANCE CYONS2100 PCB Land Pads and Mechanical Dimensions Figure 14. Land Pad Architecture and Spacing according to JEDEC MO-220 (52 Lead) Figure 15. PCB Keep Out Zones Document Number: 001-44046 Rev. *A Page 25 of 33 [+] Feedback ADVANCE CYONS2100 Orientation of Axes Figure 16 describes the relationship between the package and the x and y axes for reported motion data. Note that for a typical mouse application, this sensor orientation requires inversion (multiply by -1) of the y data. Designs using Cypress's PSoC Designer software and the Ovation II user modules have this inversion done automatically. Designs using direct reads of y registers need the inversion done in application firmware. Figure 16. Sensor Orientation PCB Mounting Height and Thickness Figure 17 shows the recommended thickness and mounting height of the PCB above the tracking surface. Figure 17. PCB Height and Thickness Document Number: 001-44046 Rev. *A Page 26 of 33 [+] Feedback CYONS2100 ADVANCE Thermal Impedances Table 22. Thermal Impedances per Package Package Typical JA[11] 42 PQFN[12] 46 C/W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 23. Solder Reflow Peak Temperature Package Minimum Peak Temperature[13] Maximum Peak Temperature 42 PQFN 240C 260C Notes 11. TJ = TA + Power x JA. 12. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. 13. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5C with Sn-Pb or 245 5C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-44046 Rev. *A Page 27 of 33 [+] Feedback ADVANCE CYONS2100 Laser Safety Considerations The CYONS2100 Laser Navigation SoC and the CYONSLENS2000 lens are designed and tested to enable manufacturers to achieve eye safety certification with minimal effort. This section provides guidelines for complying with the Class 1 emission requirements of IEC/EN 60825-1. Laser Output Power Test Procedure When installed and operated in accordance with all requirements in this data sheet, the kit consisting of the CYONS2100 Laser Navigation SoC and CYONSLENS2000 satisfies CDRH 21 CFR 1040 per Laser Notice 50 and IEC/EN 60825-1 Class 1. Registration Assistance Laser Output Power The CYONS2100 sensor package contains an integrated VCSEL and drive circuitry. Before shipping, Cypress adjusts the laser output power to eye-safe levels, taking into account specified variations in supply voltage, temperature, lens transmission, and VCSEL polarization, and factors such as VCSEL aging and test equipment accuracy. The output remains within eye-safe limits under reasonably foreseeable single-faults, as required by the IEC standard. From the perspective of a manufacturer, laser emission remains within the Class 1 limit, as defined in IEC 60825-1, Edition 2, 2007, provided the following requirements are met. The supply voltage applied to pins DVDD and AVDD of the SoC must be in the range of 2.7 to 3.6V. The operating temperature must be between 5 and 45 C. The laser output power must not be increased by any means, including but not limited to firmware, hardware, or mechanical modifications to the sensor or lens. The mechanical housing must be designed such that the CYONSLENS2000 cannot be removed by the user. The device firmware must initialize the VCSEL driver as described in the "VCSEL Driver" chapter of the OvationONS II Technical Reference Manual. To verify the laser output level, follow the steps shown in the "VCSEL Power Calibration and Verification" section of the Technical Reference Manual. The mouse or end-product supplier is responsible for certifying the end-use product with respect to the drive voltage, manuals and labels, and operating temperature specifications. Additionally, for products sold in the US, a CDRH report must be filed for each model produced, and test and inspection of the product's characteristics as they relate to laser safety and the CDRH requirements must be performed. When filing a report with the CDRH, the supplier can refer to the product report filed by Cypress for the CYONS2xxx family of products. The Cypress report is based on the previously-noted limits for voltage and temperature, and describes how the sensor design includes consideration of drive circuit failures, laser output variation with temperature, drive circuit variation with temperature and voltage, polarization sensitivity of molded optics, and measurement uncertainties. Cypress can provide assistance to customers who wish to obtain registration. Supporting documentation, including a verification test procedure to demonstrate end-product compliance with IEC and CDRH requirements is available. An application note, "Meeting Laser Safety Requirements with the CYONS2xxx Family of Laser Navigation SoCs", is also available. For further information, contact a Cypress representative. It is the responsibility of the manufacturer to ensure these conditions are always met and to demonstrate end-product compliance to the appropriate regulatory standards. Document Number: 001-44046 Rev. *A Page 28 of 33 [+] Feedback ADVANCE CYONS2100 Development Tool Selection This section presents the development tools available for all current PSoC device families including the CYONS2100. Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer. Used by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC ExpressTM. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer. HI-TECH C Compiler Cypress's PSoC Designer 5.0 supports a new HI-TECH Lite C Compiler by default, although it still supports CY3202-C iMAGEcraft C Compiler used by previous versions of PSoC Designer. An optional upgrade from HI-TECH Lite to HI-TECH Pro is available for purchase from Cypress Online Store. At http://www.cypress.com, click "Buy Kits" at the left bottom of the web page, click "PSoC (Programmable System-on-Chip)", and click "Development Kits", or search for "HI-TECH". CY3215-DK Basic Development Kit The CY3215-DK kit enables prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features are also supported through PSoC Designer. The kit includes: PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable Two CY8C29466-24PXI 28-PDIP Chip Samples CY3210-ExpressDK PSoC Express Development Kit The CY3210-ExpressDK enables advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to voltage reference, switches, upgradeable modules and more. The kit includes: PSoC Express Software CD Express Development Board Four Fan Modules Two Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit Reference Design Kits USB 2.0 Cable Two reference design kits featuring the OvationONS II family of products are available. Each kit provides a complete hardware, firmware, and software solution, ready for production. Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter Two CY8C24423A-24PXI 28-PDIP Chip Samples Two CY8C27443-24PXI 28-PDIP Chip Samples Two CY8C29466-24PXI 28-PDIP Chip Samples CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. You can purchase the optional upgrade from the Cypress Online Store at http://www.cypress.com. In the store, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. CY4631 Wired Mouse Reference Design Kit CY4666 Wireless Mouse Reference Design Kit Development Kits You can purchase the development kits from the Cypress Online Store. Document Number: 001-44046 Rev. *A Page 29 of 33 [+] Feedback ADVANCE CYONS2100 Evaluation Tools PSoCEvalUSB Board You can purchase the evaluation tools from the Cypress Online Store. LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack CY3210-MiniProg1 The CY3210-MiniProg1 kit enables a user to program PSoC devices using the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-pin CY8C29466-24PXI PDIP PSoC Device Sample 28-pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: CY3210-PSoCEval1 Modular Programmer Base Three Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all your evaluation needs. The kit includes: Device Programmers You can purchase the device programmers from the Cypress Online Store. CY3216 Modular Programmer Evaluation Board with LCD Module Getting Started Guide MiniProg Programming Unit USB 2.0 Cable 28-pin CY8C29466-24PXI PDIP PSoC Device Sample (2) CY3207ISSP In-System Serial Programmer (ISSP) PSoC Designer Software CD Getting Started Guide The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. USB 2.0 Cable CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all your evaluation needs. The kit includes: Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Third-Party Tools Several tools have been specially designed by third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools are found at http://www.cypress.com. Document Number: 001-44046 Rev. *A Page 30 of 33 [+] Feedback CYONS2100 ADVANCE Package Diagrams Figure 18. QFN Package SIDE VIEW TOP VIEW BOTTOM VIEW SEE DETAIL - B DETAIL - A NOTES: 1. ALL DIMS IN MM, [MIN/MAX] 2. REFRENCE JEDEC # MO-220 3. PKG WEIGHT: 0.2 grams DWG 001-44934 ** DETAIL - B Document Number: 001-44046 Rev. *A Page 31 of 33 [+] Feedback CYONS2100 ADVANCE Figure 19. Lens 001-44677 ** Ordering Information The CYONS2100 and CYONSLENS2000 are sold separately. When placing orders, please order both part numbers. Part Number Package CYONS2100-LBXC 42 lead PQFN CYONSLENS2000-C Lens - 4 mm Height Document Number: 001-44046 Rev. *A Application High Performance Wired Molded Optic Page 32 of 33 [+] Feedback ADVANCE CYONS2100 Document History Page Document Title: CYONS2100 OvationONSTM II Wired Gaming Laser Navigation System on Chip Document Number: 001-44046 Revision ECN Orig. of Change Submission Date ** 2261927 FJZ See ECN CYONS2100 New Data Sheet. *A 2580125 FJZ/PYRS 10/07/08 Extensive Updates Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog (c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-44046 Rev. *A Revised October 5, 2008 Page 33 of 33 OvationONSTM and OptiCheckTM are trademarks of Silicon Light Machines (a subsidiary of Cypress Semiconductor). PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. [+] Feedback