© 2011 Microchip Technology Inc. DS25007B-page 1
MCP6V26/7/8
Features
High DC Precision:
-V
OS Drift: ±50 nV/°C (maximum)
-V
OS: ±2 µV (maximum)
-A
OL: 125 dB (minimum)
- PSRR: 125 dB (minimum)
- CMRR: 120 dB (minimum)
-E
ni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz
-E
ni: 0.32 µVP-P (typical), f = 0.01 Hz to 1 Hz
Low Power and Supply Voltages:
-I
Q: 620 µA/amplifier (typical)
- Wide Supply Voltage Range: 2.3V to 5.5V
•Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 2 MHz (typical)
- Unity Gain Stable
- Available in Single and Dual
- Single with Chip Select (CS): MCP6V28
Extended Temperature Range: -40°C to +125°C
Typical Applications
Portable Instrumentation
Sensor Conditioning
Temperature Measurement
DC Offset Correction
Medical Instrumentation
Design Aids
SPICE Macro Models
•FilterLab
® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
Related Parts
Parts with lower power, lower bandwidth and higher
noise:
MCP6V01/2/3: Spread clock
MCP6V06/7/8: Non-spread clock
Description
The Microchip Technology Inc. MCP6V26/7/8 family of
operational amplifiers provides input offset voltage
correction for very low offset and offset drift. These
devices have a wide gain bandwidth product (2 MHz,
typical) and strongly reject switching noise. They are
unity gain stable, have no 1/f noise, and have good
power supply rejection ratio (PSRR) and common
mode rejection ratio (CMRR). These products operate
with a single supply voltage as low as 2.3V, while
drawing 620 µA/amplifier (typical) of quiescent current.
The Microchip Technology Inc. MCP6V26/7/8 op amps
are offered as a single (MCP6V26), single with Chip
Select (CS) (MCP6V28) and dual (MCP6V27). They
were designed using an advanced CMOS process.
Package Types (top view)
VIN+
VIN
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NCNC
VINA+
VINA
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB
VINB+
MCP6V26
MSOP, SOIC
MCP6V27
MSOP, SOIC
VIN+
VIN
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
MCP6V28
MSOP, SOIC
VINA+
VINA
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB
VINB+
MCP6V27
4×4 DFN *
* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - 1 .
EP
9
VIN+
VIN
VSS
1
2
3
4
8
7
6
5
NC NC
VDD
VOUT
NC
MCP6V26
2×3 TDFN *
EP
9
VIN+
VIN
VSS
1
2
3
4
8
7
6
5
NC CS
VDD
VOUT
NC
MCP6V28
2×3 TDFN *
EP
9
620 µA, 2 MHz Auto-Zeroed Op Amps
MCP6V26/7/8
DS25007B-page 2 © 2011 Microchip Technology Inc.
Typical Application Circuit
Offset Voltage Correction for Power Driver
10 nF
10 kΩ
10 kΩ10 kΩ
MCP661
VDD/2
500 kΩ
VIN VOUT
10 kΩ
MCP6V26
5kΩ
VDD/2
U2
U1
© 2011 Microchip Technology Inc. DS25007B-page 3
MCP6V26/7/8
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings
VDD –V
SS ..............................................................................6.5V
Current at Input Pins †† ......................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† .......... VSS 1.0V to VDD+1.0V
All other Inputs and Outputs .................. VSS 0.3V to VDD+0.3V
Difference Input voltage ............................................. |VDD –V
SS|
Output Short Circuit Current .......................................Continuous
Current at Output and Supply Pins ...................................±30 mA
Storage Temperature ..........................................-65°C to +150°C
Max. Junction Temperature .............................................. +150°C
ESD protection on all pins (HBM, CDM, MM) 4 kV,1.5 kV, 300V
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
†† See Section 4.2.1, Rail-to-Rail Inputs.
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -2 +2 µV TA = +25°C (Note 1)
Input Offset Voltage Drift
with Temperature (linear Temp. Co.)
TC1-50 +50 nV/°C TA = -40 to +125°C
(Note 1)
Input Offset Voltage Quadratic
Temperature Coefficient
TC2—±0.2 nV/°C
2TA = -40 to +125°C
Power Supply Rejection PSRR 125 142 dB (Note 1)
Input Bias Current and Impedance
Input Bias Current IB—+7 —pA
Input Bias Current across
Temperature
IB—+110 pAT
A = +85°C
IB—+1.2 +5 nAT
A = +125°C
Input Offset Current IOS —±70 pA
Input Offset Current across
Temperature
IOS —±50 pAT
A = +85°C
IOS —±60 pAT
A = +125°C
Common Mode Input Impedance ZCM —10
13||12 Ω||pF
Differential Input Impedance ZDIFF —10
13||12 Ω||pF
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production
environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset
Related Test Screens”).
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
MCP6V26/7/8
DS25007B-page 4 © 2011 Microchip Technology Inc.
Common Mode
Common-Mode Input
Voltage Range Low
VCML ——V
SS 0.15 V (Note 2)
Common-Mode Input
Voltage Range High
VCMH VDD +0.2 V (Note 2)
Common-Mode Rejection CMRR 120 136 dB VDD = 2.3V,
VCM = -0.15V to 2.5V
(Note 1, Note 2)
CMRR 125 142 dB VDD = 5.5V,
VCM = -0.15V to 5.7V
(Note 1, Note 2)
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 125 147 dB VDD =2.3V,
VOUT = 0.2V to 2.1V
(Note 1)
AOL 133 155 dB VDD =5.5V,
VOUT = 0.2V to 5.3V
(Note 1)
Output
Minimum Output Voltage Swing VOL —V
SS +5 V
SS +15 mV G = +2, 0.5V
input overdrive
Maximum Output Voltage Swing VOH VDD –15 V
DD 5 mV G = +2, 0.5V
input overdrive
Output Short Circuit Current ISC —±12 mAV
DD =2.3V
ISC —±22 mAV
DD =5.5V
Power Supply
Supply Voltage VDD 2.3 5.5 V
Quiescent Current per amplifier IQ450 620 800 µA IO = 0
POR Trip Voltage VPOR 1.15 1.65 V
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production
environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset
Related Test Screens”).
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
© 2011 Microchip Technology Inc. DS25007B-page 5
MCP6V26/7/8
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND (refer to Figure 1-5 and
Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
Amplifier AC Response
Gain Bandwidth Product GBWP 2.0 MHz
Slew Rate SR 1.0 V/µs
Phase Margin PM 65 ° G = +1
Amplifier Noise Response
Input Noise Voltage Eni —0.32 µV
P-P f = 0.01 Hz to 1 Hz
Eni —1.0 µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —50 nV/Hz f < 5 kHz
eni —29 nV/Hz f = 100 kHz
Input Noise Current Density ini —0.6 fA/Hz
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC) IMD 40 µVPK VCM tone = 50 mVPK at 1 kHz,
GN = 1
Amplifier Step Response
Start Up Time tSTR 75 µs G = +1, VOS within 50 µV of its final value
(Note 2)
Offset Correction Settling Time tSTL 150 µs G = +1, VIN step of 2V,
VOS within 50 µV of its final value
Output Overdrive Recovery Time tODR 45 µs G = -100, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point
(Note 3)
Note 1: These parameters were characterized using the circuit in Figure 1-7. In Figure 2-37 and Figure 2-38, there
is an IMD tone at DC, a residual tone at 1 kHz, other IMD tones and clock tones.
2: High gains behave differently; see Section 4.3.3, Offset at Power Up.
3: tODR includes some uncertainty due to clock edge timing.
MCP6V26/7/8
DS25007B-page 6 © 2011 Microchip Technology Inc.
TABLE 1-4: TEMPERATURE SPECIFICATIONS
TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kW to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and
Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
CS Pull-Down Resistor (MCP6V28)
CS Pull-Down Resistor RPD 35MΩ
CS Low Specifications (MCP6V28)
CS Logic Threshold, Low VIL VSS —0.3V
DD V
CS Input Current, Low ICSL —5pA
CS = VSS
CS High Specifications (MCP6V28)
CS Logic Threshold, High VIH 0.7VDD —V
DD V
CS Input Current, High ICSH —V
DD/RPD —pA
CS = VDD
CS Input High,
GND Current per amplifier
ISS —-0.4µA
CS = VDD, VDD = 2.3V
ISS —-1—µA
CS = VDD, VDD = 5.5V
Amplifier Output Leakage,
CS High
IO_LEAK —20pA
CS = VDD
CS Dynamic Specifications (MCP6V28)
CS Low to Amplifier Output On
Turn-on Time
tON —450µs
CS Low = VSS+0.3 V, G = +1 V/V,
VOUT = 0.9 VDD/2
CS High to Amplifier Output
High-Z
tOFF —1—µs
CS High = VDD 0.3 V, G = +1 V/V,
VOUT = 0.1 VDD/2
Internal Hysteresis VHYST —0.2V
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.3V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 +125 °C
Operating Temperature Range TA-40 +125 °C (Note 1)
Storage Temperature Range TA-65 +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-4x4 DFN θJA —48—°C/W(Note 2)
Thermal Resistance, 8L-MSOP θJA —211—°C/W
Thermal Resistance, 8L-SOIC θJA 150 °C/W
Thermal Resistance, 8L-2x3 TDFN θJA —53—°C/W(Note 2)
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
© 2011 Microchip Technology Inc. DS25007B-page 7
MCP6V26/7/8
1.3 Timing Diagrams
FIGURE 1-1: Amplifier Start Up.
FIGURE 1-2: Offset Correction Settling
Time.
FIGURE 1-3: Output Overdrive Recove ry.
FIGURE 1-4: Chip Select (MCP6V28).
1.4 Test Circuits
The circuits used for the DC and AC tests are shown in
Figure 1-5 and Figure 1-6. Lay the bypass capacitors
out as discussed in Section 4.3.10, Supply Bypass-
ing and Filtering. RN is equal to the parallel combina-
tion of RF and RG to minimize bias current effects.
FIGURE 1-5: AC and DC Test Circuit for
Most Non-Inv erti ng Ga in Cond iti ons .
FIGURE 1-6: AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-7 tests the op amp input’s
dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s common
mode input voltage is VCM =V
IN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
FIGURE 1-7: Test Circuit for Dynamic
Input Behavior.
VDD
VOS
VOS +5V
VOS –5V
tSTR
0V
2.3V to 5.5V
2.3V
VIN
VOS
VOS +50µV
VOS +50µV
tSTL
VIN
VOUT
VDD
VSS
tODR
tODR
VDD/2
VIL
High-Z
tON
VIH
CS
tOFF
VOUT
-2 µA
High-Z
ISS -2 µA
300 µA
A
IDD
A
300 µA
VDD/5 MΩ
ICS VDD/5 MΩ
5pA
(typical) (typical)
(typical) (typical)
(typical) (typical)
(typical)
(typical)
(typical)
VDD
RGRF
RN
VOUT
VIN
VDD/3
F
CLRL
VL
100 nF
RISO
MCP6V2X
U1
VDD
RGRF
RN
VOUT
VDD/3
VIN
F
CLRL
VL
100 nF
RISO
MCP6V2X
U1
VDD
VOUT
F
CLRL
VL
100 nF
RISO
20.0 kΩ24.9 Ω
20.0 kΩ50Ω
VIN
VREF
0.1%
0.1% 25 turn
20.0 kΩ
20.0 kΩ
0.1%
0.1%
2.49 kΩ2.49 kΩ
MCP6V2X
U1
MCP6V26/7/8
DS25007B-page 8 © 2011 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.1 DC Input Precision
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input Offset Voltage
Quadratic Temperature Coefficient.
FIGURE 2-4: Input Offset Voltage vs.
Power Supply Voltage with VCM =V
CML.
FIGURE 2-5: Input Offset Voltage vs.
Power Supply Voltage with VCM =V
CMH.
FIGURE 2-6: Input Offset Voltage vs.
Output Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
5%
10%
15%
20%
25%
30%
35%
40%
-2.0
-1.0
0.0
1.0
2.0
Input Offset Voltage (µV)
Percentage of Occurrences
20 Samples
TA = +25°C
VDD = 2.3V and 5.5V
0%
5%
10%
15%
20%
25%
30%
-50
-40
-30
-20
-10
0
10
20
30
40
50
Input Offset Voltage Drift; TC1 (nV/°C)
Percentage of Occurrences
20 Samples
VDD = 2.3V and 5.5
V
-5
-4
-3
-2
-1
0
1
2
3
4
5
0.00.51.01.52.02.53.03.54.04.55.05.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 2.3
V
VDD = 5.5V
Representative Par
t
© 2011 Microchip Technology Inc. DS25007B-page 9
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-7: Input Offset Voltage vs.
Common Mode Voltage with VDD =2.3V.
FIGURE 2-8: Input Offset Voltage vs.
Common Mode Voltage with VDD =5.5V.
FIGURE 2-9: CMRR.
FIGURE 2-10: PSRR.
FIGURE 2-11: DC Open-Loop Gain.
FIGURE 2-12: CMRR and PSRR vs.
Ambient Temper atu re .
-5
-4
-3
-2
-1
0
1
2
3
4
5
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Input Common Mode Voltage (V)
Input Offset Voltage V)
VDD = 2.3V
Representative Part
-40°C
+25°C
+85°C
+125°C
-5
-4
-3
-2
-1
0
1
2
3
4
5
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Common Mode Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
Representative Part
-40°C
+25°C
+85°C
+125°C
0%
5%
10%
15%
20%
25%
30%
35%
-0.5
-0.3
0.0
0.3
0.5
1/CMRR (µV/V)
Percentage of Occurrences
20 Samples
TA = +25°C
VDD = 2.3V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
1/PSRR (µV/V)
Percentage of Occurrences
20 Samples
TA = +25°C
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
1/AOLV/V)
Percentage of Occurrences
20 Samples
TA = +25°C
VDD = 2.3
V
VDD = 5.5V
120
125
130
135
140
145
150
155
160
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CMRR, PSRR (dB)
PSRR
CMRR
VDD = 5.5
V
VDD = 2.3
V
MCP6V26/7/8
DS25007B-page 10 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-13: DC Open-Loop Gain vs.
Ambient Temperature.
FIGURE 2-14: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA= +85°C.
FIGURE 2-15: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA= +125°C.
FIGURE 2-16: Input Bias and Offset
Currents vs. Ambient Temperature with
VDD =+5.5V.
FIGURE 2-17: Input Bias Current vs. Input
Voltage (below VSS).
120
125
130
135
140
145
150
155
160
-50-25 0 255075100125
Ambient Temperature (°C)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.3V
-100
-50
0
50
100
150
200
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Bias, Offset Currents (pA)
IB
TA = +85°C
VDD = 5.5V
IOS
-400
-200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Bias, Offset Currents (pA)
IB
TA = +12C
VDD = 5.5V
IOS
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents (A)
VDD = 5.5
V
-IOS
IB
1p
10p
100p
1n
10n
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
100n
10n
1n
100p
10p
© 2011 Microchip Technology Inc. DS25007B-page 11
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.2 Other DC Voltages and Currents
FIGURE 2-18: Input Common Mode
Voltage Headroom (Range) vs. Ambient
Temperature.
FIGURE 2-19: Output Voltage Headroom
vs. Output Current.
FIGURE 2-20: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-21: Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-22: Supply Current vs. Power
Supply Voltage.
FIGURE 2-23: Power On Reset Trip
Voltage.
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Common Mode Voltage
Headroom (V)
Lower (VCML – VSS)
Upper ( VCMH – VDD)
1 Wafer Lo
t
10
100
1000
0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom (mV)
VDD – VOH
VDD = 5.5V
VDD = 2.3V
VOL – VSS
0
1
2
3
4
5
6
7
8
9
10
-50-25 0 255075100125
Ambient Temperature (°C)
Output Headroom (mV)
VDDVOH
VDD = 5.5
V
VOL – VSS
VDD = 2.3V
RL = 10 k
-40
-30
-20
-10
0
10
20
30
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
-4C
+25°C
+85°C
+125°C
+125°C
+85°C
+25°C
-4C
0
100
200
300
400
500
600
700
800
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Supply Current (µA/amplifier)
+125°C
+85°C
+25°C
-40°C
0%
5%
10%
15%
20%
25%
30%
35%
40%
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
1.35
POR Trip Voltage (V)
Percentage of Occurrences
820 Samples
1 Wafer Lot
TA = +25°C
MCP6V26/7/8
DS25007B-page 12 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-24: Power On Reset V oltage vs.
Ambient Temperature.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
POR Trip Voltage (V)
© 2011 Microchip Technology Inc. DS25007B-page 13
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.3 Frequency Response
FIGURE 2-25: CMRR and PSRR vs.
Frequency.
FIGURE 2-26: Open-Loop Gain vs.
Frequency with VDD =2.3V.
FIGURE 2-27: Open-Loop Gain vs.
Frequency with VDD =5.5V.
FIGURE 2-28: Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
FIGURE 2-29: Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
FIGURE 2-30: Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
0
10
20
30
40
50
60
70
80
90
100
110
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
CMR
R
PSRR+
PSRR-
100 100k
1k 1M10k
-20
-10
0
10
20
30
40
50
60
70
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Open-Loop Gain (dB)
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
| AOL |
AOL
1k 10k 100k 1M 10M
VDD = 2.3V
CL = 60 pF
-20
-10
0
10
20
30
40
50
60
70
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Open-Loop Gain (dB)
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
| AOL |
AOL
1k 10k 100k 1M 10M
VDD = 5.5V
CL = 60 pF
1003.0
H
z)
902.5
°
)
u
ct (M
H
V
DD
= 5.5V
GBWP
70
80
2.0
a
rgin (
°
Prod
u
60
70
1.0
.
h
ase M
a
d
width
PM
V
DD
= 2.3V
500.5
P
h
in Ban
d
400.0
-
50
-
25
0
25
50
75
100
125
Ga
50
25
0
25
50
75
100
125
Ambient Temperature (°C)
1204.0
H
z)
100
110
3.0
3.5
°)
u
ct (M
H
80
90
20
2.5
argin (
h
Prod
u
VDD = 5.5V
VDD = 2.3V GBWP
70
80
1.5
2
.
0
h
ase M
n
dwidt
h
50
60
0.5
1.0
P
h
a
in Ba
n
PM
400.0
0
.5
0
.0
0
.5
.0
.5
2
.0
2
.5
3
.0
3
.5
4
.0
4
.5
5
.0
5
.5
6
.0
G
a
-
0
0
0
1
1
2
2
3
3
4
4
5
5
6
Common Mode Input Voltage (V)
1204.0
H
z)
100
110
3.0
3.5
°
)
u
ct (M
H
80
90
2.5
a
rgin (
°
Prod
u
VDD = 5.5V
VDD = 2.3V PM
70
80
1.5
.
h
ase M
a
d
width
50
60
1.0
P
h
i
n Ban
d
GBWP
40
50
0.0
Ga
i
.
.
.
.
.
.
.
.
.
.
.
.
Output Voltage (V)
MCP6V26/7/8
DS25007B-page 14 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-31: Closed-Loop Output
Impedance vs. Frequency with VDD =2.3V.
FIGURE 2-32: Closed-Loop Output
Impedance vs. Frequency with VDD =5.5V.
FIGURE 2-33: Channel-to-Channel
Separation vs . Frequ enc y.
FIGURE 2-34: Maximum Output Voltage
Swing vs. Frequency.
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.0E+05 1.0E+06 1.0E+07 1.0E+08
Frequency (Hz)
Closed-Loop
Output Impedance ()
VDD = 2.3
V
100k 1M 10M 100M
1
10
100
1k
10k
G = 1 V/V
G = 11 V/V
G = 101 V/V
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.0E+05 1.0E+06 1.0E+07 1.0E+08
Frequency (Hz)
VDD = 2.3V
100k 1M 10M 100M
1
10
100
1k
10k
G = 1 V/V
G = 11 V/V
G = 101 V/V 0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
VDD = 5.5V
VDD = 2.3V
1k 10k 100k 1M
© 2011 Microchip Technology Inc. DS25007B-page 15
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.4 Input Noise and Distortion
FIGURE 2-35: Input Noise Voltage Density
and Integrated Input Noise Voltage vs.
Frequency.
FIGURE 2-36: Input Noise Voltage Density
vs. Input Common Mode Voltage.
FIGURE 2-37: Int ermodulation Distortion
vs. Frequency with VCM Dis tur ba nce (se e
Figure 1-7).
FIGURE 2-38: Intermodulation Distortion
vs. Frequency with VDD Disturbance (see
Figure 1-7).
FIGURE 2-39: Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD =2.3V.
FIGURE 2-40: Input Noise vs. Time with
1 Hz and 10 Hz Filters and VDD =5.5V.
1,00010,000
;
o
ltage;
D
ensity
;
V
DD
= 5.5V
V
DD
= 2.3V
1001,000
o
ise V
o
-P
)
l
tage
D
/
Hz)
10
100
n
put N
o
E
ni
(μV
P
ise Vo
l
e
ni
(nV
/
e
ni
10
100
r
ated I
n
E
p
ut No
110
1E 01
1E 02
1E 03
1E 04
1E 05
Integ
r
In
p
10
1k
10k
100k
E
ni
(0 Hz to f)
100
1
.
E
+
01
1
.
E
+
02
1
.
E
+
03
1
.
E
+
04
1
.
E
+
05
Fre
q
uenc
y
(
Hz
)
10
1k
10k
100k
100
0
10
20
30
40
50
60
70
80
90
100
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
VDD = 5.5V
VDD = 2.3V
Input Noise Voltage Density
(nV/Hz)
f < 5 kHz
0.1
1
10
100
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
IMD Spectrum, RTI (µVPK)
GDM = 1 V/V
VCM tone = 50 mVPK, f = 1 kHz
100 1k 10k 100k
IMD tone at DC
residual 1 kHz tone
VDD = 2.3
V
VDD = 5.5
V
0.1
1
10
100
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
IMD Spectrum, RTI (µVPK)
100 1k 10k 100k
GDM = 1 V/V
VDD tone = 50 mVP-P, f = 1 kHz
IMD tone at DC
1 kHz tone
VDD = 5.5V
VDD = 2.3V
0 102030405060708090100
t (s)
Input Noise Voltage; eni(t)
(0.2 µV/div)
VDD = 2.3V
NPBW = 10 Hz
NPBW = 1 Hz
0 102030405060708090100
t (s)
Input Noise Voltage; eni (t)
(0.2 µV/div)
VDD = 5.5
V
NPBW = 10 Hz
NPBW = 1 Hz
MCP6V26/7/8
DS25007B-page 16 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.5 Time Response
FIGURE 2-41: Input Offset Voltage vs.
Time with Temperature Change.
FIGURE 2-42: Input Offset Voltage vs.
Time at Power Up.
FIGURE 2-43: The MCP6V26/7/8 Device
Shows No Input Phase Reversal with Overdrive.
FIGURE 2-44: Non-inverting Small Signal
Step Response.
FIGURE 2-45: Non-inverting Large Signal
Step Response.
FIGURE 2-46: Inverting Small Signal Step
Response.
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
0 20 40 60 80 100 120 140 160 180
Time (s)
Input Offset Voltage (µV)
0
10
20
30
40
50
60
70
80
90
100
PCB Temperature (°C)
TPCB
VOS
Temperature increased by
using heat gun for 10 seconds.
-10
0
10
20
30
40
50
60
70
80
90
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (ms)
Input Offset VoltageV)
-4
-3
-2
-1
0
1
2
3
4
5
6
Power Supply Voltage (V)
POR Tri
p
Point
VOS
VDD
G = 1
-1
0
1
2
3
4
5
6
7
012345678910
Time (ms)
Input, Output Voltages (V)
VDD = 5.5V
G = 1
VOUT
VIN
012345678910
Time (µs)
Output Voltage (10 mV/div)
VDD = 5.5V
G = 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0 5 10 15 20 25 30 35 40 45 50
Time (µs)
Output Voltage (V)
VDD = 5.5V
G = 1
012345678910
Times)
Output Voltage (10 mV/div)
VDD = 5.5V
G = -1
© 2011 Microchip Technology Inc. DS25007B-page 17
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-47: Inverting Large Signal Step
Response.
FIGURE 2-48: Slew Rate vs. Ambient
Temperature.
FIGURE 2-49: Output Overdrive Recovery
vs. Time with G = -100 V/V.
FIGURE 2-50: Output Overdrive Recovery
Time vs. Inverting Gain.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0 5 10 15 20 25 30 35 40 45 50
Time (µs)
Output Voltage (V)
VDD = 5.5V
G = -1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-50-25 0 255075100125
Ambient Temperature (°C)
Slew Rate (V/µs)
Falling Edge
VDD = 5.5V
VDD = 2.3V
Rising Edge
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Time (50 µs/div)
Output Voltage (V)
-1
0
1
2
3
4
5
6
Input Voltage × G (V/V)
VDD = 5.5V
G = -100 V/V
0.5V Overdrive
VOU
T
G VIN
VOU
T
G VIN
1
10
100
1000
1 10 100 1000
Inverting Gain Magnitude (V/V)
Overdrive Recovery Time (µs)
0.5V Output Overdrive
tODR, lo
w
tODR, high
VDD = 2.3V
VDD = 5.5V
MCP6V26/7/8
DS25007B-page 18 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF, and CS = GND.
2.6 Chip Select Response (MCP6V28 only)
FIGURE 2-51: Chip Select Current vs.
Power Supply Voltage.
FIGURE 2-52: Power Supply Current vs.
Chip Select Voltage with VDD =2.3V.
FIGURE 2-53: Power Supply Current vs.
Chip Select Voltage with VDD =5.5V.
FIGURE 2-54: Chip Select Current vs. Chip
Select V oltage.
FIGURE 2-55: Chip Select Voltage, Output
Voltage vs. Time with VDD =2.3V.
FIGURE 2-56: Chip Select Voltage, Output
Voltage vs. Time with VDD =5.5V.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Current (μA)
Power Supply Voltage (V)
CS = VDD
0
100
200
300
400
500
600
700
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
Power Supply Current (μA)
Chip Select Voltage (V)
VDD = 2.3V
G= 1
VIN = 1.15V
VL= 0V
Op Amp
turns on
here
Op Amp
turns off
here
Hysteresis
0
100
200
300
400
500
600
700
800
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Current (μA)
Chip Select Voltage (V)
VDD = 5.5V
G= 1
VIN = 2.75V
VL= 0V
Op Amp
turns on
here
Op Amp
turns off
here
Hysteresis
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Current (μA)
Chip Select Voltage (V)
VDD = 5.5V
1.0
1.5
2.0
2.5
t
put Votage (V)
VOUT On
VOUT Off
VOUT Off
CS
0.0
0.5
0 5 10 15 20 25 30 35 40 45 50
Ou
t
Time (5 μs/div)
CS
VDD = 2.3V
G = +1 V/V
VIN = VDD
RL= 10 k tied to VDD/2
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
u
tput Votage (V)
VOUT On
VOUT Off
VOUT Off
V
55V
0.0
0.5
1.0
1.5
0 5 10 15 20 25 30 35 40 45 50
O
u
Time (5 μs/div)
CS
V
DD =
5
.
5V
G = +1 V/V
VIN = VDD
RL= 10 k tied to VDD/2
© 2011 Microchip Technology Inc. DS25007B-page 19
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF, and CS = GND.
FIGURE 2-57: Chip Select Relative Logic
Thresholds vs. Ambient Temperature.
FIGURE 2-58: Chip Select Hysteresis.
FIGURE 2-59: Chip Select Turn On Time
vs. Ambient Temperature.
FIGURE 2-60: Chip Select’s Pull-down
Resistor (RPD) vs. Ambient Temperature.
FIGURE 2-61: Quiescent Current in
Shutdown vs. Power Supply Voltage.
30%
35%
40%
45%
50%
55%
60%
65%
70%
-50 -25 0 25 50 75 100 125
Relative Chip Select Logic Levels;
Low and High (V/V)
Ambient Temperature (°C)
VIH/VDD
VIL/VDD
VDD = 5.5V
VDD = 2.3V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-50 -25 0 25 50 75 100 125
Chip Select Hysteresis (V)
Ambient Temperature (°C)
VDD = 5.5V
VDD = 2.3V
0
1
2
3
4
5
6
7
-50 -25 0 25 50 75 100 125
Chip Select Turn On Time (μs)
Ambient Temperature (°C)
VDD = 5.5V
VDD = 2.3V
0
1
2
3
4
5
6
7
-50 -25 0 25 50 75 100 125
Pull-down Resistor (M)
Ambient Temperature (°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Current (μA)
Power Supply Voltage (V)
CS = VDD
Representative Part
+125°C
+85°C
+25°C
-40°C
MCP6V26/7/8
DS25007B-page 20 © 2011 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3 Power Supply Pins
The positive power supply (VDD) is 2.3V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4 Chip Select (CS) Digital Input
This pin (CS) is a CMOS, Schmitt-triggered input that
places the MCP6V28 op amp into a low power mode of
operation.
3.5 Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (θJA).
MCP6V26 MCP6V27 MCP6V28
Symbol Description
TDFN MSOP, SOIC DFN MSOP, SOIC TDFN MSOP, SOIC
661166V
OUT
, VOUTA Output (op amp A)
222222V
IN–, VINA Inverting Input (op amp A)
333333V
IN+, VINA+ Non-inverting Input (op amp A)
444444 V
SS Negative Power Supply
—— 5 5 —— V
INB+ Non-inverting Input (op amp B)
—— 6 6 —— V
INB Inverting Input (op amp B)
—— 7 7 —— V
OUTB Output (op amp B)
778877 V
DD Positive Power Supply
—— 8 8 CS Chip Select (op amp A)
1, 5, 8 1, 5, 8 1, 5 1, 5 NC No Internal Connection
9 9 9 EP Exposed Thermal Pad (EP);
must be connected to VSS
© 2011 Microchip Technology Inc. DS25007B-page 21
MCP6V26/7/8
4.0 APPLICATIONS
The MCP6V26/7/8 family of auto-zeroed op amps are
manufactured using Microchip’s state-of-the-art CMOS
process. This family is designed for low cost, low power
and high precision applications. Its low supply voltage,
low quiescent current and wide bandwidth make the
MCP6V26/7/8 devices ideal for battery-powered appli-
cations.
4.1 Overview of Auto-Zeroing
Operation
Figure 4-1 shows a simplified diagram of the
MCP6V26/7/8 auto-zeroed op amps. This will be used
to explain how the DC voltage errors are reduced in this
architecture.
FIGURE 4-1: Simplified Auto-Zeroed Op Amp Functional Diagram.
4.1.1 BUILDING BLOCKS
The Null Amplifier and Main Amplifier are designed for
high gain and accuracy using a differential topology.
They have a main input pair (+ and - pins at their top
left) used for the signal. They have an auxiliary input
pair (+ and - pins at their bottom left) used for correcting
the offset voltages. Both input pairs are added together
internally. The capacitors at the auxiliary inputs (CFW
and CH) hold the corrected values during normal
operation.
The Output Buffer is designed to drive external loads at
the VOUT pin. It also produces a single-ended output
voltage (VREF is an internal reference voltage).
All of these switches are make-before-break in order to
minimize glitch-induced errors. They are driven by two
clock phases (φ1 and φ2) that select between normal
mode and auto-zeroing mode.
The clock is derived from an internal R-C oscillator
running at a rate of fOSC1 = 850 kHz. The oscillator’s
output is divided down to the desired rate.
The internal POR ensures the part starts up in a known
good state. It also provides protection against power
supply brown-out events.
The Digital Control circuitry takes care of all of the
housekeeping details of the switching operation. It also
takes care of POR events.
VIN+
VINMain
Output VOUT
VREF
Amp.
Buffer
NC
Null
Amp.
Null
Input φ1
Switches
Null
Correct
φ2
Switches
Null
Output
Switches
CH
CFW
POR
Digital
Control Oscillator
φ1
φ2
MCP6V26/7/8
DS25007B-page 22 © 2011 Microchip Technology Inc.
4.1.2 AUTO-ZEROING ACTION
Figure 4-2 shows the connections between amplifiers
during the Normal Mode of operation (φ1). The hold
capacitor (CH) corrects the Null Amplifier’s input offset.
Since the Null Amplifier has very high gain, it
dominates the signal seen by the Main Amplifier. This
greatly reduces the impact of the Main Amplifier’s input
offset voltage on overall performance. Essentially, the
Null Amplifier and Main Amplifier behave as a regular
op amp with very high gain (AOL) and very low offset
voltage (VOS).
FIGURE 4-2: Normal Mode of Operation (
φ
1); Equivalent Amplifier Diagram.
Figure 4-3 shows the connections between amplifiers
during the Auto-zeroing Mode of operation (φ2). The
signal goes directly through the Main Amplifier, and the
flywheel capacitor (CFW) maintains a constant correc-
tion on the Main Amplifier’s offset.
The Null Amplifier uses its own high open loop gain to
drive the voltage across CH to the point where its input
offset voltage is almost zero. Because the signal input
pair is connected to VIN+, the auto-zeroing action
corrects the offset at the current common mode input
voltage (VCM) and supply voltage (VDD). This makes
the DC CMRR and PSRR very high also.
Since these corrections happen every 40 µs, or so, we
also minimize slow errors, including offset drift with
temperature (ΔVOS/ΔTA), 1/f noise, and input offset
aging.
FIGURE 4-3: Auto-zeroing Mode of Operation (
φ
2); Equivalent Diagram.
4.1.3 INTERMODULATION DISTORTION
(IMD)
The MCP6V26/7/8 op amps will show intermodulation
distortion (IMD), products when an AC signal is
present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the auto-zeroing circuitry’s non-linear
response to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
See Figure 2-37 and Figure 2-38.
VIN+
VINMain
Output VOUT
VREF
Amp.
Buffer
NC
Null
Amp.
CH
CFW
VIN+
VINMain
Output VOUT
VREF
Amp.
Buffer
NC
Null
Amp.
CH
CFW
© 2011 Microchip Technology Inc. DS25007B-page 23
MCP6V26/7/8
4.2 Other Functional Blocks
4.2.1 RAIL-TO-RAIL INPUTS
The input stage of the MCP6V26/7/8 op amps use two
differential CMOS input stages in parallel. One
operates at low common mode input voltage (VCM,
which is approximately equal to VIN+ and VIN– in
normal operation) and the other at high VCM. With this
topology, the input operates with VCM up to VDD +0.2V,
and down to VSS 0.15V, at +25°C (see Figure 2-18).
The input offset voltage (VOS) is measured at
VCM =V
SS 0.15V and VDD + 0.2V to ensure proper
operation.
The transition between the input stages occurs when
VCM VDD –1.2V (see Figure 2-7 and Figure 2-8). For
the best distortion and gain linearity, with non-inverting
gains, avoid this region of operation.
4.2.1.1 Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-43 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.1.2 Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1, Absolute Maximum
Ratings ). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-4. This structure was chosen to
protect the input transistors against many (but not all)
over-voltage conditions, and to minimize input bias
current (IB).
FIGURE 4-4: Simplified Analog Input ESD
Structures.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that are well above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs;
Figure 4-5 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
FIGURE 4-5: Protecting the Analog Inputs
Against High Voltages.
4.2.1.3 Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1, Absolute
Maximum Ratings ). This requirement is
independent of the voltage limits previously discussed.
Figure 4-6 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
FIGURE 4-6: Protecting the Analog Inputs
Against High Currents.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage
Bond
Pad VIN
V1
VDD
D1
VOUT
V2
D2
U1
MCP6V2X
V1
R1
VDD
D1
min(R1,R
2)>VSS –min(V
1,V
2)
2mA
VOUT
V2
R2
D2
min(R1,R
2)>max(V1,V
2)–V
DD
2mA
U1
MCP6V2X
MCP6V26/7/8
DS25007B-page 24 © 2011 Microchip Technology Inc.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, the currents through
diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-17.
4.2.2 RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V26/7/8
zero-drift op amps is VDD 15 mV (minimum) and
VSS + 15 mV (maximum) when RL=10kΩ is
connected to VDD/2 and VDD = 5.5V. Refer to
Figure 2-19 and Figure 2-20.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.2.3 CHIP SELECT (CS)
The single MCP6V28 has a Chip Select (CS) pin.
When CS is pulled high, the supply current for the
corresponding op amp drops to about 1 µA (typical),
and is pulled through the CS pin to VSS. When this
happens, the amplifier is put into a high impedance
state. By pulling CS low, the amplifier is enabled. If the
CS pin is left floating, the internal pull-down resistor
(about 5 MΩ) will keep the part on. Figure 1-4 shows
the output voltage and supply current response to a CS
pulse.
4.3 Application Tips
4.3.1 INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
temperature coefficients (TC1 and TC2) of input offset
voltage. The input offset voltage, at any temperature in
the specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2 DC GAIN PLOTS
Figure 2-9, Figure 2-10 and Figure 2-11 are histograms
of the reciprocals (in units of µV/V) of CMRR, PSRR
and AOL, respectively. They represent the change in
input offset voltage (VOS) with a change in common
mode input voltage (VCM), power supply voltage (VDD)
and output voltage (VOUT).
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise, not unstable behavior. We validate the op amps
stability by making multiple measurements of VOS; an
unstable part would fail, because it would show either
greater variability in VOS, or the output stuck at one of
the rails.
4.3.3 OFFSET AT POWER UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±5 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to the startup time (like
tSTR).
It can be simple to avoid this extra startup time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
4.3.4 SOURCE RESISTANCES
The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances are needed for high gains.
Without them, parasitic capacitances can cause
positive feedback and instability.
4.3.5 SOURCE CAPACITANCE
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match. Large
input capacitances and source resistances, together
with high gain, can lead to positive feedback and
instability.
VOS TA
() VOS TC1ΔTTC
2ΔT2
++=
Where:
ΔT=T
A–25°C
VOS(TA) = input offset voltage at TA
VOS = input offset voltage at +25°C
TC1= linear temperature coefficient
TC2= quadratic temperature
coefficient
© 2011 Microchip Technology Inc. DS25007B-page 25
MCP6V26/7/8
4.3.6 CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These auto-zeroed op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (RISO in Figure 4-7)
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-7: Output Resistor, RISO,
Stabi li ze s Capaci tiv e Load s.
Figure 4-8 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN2). The y-axis is
the normalized resistance (GNRISO).
GN is the circuit’s noise gain. For non-inverting gains,
GN and the Signal Gain are equal. For inverting gains,
GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-8: Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable. Bench evaluation and
simulations with the MCP6V26/7/8 SPICE macro
model are helpful.
4.3.7 STABILIZING OUTPUT LOADS
This family of auto-zeroed op amps has an output
impedance (Figure 2-31 and Figure 2-32) that has a
double zero when the gain is low. This can cause a
large phase shift in feedback networks that have low
resistance near the part’s bandwidth. This large phase
shift can cause stability problems.
Figure 4-9 shows that the load on the output is
(RL+R
ISO)||(RF+R
G), where RISO is before the load
(like Figure 4-7). This load needs to be large enough to
maintain stability; it should be at least (2 kΩ)/GN.
FIGURE 4-9: Output Load.
4.3.8 GAIN PEAKING
Figure 4-10 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG rep-
resent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel. The capacitance CFP represents the
parasitic capacitance coupling the output and
non-inverting input pins.
FIGURE 4-10: Amplifier with Parasitic
Capacitance.
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF||RG
.
CN and RN form a low-pass filter that affects the signal
at VP
. This filter has a single real pole at 1/(2πRNCN).
RISO
CL
VOUT
U1
MCP6V2X
1
10
100
1000
1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
CL/GN2 (F)
Recommended GNRISO ()
100p 1n 10n 100n
1
10
100
1k
GN = 1
GN = 2
GN = 5
GN  10
RGRF
VOUT
RLCL
U1
MCP6V2X
RF
CG
RN
VOUT
U1
MCP6V2X
RG
VM
VP
CFP
CN
MCP6V26/7/8
DS25007B-page 26 © 2011 Microchip Technology Inc.
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.3.6, Capacitive
Loads), CG and the open-loop gain’s phase shift. An
approximate limit for RF is:
EQUATION 4-2:
Some applications may modify these values to reduce
either output loading or gain peaking (step response
overshoot).
At high gains, RG and CG need to be small in order to
prevent positive feedback and oscillations.
4.3.9 REDUCING UNDESIRED NOISE
AND SIGNALS
Reduce undesired noise and signals with:
Low bandwidth signal filters:
- Minimizes random analog noise
- Reduces interfering signals
Good PCB layout techniques:
- Minimizes crosstalk
- Minimizes parasitic capacitances and
inductances that interact with fast switching
edges
Good power supply design:
- Provides isolation from other parts
- Filters interference on supply line(s)
4.3.10 SUPPLY BYPASSING AND
FILTERING
With this family of op amps, the power supply pin (VDD
for single supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm of the pin for good
high-frequency performance.
These parts also need a bulk capacitor (i.e., 1 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other low noise,
analog parts.
In some cases, high-frequency power supply noise
(e.g., switched mode power supplies) may cause
undue intermodulation distortion, with a DC offset shift;
this noise needs to be filtered. Adding a resistor into the
supply connection can be helpful. This resistor needs
to be small enough to prevent a large drop in VDD for
the op amp, which would cause a reduced output range
and possible load-induced power supply noise. It also
needs to be large enough to dissipate little power when
VDD is turned on and off quickly. Figure 4-11 shows a
circuit with resistors in the supply connections. It gives
good rejection out to 1 MHz for switched mode power
supplies. Smaller resistors and capacitors are a better
choice for designs where the power supply is not as
noisy.
FIGURE 4-11: Additional Supply Filtering.
4.3.11 PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the Printed Circuit Board (PCB), the wiring and the
thermal environment has a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6V26/7/8 op
amps minimum and maximum specifications.
4.3.11.1 PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermo-junction effect). This
effect is used in thermocouples to measure tempera-
ture. The following are examples of thermo-junctions
on a PCB:
Components (resistors, op amps, …) soldered to
a copper pad
Wires mechanically attached to the PCB
Jumpers
Solder joints
•PCB vias
Typical thermo-junctions have temperature to voltage
conversion coefficients of 10 to 100 µV/°C (sometimes
higher).
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques”) contains in depth information on
PCB layout techniques that minimize thermo-junction
effects. It also discusses other effects, such as
crosstalk, impedances, mechanical stresses and
humidity.
RF2 k
Ω
12 p F
CG
---------------
×
GN2
×
VS_ANA
50Ω50Ω
100 µF 100 µF
0.1 µF
1/4W 1/10W
to other analog parts
U1
MCP6V2X
© 2011 Microchip Technology Inc. DS25007B-page 27
MCP6V26/7/8
4.3.11.2 Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
Common mode noise (remote sensors)
Ground loops (current return paths)
Power supply coupling
Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC perfor-
mance. Non-linear distortion can convert these signals
to multiple tones, including a DC shift in voltage. When
the signal is sampled by an ADC, these AC signals can
also be aliased to DC, causing an apparent shift in
offset.
To reduce interference:
- Keep traces and wires as short as possible
- Use shielding (e.g., encapsulant)
- Use ground plane (at least a star ground)
- Place the input signal source near to the DUT
- Use good PCB layout techniques
- Use a separate power supply filter (bypass
capacitors) for these auto-zeroed op amps
4.3.11.3 Miscellaneous Effects
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias
current-related offsets.
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the tribo-electric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
Mechanical stresses can make some capacitor types
(such as ceramic) to output small voltages. Use more
appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
Humidity can cause electro-chemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
4.4 Typical Applications
4.4.1 WHEATSTONE BRIDGE
Many sensors are configured as Wheatstone bridges.
Strain gauges and pressure sensors are two common
examples. These signals can be small and the
common mode noise large. Amplifier designs with high
differential gain are desirable.
Figure 4-12 shows how to interface to a Wheatstone
bridge with a minimum of components. Because the
circuit is not symmetric, the ADC input is single ended,
there is a minimum of filtering, and the CMRR is good
enough for moderate common mode noise.
FIGURE 4-12: Simp le Des ign .
Figure 4-13 shows a higher performance circuit for
Wheatstone bridges. This circuit is symmetric and has
high CMRR. Using a differential input to the ADC helps
with the CMRR.
FIGURE 4-13: High Performance Design.
VDD
RR
RR
100R
0.01C
ADC
VDD
0.2R
0.2R
3kΩ
U1
MCP6V26
20 kΩ
F
200Ω
20 kΩ
F
ADC
VDD
200 Ω
200 Ω
3kΩ
3kΩ
F
RR
RR
VDD
10 nF
10 nF
200Ω
U1A
½ MCP6V27
U1B
½ MCP6V27
MCP6V26/7/8
DS25007B-page 28 © 2011 Microchip Technology Inc.
4.4.2 RTD SENSOR
The ratiometric circuit in Figure 4-14 conditions a three
wire RTD. It corrects for the sensor’s wiring resistance
by subtracting the voltage across the middle RW. The
top R1 does not change the output voltage; it balances
the op amp inputs. Failure (open) of the RTD is
detected by an out-of-range voltage.
FIGURE 4-14: RTD Sensor.
The voltages at the input of the ADC can be calculated
with the following:
4.4.3 THERMOCOUPLE SENSOR
Figure 4-15 shows a simplified diagram of an amplifier
and temperature sensor used in a thermocouple
application. The type K thermocouple senses the
temperature at the hot junction (THJ), and produces a
voltage at V1 proportional to THJ (in °C). The amplifier’s
gain is set so that V4/THJ is 10 mV/°C. V3 represents
the output of a temperature sensor, which produces a
voltage proportional to the temperature (in °C) at the
cold junction (TCJ), and with a 0.50V offset. V2 is set so
that V4 is 0.50V when THJ –T
CJ is 0°C.
EQUATION 4-3:
FIGURE 4-15: Thermocouple Sensor;
Simplified Circuit.
Figure 4-16 shows a more complete implementation of
this circuit. The dashed red arrow indicates a thermally
conductive connection between the thermocouple and
the MCP9700A; it needs to be very short and have low
thermal resistance.
FIGURE 4-16: Thermocouple Sensor.
R3
100 nF
10 nF
R2
R3
100 nF
ADC
VDD
2.49 kΩ
2.49 kΩ
10 nF
VDD
RW
RW
RW
RT
RB
RRTD
R1
R1
F
100Ω
3kΩ
3kΩ
20 kΩ
20 kΩ
100 kΩ
100 kΩ
2.49 kΩ
2.49 kΩ
R2
2.55 kΩ
2.55 kΩ
U1A
½ MCP6V27
U1B
½ MCP6V27
VDM GRTD VTVB
()GWVW
+=
VCM VTVBGRTD 1G
W
+()VW
++
2
------------------------------------------------------------------------------=
GRTD 12R
3R2
+=
GWGRTD R3R1
=
Where:
VT= Voltage at the top of RRTD
VB= Voltage at the bottom of RRTD
VW= Voltage across top and middle RW’s
VCM = ADC’s common mode input
VDM = ADC’s differential mode input
V1THJ(40 µV/°C)
V2= (1.00V)
V3=T
CJ(10 mV/°C) + (0.50V)
V4=250V
1+(V
2–V
3)
(10 mV/°C) (THJ –T
CJ)+(0.50V)
(RTH)/250
(RTH)
(RTH)/250
C
(RTH)
C
V4
Type K
40 µV/°C
(RTH)
(RTH)
V1
V3
(hot junction
(cold junction
V2
Thermocouple
at THJ)
at TCJ)
RTH = Thevenin Equivalent Resistance
U1
MCP6V26
(RTH)/250
0.5696(RTH)
(RTH)/250
C
(RTH)
CV4
Type K
(RTH)
4.100(RTH)
V1
Temp. Se nsor
VDD
VREF
VDD
3kΩ
RTH = Thevenin Equivalent Resistance (e.g., 10 kΩ)
U3
MCP6V26
U1
MCP1541
U2
MCP9700A
© 2011 Microchip Technology Inc. DS25007B-page 29
MCP6V26/7/8
The MCP9700A senses the temperature at its physical
location. It needs to be at the same temperature as the
cold junction (TCJ), and produces V3 (Figure 4-15).
The MCP1541 produces a 4.10V output, assuming
VDD is at 5.0V. This voltage, tied to a resistor ladder of
4.100(RTH) and 1.3224(RTH), would produce a
Thevenin equivalent of 1.00V and 250(RTH). The
1.3224(RTH) resistor is combined in parallel with the
top right RTH resistor (in Figure 4-15), producing the
0.5696(RTH) resistor.
V4 should be converted to digital, then corrected for the
thermocouple’s non-linearity. The ADC can use the
MCP1541 as its voltage reference. Alternately, an
absolute reference inside a PICmicro® device can be
used instead of the MCP1541.
4.4.4 OFFSET VOLTAGE CORRECTION
Figure 4-17 shows an MCP6V27 correcting the input
offset voltage of another op amp. R2 and C2 integrate
the offset error seen at the other op amp’s input; the
integration needs to be slow enough to be stable (with
the feedback provided by R1 and R3).
FIGURE 4-17: Offset Correction.
4.4.5 PRECISION COMPARATOR
Use high gain before a comparator to improve the
latter’s performance. Do not use MCP6V26/7/8 as a
comparator by itself; the VOS correction circuitry does
not operate properly without a feedback loop.
FIGURE 4-18: Precision Comparator.
C2
R2
R1R3
U2
VDD/2
VIN VOUT
R2
U1
MCP6V26
R4
R5
VDD/2
MCP661
VIN
R3
R2
VDD/2
U2
VOUT
R5
R4
R1
1kΩ
U1
MCP6V26
MCP6541
MCP6V26/7/8
DS25007B-page 30 © 2011 Microchip Technology Inc.
NOTES:
© 2011 Microchip Technology Inc. DS25007B-page 31
MCP6V26/7/8
5.0 DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6V26/7/8 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6V26/7/8
family of op amps is available on the Microchip web site
at www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
Filter-Lab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3 Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design require-
ment. Available at no cost from the Microchip website
at www.microchip.com/maps, the MAPS is an overall
selection tool for Microchip’s product portfolio that
includes Analog, Memory, MCUs and DSCs. Using this
tool, a customer can define a filter to sort features for a
parametric search of devices and export side-by-side
technical comparison reports. Helpful links are also
provided for Data sheets, Purchase and Sampling of
Microchip parts.
5.4 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demon-
stration and Evaluation Boards that are designed to
help customers achieve faster time to market. For a
complete listing of these boards and their correspond-
ing user’s guides and technical information, visit the
Microchip web site at www.microchip.com/analogtools.
Some boards that are especially useful are:
MCP6V01 Thermocouple Auto-Zeroed Reference
Design
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP
Evaluation Board
5.5 Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filteri ng Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview, DS00990
AN1177: “Op Amp Precision Design: DC Errors”,
DS01177
AN1228: “Op Amp Precision Design: Random Noise”,
DS01228
AN1258: “Op Amp Precision Design: PCB Layout
Techniques, DS01258
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
MCP6V26/7/8
DS25007B-page 32 © 2011 Microchip Technology Inc.
NOTES:
© 2011 Microchip Technology Inc. DS25007B-page 33
MCP6V26/7/8
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead TDFN (2x3x0.75 mm)
(MCP6V26, MCP6V28)
Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
8-Lead DFN (4x4x0.9 mm) (MCP6V27)Example
YYWW
NNN
XXXXXX
XXXXXX
PIN 1 PIN 1
3
e
6V27
E/MD
1129
256
8-Lead MSOP (3x3 mm) Example
6V27E
129256
8-Lead SOIC (3.90 mm) Example
NNN
MCP6V27E
SN^^ 1129
256
3
e
Device Code
MCP6V26T-E/MNY ABA
MCP6V28T-E/MNY ABB
ABA
129
25
MCP6V26/7/8
DS25007B-page 34 © 2011 Microchip Technology Inc.
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
© 2011 Microchip Technology Inc. DS25007B-page 35
MCP6V26/7/8
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
MCP6V26/7/8
DS25007B-page 36 © 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc. DS25007B-page 37
MCP6V26/7/8
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D
N
E
E1
NOTE 1
12
e
b
A
A1
A2 c
L1 L
φ
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MCP6V26/7/8
DS25007B-page 38 © 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc. DS25007B-page 39
MCP6V26/7/8
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6V26/7/8
DS25007B-page 40 © 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc. DS25007B-page 41
MCP6V26/7/8
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MCP6V26/7/8
DS25007B-page 42 © 2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2011 Microchip Technology Inc. DS25007B-page 43
MCP6V26/7/8
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6V26/7/8
DS25007B-page 44 © 2011 Microchip Technology Inc.
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© 2011 Microchip Technology Inc. DS25007B-page 45
MCP6V26/7/8
APPENDIX A: REVISION HISTORY
Revision B (August 2011)
The following is the list of modifications:
1. Added the MCP6V26 and MCP6V28 single op
amps.
a) Updated package drawings on page 1.
b) Updated the pinout table (Ta b l e 3 - 1 ).
c) Added 8-lead, 2×3 TDFN package to the
Thermal Characteristics Table (Tab le 1 -4 ).
d) Added 8-lead, 2×3 TDFN package to
Section 6.0 “Packaging Information”.
e) Added parts numbers to Product Identifica-
tion System.
2. Added Chip Select (CS) information.
a) Added Digital Electrical Specifications table
(Ta b l e 1 - 3 ).
b) Added Timing Diagram (Figure 1-4).
c) Added Section 2.6 “Chip Select
Response (MCP6V28 only)” to the Typical
Performance Curves.
d) Added Section 4.2.3 “Chip Select (CS)”
to the applications write up.
3. Added information on positive feedback and
parasitic feedback capacitance.
a) Added to Section 4.3.4 “Source
Resistances”.
b) Added to Section 4.3.5 “Source
Capacitance”.
c) Modified Figure 4-10.
d) Added to Section 4.3.8 “Gain Peaking”.
4. Other minor typographical corrections.
Revision A (March 2011)
Original data sheet for the MCP6V27 dual op
amps.
MCP6V26/7/8
DS25007B-page 46 © 2011 Microchip Technology Inc.
APPENDIX B: OFFSET RELATED
TEST SCREENS
Input offset voltage-related specifications in the DC
spec table (Ta b l e 1 - 1 ) are based on bench
measurements (see Section 2.1 “DC Input
Precision”). These measurements are much more
accurate because:
More compact circuit
Soldered parts on the PCB (to validate other
measurements)
More time spent averaging (reduces noise)
Better temperature control
- Reduced temperature gradients
- Greater accuracy
We use production screens to ensure the quality of our
outgoing products. These screens are set at wider
limits to eliminate any fliers; see Table B-1.
TABLE B-1: OFFSET RELATED TEST SCREENS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Max Units Conditions
Input Offset
Input Offset Voltage VOS -10 +10 µV TA = +25°C (Note 1, Note 2)
Input Offset Voltage Drift with Temperature
(linear Temp. Co.)
TC1——nV/°CT
A = -40 to +125°C (Note 3)
Power Supply Rejection PSRR 115 dB (Note 1)
Common Mode
Common Mode Rejection CMRR 106 dB VDD = 2.3V, VCM = -0.15V to 2.5V (Note 1)
CMRR 116 dB VDD = 5.5V, VCM = -0.15V to 5.7V (Note 1)
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 114 dB VDD = 2.3V, VOUT = 0.2V to 2.1V (Note 1)
AOL 122 dB VDD = 5.5V, VOUT = 0.2V to 5.3V (Note 1)
Note 1: Due to thermal junctions and other errors in the production environment, these specifications are only
screened in production.
2: VOS is also sample screened at +125°C.
3: TC1 is not measured in production.
© 2011 Microchip Technology Inc. DS25007B-page 47
MCP6V26/7/8
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6V26 Single Op Amp
MCP6V26T Single Op Amp (Tape and Reel)
MCP6V27 Dual Op Amp
MCP6V27T Dual Op Amp (Tape and Reel)
MCP6V28 Single Op Amp with Chip Select
MCP6V28T Single Op Amp with Chip Select
(Tape and Reel)
Temperature Range: E = -40°C to +125°C
Package: MD = Plastic Dual Flat, No-Lead (4×4x0.9), 8-lead
MNY * = Plastic Dual Flat, No-Lead (2×3x0.75), 8-lead
MS = Plastic Micro Small Outline Package, 8-lead
SN = Plastic SOIC (150mil Body), 8-lead
* Y = Nickel Palladium gold manufacturing designator. Only
available on the TDFN package.
PART NO. –X /XX
PackageTemperature
Range
Device
Examples:
a) MCP6V26T-E/MNY: Extended temperature,
8LD 2×3 TDFN
package
b) MCP6V26-E/MS: Extended temperature,
8LD MSOP package
a) MCP6V26T-E/SN: Tape and Reel,
Extended temperature,
8LD SOIC package
a) MCP6V27-E/MD: Extended temperature,
8LD 4x4 DFN package
b) MCP6V27-E/MS: Extended temperature,
8LD MSOP package
c) MCP6V27-E/SN: Extended temperature,
8LD SOIC package
a) MCP6V28T-E/MNY: Extended temperature,
8LD 2×3 TDFN
package
b) MCP6V28-E/MS: Extended temperature,
8LD MSOP package
c) MCP6V28T-E/SN: Tape and Reel,
Extended temperature,
8LD SOIC package
MCP6V26/7/8
DS25007B-page 48 © 2011 Microchip Technology Inc.
NOTES:
© 2011 Microchip Technology Inc. DS25007B-page 49
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-503-0
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS25007B-page 50 © 2011 Microchip Technology Inc.
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08/02/11