© 2011 Microchip Technology Inc. DS25007B-page 1
MCP6V26/7/8
Features
• High DC Precision:
-V
OS Drift: ±50 nV/°C (maximum)
-V
OS: ±2 µV (maximum)
-A
OL: 125 dB (minimum)
- PSRR: 125 dB (minimum)
- CMRR: 120 dB (minimum)
-E
ni: 1.0 µVP-P (typical), f = 0.1 Hz to 10 Hz
-E
ni: 0.32 µVP-P (typical), f = 0.01 Hz to 1 Hz
• Low Power and Supply Voltages:
-I
Q: 620 µA/amplifier (typical)
- Wide Supply Voltage Range: 2.3V to 5.5V
•Easy to Use:
- Rail-to-Rail Input/Output
- Gain Bandwidth Product: 2 MHz (typical)
- Unity Gain Stable
- Available in Single and Dual
- Single with Chip Select (CS): MCP6V28
• Extended Temperature Range: -40°C to +125°C
Typical Applications
• Portable Instrumentation
• Sensor Conditioning
• Temperature Measurement
• DC Offset Correction
• Medical Instrumentation
Design Aids
• SPICE Macro Models
•FilterLab
® Software
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
Related Parts
Parts with lower power, lower bandwidth and higher
noise:
• MCP6V01/2/3: Spread clock
• MCP6V06/7/8: Non-spread clock
Description
The Microchip Technology Inc. MCP6V26/7/8 family of
operational amplifiers provides input offset voltage
correction for very low offset and offset drift. These
devices have a wide gain bandwidth product (2 MHz,
typical) and strongly reject switching noise. They are
unity gain stable, have no 1/f noise, and have good
power supply rejection ratio (PSRR) and common
mode rejection ratio (CMRR). These products operate
with a single supply voltage as low as 2.3V, while
drawing 620 µA/amplifier (typical) of quiescent current.
The Microchip Technology Inc. MCP6V26/7/8 op amps
are offered as a single (MCP6V26), single with Chip
Select (CS) (MCP6V28) and dual (MCP6V27). They
were designed using an advanced CMOS process.
Package Types (top view)
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NCNC
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB–
VINB+
MCP6V26
MSOP, SOIC
MCP6V27
MSOP, SOIC
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
MCP6V28
MSOP, SOIC
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB–
VINB+
MCP6V27
4×4 DFN *
* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - 1 .
EP
9
VIN+
VIN–
VSS
1
2
3
4
8
7
6
5
NC NC
VDD
VOUT
NC
MCP6V26
2×3 TDFN *
EP
9
VIN+
VIN–
VSS
1
2
3
4
8
7
6
5
NC CS
VDD
VOUT
NC
MCP6V28
2×3 TDFN *
EP
9
620 µA, 2 MHz Auto-Zeroed Op Amps
MCP6V26/7/8
DS25007B-page 2 © 2011 Microchip Technology Inc.
Typical Application Circuit
Offset Voltage Correction for Power Driver
10 nF
10 kΩ
10 kΩ10 kΩ
MCP661
VDD/2
500 kΩ
VIN VOUT
10 kΩ
MCP6V26
5kΩ
VDD/2
U2
U1
© 2011 Microchip Technology Inc. DS25007B-page 3
MCP6V26/7/8
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Absolute Maximum Ratings †
VDD –V
SS ..............................................................................6.5V
Current at Input Pins †† ......................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† .......... VSS – 1.0V to VDD+1.0V
All other Inputs and Outputs .................. VSS – 0.3V to VDD+0.3V
Difference Input voltage ............................................. |VDD –V
SS|
Output Short Circuit Current .......................................Continuous
Current at Output and Supply Pins ...................................±30 mA
Storage Temperature ..........................................-65°C to +150°C
Max. Junction Temperature .............................................. +150°C
ESD protection on all pins (HBM, CDM, MM) ≥4 kV,1.5 kV, 300V
†Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
†† See Section 4.2.1, Rail-to-Rail Inputs.
1.2 Specifications
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -2 — +2 µV TA = +25°C (Note 1)
Input Offset Voltage Drift
with Temperature (linear Temp. Co.)
TC1-50 — +50 nV/°C TA = -40 to +125°C
(Note 1)
Input Offset Voltage Quadratic
Temperature Coefficient
TC2—±0.2 —nV/°C
2TA = -40 to +125°C
Power Supply Rejection PSRR 125 142 — dB (Note 1)
Input Bias Current and Impedance
Input Bias Current IB—+7 —pA
Input Bias Current across
Temperature
IB—+110 — pAT
A = +85°C
IB—+1.2 +5 nAT
A = +125°C
Input Offset Current IOS —±70 — pA
Input Offset Current across
Temperature
IOS —±50 — pAT
A = +85°C
IOS —±60 — pAT
A = +125°C
Common Mode Input Impedance ZCM —10
13||12 — Ω||pF
Differential Input Impedance ZDIFF —10
13||12 — Ω||pF
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production
environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset
Related Test Screens”).
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
MCP6V26/7/8
DS25007B-page 4 © 2011 Microchip Technology Inc.
Common Mode
Common-Mode Input
Voltage Range Low
VCML ——V
SS −0.15 V (Note 2)
Common-Mode Input
Voltage Range High
VCMH VDD +0.2 — — V (Note 2)
Common-Mode Rejection CMRR 120 136 — dB VDD = 2.3V,
VCM = -0.15V to 2.5V
(Note 1, Note 2)
CMRR 125 142 — dB VDD = 5.5V,
VCM = -0.15V to 5.7V
(Note 1, Note 2)
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 125 147 — dB VDD =2.3V,
VOUT = 0.2V to 2.1V
(Note 1)
AOL 133 155 — dB VDD =5.5V,
VOUT = 0.2V to 5.3V
(Note 1)
Output
Minimum Output Voltage Swing VOL —V
SS +5 V
SS +15 mV G = +2, 0.5V
input overdrive
Maximum Output Voltage Swing VOH VDD –15 V
DD −5 — mV G = +2, 0.5V
input overdrive
Output Short Circuit Current ISC —±12 — mAV
DD =2.3V
ISC —±22 — mAV
DD =5.5V
Power Supply
Supply Voltage VDD 2.3 — 5.5 V
Quiescent Current per amplifier IQ450 620 800 µA IO = 0
POR Trip Voltage VPOR 1.15 — 1.65 V
TABLE 1-1: DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL and CS = GND (refer to Figure 1-5 and Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
Note 1: Set by design and characterization. Due to thermal junction and other effects in the production
environment, these parts can only be screened in production (except TC1; see Appendix B: “Offset
Related Test Screens”).
2: Figure 2-18 shows how VCML and VCMH changed across temperature for the first production lot.
© 2011 Microchip Technology Inc. DS25007B-page 5
MCP6V26/7/8
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kΩ to VL, CL = 60 pF and CS = GND (refer to Figure 1-5 and
Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
Amplifier AC Response
Gain Bandwidth Product GBWP — 2.0 — MHz
Slew Rate SR — 1.0 — V/µs
Phase Margin PM — 65 — ° G = +1
Amplifier Noise Response
Input Noise Voltage Eni —0.32 — µV
P-P f = 0.01 Hz to 1 Hz
Eni —1.0 — µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —50 — nV/√Hz f < 5 kHz
eni —29 — nV/√Hz f = 100 kHz
Input Noise Current Density ini —0.6 — fA/√Hz
Amplifier Distortion (Note 1)
Intermodulation Distortion (AC) IMD — 40 — µVPK VCM tone = 50 mVPK at 1 kHz,
GN = 1
Amplifier Step Response
Start Up Time tSTR — 75 — µs G = +1, VOS within 50 µV of its final value
(Note 2)
Offset Correction Settling Time tSTL — 150 — µs G = +1, VIN step of 2V,
VOS within 50 µV of its final value
Output Overdrive Recovery Time tODR — 45 — µs G = -100, ±0.5V input overdrive to VDD/2,
VIN 50% point to VOUT 90% point
(Note 3)
Note 1: These parameters were characterized using the circuit in Figure 1-7. In Figure 2-37 and Figure 2-38, there
is an IMD tone at DC, a residual tone at 1 kHz, other IMD tones and clock tones.
2: High gains behave differently; see Section 4.3.3, Offset at Power Up.
3: tODR includes some uncertainty due to clock edge timing.
MCP6V26/7/8
DS25007B-page 6 © 2011 Microchip Technology Inc.
TABLE 1-4: TEMPERATURE SPECIFICATIONS
TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.3V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT =V
DD/2, VL=V
DD/2, RL = 10 kW to VL, CL = 60 pF, and CS = GND (refer to Figure 1-5 and
Figure 1-6).
Parameters Sym Min Typ Max Units Conditions
CS Pull-Down Resistor (MCP6V28)
CS Pull-Down Resistor RPD 35—MΩ
CS Low Specifications (MCP6V28)
CS Logic Threshold, Low VIL VSS —0.3V
DD V
CS Input Current, Low ICSL —5—pA
CS = VSS
CS High Specifications (MCP6V28)
CS Logic Threshold, High VIH 0.7VDD —V
DD V
CS Input Current, High ICSH —V
DD/RPD —pA
CS = VDD
CS Input High,
GND Current per amplifier
ISS —-0.4—µA
CS = VDD, VDD = 2.3V
ISS —-1—µA
CS = VDD, VDD = 5.5V
Amplifier Output Leakage,
CS High
IO_LEAK —20—pA
CS = VDD
CS Dynamic Specifications (MCP6V28)
CS Low to Amplifier Output On
Turn-on Time
tON —450µs
CS Low = VSS+0.3 V, G = +1 V/V,
VOUT = 0.9 VDD/2
CS High to Amplifier Output
High-Z
tOFF —1—µs
CS High = VDD – 0.3 V, G = +1 V/V,
VOUT = 0.1 VDD/2
Internal Hysteresis VHYST —0.2—V
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.3V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +125 °C
Operating Temperature Range TA-40 — +125 °C (Note 1)
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-4x4 DFN θJA —48—°C/W(Note 2)
Thermal Resistance, 8L-MSOP θJA —211—°C/W
Thermal Resistance, 8L-SOIC θJA — 150 — °C/W
Thermal Resistance, 8L-2x3 TDFN θJA —53—°C/W(Note 2)
Note 1: Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C).
2: Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
© 2011 Microchip Technology Inc. DS25007B-page 7
MCP6V26/7/8
1.3 Timing Diagrams
FIGURE 1-1: Amplifier Start Up.
FIGURE 1-2: Offset Correction Settling
Time.
FIGURE 1-3: Output Overdrive Recove ry.
FIGURE 1-4: Chip Select (MCP6V28).
1.4 Test Circuits
The circuits used for the DC and AC tests are shown in
Figure 1-5 and Figure 1-6. Lay the bypass capacitors
out as discussed in Section 4.3.10, Supply Bypass-
ing and Filtering. RN is equal to the parallel combina-
tion of RF and RG to minimize bias current effects.
FIGURE 1-5: AC and DC Test Circuit for
Most Non-Inv erti ng Ga in Cond iti ons .
FIGURE 1-6: AC and DC Test Circuit for
Most Inverting Gain Conditions.
The circuit in Figure 1-7 tests the op amp input’s
dynamic behavior (i.e., IMD, tSTR, tSTL and tODR). The
potentiometer balances the resistor network (VOUT
should equal VREF at DC). The op amp’s common
mode input voltage is VCM =V
IN/2. The error at the
input (VERR) appears at VOUT with a noise gain of
10 V/V.
FIGURE 1-7: Test Circuit for Dynamic
Input Behavior.
VDD
VOS
VOS +50µV
VOS –50µV
tSTR
0V
2.3V to 5.5V
2.3V
VIN
VOS
VOS +50µV
VOS +50µV
tSTL
VIN
VOUT
VDD
VSS
tODR
tODR
VDD/2
VIL
High-Z
tON
VIH
CS
tOFF
VOUT
-2 µA
High-Z
ISS -2 µA
300 µA
1µA
IDD
1µA
300 µA
VDD/5 MΩ
ICS VDD/5 MΩ
5pA
(typical) (typical)
(typical) (typical)
(typical) (typical)
(typical)
(typical)
(typical)
VDD
RGRF
RN
VOUT
VIN
VDD/3
1µF
CLRL
VL
100 nF
RISO
MCP6V2X
U1
VDD
RGRF
RN
VOUT
VDD/3
VIN
1µF
CLRL
VL
100 nF
RISO
MCP6V2X
U1
VDD
VOUT
1µF
CLRL
VL
100 nF
RISO
20.0 kΩ24.9 Ω
20.0 kΩ50Ω
VIN
VREF
0.1%
0.1% 25 turn
20.0 kΩ
20.0 kΩ
0.1%
0.1%
2.49 kΩ2.49 kΩ
MCP6V2X
U1
MCP6V26/7/8
DS25007B-page 8 © 2011 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.1 DC Input Precision
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Offset Voltage Drift.
FIGURE 2-3: Input Offset Voltage
Quadratic Temperature Coefficient.
FIGURE 2-4: Input Offset Voltage vs.
Power Supply Voltage with VCM =V
CML.
FIGURE 2-5: Input Offset Voltage vs.
Power Supply Voltage with VCM =V
CMH.
FIGURE 2-6: Input Offset Voltage vs.
Output Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
5%
10%
15%
20%
25%
30%
35%
40%
-2.0
-1.0
0.0
1.0
2.0
Input Offset Voltage (µV)
Percentage of Occurrences
20 Samples
TA = +25°C
VDD = 2.3V and 5.5V
0%
5%
10%
15%
20%
25%
30%
-50
-40
-30
-20
-10
0
10
20
30
40
50
Input Offset Voltage Drift; TC1 (nV/°C)
Percentage of Occurrences
20 Samples
VDD = 2.3V and 5.5
V
-5
-4
-3
-2
-1
0
1
2
3
4
5
0.00.51.01.52.02.53.03.54.04.55.05.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 2.3
V
VDD = 5.5V
Representative Par
t
© 2011 Microchip Technology Inc. DS25007B-page 9
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-7: Input Offset Voltage vs.
Common Mode Voltage with VDD =2.3V.
FIGURE 2-8: Input Offset Voltage vs.
Common Mode Voltage with VDD =5.5V.
FIGURE 2-9: CMRR.
FIGURE 2-10: PSRR.
FIGURE 2-11: DC Open-Loop Gain.
FIGURE 2-12: CMRR and PSRR vs.
Ambient Temper atu re .
-5
-4
-3
-2
-1
0
1
2
3
4
5
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Input Common Mode Voltage (V)
Input Offset Voltage (µV)
VDD = 2.3V
Representative Part
-40°C
+25°C
+85°C
+125°C
-5
-4
-3
-2
-1
0
1
2
3
4
5
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Common Mode Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
Representative Part
-40°C
+25°C
+85°C
+125°C
0%
5%
10%
15%
20%
25%
30%
35%
-0.5
-0.3
0.0
0.3
0.5
1/CMRR (µV/V)
Percentage of Occurrences
20 Samples
TA = +25°C
VDD = 2.3V
VDD = 5.5V
0%
5%
10%
15%
20%
25%
30%
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
1/PSRR (µV/V)
Percentage of Occurrences
20 Samples
TA = +25°C
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
1/AOL (µV/V)
Percentage of Occurrences
20 Samples
TA = +25°C
VDD = 2.3
V
VDD = 5.5V
120
125
130
135
140
145
150
155
160
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CMRR, PSRR (dB)
PSRR
CMRR
VDD = 5.5
V
VDD = 2.3
V
MCP6V26/7/8
DS25007B-page 10 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-13: DC Open-Loop Gain vs.
Ambient Temperature.
FIGURE 2-14: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA= +85°C.
FIGURE 2-15: Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA= +125°C.
FIGURE 2-16: Input Bias and Offset
Currents vs. Ambient Temperature with
VDD =+5.5V.
FIGURE 2-17: Input Bias Current vs. Input
Voltage (below VSS).
120
125
130
135
140
145
150
155
160
-50-25 0 255075100125
Ambient Temperature (°C)
DC Open-Loop Gain (dB)
VDD = 5.5V
VDD = 2.3V
-100
-50
0
50
100
150
200
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Bias, Offset Currents (pA)
IB
TA = +85°C
VDD = 5.5V
IOS
-400
-200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Bias, Offset Currents (pA)
IB
TA = +125°C
VDD = 5.5V
IOS
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents (A)
VDD = 5.5
V
-IOS
IB
1p
10p
100p
1n
10n
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
© 2011 Microchip Technology Inc. DS25007B-page 11
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.2 Other DC Voltages and Currents
FIGURE 2-18: Input Common Mode
Voltage Headroom (Range) vs. Ambient
Temperature.
FIGURE 2-19: Output Voltage Headroom
vs. Output Current.
FIGURE 2-20: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-21: Output Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-22: Supply Current vs. Power
Supply Voltage.
FIGURE 2-23: Power On Reset Trip
Voltage.
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Common Mode Voltage
Headroom (V)
Lower (VCML – VSS)
Upper ( VCMH – VDD)
1 Wafer Lo
t
10
100
1000
0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom (mV)
VDD – VOH
VDD = 5.5V
VDD = 2.3V
VOL – VSS
0
1
2
3
4
5
6
7
8
9
10
-50-25 0 255075100125
Ambient Temperature (°C)
Output Headroom (mV)
VDD – VOH
VDD = 5.5
V
VOL – VSS
VDD = 2.3V
RL = 10 kΩ
-40
-30
-20
-10
0
10
20
30
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
-40°C
+25°C
+85°C
+125°C
+125°C
+85°C
+25°C
-40°C
0
100
200
300
400
500
600
700
800
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power Supply Voltage (V)
Supply Current (µA/amplifier)
+125°C
+85°C
+25°C
-40°C
0%
5%
10%
15%
20%
25%
30%
35%
40%
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
1.35
POR Trip Voltage (V)
Percentage of Occurrences
820 Samples
1 Wafer Lot
TA = +25°C
MCP6V26/7/8
DS25007B-page 12 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-24: Power On Reset V oltage vs.
Ambient Temperature.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
POR Trip Voltage (V)
© 2011 Microchip Technology Inc. DS25007B-page 13
MCP6V26/7/8
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
2.3 Frequency Response
FIGURE 2-25: CMRR and PSRR vs.
Frequency.
FIGURE 2-26: Open-Loop Gain vs.
Frequency with VDD =2.3V.
FIGURE 2-27: Open-Loop Gain vs.
Frequency with VDD =5.5V.
FIGURE 2-28: Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
FIGURE 2-29: Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
FIGURE 2-30: Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
0
10
20
30
40
50
60
70
80
90
100
110
1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
CMR
R
PSRR+
PSRR-
100 100k
1k 1M10k
-20
-10
0
10
20
30
40
50
60
70
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Open-Loop Gain (dB)
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
| AOL |
∠AOL
1k 10k 100k 1M 10M
VDD = 2.3V
CL = 60 pF
-20
-10
0
10
20
30
40
50
60
70
1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Open-Loop Gain (dB)
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
| AOL |
∠AOL
1k 10k 100k 1M 10M
VDD = 5.5V
CL = 60 pF
1003.0
H
z)
902.5
°
)
u
ct (M
H
V
DD
= 5.5V
GBWP
70
80
2.0
a
rgin (
°
Prod
u
60
70
1.0
.
h
ase M
a
d
width
PM
V
DD
= 2.3V
500.5
P
h
in Ban
d
400.0
-
50
-
25
0
25
50
75
100
125
Ga
50
25
0
25
50
75
100
125
Ambient Temperature (°C)
1204.0
H
z)
100
110
3.0
3.5
°)
u
ct (M
H
80
90
20
2.5
argin (
h
Prod
u
VDD = 5.5V
VDD = 2.3V GBWP
70
80
1.5
2
.
0
h
ase M
n
dwidt
h
50
60
0.5
1.0
P
h
a
in Ba
n
PM
400.0
0
.5
0
.0
0
.5
.0
.5
2
.0
2
.5
3
.0
3
.5
4
.0
4
.5
5
.0
5
.5
6
.0
G
a
-
0
0
0
1
1
2
2
3
3
4
4
5
5
6
Common Mode Input Voltage (V)
1204.0
H
z)
100
110
3.0
3.5
°
)
u
ct (M
H
80
90
2.5
a
rgin (
°
Prod
u
VDD = 5.5V
VDD = 2.3V PM
70
80
1.5
.
h
ase M
a
d
width
50
60
1.0
P
h
i
n Ban
d
GBWP
40
50
0.0
Ga
i
.
.
.
.
.
.
.
.
.
.
.
.
Output Voltage (V)
MCP6V26/7/8
DS25007B-page 14 © 2011 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +2.3V to 5.5V, VSS = GND, VCM =V
DD/3, VOUT =V
DD/2,
VL=V
DD/2, RL=10kΩ to VL, CL = 60 pF and CS = GND.
FIGURE 2-31: Closed-Loop Output
Impedance vs. Frequency with VDD =2.3V.
FIGURE 2-32: Closed-Loop Output
Impedance vs. Frequency with VDD =5.5V.
FIGURE 2-33: Channel-to-Channel
Separation vs . Frequ enc y.
FIGURE 2-34: Maximum Output Voltage
Swing vs. Frequency.
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.0E+05 1.0E+06 1.0E+07 1.0E+08
Frequency (Hz)
Closed-Loop
Output Impedance (Ω)
VDD = 2.3
V
100k 1M 10M 100M
1
10
100
1k
10k
G = 1 V/V
G = 11 V/V
G = 101 V/V
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.0E+05 1.0E+06 1.0E+07 1.0E+08
Frequency (Hz)
VDD = 2.3V
100k 1M 10M 100M
1
10
100
1k
10k
G = 1 V/V
G = 11 V/V
G = 101 V/V 0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
VDD = 5.5V
VDD = 2.3V
1k 10k 100k 1M