©
1990, 1993, 1994
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
Description
The
µ
PD43256B is a high speed, low power, and 262, 144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available (L, LL, A, and B versions). And A and B versions are wide voltage operations.
The
µ
PD43256B is packed in 28-pin plastic DIP, 28-pin plastic SOP and 28-pin plastic TSOP (I).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Wide voltage range (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• 2 V data retention
• OE input for easy application
Access time Operating Operating Standby
Data retention
Part number ns (MAX.) supply voltage temperature supply current
supply current
Note 1
V°C
µ
A (MAX.)
µ
A (MAX.)
µ
PD43256B-L 70, 85 4.5 to 5.5 0 to 70 50 3
µ
PD43256B-LL 70, 85 15 2
µ
PD43256B-A
85, 100
Note 2
, 120
Note 2
3.0 to 5.5
µ
PD43256B-BNote 2 100, 120, 150 2.7 to 5.5
Notes 1. TA ≤ 40 ˚C, VCC = 3 V
2. Access time : 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
Version X and P
This data sheet can be applied to the version X and P. Each version is identified with its lot number. Letter X in
the fifth character position in a lot number signifies version X, letter P, version P.
The information in this document is subject to change without notice.
The mark shows major revised points.
Document No. M10770EJ9V0DS00 (9th edition)
Date Published May 1997 N
Printed in Japan
D43256B
JAPAN
Lot number
2
µ
PD43256B
Ordering Information
Access time Operating Operating
Part number Package ns (MAX.) supply voltage temperature Remark
V˚C
µ
PD43256BCZ-70L 28-pin plastic 70 4.5 to 5.5 0 to 70 L Version
µ
PD43256BCZ-85L DIP (600 mil) 85
µ
PD43256BCZ-70LL 70 LL Version
µ
PD43256BCZ-85LL 85
µ
PD43256BGU-70L 28-pin plastic 70 L Version
µ
PD43256BGU-85L SOP (450 mil) 85
µ
PD43256BGU-70LL 70 LL Version
µ
PD43256BGU-85LL 85
µ
PD43256BGU-A85 85 3.0 to 5.5 A Version
µ
PD43256BGU-A10 100
µ
PD43256BGU-A12 120
µ
PD43256BGU-B10 100 2.7 to 5.5 B Version
µ
PD43256BGU-B12 120
µ
PD43256BGU-B15 150
µ
PD43256BGW-70LL-9JL 28-pin plastic 70 4.5 to 5.5 LL Version
µ
PD43256BGW-85LL-9JL TSOP (I) 85
µ
PD43256BGW-A85-9JL (8 × 13.4 mm) 85 3.0 to 5.5 A Version
µ
PD43256BGW-A10-9JL (Normal bent) 100
µ
PD43256BGW-A12-9JL 120
µ
PD43256BGW-B10-9JL 100 2.7 to 5.5 B Version
µ
PD43256BGW-B12-9JL 120
µ
PD43256BGW-B15-9JL 150
µ
PD43256BGW-70LL-9KL 28-pin plastic 70 4.5 to 5.5 LL Version
µ
PD43256BGW-85LL-9KL TSOP (I) 85
µ
PD43256BGW-A85-9KL (8 × 13.4 mm) 85 3.0 to 5.5 A Version
µ
PD43256BGW-A10-9KL (Reverse bent) 100
µ
PD43256BGW-A12-9KL 120
µ
PD43256BGW-B10-9KL 100 2.7 to 5.5 B Version
µ
PD43256BGW-B12-9KL 120
µ
PD43256BGW-B15-9KL 150
3
µ
PD43256B
Pin Configuration (Marking Side)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
28-pin plastic DIP (600 mil)
PD43256BCZ
28-pin plastic SOP (450 mil)
PD43256BGU
µ
µ
A0 - A14 : Address inputs
I/O1 - I/O8: Data inputs/outputs
CS : Chip Select
WE : Write Enable
OE : Output Enable
VCC : Power supply
GND : Ground
4
µ
PD43256B
1
28-pin plastic TSOP (I) (8 × 13.4 mm)
(Normal bent)
PD43256BGW-9JL
µ
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
OE
A11
A9
A8
A13
WE
V
CC
A14
A12
A7
A6
A5
A4
A3
1
28-pin plastic TSOP (I) (8 × 13.4 mm)
(Reverse bent)
PD43256BGW-9KL
µ
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
OE
A11
A9
A8
A13
WE
V
CC
A14
A12
A7
A6
A5
A4
A3
5
µ
PD43256B
Block Diagram
A0
|
A14
I/O1
|
I/O8
Address buffer
Row decoder
Memory cell array
262,144 bits
Input data
controller Sense/Switch
Column decoder
Address buffer
Output data
controller
CS
OE
VCC
WE
GND
Truth Table
CS OE WE Mode I/O Supply current
H×× Not selected High impedance ISB
L H H Output disable ICCA
L×L Write DIN
L L H Read DOUT
Remark ×: Don’t care
6
µ
PD43256B
Electrical Characteristics
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply voltage VCC –0.5Note to +7.0 V
Input/Output voltage VT–0.5Note to VCC + 0.5 V
Operating ambient temperature TA0 to 70 ˚C
Storage temperature Tstg –55 to +125 ˚C
Note –3.0 V (MIN.) (Pulse width 50 ns)
Caution Exposing the device to stress above those listed in absolute maximum ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational sections of this characteristics. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol
µ
PD43256B-L
µ
PD43256B-A
µ
PD43256B-B Unit
µ
PD43256B-LL
MIN. MAX. MIN. MAX. MIN. MAX.
Supply voltage VCC 4.5 5.5 3.0 5.5 2.7 5.5 V
High level input voltage VIH 2.2
VCC + 0.5
2.2
VCC + 0.5
2.2
VCC + 0.5
V
Low level input voltage VIL –0.3Note +0.8 –0.3Note +0.5 –0.3Note +0.5 V
Operating ambient temperature TA070070070˚C
Note –3.0 V (MIN.) (Pulse width 50 ns)
7
µ
PD43256B
DC Characteristics (Recommended operating conditions unless otherwise noted) (1/2)
Parameter Symbol Test conditions
µ
PD43256B-L
µ
PD43256B-LL Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0
µ
A
I/O leakage current ILO VI/O = 0 V to VCC –1.0 +1.0 –1.0 +1.0
µ
A
OE = VIH or CS = VIH or WE = VIL
Operating supply current ICCA1 CS = VIL, Minimum cycle time, 45 45 mA
II/O = 0 mA
ICCA2 CS = VIL, II/O = 0 mA 10 10
ICCA3 CS ≤ 0.2 V, Cycle = 1 MHz, 10 10
II/O = 0 mA
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
Standby supply current ISB CS = VIH 33mA
ISB1 CS ≥ VCC – 0.2 V 1.0 50 0.5 15
µ
A
High level output voltage VOH1 IOH = –1.0 mA 2.4 2.4 V
VOH2 IOH = –0.1 mA
VCC–0.5 VCC–0.5
Low level output voltage VOL IOL = 2.1 mA 0.4 0.4 V
Remarks 1. VIN: Input voltage
2. These DC Characteristics are in common regardless of package types.
8
µ
PD43256B
DC Characteristics (Recommended operating conditions unless otherwise noted) (2/2)
Parameter Symbol Test conditions
µ
PD43256B-A
µ
PD43256B-B Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage current ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0
µ
A
I/O leakage current ILO VI/O = 0 V to VCC –1.0 +1.0 –1.0 +1.0
µ
A
CS = VIH or WE = VIL or OE = VIH
Operating supply current ICCA1 CS = VIL,
µ
PD43256B-A85 45 — mA
Minimum cycle time,
µ
PD43256B-A10
II/O = 0 mA
µ
PD43256B-A12
µ
PD43256B-B10 — 45
µ
PD43256B-B12
µ
PD43256B-B15
VCC ≤ 3.3 V — 20
ICCA2 CS = VIL, II/O = 0 mA 10 10
VCC ≤ 3.3 V — 5
ICCA3 CS ≤ 0.2 V, Cycle = 1 MHz, 10 10
II/O = 0 mA, VIL ≤ 0.2 V,
VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V — 5
Standby supply current ISB CS = VIH 33mA
VCC ≤ 3.3 V — 2
ISB1 CS ≥ VCC – 0.2 V 0.5 15 0.5 15
µ
A
VCC ≤ 3.3 V — 0.5 10
High level output voltage VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V 2.4 2.4 V
IOH = –0.5 mA, VCC < 4.5 V 2.4 2.4
VOH2 IOH = –0.1 mA — —
IOH = –0.02 mA
VCC–0.1 VCC–0.1
Low level output voltage VOL IOL = 2.1 mA, VCC ≥ 4.5 V 0.4 0.4 V
IOL = 1.0 mA, VCC < 4.5 V 0.4 0.4
VOL1 IOL = 0.02 mA 0.1 0.1
Remarks 1. VIN: Input voltage
2. These DC characteristics are in common regardless of package types.
Capacitance (TA = 25 ˚C, f = 1 MHz)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Input capacitance CIN VIN = 0 V 5 pF
Input/Output capacitance CI/O VI/O = 0 V 8 pF
Remarks 1. VIN: Input voltage
2. These parameters are periodically sampled and not 100 % tested.
9
µ
PD43256B
AC Characteristics (Recommended operating conditions unless otherwise noted)
AC Test Conditions
Input waveform (Rise/fall time ≤ 5 ns)
Input pulse levels
0.8 V to 2.2 V:
µ
PD43256B-L, 43256B-LL
0.5 V to 2.2 V:
µ
PD43256B-A, 43256B-B
1.5 V 1.5 V
Test points
Output waveform
1.5 V 1.5 V
Test points
Output load
µ
PD43256B-A, 43256B-B : 1TTL + 100 pF
µ
PD43256B-L, 43256B-LL:
AC characteristics with notes should be measured with the output load shown in
Figure 1 and Figure 2.
Figure 1 Figure 2
(For tAA, tACS, tOE, tOH) (For tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
I/O (Output)
1.8 kΩ
100 pF
C
L
990 Ω
+5 V
I/O (Output)
1.8 kΩ
5 pF
CL
990 Ω
Remark CL includes capacitances of the probe and jig, and stray capacitances.
10
µ
PD43256B
Read Cycle (1/2)
VCC ≥ 4.5 V
µ
PD43256B-85
Parameter Symbol
µ
PD43256B-70
µ
PD43256B-A85/A10/A12
Unit
Condition
µ
PD43256B-B10/B12/B15
MIN. MAX. MIN. MAX.
Read cycle time tRC 70 85 ns
Address access time tAA 70 85 ns Note 1
CS access time tACS 70 85 ns
OE access time tOE 35 40 ns
Output hold from address change
tOH 10 10 ns
CS to output in low impedance tCLZ 10 10 ns Note 2
OE to output in low impedance tOLZ 55ns
CS to output in high impedance tCHZ 30 30 ns
OE to output in high impedance tOHZ 30 30 ns
Notes 1. See the output load shown in Figure 1 except for
µ
PD43256B-A, 43256B-B.
2. See the output load shown in Figure 2 except for
µ
PD43256B-A, 43256B-B.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
VCC ≥ 3.0 V VCC ≥ 2.7 V
Parameter
Symbol
µ
PD43256B-A85
µ
PD43256B-A10
µ
PD43256B-A12
µ
PD43256B-B10
µ
PD43256B-B12
µ
PD43256B-B15
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time tRC
85 100 120 100 120 150 ns
Address access time tAA
85 100 120 100 120 150 ns
Note
CS access time tACS
85 100 120 100 120 150 ns
OE access time tOE
50 60 60 60 60 70 ns
Output hold from address change tOH
10 10 10 10 10 10 ns
CS to output in low impedance tCLZ
10 10 10 10 10 10 ns
OE to output in low impedance tOLZ
555555ns
CS to output in high impedance tCHZ
35 35 40 35 40 50 ns
OE to output in high impedance tOHZ
35 35 40 35 40 50 ns
Note Loading condition is 1TTL + 100 pF.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Con-
dition
11
µ
PD43256B
Read Cycle Timing Chart
Remark In read cycle, WE should be fixed to high level.
t
RC
t
AA
t
ACS
t
CLZ
t
OE
t
OLZ
t
OHZ
t
CHZ
t
OH
Address (Input)
CS (Input)
OE (Input)
I/O (Output) High impedance High impedance
Data out
12
µ
PD43256B
Write Cycle (1/2)
VCC ≥ 4.5 V
µ
PD43256B-85
Parameter Symbol
µ
PD43256B-70
µ
PD43256B-A85/A10/A12
Unit
Condition
µ
PD43256B-B10/B12/B15
MIN. MAX. MIN. MAX.
Write cycle time tWC 70 85 ns
CS to end of write tCW 50 70 ns
Address valid to end of write tAW 50 70 ns
Write pulse width tWP 55 60 ns
Data valid to end of write tDW 30 35 ns
Data hold time tDH 00ns
Address setup time tAS 00ns
Write recovery time tWR 00ns
WE to output in high impedance tWHZ 30 30 ns Note
Output active from end of write tOW 10 10 ns
Note See the output load shown in Figure 2 except for
µ
PD43256B-A, 43256B-B.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
VCC ≥ 3.0 V VCC ≥ 2.7 V
Parameter
Symbol
µ
PD43256B-A85
µ
PD43256B-A10
µ
PD43256B-A12
µ
PD43256B-B10
µ
PD43256B-B12
µ
PD43256B-B15
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time tWC
85 100 120 100 120 150 ns
CS to end of write tCW
70 70 90 70 90 100 ns
Address valid to end of write tAW
70 70 90 70 90 100 ns
Write pulse width tWP
60 60 80 60 80 90 ns
Data valid to end of write tDW
60 60 70 60 70 80 ns
Data hold time tDH
000000ns
Address setup time tAS
000000ns
Write recovery time tWR
000000ns
WE to output in high impedance tWHZ
30 35 40 35 40 50 ns
Note
Output active from end of write tOW
10 10 10 10 10 10 ns
Note Loading condition is 1TTL + 100 pF.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Con-
dition
13
µ
PD43256B
Write Cycle Timing Chart 1 (WE Controlled)
t
WC
t
CW
t
AW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out High
impe-
dance
High
impe-
dance
Data in Indefinite data out
Address (Input)
CS (Input)
WE (Input)
I/O (Input/Output)
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level CS and a low level WE.
2. When WE is at low level, the I/O pins are always high impedance. When WE is at high level,
read operation is executed. Therefore OE should be at high level to make the I/O pins high
impedance.
3. If CS changes to low level at the same time or after the change of WE to low level, the I/O pins
will remain high impedance state.
14
µ
PD43256B
Write Cycle Timing Chart 2 (CS Controlled)
t
WC
t
AS
t
CW
t
AW
t
WP
t
WR
t
DW
t
DH
Data In
High impedance
Address (Input)
CS (Input)
WE (Input)
I/O (Input) High
impedance
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remark Write operation is done during the overlap time of a low level CS and a low level WE.
15
µ
PD43256B
Low VCC Data Retention Characteristics
L Version (
µ
PD43256B-L: TA = 0 to 70 ˚C)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Data retention supply voltage VCCDR CS ≥ VCC – 0.2 V 2.0 5.5 V
Data retention supply current ICCDR VCC = 3.0 V, CS ≥ VCC – 0.2 V 0.5 20Note
µ
A
Chip deselection to data tCDR 0ns
retention mode
Operation recovery time tR5ms
Note 3
µ
A (TA ≤ 40 ˚C)
LL Version (
µ
PD43256B-LL: TA = 0 to 70 ˚C)
A Version (
µ
PD43256B-A: TA = 0 to 70 ˚C)
B Version (
µ
PD43256B-B: TA = 0 to 70 ˚C)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Data retention supply voltage
VCCDR CS ≥ VCC – 0.2 V 2.0 5.5 V
Data retention supply current
ICCDR VCC = 3.0 V, CS ≥ VCC – 0.2 V 0.5 7Note
µ
A
Chip deselection to data tCDR 0ns
retention mode
Operation recovery time tR5ms
Note 2
µ
A (TA ≤ 40 ˚C), 1
µ
A (TA ≤ 25 ˚C)
16
µ
PD43256B
Data Retention Timing Chart
t
CDR
Data retention mode t
R
5.0 V
4.5 V
V
CCDR
V
IL
(MAX.)
GND
Note
CS ≥ V
CC
– 0.2 V
V
IH
(MIN.)
CS
V
CC
Note A Version: 3.0 V, B Version: 2.7 V
Remark The other pins (address, OE, WE, I/Os) can be in high impedance state.
17
µ
PD43256B
Package Drawings
28 PIN PLASTIC DIP (600 mil)
ITEM MILLIMETERS INCHES
A
B
C
F
G
H
I
J
K
38.10 MAX.
2.54 (T.P.)
3.6±0.3
0.51 MIN.
4.31 MAX.
2.54 MAX.
L
0.25
15.24 (T.P.)
5.72 MAX.
13.2
N
1.2 MIN.
1.500 MAX.
0.100 MAX.
0.047 MIN.
0.142±0.012
0.020 MIN.
0.170 MAX.
0.226 MAX.
0.600 (T.P.)
0.520
0.01
0.100 (T.P.)
P28C-100-600A1-1
D 0.50±0.10 0.020
M 0.25 0.010
+0.10
–0.05
R 0 ~ 15 °
0 ~ 15°
+0.004
–0.005
+0.004
–0.003
NOTES
Each lead centerline is located within 0.25 mm (0.01 inch)
of its true position (T.P.) at maximum material condition.
Item "K" to center of leads when formed parallel.
1)
2)
28
1
15
14
A
M R
K
L
B
I
J
G
H
C
F
D
M
N
18
µ
PD43256B
28 15
1 14
N
C
D M
M
I
A H
P
F
GE
B L
J
K
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
28 PIN PLASTIC SOP (450 mil)
P28GU-50-450A-1
ITEM MILLIMETERS INCHES
A
B
C
D
E
F
G
H
I
J
19.05 MAX.
1.27 (T.P.)
3.0 MAX.
2.55±0.1
11.8±0.3
1.27 MAX.
K
L
0.12
0.7±0.2
1.7±0.2
8.4±0.1
0.20
M 0.10
0.40±0.10
0.2±0.1
N
+0.07
–0.03
0.750 MAX.
0.050 MAX.
0.016
0.008±0.004
0.119 MAX.
0.100
0.465
0.331
0.067±0.008
0.008
0.028
0.005
0.004
+0.008
–0.009
0.050 (T.P.)
P 5°±5° 5°±5°
+0.004
–0.005
+0.005
–0.004
+0.012
–0.013
+0.004
–0.005
+0.003
–0.002
detail of lead end
19
µ
PD43256B
28PIN PLASTIC TSOP ( I ) (8×13.4)
ITEM MILLIMETERS INCHES
NOTE
(1) Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
P28GW-55-9JL-1
M 0.08 0.003
N 0.10 0.004
H 12.4±0.2 0.488±0.008
I 11.8±0.1 0.465
+0.004
–0.005
J 0.8±0.2 0.031
+0.009
–0.008
S 1.2 MAX. 0.048 MAX.
A 8.0±0.1 0.315±0.004
B 0.6 MAX. 0.024 MAX.
C 0.55 (T.P.) 0.022 (T.P.)
G 1.0 0.039
K 0.145 0.006±0.001
L 0.5±0.1 0.020
+0.004
–0.005
P 13.4±0.2 0.528
+0.008
–0.009
Q 0.1±0.05 0.004±0.002
R 3 °
+7°
–3° 3°+7°
–3°
D 0.22 0.009±0.003
+0.08
–0.07
M
detail of lead end
Q R
G
B
C
D M
J
N
L
K
+0.025
–0.015
1
14
28
15
S
A
P
I
H
(2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX. 
<0.331 inch MAX.>)
20
µ
PD43256B
28PIN PLASTIC TSOP ( I ) (8×13.4)
ITEM MILLIMETERS INCHES
NOTE
P28GW-55-9KL-1
M 0.08 0.003
N 0.10 0.004
H 12.4±0.2 0.488±0.008
I 11.8±0.1 0.465
+0.004
–0.005
J 0.8±0.2 0.031
+0.009
–0.008
S 1.2 MAX. 0.048 MAX.
A 8.0±0.1 0.315±0.004
B 0.6 MAX. 0.024 MAX.
C 0.55 (T.P.) 0.022 (T.P.)
G 1.0 0.039
K 0.145 0.006±0.001
L 0.5±0.1 0.020
+0.004
–0.005
P 13.4±0.2 0.528
+0.008
–0.009
Q 0.1±0.05 0.004±0.002
R 3 °
+7°
–3° 3°+7°
–3°
D 0.22 0.009±0.003
+0.08
–0.07
detail of lead end
R
Q
B
C
D
J
N
L
K
+0.025
–0.015
M
M
G
1
14
28
15 S
A
P
I
H
(1) Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
(2) "A" excludes mold flash. (Includes mold flash : 8.4mm MAX. 
<0.331 inch MAX.>)
21
µ
PD43256B
Recommended Soldering Conditions
The following conditions (See table below) must be met when soldering
µ
PD43256B. For more details, refer
to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case soldering is done
under different conditions.
Types of Surface Mount Device
µ
PD43256BGU: 28-pin plastic SOP (450 mil)
µ
PD43256BGW-9JL: 28-pin plastic TSOP (I) (8 × 13.4 mm) (Normal bent)
µ
PD43256BGW-9KL: 28-pin plastic TSOP (I) (8 × 13.4 mm) (Reverse bent)
Please consult with our sales offices.
Type of Through Hole Mount Device
µ
PD43256BCZ: 28-pin plastic DIP (600 mil)
Soldering process Soldering conditions
Wave soldering Solder temperature: 260 ˚C or below,
(only to leads) Flow time: 10 seconds or below
Partial heating method Terminal temperature: 300 ˚C or below,
Time: 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
22
µ
PD43256B
[MEMO]
23
µ
PD43256B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
2
µ
PD43256B
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5