af FEATURES TECHNOLOGY # Sample Rate: 100ksps B Single 5V Supply = Bipolar Input Range: +10V = Power Dissipation: 55mW Typ # Integral Nonlinearity: +2.0LSB Max @ Guaranteed No Missing Codes H Signal-to-Noise Ratio: 86dB Typ = Operates with Internal or External Reference # Internal Synchronized Clock # 28-Pin 0.3 PDIP, SSOP and SW Packages |mproved 2nd Source to ADS/805 and AD9/6 APPLICATIONS Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing LINEAR soos 16-Bit, 10O0ksps, sampling ADC DESCRIPTION The LTC1605 is a 100ksps, sampling 16-bit A/D con- verter that draws only 55mW (typical) from a single 5V supply. This easy-to-use device includes sample-and- hold, precision reference, switched capacitor successive approximation A/D and trimmed internal clock. The LTC1605s input range is an industry standard +1 OV. Maximum DC specs include + 2.0LSB INL and 16-bits no missing codes over temperature. An external reference can be used if greater accuracy over temperature is needed. The ADC has a microprocessor compatible, 16-bit or two byte parallel output port. A convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. FLTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION Low Power, 1D0kHz, 16-Bit Sampling ADC on 5V Supply Typical INL Gurve 5V . 27 as aa Voic Vana +10y 2000 67013 157022, 16-BIT 10uF O4pF aa t 16-BIT SAMPLING ADG INPUT DIS TO DO OR 2 BYTE PARALLEL 33.2Kk CAP BUSY 2.2pF. / \ BUFFER cs CONTROL LOGIC AND TIMING RIC REF Ak w| REFERENGE BYTE 2.DuF AGNDI AGND2 DGND Hh. He 1605 +TAOT tif F Bus 0 16384 32768 CODE 49152 65535 DIGITAL CONTROL SIGNALS 1605- TAG LY WieLTC 1605 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Notes 1, 2) TOP VIEW ORDER PART va veseseeeceseeeneesneesssseensesneesceneesneetaescesneeseesneesseneesneenes Vv al NUMBER DIG 10 VANA -.-----2ccescecceccceceeseeseesecoeessententecstenseneeaees 0.3V vin 11] 128] Voig VDIG -eseccocececeseccescecescesescecesssesessessssseseseseessesensecenseneaee iV AGNDI [2 | 27] Vana LTC1605ACG Ground Voltage Difference rEF [3] 26] BUSY LTC1605ACN DGND, AGND1 and AGND2 ....... ee eeeeeeeeees +0.3V car [4] 2s] cs LTC1605ACSW Analog Inputs (Note 3) aanoe [| 24] BG LTC1605AIG VIN svsssntvsetnseetnseetnetennetetnetntnetetetntee #25y | sews Le es] eve | LTC1605AIN (| Vana + 0.3V to AGND? - 0.3V - - LTC1605AISW REF .......seseesesessecessesseceeeesees Indefinite Short to AGND2 ow [3 0] 02 LTC1605CG Momentary Short to Vana ot fra ral ps LTC1605CN Digital Input Voltage (Note 4) ........... Vg 0.3V to 10V bio fi Fa] v4 LIC16050SW Digital Output Voltage........ Vpgnp 0.3V to Vpic + 0.3V no [i FZ] os LTC1605IG Power Dissipation.............cccssssssessesessesesseesesees 500mW pe [73] 16] D6 LTCT60SIN Operating Ambient Temperature Range peno [14] 15] D7 LTCI605ISW LTC1605C 0... esceesecsesseseesseeseeseseeeeeseees 0C to 70C G PACKAGE LT C1605 0... eeeeceestescsseseeseesteseseeeeeaes 40C to 85C 26-LEAD PLASTIC SSOP Storage Temperature Range ................. 65C to 150C OM EADPHIP OSLEAD PLASTIC 80 WIDE Lead Temperature (Soldering, 10 sec)... 300C Tiyay = 125C, 8 a = 95C/W (6) Timax = 125C, By, = 130 CAV (N) Tymax = 125C, 8 ya = 130 AW (SW) Consult factory for Military grade parts. CONVERTER CHARACTERISTICS With external reference (Notes 5, 6). LTC1605 LTC1605A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resolution e 16 16 Bits No Missing Codes e 15 16 Bits Transition Noise 1.0 1.0 LSB Integral Linearity Error (Nate 7) e +3 +2 LSB Bipolar Zero Error Ext. Reference = 2.5V (Note 8) e +10 +10 mv Bipolar Zero Error Drift +2 +2 ppm/C Full-Scale Error Drift +7 +5 ppm? Full-Scale Error Ext. Reference = 2.5V (Notes 12, 13) e +0.50 +0.25 % Full-Scale Error Drift Ext. Reference = 2.5V +2 +2 ppm? Power Supply Sensitivity Vana = Voie = Yop Vpp = 5V 45% (Note 9) +8 +8 LSB 2 LY WineLTC 1605 ANALOG INPUT ote 5) LTC1605/LTC1605A SYMBOL | PARAMETER CONDITIONS MIN TYP MAX UNITS Vin Analog Input Range (Note 9) 475V < Vana < 5.25V, 4.75V < Voie < 5.25V e +10 V liny Analog Input Leakage Current CS = High e +1 LA Cin Analog Input Capacitance 10 pF Rin Analog Input Impedance 20 kQ DYNAMIC ACCURACY (notess, 14) LTC1605/LTC1605A SYMBOL | PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N + D) | Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal (Note 14) 87.5 dB 10kHz Input Signal 87 dB 20kHz, -60dB Input Signal 30 dB THD Total Harmonic Distortion 1kHz Input Signal, First 5 Harmonics - 102 dB 10kHz Input Signal, First 5 Harmonics -94 dB Peak Harmonic or Spurious Noise 1kHz Input Signal -102 dB 10kHz Input Signal 94 dB Full-Power Bandwidth (Note 15) 275 kHz Aperture Delay 40 ns Aperture Jitter Sufficient to Meet AC Specs Transient Response Full-Scale Step (Note 9) 2 ps Overvoltage Recovery (Note 16) 150 ns INTERNAL REFERENCE CHARACTERISTICS notes) LTC1605/LTC1605A PARAMETER CONDITIONS MIN TYP MAX UNITS Veer Output Voltage lout =9 @| 2470 2.500 2.520 V Vacr Output Tempco laut = 9 +5 poms Internal Reference Source Current 1 LA External Reference Voltage for Specified Linearity | (Notes 9, 10) 2.30 2.50 2.70 V External Reference Current Drain Ext. Reference = 2.5 (Note 9) e 100 LA CAP Output Voltage lout =9 2.50 V DIGITAL INPUTS AND DIGITAL OUTPUTS notes) LTC1605/LTC1605A SYMBOL | PARAMETER CONDITIONS MIN TYP MAX UNITS Vin High Level Input Voltage Vop = 6.25V @, 24 V VIL Low Level Input Voltage Vop = 4.75V e 0.8 V lin Digital Input Current Vin = OV to Vpp e +10 LA Gin Digital Input Capacitance 5 pF Vou High Level Output Voltage Vpp = 4.75 Iq =-10pA 45 V In=-200uA | @) 4.0 Vv Var Low Level Output Voltage Vpp = 4.75 Iq = 160nA 0.05 V Iq = 1.6mA e 0.10 04 Vv LY WieLTC 1605 DIGITAL INPUTS AND DIGITAL OUTPUTS | (oie 5) LTC1605/LTC1605A SYMBOL | PARAMETER CONDITIONS MIN TYP MAX UNITS loz Hi-Z Output Leakage D15 to DO Vout = OV to Vpp. CS High e +10 pA Coz Hi-Z Output Capacitance D15 to DO CS High (Note 9) e 15 pF Isnuace | Output Source Current Vour = OV -10 mA Isink Output Sink Current Vour = Yop 10 mA TIMING CHARACTERISTICS (notes) LTC1605/LTC1605A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fsampLemax) | Maximum Sampling Frequency e) 100 kHz teony Conversion Time e ps taco Acquisition Time e ps ty Convert Pulse Width (Note 11) e 40 ns te Data Valid Delay After R/CL (Note 9) e 8 MS ts BUSY Delay from R/CL C, = 50pF e 65 ns t BUSY Low 8 US ts BUSY Delay After End of Conversion 220 ns tg Aperture Delay 40 ns t7 Bus Relinquish Time e 10 35 83 ns tg BUSY Delay After Data Valid e 50 200 ns tg Previous Data Valid After R/CL 74 us to RIC to GS Setup Time (Notes 9, 10) 10 ns ty Time Between Conversions 10 ps tye Bus Access and Byte Delay (Notes 9, 10) 10 83 ns POWER REQUIREMENTS nies) LTC1605/LTC1605A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Vop Positive Supply Voltage (Notes 9, 10) 4.75 5.25 Vv Ipp Positive Supply Current e 11 16 mA Pois Power Dissipation 55 80 mW The @ indicates specifications which apply over the full operating temperature range all other limits and typicals Ty = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together (unless otherwise noted). Note 3: When these pin voltages are taken below ground or above Vana = Voie = Vpp. they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below ground or above Vpp without latch-up. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 90mA below ground without latchup. These pins are not clamped to Vpp. Note 5: Vpp = 5, fganp_e = 190KHz, t, = t; = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a Viy input with respect to ground. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from 0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 11111111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. A LY WineLTC 1605 ELECTRICAL CHARACTERISTICS Note 11: With CS low the falling R/C edge starts a conversion. If R/C returns high at a critical point during the conversion it can create small errors. For best results ensure that R/C returns high within 3ps after the start of the conversion. Note 12: As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. Note 13: Full-scale error is the worst-case of -FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. Note 14: All specifications in dB are referred to a full-scale +10V input. Note 15: Full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60dB or 10 bits of accuracy. Note 16: Recovers to specified performance after (2 * FS) input overvoltage. TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage Supply Current vs Temperature Change in CAP Voltage vs Load Current 12.5 12.0 0.05 tsamp_e = 1OOkHZ tsampLe = 100kHz 0.04 = 0.03 12.0 z SOM = = 115 = ont Ens = ~~ = 0 a m= _ SL a 11.0 511.0 =o a = 3 -0.03 = 3 = 0.04 & 10.5 wu o 0.05 a = 105 = -0.06 w - 10.0 S GS Bee -0.09 9.5 10.0 -0.10 450 4.75 5.00 525 5.50 50 -25 0 2 50 75 100 -80 -70 -60 -50 -40 -30 -20 -10 0 10 LOAD CURRENT (mA SUPPLY VOLTAGE (} TEMPERATURE (C) (mA) 1605 + TPLO1 Typical INL Curve INL (LSBs) -1.0 -1.5 -2.0 9 16384 32768 49152 65535 CODE 1605+ TPOOd 185 + TPOO2 Typical DNL Curve DNL (LSBs) oS 9 16384 32768 CODE 49152 65535 105" TPOOS W05*TPEOS Power Supply Feedthrough vs Ripple Frequency | nm o | ww So | 1 1 i a ao | 1 1 I on oa | { 1 1 4 | a So | 1 1 POWER SUPPLY FEEDTHROUGH (dB) I ~ = | I I 1 10 6100 Tk 10k RIPPLE FREQUENCY (Hz) 100k 1M 1605+ TPCOG LY WieLTC 1605 TYPICAL PERFORMANCE CHARACTERISTICS LTC1605 Nonaveraged 4096 Point FFT Plot 0 -10 -20 isampLe = 100kHz 30 fin = 1kHz SINAD = 87.5d0B I _ 2 THD = -101.7dB dB) = -50 I n a MAGNITUDE [ol om oo I o So -100 -110 -120 130 - - 0 5 10 15 20 FREQUENCY (KHz) SINAD vs Input Frequency SINAD (dB) 1 10 100 INPUT FREQUENCY (kHz) 1605 TPLOB 25 30 35 A0 AS 50 1605 *TPOO? Total Harmonic Distortion vs Input Frequency I ~ 2S | x = 100 TOTAL HARMONIC DISTORTION (dB) 8 -110 1 10 100 INPUT FREQUENGY' ( kHz} 1605 + TPCOS PIN FUNCTIONS Vin (Pin 1): Analog Input. Connect through a 200 resistor to the analog input. Full-scale input range is +10V. AGND1 (Pin 2): Analog Ground. Tie to analog ground plane. REF (Pin 3): 2.5V Reference Output. Bypass with 2.2uF tantalum capacitor. Can be driven with an external refer- ence. CAP (Pin 4): Reference Buffer Output. Bypass with 2.2uF tantalum capacitor. AGND2 (Pin 5): Analog Ground. Tie to analog ground plane. D15 to D (Pins 6 to 13): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. DGND (Pin 14): Digital Ground. D7 to DO (Pins 15 to 22): Three-State Data Outputs. Hi-Z state when CS is high or when R/C is low. BYTE (Pin 23): Byte Select. With BYTE low, data will be output with Pin 6 (D15) being the MSB and Pin 22 (D0) being the LSB. With BYTE high the upper eight bits and the lower eight bits will be switched. The MSB is output 6 LY WineLTC 1605 PIN FUNCTIONS on Pin 15 and bit 8 is output on Pin 22. Bit7is outputon BUSY (Pin 26): Output Shows Converter Status. Itis low Pin 6 and the LSB is output on Pin 13. when aconversionis in progress. Data valid on the rising R/C (Pin 24): Read/Convert Input. With CS low, a falling edge of BUSY. CS or R/C must be high when BUSY rises edge on R/C puts the internal sample-and-hold into the or another conversion will start without time for signal hold state and starts a conversion. With CS low, a rising acquisition. edge on R/C enables the output data bits. Vana (Pin 27): 5V Analog Supply. Bypass to ground with CS (Pin 25): Chip Select. Internally ORd with R/C. With 2 0.1pF ceramic and a 10pF tantalum capacitor. R/C low, a falling edge on CS will initiate a conversion. Vpjg (Pin 28): 5V Digital Supply. Connect directly to Pin With R/C high, a falling edge on CS willenable the output = 27. data. Load Circuit for Access Timing Load Circuit for Output Float Delay a: r = _t 7 = LT C1605 #7001 = =... THO2 A.HI-2 TO Voy AND g_ TO Voy B. HI-Z TO VoL AND Vgy TO Voi A. Voy TO Hi-Z B. Vg. TO HI-2 FUNCTIONAL BLOCK DIAGRAM C o0k SAMPLE in / I 10k 4k Vana i CSAMPLE = | oo L Vic ak ZEROING SWITCHES = REF 2 oo + REF BUF 16-BIT CAPACITIVE DAC coMP CAP I (ov) SUCCESSIVE APPROXIMATION DIS , 7 QUTPUT LATCHES : REGISTER 7 : AGND] I bo sone INTERNAL beNp 4 CLOCK CONTROL LogIG | | | tT L I l LTC1605 + BO cs RIG BYTE BUSY LY Wie /LTC 1605 APPLICATIONS INFORMATION Conversion Details The LTC1605 uses a Successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit or two byte parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to micro- processors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion startis controlled by the CS and R/C inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal 16-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, Vjy is connected through the resistor divider to the sample-and-hold capacitor during the acquire phase andthe comparator offsetis nulled by the autozero switches. In this acquire phase, a minimum delay of 2us will provide enough time for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the autozero switches open, putting the comparator into the compare mode. The input switch switches Csayp, to ground, injecting the analog input charge onto the summing junc- tion. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the Vij) input charge. The SAR contents (a 16-bit data word) that represents the Vy are loaded into the 16-bit outputlatches. SAMPLE C. Rin SAMPLE SAMPLE COMPARATOR DAG Voac 16-BIT LATGH 105 FO Figure 1. LTC1605 Simplified Equivalent Circuit Driving the Analog Inputs The nominal input range for the LTC1605 is +10V or (+4Vpecr) and the input is overvoltage protected to+25V. The input impedance is typically 20kQ, therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 1000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linear- ity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1605. More detailed information is available in the Linear Technology data books and LinearView' CD-ROM. 200 Ain VIN L = CAP 1000pF 83.2K TOS + FOR Figure 2. Analog Input Filtering LT1007 - Low noise precision amplifier. 2.7mA supply current +5V to +15V supplies. Gain bandwidth product 8MHz. DC applications. LT1097 - Low cost, low power precision amplifier. 300A Supply current. +5V to +15V supplies. Gain bandwidth product 0.7MHz. DC applications. LT1227 - 140MHz video current feedback amplifier. 10mA supply current. +5V to + 15V supplies. Low noise and low distortion. LT1360 - 3/MHz voltage feedback amplifier. 3.8mA sup- ply current. +5V to + 15V supplies. Good AC/DC specs. LT1363 - 50MHz voltage feedback amplifier. 6.3mA sup- ply current. Good AC/DC specs. LT1364/LT1365 - Dual and quad 50MHz voltage feedback amplifiers. 6.3mA supply current per amplifier. Good AC/ DC specs. LinearView is a trademark of Linear Technology Corporation LY WineLTC 1605 APPLICATIONS INFORMATION Internal Voltage Reference The LTC1605 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the ADC is equal to (+4 Veer) or nominally +10V. The output of the reference is connected to the input of a unity-gain buffer through a 4k resistor (see Figure 3). The input to the buffer or the output of the reference is available at REF (Pin 3). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at CAP (Pin 4). The CAP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. BANDGAP REFERENCE | INTERNAL CAPACITOR DAG ] + 1605 + FOS Figure 3. Internal or External Reference Source For minimum code transition noise the REF pin and the CAP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2uF tantalum). Offset and Gain Adjustments The LTC 1605 offset and full-scale errors have been trimmed at the factory with the external resistors shown in Figure 4. This allows for external adjustment of offset and full scale in applications where absolute accuracy is important. See Figure 5 for the offset and gain trim circuit. First adjust the offset to zero by adjusting resistor R3. Apply an input voltage of -152.6mV (-0.5LSB) and adjust R3 so the code is changing between 1111 111111111111 and0000 0000 0000 0000. The gain error is trimmed by adjusting resistor R4. An input voltage of 9.999542V (+FS 1.5LSB) is applied to Vj, and R4 is adjusted until the output code is changing between 0111 1111 11111110 and 0111 1111 11111111. Figure 6 shows the bipolar transfer character- istic of the LTC1605. 10 INPUT (OS Fo +10 INPUT it] T 2.2uF Figure 5. +10V Input with Offset and Gain Trim 011..111 011..110 BIPOLAR ZERO | 000...001 000...000 111..111 111...110 OUTPUT GODE 100...001 100...000 FS = 20 1LSB = FS/65536 FS/2 -1 OV 1 LSB LSB INPUT VOLTAGE (V) F8/2 1L8B Figure 6. LTG1605 Bipolar Transfer Characteristics DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC LY Wie 9LTC 1605 APPLICATIONS INFORMATION signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conver- sions. For example in Figure 7 the distribution of output code is shown fora DC input that has been digitized 10000 times. The distribution is Gaussian and the RMS code transition is about 1LSB. 4500 4000 3500 3000 & 2500 2 2000 1500 1000 500 0 -5 -4-3-2-10 12 3 4 5 CODE 1605 FO? Figure 7. Histogram for 10000 Conversions DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve atypical conversion time of 7us. No external adjustments are required and, with the typical acquisition time of 1ps, throughput performance of 100ksps is assured. Timing and Control Conversion start and data read are controlled by two digital inputs: CS and R/C. To start a conversion and put the sample-and-hold into the hold mode bring CS and R/C low for no less than 40ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output and this is low while the conversion is in progress. There are two modes of operation. The first modeis shown in Figure 8. The digital input R/C is used to control the start of conversion. CS is tied low. When R/C goes low the sample-and-hold goes into the hold mode and a conver- sion is started. BUSY goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated. R/C should remain low for noless than 40ns. During the time R/C is low the digital outputs are in a Hi-Z state. R/C should be brought back high within 3ys after the start of the conversion to ensure that no errors occur in the digitized result. The second mode, shown in Figure 9, uses the CS signal to control the start of a conversion and the reading of the digital output. In this mode the R/C input signal should be brought low no less than 10ns before the falling edge of CS. The minimum pulse width for CS is 40ns. When CS falls, BUSY goes low and will stay low until the end of the conversion. BUSY will go high after the conversion has been completed. The new data is valid when CS is brought back low again to initiate be fy RIG \ } AoA \_S | BUSY ) fs te ~ \ MODE ACQUIRE CONVERT X ACQUIRE pan ts _ X CONVERT nae tconv taca | j DATA MODE NOT VALID eae ion DATA HI-Z DATA VALID VALID | ut tg * PREVIOUS Hlez PREVIOUS DATA VALID DATA VALID ty be tg amy 1605 + FOB Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low) 10 LY WineLTC 1605 APPLICATIONS INFORMATION MODE ACQUIRE CONVERT ACQUIRE tconv DATA BUS pZ lig y 1 805 FOR Figure 9. Using CS to Control Conversion and Read Timing to | a | pe tio BYTE } PINS 67013 ae HIGH BYTE LOW BYTE - ty Le tes 17 HI-Z ) HI-2 PINS 15 TO 22 LOW BYTE HIGH BYTE 1805 = FOS Figure 10. Using CS and BYTE to Control Data Bus Read Timing 0 10 > tsayipLe = 100kHz Tin = 1KH2 SINAD = 87.5dB THD = 101.7dB | I ew oo MAGNITUDE (dB) based co oc oc fc So -100 -110 -120 -130 - 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) 1605 F11 Figure 11. LTC1605 Nonaveraged 4096 Point FFT Plot LY Wie 17LTC 1605 APPLICATIONS INFORMATION a read. Again it is recommended that both R/C and CS return high within Sus after the start of the conversion. Output Data The output data can be read as a 16-bit word or it can be read as two 8-bit bytes. The format of the output data is twos complement. The digital input pin BYTE is used to control the two byte read. With the BYTE pin low the first eight MSBs are output on the D15 to D8 pins and the eight LSBs are output on the D7 to DO pins. When the BYTE pin istaken high the eight LSBs replace the eight MSBs (Figure 10). Dynamic Performance FFT (Fast Fourier Transform) test techniques are used to test the ADCs frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algo- rithm, the ADCs spectral content can be examined for frequencies outside the fundamental. Figure 11 shows a typical LTC1605 FFT plot which yields a SINAD of 87.5dB and THD of -102qB. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 11 shows a typical SINAD of 87.5dB with a 100kHz sampling rate and a 1kHz input. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal tothe fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: g Ve + V2 + V42 wet Vy? THD = 20lo V, where V; is the RMS amplitude of the fundamental fre- quency and Vo through Vy are the amplitudes of the second through Nth harmonics. Board Layout, Power Supplies and Decoupling Wire wrap boards are not recommended for high resolu- tion or high speed A/D converters. To obtain the best performance from the LTC1605, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. Figures 12 through 15 show a layout for a suggested evaluation circuit which will help obtain the best perfor- mance from the 16-bit ADC. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1605 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise opera- tion of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the power supply ground connection. 12 LY WineLTC 1605 APPLICATIONS INFORMATION LED ENABLE [I @ | JP2 @ MEVERSED fh pt) pee - ams ' D4 Peat (eae me acl ae Sib fame = us is ay OEE = Low power = = 16-BIT ADC F =. = mt -_ Sh =| f= mme ExT w = =v2 mule elon re nig E = lel PB coe ee ee oles EXT_CLK Ze St: dees rome S| ES OED ge] Eile olan @ SSE a FeaE oe l Figure 12. Component Side Silkscreen for the Suggested LTC1605 Evaluation Circuit ANALOG DIGITAL ANALOG GROUND PLANE GROUND PLANE GROUND PLANE | Figure 13. Bottom Side Showing Analog Ground Plane Figure 14. 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Ca a0 CS BL ' Nhy pSOHpe 091911 on $14 _wr-- zn HN ge 80 eh oy Nn A= ws 6d 42L BY + zd _- or ane we ve" OLY Pon nee nee en eee eee ne nen a p2souen 5 > @-$$_+vy__ 1 = ' gid 99 7+ MebhL ee Oey I . . T . I an a Pave soe poe sp yp ap he yp ' AA + Sta NA 13 x PST OT sT e or o e t | | oe ssi PY | t t t ' I aLTC 1605 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.397 -0.407* ~ (10.07 10.33) 27 26 25 24 23 22 21 2019 18 17 16 15 | AAA he is] he 0.301 0.311 (7.85 7.90) HHHHYE RYU HHH 1 23 465 6 7 8 9 10111213 14 0.205 - 0.212** oan sme-0ue 3 J ay ey 0.005 0.008 0.022 - oop-oan a 0.0258 _,| Le t a: " #) (0.13 - 0.22) (0.55 - 0.95 0.002 0.008 0.010 0.015 (0.05 0.21) DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH (0.25 0.38) . . SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GES SSOP OBB N Package 28-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.370" (34.789) ~ MAX [pa] 27) [ea) [rs] [oe] | 23] [oe] [21] Jon fio] fia] fiz] fie] fis] 0.255 + 0.015" (8.477 + 0.381) TRIAS Me es 9.300 - 0.325 0.130 + 0.005 0.045 - 0.085 Lae (7.620 8.255) (3302 +0127) (1.143 - 1.851) 4 A 0.020 (0.508) Y MIN 0.085 yj (1.651) 0.009 0.015 TYP oe (1228-00 nies 4 sans 0.05 ' 186 (2.175) >| nen on 0.018 + 0.003 nS MIN MIN (0.457 + 0.078) +0.889 8.255 9 394 0.1004 0.010 (2.5404 0.254) THESE DIMENSIONS DO NOT |NGLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXGEED 0.010 INGH (0.254mm} tes i107 Information furnished by Linear Technology Gorporation is believed to be accurate and reliable. f y LINEAR However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- TECHNOLOGY tation thatthe interconnection ofits circuitsas described hereinwill notinfringe on existing patent rights.LTC 1605 PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 0.712" a (17.70 18.08) 0.394 - 0.419 NOTE 1 la 0.394-0.419_ m | / (10.007 10.643) ism COOGEE bE LU / Wao 27598) 12 3 4 5 6 7 8 $ 0 11 12 13 14 0.093 - 0.104 0.037 0.045 0.010 - 0.029 (0.254 0.737)" | (2.362 2.642) (0.940 1.143) A Fae \ 4 Joa WE Jk Poo 0.009 - 0.013 (1.270) 0.004 0.012 (0.229 0.330) NOTE 1 TyP (0.102 0.305) 0.014 - 0.019 (ot 21.270) (0.356-0482) NOTE: TYP 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. son pune) os THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXGEED 0.010" (0.254mm) PER SIDE PART NUMBER DESCRIPTION COMMENTS LT1019-2.5 Precision Bandgap Reference 0.05% Max, 5ppm/C Max LTG1274/LTC1277 Low Power 12-Bit, 100ksps ADCs 10mW Power Dissipation, Parallel/Byte Interface LTCG1415 Single 5V, 12-Bit, 1.25Msps ADC 55mW Power Dissipation, 72dB SINAD LTG1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation LT1460-2.5 Micropower Precision Series Reference 0.075% Max, 10ppm/C Max, Only 130wA Supply Current LTG1594/LTC1598 Micropower 4-/8-Channel 12-Bit ADCs Serial I/O, 8V and 5V Versions 1605fa Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900* FAX: (408) 434-0507 * www.linear-tech.com LT/TP 0888 2K REV A* PRINTED IN THE USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 1997