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FEATURES DESCRIPTION
APPLICATIONS
APPLICATION CIRCUIT
PGND
ROUT-
PVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
PVDD
LOUT-
1ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
CS
Ci
VDD
Right HP
Audio Source Ci
Ci
CS
Ci
Ci
Ci
CS
Power Supply
Right Line
Audio Source
Left Line
Audio Source
Left HP
Audio Source
Power Supply
VDD
100 kΩ
100 kΩ
CC
In From DAC
or
Potentiometer
(DC Voltage)
C(BYP)
System
Control
CC
Right
Speaker
Left
Speaker
Headphone
s
1 kΩ
1 kΩ
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Volume [Pin 21] - V
DC VOLUME CONTROL
SE Volume,
SEDIFF [Pin 20] = 0 V
SE Volume,
SEDIFF [Pin 20] = 1 V
Volume - dB
BTL Volume
BTL Volume (dB) ∝ Volume (V)
SE Volume (dB) ∝ Volume (V) - SEDIFF
(V)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
3-W STEREO AUDIO POWER AMPLIFIERWITH ADVANCED DC VOLUME CONTROL
•Advanced DC Volume Control With 2-dB
The TPA6011A4 is a stereo audio power amplifierSteps
that drives 3 W/channel of continuous RMS powerFrom -40 dB to 20 dB
into a 3- Ωload. Advanced dc volume controlminimizes external components and allows BTL– Fade Mode
(speaker) volume control and SE (headphone) vol-– Maximum Volume Setting for SE Mode
ume control. Notebook and pocket PCs benefit from– Adjustable SE Volume Control
the integrated feature set that minimizes externalReferenced to BTL Volume Control
components without sacrificing functionality.•3 W Into 3- ΩSpeakers
To simplify design, the speaker volume level isadjusted by applying a dc voltage to the VOLUME•Stereo Input MUX
terminal. Likewise, the delta between speaker volume•Differential Inputs
and headphone volume can be adjusted by applyinga dc voltage to the SEDIFF terminal. To avoid anunexpected high volume level through the•Notebook PC
headphones, a third terminal, SEMAX, limits the•LCD Monitors
headphone volume level when a dc voltage is ap-plied. Finally, to ensure a smooth transition between•Pocket PC
active and shutdown modes, a fade mode ramps thevolume up and down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIIONS
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
AVAILABLE OPTIONS
PACKAGET
A
24-PIN TSSOP (PWP)
(1)
40 °C to 85 °C TPA6011A4PWP
(1) The PWP package is available taped and reeled. To order a tapedand reeled part, add the suffix R to the part number(e.g., TPA6011A4PWPR).
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
V
SS
Supply voltage, V
DD
, PV
DD
-0.3 V to 6 VV
I
Input voltage -0.3 V to V
DD
+0.3 VContinuous total power dissipation See Dissipation Rating TableT
A
Operating free-air temperature range -40 °C to 85 °CT
J
Operating junction temperature range -40 °C to 150 °CT
stg
Storage temperature range -65 °C to 150 °CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING
PWP 2.7 mW 21.8 mW/ °C 1.7 W 1.4 W
MIN MAX UNIT
V
SS
Supply voltage, V
DD
, PV
DD
4.0 5.5 VSE/ BTL, HP/ LINE, FADE 0.8 ×V
DD
VV
IH
High-level input voltage
SHUTDOWN 2 VSE/ BTL, HP/ LINE, FADE 0.6 ×V
DD
VV
IL
Low-level input voltage
SHUTDOWN 0.8 VT
A
Operating free-air temperature -40 85 °C
2
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ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
T
A
= 25 °C, V
DD
= PV
DD
= 5.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5.5 V, Gain = 0 dB, SE/ BTL = 0 V 30 mV| V
OO
| Output offset voltage (measured differentially)
V
DD
= 5.5 V, Gain = 20 dB, SE/ BTL = 0 V 50 mVPSRR Power supply rejection ratio V
DD
= PV
DD
= 4.0 V to 5.5 V -42 -70 dBHigh-level input current (SE/ BTL, FADE, HP/ LINE, V
DD
= PV
DD
= 5.5 V,| I
IH
| 1 µASHUTDOWN, SEDIFF, SEMAX, VOLUME) V
I
= V
DD
= PV
DD
Low-level input current (SE/ BTL, FADE, HP/ LINE,| I
IL
| V
DD
= PV
DD
= 5.5 V, V
I
= 0 V 1 µASHUTDOWN, SEDIFF, SEMAX, VOLUME)
V
DD
= PV
DD
= 5.5 V, SE/ BTL = 0 V,
6.0 7.5 9.0SHUTDOWN = 2 VI
DD
Supply current, no load mAV
DD
= PV
DD
= 5.5 V, SE/ BTL = 5.5 V,
3.0 5 6SHUTDOWN = 2 VV
DD
= 5 V = PV
DD
, SE/ BTL = 0 V,I
DD
Supply current, max power into a 3- Ωload SHUTDOWN = 2 V, R
L
= 3 Ω, 1.5 A
RMSP
O
= 2 W, stereoI
DD(SD)
Supply current, shutdown mode SHUTDOWN = 0.0 V 1 20 µA
T
A
= 25 °C, V
DD
= PV
DD
= 5 V, R
L
= 3 Ω, Gain = 6 dB (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THD = 1%, f = 1 kHz 2P
O
Output power WTHD = 10%, f = 1 kHz, V
DD
= 5.5 V 3THD+N Total harmonic distortion + noise P
O
= 1 W, R
L
= 8 Ω, f = 20 Hz to 20 kHz <0.4%V
OH
High-level output voltage R
L
= 8 Ω, Measured between output and V
DD
700 mVV
OL
Low-level output voltage R
L
= 8 Ω, Measured between output and GND 400 mVV
(Bypass
Bypass voltage (Nominally V
DD
/2) Measured at pin 17, No load, V
DD
= 5.5 V 2.65 2.75 2.85 V)
B
OM
Maximum output power bandwidth THD = 5% >20 kHzBTL -63 dBSupply ripple rejection ratio f = 1 kHz, Gain = 0 dB, C
(BYP)
= 0.47 µF
SE -57 dBf = 20 Hz to20 kHz, Gain = 0 dB,Noise output voltage BTL 36 µV
RMSC
(BYP)
= 0.47 µFZ
I
Input impedance (see Figure 26 ) VOLUME = 5.0 V 14 k Ω
3
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1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PGND
ROUT-
PVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
PVDD
LOUT-
ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
PWP PACKAGE
(TOP VIEW)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Terminal Functions
TERMINAL
I/O DESCRIPTIONNAME NO.
PGND 1, 13 - Power groundLOUT- 12 O Left channel negative audio outputPV
DD
3, 11 - Supply voltage terminal for power stageLHPIN 10 I Left channel headphone input, selected when HP/ LINE is held highLLINEIN 9 I Left channel line input, selected when HP/ LINE is held lowLIN 8 I Common left channel input for fully differential input. AC ground for single-ended inputs.V
DD
7 - Supply voltage terminalRIN 6 I Common right channel input for fully differential input. AC ground for single-ended inputs.RLINEIN 5 I Right channel line input, selected when HP/ LINE is held lowRHPIN 4 I Right channel headphone input, selected when HP/ LINE is held highROUT- 2 O Right channel negative audio outputROUT+ 24 O Right channel positive audio outputSHUTDOWN 15 I Places the amplifier in shutdown mode if a TTL logic low is placed on this terminalPlaces the amplifier in fade mode if a logic low is placed on this terminal; normal operation if a logic high isFADE 16 I
placed on this terminalBYPASS 17 I Tap to voltage divider for internal midsupply bias generator used for analog referenceAGND 18 - Analog power supply groundSEMAX 19 I Sets the maximum volume for single ended operation. DC voltage range is 0 to V
DD
.SEDIFF 20 I Sets the difference between BTL volume and SE volume. DC voltage range is 0 to V
DD
.VOLUME 21 I Terminal for dc volume control. DC voltage range is 0 to V
DD
.Input MUX control. When logic high, RHPIN and LHPIN inputs are selected. When logic low, RLINEIN andHP/ LINE 22 I
LLINEIN inputs are selected.Output MUX control. When this terminal is high, SE outputs are selected. When this terminal is low, BTLSE/ BTL 23 I
outputs are selected.LOUT+ 14 O Left channel positive audio output.
4
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FUNCTIONAL BLOCK DIAGRAM
Power
Management
32-Step
Volume
Control
MUX
Control
R
MUX
RHPIN
ROUT+
SHUTDOWN
ROUT-
PVDD
PGND
VDD
BYPASS
AGND
LOUT+
LOUT-
RLINEIN
RIN
HP/LINE
VOLUME
SEDIFF
SEMAX
FADE
_
+
HP/LINE
_
+
_
+
BYP
_
+
BYP
BYP EN SE/BTL
L
MUX _
+
HP/LINE
_
+
_
+
BYP
_
+
BYP
BYP EN SE/BTL
SE/BTL
LHPIN
LLINEIN
LIN
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
NOTE: All resistor wipers are adjusted with 32 step volume control.
5
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TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 1. DC Volume Control (BTL Mode, V
DD
= 5 V)
(1)
VOLUME (PIN 21)
GAIN OF AMPLIFIER
(Typ)FROM (V) TO (V)
0.00 0.26 -85
(2)
0.33 0.37 -400.44 0.48 -380.56 0.59 -360.67 0.70 -340.78 0.82 -320.89 0.93 -301.01 1.04 -281.12 1.16 -261.23 1.27 -241.35 1.38 -221.46 1.49 -201.57 1.60 -181.68 1.72 -161.79 1.83 -141.91 1.94 -122.02 2.06 -102.13 2.17 -82.25 2.28 -6
(2)
2.36 2.39 -42.47 2.50 -22.58 2.61 02.70 2.73 22.81 2.83 42.92 2.95 63.04 3.06 83.15 3.17 103.26 3.29 123.38 3.40 143.49 3.51 163.60 3.63 183.71 5.00 20
(2)
(1) For other values of V
DD
, scale the voltage values in the table by a factor of V
DD
/5.(2) Tested in production. Remaining gain steps are specified by design.
6
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TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 2. DC Volume Control (SE Mode, V
DD
= 5 V)
(1)
SE_VOLUME = VOLUME - SEDIFF or SEMAX
GAIN OF AMPLIFIER
(Typ)FROM (V) TO (V)
0.00 0.26 -85
(2)
0.33 0.37 -460.44 0.48 -440.56 0.59 -420.67 0.70 -400.78 0.82 -380.89 0.93 -361.01 1.04 -341.12 1.16 -321.23 1.27 -301.35 1.38 -281.46 1.49 -261.57 1.60 -241.68 1.72 -221.79 1.83 -201.91 1.94 -182.02 2.06 -162.13 2.17 -142.25 2.28 -122.36 2.39 -102.47 2.50 -82.58 2.61 -6
(2)
2.70 2.73 -42.81 2.83 -22.92 2.95 0
(2)
3.04 3.06 23.15 3.17 43.26 3.29 6
(2)
3.38 3.40 83.49 3.51 103.60 3.63 123.71 5.00 14
(1) For other values of V
DD
, scale the voltage values in the table by a factor of V
DD
/5.(2) Tested in production. Remaining gain steps are specified by design.
7
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TYPICAL CHARACTERISTICS
Table of Graphs
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k100 1 k 10 k
VDD = 5 V
RL = 3 Ω
Gain = 20 dB
BTL
PO = 1.75 W
PO = 0.5 W
PO = 1 W
THD+N − Total Harmonic Distortion + Noise (BTL) − %
f − Frequency − Hz
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
PO = 0.25 W
PO = 1.5 W
PO = 1 W
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise (BTL) − %
VDD = 5 V
RL = 4 Ω
Gain = 20 dB
BTL
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
FIGURE
vs Frequency 1, 2 3THD+N Total harmonic distortion plus noise (BTL)
vs Output power 6, 7, 8vs Frequency 4, 5THD+N Total harmonic distortion plus noise (SE) vs Output power 9vs Output voltage 10Closed loop response 11, 12vs Temperature 13I
CC
Supply current
vs Supply voltage 14, 15, 16P
D
Power Dissipation vs Output power 17, 18P
O
Output power vs Load resistance 19, 20Crosstalk vs Frequency 21, 22HP/ LINE attenuation vs Frequency 23PSRR Power supply ripple rejection (BTL) vs Frequency 24PSRR Power supply ripple rejection (SE) vs Frequency 25Z
I
Input impedance vs BTL gain 26V
n
Output noise voltage vs Frequency 27
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)vs vsFREQUENCY FREQUENCY
Figure 1. Figure 2.
8
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10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise (SE) − %
PO = 75 mW
VDD = 5 V
RL = 32 Ω
Gain = 14 dB
SE
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20 k50 100 200 500 1 k 2 k 5 k 10 k
f − Frequency − Hz
THD+N − Total Harmonic Distortion + Noise (SE) − %
VO = 1 VRMS
VDD = 5 V
RL = 10 kΩ
Gain = 14 dB
SE
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise (BTL) − %
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
0.01 100.1 1
f = 20 kHz
f = 1 kHz
f = 20 Hz
VDD = 5 V
RL = 3 Ω
Gain = 20 dB
BTL
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (SE)vs vsFREQUENCY FREQUENCY
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (BTL)vs vsFREQUENCY OUTPUT POWER
Figure 5. Figure 6.
9
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10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
50.02 0.05 0.1 0.2 0.5 1 2
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise (BTL) − %
1 kHz
20 kHz
VDD = 5 V
RL = 8 Ω
Gain = 20 dB
BTL
20 Hz
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
50.02 0.05 0.1 0.2 0.5 1 2
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise (BTL) − %
1 kHz
20 kHz
20 Hz
VDD = 5 V
RL = 4 Ω
Gain = 20 dB
BTL
10
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
0500 m 1 1.5 2
VO − Output Voltage − rms
THD+N − Total Harmonic Distortion + Noise (SE) − %
1 kHz
20 kHz
20 Hz
VDD = 5 V
RL = 10 kΩ
Gain = 14 dB
SE
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10 m 200 m50 m 100 m
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise (SE) − %
1 kHz
20 kHz
20 Hz
VDD = 5 V
RL = 32 Ω
Gain = 14 dB
SE
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)vs vsOUTPUT POWER OUTPUT POWER
Figure 7. Figure 8.
TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (SE)vs vsOUTPUT POWER OUTPUT VOLTAGE
Figure 9. Figure 10.
10
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150
120
90
60
30
0
−30
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
10 100 1 k 10 k 100 k 1 M
−180
−150
−120
−90
−60
180
Gain
Phase
VDD = 5 Vdc
RL = 8 Ω
Mode = BTL
Gain = 0 dB
f − Frequency − Hz
Closed Loop Gain − dB
Phase − Degrees
150
120
90
60
30
0
−30
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
10 100 1 k 10 k 100 k 1 M
−180
−150
−120
−90
−60
180
Gain
Phase
VDD = 5 Vdc
RL = 8 Ω
Mode = BTL
Gain = 20 dB
f − Frequency − Hz
Closed Loop Gain − dB
Phase − Degrees
0
1
2
3
4
5
6
7
8
9
10
−40 −25 5 20 35 50 65 95−10 110 125
− Supply Current − mA
TA − Free-Air Temperature − °C
IDD
VDD = 5 V
Mode = BTL
SHUTDOWN = VDD
80
−1
0
1
2
3
4
5
6
7
8
9
10
00.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Mode = BTL
SHUTDOWN = VDD
VDD − Supply Voltage − V
TA = 125°C
TA = 25°C
TA = −40°C
− Supply Current − mA
IDD
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE
Figure 11. Figure 12.
SUPPLY CURRENT SUPPLY CURRENTvs vsFREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 13. Figure 14.
11
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0
50
100
150
200
250
300
350
400
450
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Mode = SD
SHUTDOWN = 0 V
VDD − Supply Voltage − V
− Supply Current −
IDD
TA = 125°C
TA = 25°C
TA = −40°C
nA
1
2
3
4
5
6
7
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Mode = SE
SHUTDOWN = VDD
VDD − Supply Voltage − V
− Supply Current − mAIDD
TA = 125°C
TA = 25°C
TA =−40°C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
PO − Output Power − W
− Power Dissipation (PER CHANNEL) − WPD
VDD = 5 V
BTL
4 Ω
8 Ω
3 Ω
0
20
40
60
80
100
120
140
160
180
200
0 100 150 200 250 30050
8 Ω
16 Ω
32 Ω
PO − Output Power − mW
VDD = 5 V
SE
− Power Dissipation (PER CHANNEL) − mWPD
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
SUPPLY CURRENT SUPPLY CURRENTvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 15. Figure 16.
POWER DISSIPATION (PER CHANNEL) POWER DISSIPATION (PER CHANNEL)vs vsOUTPUT POWER OUTPUT POWER
Figure 17. Figure 18.
12
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0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0 8 16 24 32 40 48 56 64
RL − Load Resistance − Ω
− Output Power − WPO
VDD = 5 V
THD+N = 1%
Gain = 20 dB
BTL
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0 8 16 24 32 40 48 56 64
RL − Load Resistance − Ω
− Output Power − WPO
VDD = 5.5 V
Gain = 20 dB
BTL
2.4
2.6
2.8
3
THD+N = 10%
THD+N = 1%
3.2
−120
0
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
20 20 k100 1 k 10 k
f − Frequency − Hz
Crosstalk − dB
Left to Right
Right to Left
VDD = 5 V
PO = 1 W
RL = 8 Ω
Gain = 0dB
BTL
−120
0
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
20 20 k100 1 k 10 k
f − Frequency − Hz
Crosstalk − dB
Left to Right
Right to Left
VDD = 5 V
PO = 1 W
RL = 8 Ω
Gain = 20 dB
BTL
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
OUTPUT POWER OUTPUT POWERvs vsLOAD RESISTANCE LOAD RESISTANCE
Figure 19. Figure 20.
CROSSTALK CROSSTALKvs vsFREQUENCY FREQUENCY
Figure 21. Figure 22.
13
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20 20 k100 1 k 10 k
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio (BTL) − dB
0
−80
−70
−60
−50
−40
−30
−20
−10 VDD = 5 V
RL = 8 Ω
C(BYP) =0.47 µF
BTL
Gain = 1
Gain = 10
−120
0
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
20 20 k100 1 k 10 k
f − Frequency − Hz
HP/Line Attenuation − dB
Line Active
HP Active
VDD = 5 V
VI = 1 VRMS
RL = 8 Ω
BTL
20 20 k100 1 k 10 k
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio (SE) − dB
−100
+0
−90
−80
−70
−60
−50
−40
−30
−20
−10
Gain = 14 dB
Gain = 0 dB
VDD = 5 V
RL = 32 Ω
C(BYP) =0.47 µF
SE
0
10
20
30
40
50
60
70
80
90
−40 −30 −20 −10 010 20
BTL Gain − dB
− Input Impedamce − ZIkΩ
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
HP/LINE ATTENUATION POWER SUPPLY REJECTION RATIO (BTL)vs vsFREQUENCY FREQUENCY
Figure 23. Figure 24.
POWER SUPPLY REJECTION RATIO (SE) INPUT IMPEDANCEvs vsFREQUENCY BTL GAIN
Figure 25. Figure 26.
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100
80
20
10 100 1 k
− Output Noise Voltage −
120
140
10 k 20 k
180
40
0
60
160
VnVµRMS
Gain = 0 dB
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 8 Ω
BTL
Gain = 20 dB
f − Frequency − Hz
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
OUTPUT NOISE VOLTAGE
vsFREQUENCY
Figure 27.
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APPLICATION INFORMATION
SELECTION OF COMPONENTS
PGND
ROUT-
PVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
PVDD
LOUT-
1ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
CS
Ci
VDD
Right HP
Audio Source Ci
Ci
CS
Ci
Ci
Ci
CS
Power Supply
Right Line
Audio Source
Left Line
Audio Source
Left HP
Audio Source
Power Supply
VDD
100 kΩ
100 kΩ
CC
In From DAC
or
Potentiometer
(DC Voltage)
C(BYP)
System
Control
CC
Right
Speaker
Left
Speaker
Headphones
1 kΩ
1 kΩ
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Figure 28 and Figure 29 are schematic diagrams of typical notebook computer application circuits.
A. A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noisesignals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 28. Typical TPA6011A4 Application Circuit Using Single-Ended Inputs and Input MUX
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PGND
ROUT-
PVDD
RHPIN
RLINEIN
RIN
VDD
LIN
LLINEIN
LHPIN
PVDD
LOUT-
1ROUT+
SE/BTL
HP/LINE
VOLUME
SEDIFF
SEMAX
AGND
BYPASS
FADE
SHUTDOWN
LOUT+
PGND
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24
CS
NC
VDD
Ci
Ci
CS
Ci
Ci
CS
Power Supply
Left Negative
Differential Input Signal
Power Supply
VDD
100 kΩ
100 kΩ
CC
In From DAC
or
Potentiometer
(DC Voltage)
C(BYP)
System
Control
CC
Right
Speaker
Left
Speaker
Headphones
1 kΩ
1 kΩ
NC
Left Positive Differential
Input Signal
Right Negative
Differential Input Signal
Right Positive
Differential Input Signal
SE/ BTL OPERATION
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
APPLICATION INFORMATION (continued)
A. A 0.1-µF ceramic capacitor should be placed as close as possible to the IC. For filtering lower-frequency noisesignals, a larger electrolytic capacitor of 10 µF or greater should be placed near the audio power amplifier.
Figure 29. Typical TPA6011A4 Application Circuit Using Differential Inputs
The ability of the TPA6011A4 to easily switch between BTL and SE modes is one of its most important costsaving features. This feature eliminates the requirement for an additional headphone amplifier in applicationswhere internal stereo speakers are driven in BTL mode but external headphone or speakers must beaccommodated. Internal to the TPA6011A4, two separate amplifiers drive OUT+ and OUT-. The SE/ BTL inputcontrols the operation of the follower amplifier that drives LOUT- and ROUT-. When SE/ BTL is held low, theamplifier is on and the TPA6011A4 is in the BTL mode. When SE/ BTL is held high, the OUT- amplifiers are in ahigh output impedance state, which configures the TPA6011A4 as an SE driver from LOUT+ and ROUT+. I
DD
isreduced by approximately one-third in SE mode. Control of the SE/ BTL input can be from a logic-level CMOSsource or, more typically, from a resistor divider network as shown in Figure 30 . The trip level for the SE/ BTLinput can be found in the recommended operating conditions table.
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SE/BTL
ROUT+ 24
R
MUX
RHPIN
RLINEIN5
4
6 RIN
ROUT- 2 1 kΩ
CO
330 µF
100 kΩ
23
100 kΩ
VDD
Input
MUX
Control
22 HP/LINE
_
+_
+
Bypass
_
+
Bypass EN
_
+
Bypass
LOUT+
HP/ LINE OPERATION
SHUTDOWN MODES
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
APPLICATION INFORMATION (continued)
Figure 30. TPA6011A4 Resistor Divider Network Circuit
Using a 1/8-in. (3,5 mm) stereo headphone jack, the control switch is closed when no plug is inserted. Whenclosed the 100-k Ω/1-k Ωdivider pulls the SE/ BTL input low. When a plug is inserted, the 1-k Ωresistor isdisconnected and the SE/ BTL input is pulled high. When the input goes high, the OUT- amplifier is shut downcausing the speaker to mute (open-circuits the speaker). The OUT+ amplifier then drives through the outputcapacitor (C
o
) into the headphone jack.
The HP/ LINE input controls the internal input multiplexer (MUX). Refer to the block diagram in Figure 30 . Thisallows the device to switch between two separate stereo inputs to the amplifier. For design flexibility, theHP/ LINE control is independent of the output mode, SE or BTL, which is controlled by the aforementionedSE/ BTL pin. To allow the amplifier to switch from the LINE inputs to the HP inputs when the output switches fromBTL mode to SE mode, simply connect the SE/ BTL control input to the HP/ LINE input.
When this input is logic high, the RHPIN and LHPIN inputs are selected. When this terminal is logic low, theRLINEIN and LLINEIN inputs are selected. This operation is also detailed in Table 3 and the trip levels for a logiclow (V
IL
) or logic high (V
IH
) can be found in the recommended operating conditions table.
The TPA6011A4 employs a shutdown mode of operation designed to reduce supply current (I
DD
) to the absoluteminimum level during periods of nonuse for battery-power conservation. The SHUTDOWN input terminal shouldbe held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs tomute and the amplifier to enter a low-current state, I
DD
= 20 µA. SHUTDOWN should never be left unconnectedbecause amplifier operation would be unpredictable.
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FADE OPERATION
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 3. HP/ LINE, SE/ BTL, and Shutdown Functions
INPUTS
(1)
AMPLIFIER STATE
HP/ LINE SE/ BTL SHUTDOWN INPUT OUTPUT
X X Low X MuteLow Low High Line BTLLow High High Line SEHigh Low High HP BTLHigh High High HP SE
(1) Inputs should never be left unconnected.
For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdownmode and conversely ramp the gain down when going into shutdown. This mode provides a smooth transitionbetween the active and shutdown states and virtually eliminates any pops or clicks on the outputs.
When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places theamplifier in the fade-off mode. The voltage trip levels for a logic low (V
IL
) or logic high (V
IH
) can be found in therecommended operating conditions table.
When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channelgain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clockfrequency of 58 Hz, this equates to 34 ms (1/24 Hz) per step. The gain steps down until the lowest gain step isreached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown.For example, if the amplifier is in the highest gain mode of 20 dB, the time it takes to ramp down the channelgain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from thehighest gain, or 31 steps, and multiplying by the time per step, or 34 ms.
After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitorfrom the nominal voltage of V
DD
/2 to ground. This time is dependent on the value of the bypass capacitor. For a0.47-µF capacitor that is used in the application diagram in Figure 28 , the time is approximately 500 ms. Thistime scales linearly with the value of bypass capacitor. For example, if a 1-µF capacitor is used for bypass, thetime period to discharge the capacitor to ground is twice that of the 0.47-µF capacitor, or 1 second. Figure 30below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode.The gain is set to the highest level and the output is at V
DD
when the amplifier is shut down.
When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins thestart-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value ofV
DD
/2, the gain increases in 2-dB steps from the lowest gain level to the gain level set by the dc voltage appliedto the VOLUME, SEDIFF, and SEMAX pins.
In the fade-off mode, the amplifier stores the gain value prior to starting the shutdown sequence. The output ofthe amplifier immediately drops to V
DD
/2 and the bypass capacitor begins a smooth discharge to ground. Whenshutdown is released, the bypass capacitor charges up to V
DD
/2 and the channel gain returns immediately to thevalue stored in memory. Figure 31 below is a waveform captured at the output during the shutdown sequencewhen the part is in the fade-off mode. The gain is set to the highest level, and the output is at V
DD
when theamplifier is shut down.
The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does notchange the power-up sequence. Upon a power-up condition, the TPA6011A4 begins in the lowest gain settingand steps up 2 dB every 2 clock cycles until the final value is reached as determined by the dc voltage applied tothe VOLUME, SEDIFF, and SEMAX pins.
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ROUT+
Device Shutdown
ROUT+
Device Shutdown
VOLUME, SEDIFF, AND SEMAX OPERATION
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Figure 31. Shutdown Sequence in the Figure 32. Shutdown Sequence in theFade-on Mode Fade-off Mode
Three pins labeled VOLUME, SEDIFF, and SEMAX control the BTL volume when driving speakers and the SEvolume when driving headphones. All of these pins are controlled with a dc voltage, which should not exceedV
DD
.
When driving speakers in BTL mode, the VOLUME pin is the only pin that controls the gain. Table 1 shows thegain for the BTL mode. The voltages listed in the table are for V
DD
= 5 V. For a different V
DD
, the values in thetable scale linearly. If V
DD
= 4 V, multiply all the voltages in the table by 4 V/5 V, or 0.8.
The TPA6011A4 allows the user to specify a difference between BTL gain and SE gain. This is desirable to avoidany listening discomfort when plugging in headphones. When switching to SE mode, the SEDIFF and SEMAXpins control the singe-ended gain proportional to the gain set by the voltage on the VOLUME pin. When SEDIFF= 0 V, the difference between the BTL gain and the SE gain is 6 dB. Refer to the section labeled bridged-tiedload versus single-ended load for an explanation on why the gain in BTL mode is 2x that of single-ended mode,or 6dB greater. As the voltage on the SEDIFF terminal is increased, the gain in SE mode decreases. The voltageon the SEDIFF terminal is subtracted from the voltage on the VOLUME terminal and this value is used todetermine the SE gain.
Some audio systems require that the gain be limited in the single-ended mode to a level that is comfortable forheadphone listening. Most volume control devices only have one terminal for setting the gain. For example, if thespeaker gain is 20 dB, the gain in the headphone channel is fixed at 14 dB. This level of gain could causediscomfort to listeners and the SEMAX pin allows the designer to limit this discomfort when plugging inheadphones. The SEMAX terminal controls the maximum gain for single-ended mode.
The functionality of the SEDIFF and SEMAX pin are combined to set the SE gain. A block diagram of thecombined functionality is shown in Figure 33 . The value obtained from the block diagram for SE_VOLUME is adc voltage that can be used in conjunction with Table 2 to determine the SE gain. Again, the voltages listed inthe table are for V
DD
= 5 V. The values must be scaled for other values of V
DD
.
Table 1 and Table 2 show a range of voltages for each gain step. There is a gap in the voltage between eachgain step. This gap represents the hysteresis about each trip point in the internal comparator. The hysteresisensures that the gain control is monotonic and does not oscillate from one gain step to another. If apotentiometer is used to adjust the voltage on the control terminals, the gain increases as the potentiometer isturned in one direction and decreases as it is turned back the other direction. The trip point, where the gain
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SEMAX (V)
VOLUME-SEDIFF
SEDIFF (V)
-
+
VOLUME (V) YES
NO
SE_VOLUME (V) = VOLUME (V) - SEDIFF (V)
SE_VOLUME (V) = SEMAX (V)
Is SEMAX>
(VOLUME-SEDIFF)
?
0
2
4
2.702.61 2.73 2.81
BTL Gain - dB
Voltage on VOLUME Pin - V
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
actually changes, is different depending on whether the voltage is increased or decreased as a result of thehysteresis about each trip point. The gaps in Table 1 and Table 2 can also be thought of as indeterminate stateswhere the gain could be in the next higher gain step or the lower gain step depending on the direction thevoltage is changing. If using a DAC to control the volume, set the voltage in the middle of each range to ensurethat the desired gain is achieved.
A pictorial representation of the volume control can be found in Figure 34 . The graph focuses on three gain stepswith the trip points defined in Table 1 for BTL gain. The dotted line represents the hysteresis about each gainstep.
Figure 33. Block Diagram of SE Volume Control
Figure 34. DC Volume Control Operation
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INPUT RESISTANCE
CIN Ri
Rf
Input Signal
ƒ3 dB 1
2CRi
(1)
INPUT CAPACITOR, C
i
fc(highpass) 1
2RiCi
−3 dB
fc
(2)
Ci1
2Rifc
(3)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallestvalue to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the -3 dBor cutoff frequency also changes by over six times.
Figure 35. Resistor on Input for Cut-Off Frequency
The input resistance at each gain setting is given in Figure 26 .
The -3-dB frequency can be calculated using Equation 1 .
In the typical application an input capacitor (C
i
) is required to allow the amplifier to bias the input signal to theproper dc level for optimum operation. In this case, C
i
and the input impedance of the amplifier (R
i
) form ahigh-pass filter with the corner frequency determined in Equation 2 .
The value of C
i
is important to consider as it directly affects the bass (low frequency) performance of the circuit.Consider the example where R
i
is 70 k Ωand the specification calls for a flat-bass response down to 40 Hz.Equation 2 is reconfigured as Equation 3 .
In this example, C
i
is 56.8 nF, so one would likely choose a value in the range of 56 nF to 1 µF. A furtherconsideration for this capacitor is the leakage path from the input source through the input network (C
i
) and thefeedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier thatreduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum orceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitorshould face the amplifier input in most applications as the dc level there is held at V
DD
/2, which is likely higherthan the source dc level. Note that it is important to confirm the capacitor polarity in the application.
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POWER SUPPLY DECOUPLING, C
(S)
MIDRAIL BYPASS CAPACITOR, C
(BYP)
OUTPUT COUPLING CAPACITOR, C
(C)
fc(high) 1
2RLC(C)
−3 dB
fc
(4)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
The TPA6011A4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling toensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also preventsoscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved byusing two capacitors of different types that target different types of noise on the power supply leads. For higherfrequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramiccapacitor, typically 0.1 µF placed as close as possible to the device V
DD
lead, works best. For filteringlower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near the audiopower amplifier is recommended.
The midrail bypass capacitor (C
(BYP)
) is the most critical capacitor and serves several important functions. Duringstart-up or recovery from shutdown mode, C
(BYP)
determines the rate at which the amplifier starts up. The secondfunction is to reduce noise produced by the power supply caused by coupling into the output drive signal. Thisnoise is from the midrail generation circuit internal to the amplifier, which appears as degraded PSRR andTHD+N.
Bypass capacitor (C
(BYP)
) values of 0.47-µF to 1-µF ceramic or tantalum low-ESR capacitors are recommendedfor the best THD and noise performance. For the best pop performance, choose a value for C
(BYP)
that is equal toor greater than the value chosen for C
i
. This ensures that the input capacitors are charged up to the midrailvoltage before C
(BYP)
is fully charged to the midrail voltage.
In the typical single-supply SE configuration, an output coupling capacitor (C
(C)
) is required to block the dc bias atthe output of the amplifier, thus preventing dc currents in the load. As with the input coupling capacitor, theoutput coupling capacitor and impedance of the load form a high-pass filter governed by Equation 4 .
The main disadvantage, from a performance standpoint, is the load impedances are typically small, which drivesthe low-frequency corner higher, degrading the bass response. Large values of C
(C)
are required to pass lowfrequencies into the load. Consider the example where a C
(C)
of 330 µF is chosen and loads vary from 3 Ω,4 Ω,8Ω, 32 Ω, 10 k Ω, and 47 k Ω. Table 4 summarizes the frequency response characteristics of each configuration.
Table 4. Common Load Impedances vs Low FrequencyOutput Characteristics in SE Mode
LOWESTR
L
C
(C)
FREQUENCY
3Ω330 µF 161 Hz4Ω330 µF 120 Hz8Ω330 µF 60 Hz32 Ω330 µF 15 Hz10,000 Ω330 µF 0.05 Hz47,000 Ω330 µF 0.01 Hz
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USING LOW-ESR CAPACITORS
BRIDGED-TIED LOAD vs SINGLE-ENDED LOAD
Power V(rms)2
RL
V(rms) VO(PP)
2 2
(5)
RL2x VO(PP)
VO(PP)
-VO(PP)
VDD
VDD
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
As Table 4 indicates, most of the bass response is attenuated into a 4- Ωload, an 8- Ωload is adequate,headphone response is good, and drive into line level inputs (a home stereo for example) is exceptional.
Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal)capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across thisresistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of thisresistance, the more the real capacitor behaves like an ideal capacitor.
Figure 36 shows a Class-AB audio power amplifier (APA) in a BTL configuration. The TPA6011A4 BTL amplifierconsists of two Class-AB amplifiers driving both ends of the load. There are several potential benefits to thisdifferential drive configuration, but, initially consider power to the load. The differential drive to the speakermeans that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles thevoltage swing on the load as compared to a ground referenced load. Plugging 2 ×V
O(PP)
into the power equation,where voltage is squared, yields 4 ×the output power from the same supply rail and load impedance (seeEquation 5 ).
Figure 36. Bridge-Tied Load Configuration
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f(c) 1
2RLCC
(6)
RL
C(C) VO(PP)
VO(PP)
VDD
-3 dB
fc
SINGLE-ENDED OPERATION
BTL AMPLIFIER EFFICIENCY
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
In a typical computer sound channel operating at 5 V, bridging raises the power into an 8- Ωspeaker from asingled-ended (SE, ground reference) limit of 250 mW to 1 W. In sound power that is a 6-dB improvement, whichis loudness that can be heard. In addition to increased power there are frequency response concerns. Considerthe single-supply SE configuration shown in Figure 37 . A coupling capacitor is required to block the dc offsetvoltage from reaching the load. These capacitors can be quite large (approximately 33 µF to 1000 µF), so theytend to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limitinglow-frequency performance of the system. This frequency limiting effect is due to the high-pass filter networkcreated with the speaker impedance and the coupling capacitance and is calculated with Equation 6 .
For example, a 68-µF capacitor with an 8- Ωspeaker would attenuate low frequencies below 293 Hz. The BTLconfiguration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequencyperformance is then limited only by the input network and speaker response. Cost and PCB space are alsominimized by eliminating the bulky coupling capacitor.
Figure 37. Single-Ended Configuration and Frequency Response
Increasing power to the load does carry a penalty of increased internal power dissipation. The increaseddissipation is understandable considering that the BTL configuration produces 4 ×the output power of the SEconfiguration. Internal dissipation versus output power is discussed further in the crest factor and thermalconsiderations section.
In SE mode (see Figure 37 ), the load is driven from the primary amplifier output for each channel (OUT+).
The amplifier switches single-ended operation when the SE/ BTL terminal is held high. This puts the negativeoutputs in a high-impedance state, and effectively reduces the amplifier's gain by 6 dB.
Class-AB amplifiers are inefficient. The primary cause of these inefficiencies is voltage drop across the outputstage transistors. There are two components of the internal voltage drop. One is the headroom or dc voltagedrop that varies inversely to output power. The second component is due to the sinewave nature of the output.The total voltage drop can be calculated by subtracting the RMS value of the output voltage from V
DD
. Theinternal voltage drop multiplied by the RMS value of the supply current (I
DD
rms) determines the internal powerdissipation of the amplifier.
An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the powersupply to the power delivered to the load. To accurately calculate the RMS and average values of power in theload and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 38 ).
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V(LRMS)
VOIDD
IDD(avg)
Efficiency of a BTL amplifier PL
PSUP
Where:
PLVLrms2
RL, andVLRMS VP
2
, therefore, PLVP2
2RL
and PSUP VDD IDDavg and IDDavg 1
0
VP
RLsin(t) dt 1
VP
RL[cos(t)]
02VP
RL
Therefore,
PSUP 2 VDD VP
RL
(7)
Efficiency of a BTL amplifier
VP2
2 RL
2 VDD VP
RL
VP
4 VDD
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP2 PLRL
BTL 2 PLRL
4 VDD
Where:
Therefore,
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
(8)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Figure 38. Voltage and Current Waveforms for BTL Amplifiers
Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are verydifferent between SE and BTL configurations. In an SE application the current waveform is a half-wave rectifiedshape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different.Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, whichsupports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform.The following equations are the basis for calculating amplifier efficiency.
substituting PL and PSUP into Equation 7 ,
Table 5 employs Equation 8 to calculate efficiencies for four different output power levels. Note that the efficiencyof the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting ina nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at fulloutput power is less than in the half power range. Calculating the efficiency for a specific system is the key toproper power supply design. For a stereo 1-W audio system with 8- Ωloads and a 5-V supply, the maximum drawon the power supply is almost 3.25 W.
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CREST FACTOR AND THERMAL CONSIDERATIONS
PdB 10Log PW
Pref
10Log 4 W
1 W 6 dB
(9)
PW10PdB10 Pref
= 250 mW (12-db crest factor)
= 125 mW (15-db crest factor)
= 63 mW (18-db crest factor)
= 500 mW (9-db crest factor)
= 1000 mW (6-db crest factor)
= 2000 mW (3-db crest factor)
(10)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 5. Efficiency vs Output Power in 5-V, 8- ΩBTL Systems
OUTPUT POWER EFFICIENCY PEAK VOLTAGE INTERNAL DISSIPATION(W) (%) (V) (W)
0.25 31.4 2.00 0.550.50 44.4 2.83 0.621.00 62.8 4.00 0.591.25 70.2 4.47
(1)
0.53
(1) High peak voltages cause the THD to increase.
A final point to remember about Class-AB amplifiers (either SE or BTL) is how to manipulate the terms in theefficiency equation to utmost advantage when possible. Note that in equation 8, V
DD
is in the denominator. Thisindicates that as V
DD
goes down, efficiency goes up.
Class-AB power amplifiers dissipate a significant amount of heat in the package under normal operatingconditions. A typical music CD requires 12 dB to 15 dB of dynamic range, or headroom above the average poweroutput, to pass the loudest portions of the signal without distortion. In other words, music typically has a crestfactor between 12 dB and 15 dB. When determining the optimal ambient operating temperature, the internaldissipated power at the average output power level must be used. From the TPA6011A4 data sheet, one cansee that when the TPA6011A4 is operating from a 5-V supply into a 3- Ωspeaker, that 4-W peaks are available.Use equation 9 to convert watts to dB.
Subtracting the headroom restriction to obtain the average listening level without distortion yields:•6 dB - 15 dB = -9 dB (15-dB crest factor)•6 dB - 12 dB = -6 dB (12-dB crest factor)•6 dB - 9 dB = -3 dB (9-dB crest factor)•6 dB - 6 dB = 0 dB (6-dB crest factor)•6 dB - 3 dB = 3 dB (3-dB crest factor)
To convert dB back into watts use equation 10.
This is valuable information to consider when attempting to estimate the heat dissipation requirements for theamplifier system. Comparing the worst case, which is 2 W of continuous power output with a 3-dB crest factor,against 12-dB and 15-dB applications significantly affects maximum ambient temperature ratings for the system.Using the power dissipation curves for a 5-V, 3- Ωsystem, the internal dissipation in the TPA6011A4 andmaximum ambient temperatures is shown in Table 6 .
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PD(max)
2V2
DD
2RL
(11)
ΘJA 1
Derating Factor 1
0.022 45°CW
(12)
TAMax TJMax ΘJA PD
150 45(0.6 2)96°C(15-dB crest factor)
(13)
TPA6011A4
SLOS392A – FEBRUARY 2002 – REVISED JULY 2004
Table 6. TPA6011A4 Power Rating, 5-V, 3- ΩStereo
PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENTAVERAGE OUTPUT POWER(W) (W/Channel) TEMPERATURE
4 2 W (3 dB) 1.7 -3 °C4 1 W (6 dB) 1.6 6 °C4 500 mW (9 dB) 1.4 24 °C4 250 mW (12 dB) 1.1 51 °C4 125 mW (15 dB) 0.8 78 °C4 63 mW (18 dB) 0.6 96 °C
Table 7. TPA6011A4 Power Rating, 5-V, 8- ΩStereo
PEAK OUTPUT POWER POWER DISSIPATION MAXIMUM AMBIENTAVERAGE OUTPUT POWER(W) (W/Channel) TEMPERATURE
2.5 1250 mW (3-dB crest factor) 0.55 100 °C2.5 1000 mW (4-dB crest factor) 0.62 94 °C2.5 500 mW (7-dB crest factor) 0.59 97 °C2.5 250 mW (10-dB crest factor) 0.53 102 °C
The maximum dissipated power (P
D(max)
) is reached at a much lower output power level for an 8- Ωload than fora 3- Ωload. As a result, this simple formula for calculating P
D(max)
may be used for an 8- Ωapplication.
However, in the case of a 3- Ωload, the P
D(max)
occurs at a point well above the normal operating power level.The amplifier may therefore be operated at a higher ambient temperature than required by the P
D(max)
formula fora 3- Ωload.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factorfor the PWP package is shown in the dissipation rating table. Use equation 12 to convert this to θ
JA.
.
To calculate maximum ambient temperatures, first consider that the numbers from the dissipation graphs are perchannel, so the dissipated power needs to be doubled for two channel operation. Given θ
JA
, the maximumallowable junction temperature, and the total internal dissipation, the maximum ambient temperature can becalculated using Equation 13 . The maximum recommended junction temperature for the TPA6011A4 is 150 °C.The internal dissipation figures are taken from the Power Dissipation vs Output Power graphs.
NOTE:
Internal dissipation of 0.6 W is estimated for a 2-W system with 15-dB crest factor perchannel.
Table 6 and Table 7 show that some applications require no airflow to keep junction temperatures in thespecified range. The TPA6011A4 is designed with thermal protection that turns the device off when the junctiontemperature surpasses 150 °C to prevent damage to the IC. Table 6 and Table 7 were calculated for maximumlistening volume without distortion. When the output level is reduced the numbers in the table changesignificantly. Also, using 8- Ωspeakers increases the thermal performance by increasing amplifier efficiency.
28
www.ti.com
PowerPAD i s a trademark of Texas Instruments
PWP (R-PDSO-G24)
THERMAL INFORMATION
THERMAL PAD MECHANICAL DATA
13
12
24
1
This PowerPAD™ pack age i ncorporat es an expos ed thermal pad that is designed to be attached directly to an
external heatsink. When t he t herm al pad i s soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addi t i on, through t he us e of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsi nk st ruc ture des i gned i nt o the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
The exposed thermal pad dimensions for thi s package are shown in the following illustration.
For additional inf orm at i on on t he P owerPA D pac k age and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, Powe rPAD Therm a lly E n hanced Package, Te xas Ins trumen ts Lit e rature No. SLMA002
and Application Brief, PowerPA D Made Easy, Texas I nstruments L iterat ure No. SLMA004. Both documents are
available at www.ti.com.
Exposed Thermal Pad Dimensions
NOTE: All linear dimensions are in millimeters
Top View
PPTD030
Exposed Thermal Pad
5,16
4,10
2,40
1,65
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPA6011A4PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA6011A4PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA6011A4PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA6011A4PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA6011A4PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA6011A4PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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