Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Features Description * I2C-Bus compatible The PT7C4311 serial real-time clock is a low-power * Includes time (Hour/Minute/Second) and calendar clock/calendar with a programmable square-wave output. (Century/Year/Month/Date/Day) counter functions Address and data are transferred serially via a 2-wire * Year 2000 compliant bidirectional bus. The clock/calendar provides seconds, * Automatic switch-over and deselect circuitry minutes, hours, day, date, month, and year information. * Time keeping voltage: 1.5V to 5.5V The date at the end of the month is automatically * Software clock calibration adjusted for months with fewer than 31 days, including * 56 bytes of general purpose RAM corrections for leap year. The clock operates in the 24- * Ultra-low battery supply current of 1A hour format indicator. * Low operating current of 300A * Battery or super cap back-up * Operating temperature: -40C to 85C * Automatic leap year compensation * Special software programmable output Table 1 shows the basic functions of PT7C4311. More details are shown in section: overview of functions. Ordering Information Part Number PT7C4311WE Table 1. Basic functions of PT7C4300 Item Function 1 Oscillator Package Lead free and Green 8-Pin SOIC PT7C4311 Source: Crystal: 32.768kHz Oscillator enable/disable - Oscillator fail detect 12-hour Time display 24-hour 2 Time 3 Time count chain enable/disable Programmable square wave output (Hz) 4 Programmable high/low level output 512Hz Century bit 2 5 Communication 2-wire I C bus 6 RAM 7 Battery backup 8 Clock calibration 56x8 PT0322(08/09) Ver: 2 1 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Block PT0322(08/09) Ver: 2 2 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Configuration Pin Description Pin no. Pin Type Description 1 X1 I Oscillator Circuit Input. Together with X1, 32.768kHz crystal is connected between them. Or external clock input. 2 X2 O Oscillator Circuit Output. Together with X1, 32.768kHz crystal is connected between them. 3 VBAT P Battery Supply Voltage. When VCC>VSO1, VCC will power the IC. While VCC<VSO1, VBAT will power the IC. 4 GND P Ground. 5 SDA I/O Serial Data Input/Output. SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open-drain output and requires an external pull-up resistor. 6 SCL I Serial Clock Input. SCL is used to synchronize data movement on the I2C serial interface. 7 FT/OUT O Frequency Test / Output Driver. Open drain. 512Hz output when Frequency Test is selected. Output DC level by register selection. Frequency Test is prior. 8 VCC P Supply Voltage. When VCC>VSO1, VCC will power the IC. While VCC<VSO1, VBAT will power the IC. Note: 1. VSO: Battery Back-up Switchover Voltage PT0322(08/09) Ver: 2 3 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Function Description Overview of Functions 1. Clock function CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100. 2. Interface with CPU 2-wire I2C interface. The PT7C4311 continually monitors VCC for an out of tolerance condition. Should VCC fall below VSO, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VSO, the device automatically switches from battery to VCC at VSO and recognizes inputs. 3. Oscillator enable/disable Oscillator and time count chain can be enabled or disabled at the same time by ST bit. 4. Calibration function With the calibration bits properly set, accuracy PT7C4311 can be improved to better than 2 ppm at 25C. PT0322(08/09) Ver: 2 4 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Registers 1. Allocation of registers Register definition Addr. (hex) *1 Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 Seconds (00-59) ST*2 S40 S20 S10 S8 S4 S2 S1 01 Minutes (00-59) x M40 M20 M10 M8 M4 M2 M1 02 Hours (00-23) CEB*3 CB*3 H20 H10 H8 H4 H2 H1 03 Days of the week (01-07) x x x x x W4 W2 W1 04 Dates (01-31) x x D20 D10 D8 D4 D2 D1 05 Months (01-12) x x x*8 MO10 MO8 MO4 MO2 MO1 06 Years (00-99) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 07 Control*3 OUT*4 FT*5 S*6 x x x x x 08~3F RAM Calibration*7 x x x Caution points: *1. PT7C4311 uses 3 bits for address. That is if write data to 08H, the data will be written to 00H address register. *2. Stop bit. When this bit is set to 1, oscillator and time count chain are both stopped. *3. CEB: Century Enable Bit. CB: Century Bit. *4. Control FT/OUT pin output DC level when 512Hz square wave is disabled. *5. Frequency Test. 512Hz square wave output is enabled at FT/OUT pin, which is using for frequency test. *6. Sign Bit. "1" indicates positive calibration; "0"indicates negative calibration. *7. Using for modifying count frequency. If 20ppm is wanted to slow down the count frequency, 10 (01010) should be loaded. Calibration will not affect FT/OUT output frequency. *8. Don't care. PT0322(08/09) Ver: 2 5 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 2. Control and status register Addr. (hex) Description D7 D6 D5 07 Control (default) OUT 0 FT 0 S 1 D4 1 a) OUT * OUT: Set pin 7 output DC level.. OUT Data Read / Write 1 Set high level at pin 7. 0 Set low level at pin 7. Read / Write c) * Calibration bits S: Sign bit. S Read / Write Disable 512Hz output at pin 7. 1 Enable 512Hz output at pin 7. D2 D1 D0 1 Calibration 1 1 1 Description Default b) 512Hz output * FT: 512Hz square wave output Enable bit, using for Frequency Test. FT Data 0 D3 Description Default Data Description 1 Indicate positive calibration. 0 Indicate negative calibration. Default Calibration: Calibration occurs within a 64minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. For example, a reading of 512.01024Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. Clock calibration PT0322(08/09) Ver: 2 6 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 3. Time Counter Time digit display (in BCD code): * Second digits: Range from 00 to 59 and carried to minute digits when incremented from 59 to 00. * Minute digits: Range from 00 to 59 and carried to hour digits when incremented from 59 to 00. * Hour digits: See description on the /12, 24 bit. Carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. Addr. (hex) Description D7 00 Seconds (default) ST 0 S40 S20 S10 S8 S4 S2 S1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 01 Minutes (default) x*2 0 M40 M20 M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 02 Hours (default) CEB*3 CB*3 0 0 D6 D5 D4 H20 D3 D2 D1 D0 H10 H8 H4 H2 H1 Undefined Undefined Undefined Undefined Undefined Undefined * Note 1: ST bit: Stop oscillation and time count chain. * Note 2: Do not care. * Note 3: Century Enable Bit and Century Bit. 4. Days of the week Counter The day counter is a divide-by-7 counter that counts from 01 to 07 and up 07 before starting again from 01. Values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Addr. Description D7 D6 D5 D4 D3 D2 D1 D0 (hex) x Days of the week (default) Undefined 03 5. x Undefined x Undefined x Undefined x W4 W2 W1 Undefined Undefined Undefined Undefined Calendar Counter The data format is BCD format. * Day digits: Range from 1 to 31 (for January, March, May, July, August, October and December). Range from 1 to 30 (for April, June, September and November). Range from 1 to 29 (for February in leap years). Range from 1 to 28 (for February in ordinary years). Carried to month digits when cycled to 1. * Month digits: Range from 1 to 12 and carried to year digits when cycled to 1. * Year digits: Range from 00 to 99 and 00, 04, 08, ... , 92 and 96 are counted as leap years. Addr. (hex) Description 04 Dates (01-31) (default) x x D20 D10 D8 D4 D2 D1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 05 Months (01-12) (default) x x x M10 M8 M4 M2 M1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 06 Years (00-99) (default) Y80 Y40 Y20 Y10 Y8 Y4 Y2 Y1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined D7 D6 D5 D4 PT0322(08/09) D3 D2 D1 D0 Ver: 2 7 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Communication 1. I2C Bus Interface a) Overview of I2C-BUS The I2C bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. Both the SCL and SDA signals are held at high level whenever communications are not being performed. The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at high level. During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and on the receiving side the data is captured while the SCL line is at high level. In either case, the data is transferred via the SCL line at a rate of one bit per clock pulse. The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when its slave address matches the slave address in the received data. b) System Configuration All ports connected to the I2C bus must be either open drain or open collector ports in order to enable AND connections to multiple devices. SCL and SDA are both connected to the VDD line via a pull-up resistance. Consequently, SCL and SDA are both held at high level when the bus is released (when communication is not being performed). V cc RP RP SD A SCL M aster M CU Slave RTC O ther Peripheral D evice N ote: W hen there is only one m aster, the M CU is ready for driving SCL to "H " and R P of SCL m ay not required. Fig.1 System configuration PT0322(08/09) Ver: 2 8 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| c) Starting and Stopping I2C Bus Communications Fig.2 Starting and stopping on I2C bus START condition, repeated START condition, and STOP condition * START condition SDA level changes from high to low while SCL is at high level * STOP condition SDA level changes from low to high while SCL is at high level * Repeated START condition (RESTART condition) In some cases, the START condition occurs between a previous START condition and the next STOP condition, in which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the START condition, the SDA level changes from high to low while SCL is at high level. d) Data Transfers and Acknowledge Responses during I2C-BUS Communication * Data transfers Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount (bytes) of data that are transferred between the START condition and STOP condition. The address auto increment function operates during both write and read operations. Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level. The receiver (receiving side) captures data while the SCL line is at high level. *Note: with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART, or STOP condition. PT0322(08/09) Ver: 2 9 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| * Data acknowledge response (ACK signal) When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This does not include instances where the master device intentionally does not generate an ACK signal.) Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases the SDA line and the receiver sets the SDA line to low (= acknowledge) level. SCL from Master 8 2 1 9 SDA from transmitter (sending side) Release SDA Low active SDA from receiver (receiving side) ACK signal After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the transmitter. When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a STOP condition from the Master. e) Slave Address The I2C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin, slave addresses are allocated to each device. All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device responds to this communication only when the specified slave address it has received matches its own slave address. Slave addresses have a fixed length of 7 bits. See table for the details. An R/W bit is added to each 7-bit slave address during 8-bit transfers. 2. Operation Transfer data Read Write D1 h D0 h Slave address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 1 0 1 0 0 0 R / W bit bit 0 1 (= Read) 0 (= Write) I2C Bus's Basic Transfer Format S Start indication Sr Restart indication P Stop indication PT0322(08/09) A RTC Acknowledge A Master Acknowledge Ver: 2 10 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| a) Write via I2C bus Slave address (7 bits) S 1 Start b) * 1 0 1 0 write 0 0 A 0 A C K Slave address + write specification A C K Address Specifies the write start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Write data A P A C K Stop Read via I2C bus Standard read Slave address (7 bits) S 1 Start 1 0 1 0 0 write 0 Slave address (7 bits) 1 1 0 1 0 0 A C K Read 0 Addr. setting A A 0 Slave address + write specification Sr A 1 A C K Restart Slave address + read specification * Addr. setting A A C K Address Specifies the read start address. bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (1) Data is read from the specified start address and address auto increment. A A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (2) Address auto increment to set the address for the next data to be read. /A P N O Stop A C K Simplified read Slave address (7 bits) S 1 Start 1 0 1 0 0 Read 0 Slave address + read specification A 1 A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (1) Data is read from the address pointed by the internal address register and address auto increment. A A C K bit bit bit bit bit bit bit bit 7 6 5 4 3 2 1 0 Data read (2) Address register auto increment to set the address for the next data to be read. /A P N O Stop A C K Note: 1. The above steps are an example of transfers of one or two bytes only. There is no limit to the number of bytes transferred during actual communications. 2. 49H, 4AH are used as test mode address. Customer should not use the addresses. PT0322(08/09) Ver: 2 11 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Maximum Ratings Storage Temperature...................................................................................................................-55oCto +125oC Ambient Temperature with Power Applied.........................................................................-40oCto +85oC Supply Voltage to Ground Potential (Vcc to GND) ........................................................-0.3V to +7.0V DC Input (All Other Inputs except Vcc & GND).............................................................-0.3V to +7.0V DC Output Voltage......................................................................................................................-0.3V to +7.0V Power Dissipation.........................................................................................................................250mW Output Current...............................................................................................................................20mA Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol VCC Description Min Type Max Timing data and RAM data maintaining voltage 1.2 - 5.5 Timing data writing voltage 1.5 - 5.5 Timing data reading voltage 1.5 - 5.5 RAM data writing voltage 3.0 - 5.5 RAM data reading voltage 1.5 - 5.5 VIH Input high level 0.7 VCC - VCC+0.3 VIL Input low level -0.3 - 0.3 VCC TA Operating temperature -40 - 85 PT0322(08/09) Unit V C Ver: 2 12 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| DC Electrical Characteristics (Unless otherwise specified, VCC = 1.5 ~ 5.5 V, TA = -40 C to +85 C.) Sym. Description Pin ICC Timing data and RAM data maintaining voltage Timing data writing voltage Timing data reading voltage RAM data writing voltage RAM data reading voltage Supply voltage Battery Back-up Switchover Voltage3,4 Current consumption IST Standby current VCC VCC VBAT1 VSO2 Condition Min Typ Max Unit VCC - 1.2 - 5.5 VCC VCC VCC VCC VBAT - 1.5 1.5 3.0 1.5 2.0 3 5.5 5.5 5.5 5.5 5.5 - - VCC Switch freq. = 100kHz VBAT 0.80 - VBAT 0.50 - VBAT 0.305 300 A - - 70 A - 650 800 nA -0.3 - 0.7VCC - - SDA, SCL = VCC - 0.3V V V V IBAT Current consumption VBAT VIL Low-level input voltage - OSC on, VCC = 0V, VBAT = 3V, TA=25C - VIH High-level input voltage - - SDA FT/ OUT SCL IOL = 3mA - - - - - 5.5 IIL Low-level output voltage Pull-up Supply voltage (Open drain) Input leakage current 0.3VCC VCC +0.5 0.4 0<VIN<VCC - - 1 A IOZ Output current when OFF SDA 0<VOUT<VCC - - 1 A VOL V V Note: 1. After switchover (VSO), VBAT(min) can be 2.0V for crystal with RS=40k. 2. Switch-over and deselect point. 3. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted). 4. All voltages referenced to GND. 5. In 3.3V application, if initial battery voltage is 3.4V, it may be necessary to reduce battery voltage (i.e., through wave soldering the battery) in order to avoid inadvertent switchover/deselection for VCC - 10% operation. PT0322(08/09) Ver: 2 13 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| AC Electrical Characteristics Sym VHM VHL Description Rising and falling threshold voltage high Rising and falling threshold voltage low Value 0.8 VCC 0.2 VCC Unit V V Signal VHM VLM tr tf Over the operating range Symbol Item Min. Typ. Max. Unit 4.7 - 100 - kHz s ns ns fSCL tSU;STA SCL clock frequency START condition set-up time tHD;STA START condition hold time 4 - - tSU;DAT tHD;DAT1 tHD;DAT2 Data set-up time (RTC read/write) Data hold time (RTC write) Data hold time (RTC read) 250 0 0 - - tSU;STO STOP condition setup time 4.7 - - tBUF Bus idle time between a START and STOP condition 4.7 - - s tLOW When SCL = "L" 4.7 - - s tHIGH When SCL = "H" 4 - - s tr Rise time for SCL and SDA - - 1 s tf Fall time for SCL and SDA - - 0.3 s s s s Timing Diagram S SCL Sr tLOW fSCL tHIGH P tHD;STA tSP tSU;STA tBUF SDA tHD;STA S Start condition Sr Restart condition tSU;DAT tHD;DAT P tSU;STA tSU;STO tHD;STA Stop condition PT0322(08/09) Ver: 2 14 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Recommended Layout for Crystal Note: The crystal, traces and crystal input pins should be isolated from RF generating signals. Built-in Capacitors Specifications and Recommended External Capacitors Parameter Symbol Typ Unit X1 to GND CG 18 pF Build-in capacitors 18 pF X2 to GND CD Recommended External X1 to GND C1 8 pF capacitors X2 to GND C2 8 pF Note: The frequency of crystal can be optimized by external capacitor C1 and C2, for frequency=32.768Hz, C1 and C2 should meet the equation as below: Cpar + [(C1+CG)*(C2+CD)]/ [(C1+CG)+(C2+CD)] =CL Cpar is all parasitical capacitor between X1 and X2. CL is crystal's load capacitance. Crystal Specifications Parameter Nominal Frequency Series Resistance Load Capacitance Symbol fO ESR CL Min - Typ 32.768 12.5 PT0322(08/09) Max 70 - Unit kHz k pF Ver: 2 15 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information WE(Lead free and Green 8-Pin SOIC) 8 .149 .157 .0099 0.25 o .0196 0.50 x 45 3.78 3.99 .0075 .0098 0-8o 0.40 1.27 1 .189 .196 .016 .026 0.406 0.660 REF 4.80 5.00 0.19 0.25 .016 .050 .2284 .2440 5.80 6.20 .053 .068 1.35 1.75 X.XX X.XX SEATING PLANE .050 BSC 1.27 .0040 .0098 DENOTES DIMENSIONS IN MILLIMETERS Note: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012 AA 0.10 0.25 .013 0.330 .020 0.508 PT0322(08/09) Ver: 2 16 Data Sheet PT7C4311 Real-time Clock Module (I2C Bus) ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Notes Email: support@pti.com.cnWeb Site: www.pti.com.cn, www.pti-ic.com China: No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Asia Pacific: Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 U.S.A.: 3545 North First Street, San Jose, California 95134, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100 Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation. PT0322(08/09) Ver: 2 17