Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 LM8272 Dual RRIO, High Output Current & Unlimited Cap Load Op Amp in Miniature Package 1 Features 3 Description (VS = 12V, TA = 25C, Typical values unless specified). 1 * * * * * * * * * * GBWP 15MHz Wide supply voltage range 2.5 V to 24 V Slew rate 15 V/s Supply current/channel 0.95 mA Cap load tolerance Unlimited Output short circuit current 13 0mA Output current (1 V from rails) 65 mA Input common mode voltage 0.3 V beyond rails Input voltage noise 15 nV/Hz Input current noise 1.4 pA/Hz 2 Applications * * * * TFT-LCD flat panel VCOM driver A/D converter buffer High side/low side sensing Headphone amplifier The LM8272 is a Rail-to-Rail input and output Op Amp which can operate with a wide supply voltage range. This device has high output current drive, greater than Rail-to-Rail input common mode voltage range, and unlimited capacitive load drive capability, while requiring only 0.95mA/channel supply current. It is specifically designed to handle the requirements of flat panel TFT panel VCOM driver applications as well as being suitable for other low power and medium speed applications which require ease of use and enhanced performance over existing devices. Greater than Rail-to-Rail input common mode voltage range with 50 dB of Common Mode Rejection allows high side and low side sensing among many applications without concerns for exceeding the range and with no compromise in accuracy. An exceptionally wide operating supply voltage range of 2.5 V to 24 V removes any concerns over functionality under extreme conditions and offers flexibility of use in multitude of applications. In addition, most device parameters are insensitive to power supply variations. This design enhancement is yet another step in simplifying its usage. The LM8272 is offered in the 8-pin VSSOP package. Device Information(1) PART NUMBER LM8272 PACKAGE VSSOP (8) BODY SIZE (NOM) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic Large Signal Step Response for Various Cap. Load 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. 5V Electrical Characteristics ..................................... 12V Electrical Characteristics ................................... Typical Performance Characteristics ........................ Application and Implementation ........................ 14 7.1 Block Diagram and Operational Description A) Input Stage: ......................................................... B) Output Stage: ..................................................... C) Output Voltage Swing Close to V-: .................... Driving Capactive Loads: ........................................ Estimating the Output Voltage Swing ..................... Output Short Circuit Current and Dissipation Issues:...................................................................... 7.7 Other Application Hints: .......................................... 7.8 LM8272 Advantages: .............................................. 7.2 7.3 7.4 7.5 7.6 8 17 18 18 Device and Documentation Support.................. 19 8.1 8.2 8.3 8.4 9 14 15 15 16 16 Community Resources............................................ Trademarks ............................................................. Electrostatic Discharge Caution .............................. Glossary .................................................................. 19 19 19 19 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (August 2014) to Revision F Page * Changed pin 5 From: -IN B To: +IN B Non-Inverting Input B in the Pin Functions table ....................................................... 3 * Changed pin 6 From: +IN B To: -IN B Inverting Input B in the Pin Functions table............................................................... 3 * Moved "Storage temperature range" to the Absolute Maximum Ratings (1) (2) ........................................................................ 4 * Changed Handling Ratings To: ESD Ratings ........................................................................................................................ 4 Changes from Revision D (March 2013) to Revision E Page * Changed data sheet structure and organization. Added, updated, or renamed the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Mechanical, Packaging, and Ordering Information. ............................................................................................................................................................. 1 * Deleted TJ = 25C................................................................................................................................................................... 5 * Deleted TJ = 25C .................................................................................................................................................................. 6 Changes from Revision C (March 2013) to Revision D * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 18 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 5 Pin Configuration and Functions 8-Pin VSSOP Top View Pin Functions PIN I/O DESCRIPTION NUMBER NAME 1 OUT A O Output A 2 -IN A I Inverting Input A 3 +IN A I Non-Inverting Input A 4 V- I Negative Supply 5 +IN B I Non-Inverting Input B 6 -IN B I Inverting Input B 7 OUT B O Output B 8 V+ I Positive Supply Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 3 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) MIN VIN Differential Output Short Circuit Duration MAX UNIT +/-10 V See (3) (4) Supply Voltage (V+ - V-) 27 V V+ +0.3, V- -0.3 V +150 C +150 C Infrared or Convection (20 sec.) 235 C Wave Soldering (10 sec.) 260 C Voltage at Input/Output pins Junction Temperature (5) -65 Storage temperature range, Tstg Soldering Information: (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Rating indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. Output short circuit duration is infinite for VS 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is 1.5 ms. The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. 6.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) 2000 Machine Model (MM) (3) 200 UNIT V Human body model, 1.5 k in series with 100 pF. Machine Model, 0 is series with 200 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply Voltage (V+ - V-) Operating Temperature Range (1) (1) NOM MAX UNIT 2.5 24 V -40 +85 C The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. 6.4 Thermal Information THERMAL METRIC (1) RJA (1) (2) 4 Junction-to-ambient thermal resistance (2) DGK 8 Pins 235 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(max), RJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/ RJA. All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 6.5 5V Electrical Characteristics Unless otherwise specified, all limited ensured for V+ = 5V, V- = 0V, VCM = 0.5V, VO = V+/2, and RL > 1M to V-. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS VOS Input Offset Voltage VCM = 0.5V & VCM = 4.5V TC VOS Input Offset Average Drift VCM = 0.5V & VCM = 4.5V (3) IB Input Bias Current See IOS Input Offset Current CMRR Common Mode Rejection Ratio VCM stepped from 0V to 5V +PSRR Positive Power Supply Rejection Ratio V+ from 4.5V to 13V CMVR Input Common-Mode Voltage Range CMRR > 50dB TYP (1) LIMIT (2) UNIT +/-0.7 +/-5 +/- 7 mV max +/-2 -- -- 2.00 2.70 A max 20 250 400 nA max 80 64 61 dB min 100 78 74 dB min -0.3 -0.1 0.0 V max 5.3 5.1 5.0 V min 80 64 60 dB min V min (4) AVOL Large Signal Voltage Gain VO = 0.5 to 4.5V, RL = 10k to V+/2 VO Output Swing High RL = 10k to V- 4.93 4.85 ISOURCE = 5mA 4.85 4.70 Output Swing Low RL = 10k to V+ 215 250 ISINK = 5mA 300 350 Output Short Circuit Current Sourcing to V- VID = 200mV (5) 100 -- Sinking to V+ VID = -200mV (5) 100 -- ISC V/C mV max mA IOUT Output Current VID = 200mV, VO = 1V from rails 55 -- mA IS Supply Current (Both Channel) No load, VCM = 0.5V 1.8 2.3 2.8 mA max SR Slew Rate (6) AV = +1, VI = 5VPP 12 -- V/s fu Unity Gain Frequency VI = 10mVp, RL = 2K to V+/2 7.5 -- MHz GBWP Gain-Bandwidth Product f = 50KHz 13 -- MHz Phim Phase Margin VI = 10mVp, RL = 2k to V+/2 55 -- deg en Input-Referred Voltage Noise f = 2KHz, RS = 50 15 -- nV/Hz in Input-Referred Current Noise f = 2KHz 1.4 -- pA/Hz fmax Full Power Bandwidth ZL = (20pF || 10k) to V+/2 700 -- kHz (1) (2) (3) (4) (5) (6) Typical Values represent the most likely parametric norm. All limits are ensured by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Short circuit test is a momentary test. Output short circuit duration is infinite for VS 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 5 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com 6.6 12V Electrical Characteristics Unless otherwise specified, all limited ensured for V+ = 12V, V- = 0V, VCM = 6V, VO = 6V, and RL > 1M to V-. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS VOS Input Offset Voltage VCM = 0.5V & VCM = 11.5V TC VOS Input Offset Average Drift VCM = 0.5V & VCM = 11.5V (3) IB Input Bias Current See IOS Input Offset Current CMRR Common Mode Rejection Ratio VCM stepped from 0V to 12V +PSRR Positive Power Supply Rejection Ratio V+ from 4.5V to 13V, VCM = 0.5V -PSRR Negative Power Supply Rejection Ratio CMVR Input Common-Mode Voltage Range TYP (1) LIMIT (2) UNIT +/-0.7 +/-7 +/- 9 mV max +/-2 -- -- 2.00 2.80 A max 30 275 550 nA max 88 74 72 dB min 100 78 74 dB min 85 -- dB -0.3 -0.1 0 V max 12.3 12.1 12.0 V min 83 74 70 dB min V min (4) CMRR > 50dB AVOL Large Signal Voltage Gain VO = 1V to 11V RL = 10k to V+/2 VO Output Swing High RL 10k to V+/2 11.8 11.7 ISOURCE = 5mA 11.6 11.5 Output Swing Low RL = 10k to V+/2 0.25 0.3 .40 .45 Output Short Circuit Current Sourcing to V- VID = 200mV (5) 130 110 130 110 ISC ISINK = 5mA + Sinking to V VID = 200mV (5) V/C V max mA min IOUT Output Current VID = 200mV, VO = 1V from rails 65 -- mA IS Supply Current (Both Channel) No load, VCM = 0.5V 1.9 2.4 2.9 mA max SR Slew Rate (6) AV = +1, VI = 10VPP, CL = 10pF 15 -- AV = +1, VI = 10VPP, CL = 0.1F 1 -- V/s ROUT Close Loop Output Resistance AV = +1, f = 100KHz 3 -- fu Unity Gain Frequency VI = 10mVp, RL = 2k to V+/2 8 -- MHz GBWP Gain-Bandwidth Product f = 50KHz 15 -- MHz Phim Phase Margin VI = 10mVp, RL = 2k to V+/2 57 -- Deg GM Gain Margin VI = 10mVp, RL = 2k to V+/2 20 -- dB AV = +1, RL = 2k to V /2 12.5 -- AV = +1, RL = 600 to V+/2 10.5 -- AV = +10, RL = 600 to V+/2 1.0 -- -3dB BW (1) (2) (3) (4) (5) (6) 6 Small Signal -3db Bandwidth + MHz Typical Values represent the most likely parametric norm. All limits are ensured by testing or statistical analysis. Offset voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. Positive current corresponds to current flowing into the device. Short circuit test is a momentary test. Output short circuit duration is infinite for VS 6V at room temperature and below. For VS > 6V, allowable short circuit duration is 1.5ms. Slew rate is the slower of the rising and falling slew rates. Connected as a Voltage Follower. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 12V Electrical Characteristics (continued) Unless otherwise specified, all limited ensured for V+ = 12V, V- = 0V, VCM = 6V, VO = 6V, and RL > 1M to V-. Boldface limits apply at the temperature extremes. PARAMETER TEST CONDITIONS TYP (1) LIMIT (2) 15 -- nV/Hz UNIT en Input-Referred Voltage Noise f = 2KHz, RS = 50 in Input-Referred Current Noise f = 2KHz 1.4 -- pA/Hz fmax Full Power Bandwidth ZL = (20pF || 10k) to V+/2 300 -- kHz THD+N Total Harmonic Distortion +Noise AV = +2, RL = 2k to V+/2 VO = 8VPP, VS = 5V 0.02% -- CT Rej. Cross-Talk Rejection f = 5MHz, Driver RL = 10k to V+/2 68 -- Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 dB 7 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com 6.7 Typical Performance Characteristics Figure 1. VOS Distribution Figure 2. VOS vs. VCM for 3 Representative Units Figure 3. VOS vs. VCM for 3 Representative Units Figure 4. VOS vs. VCM for 3 Representative Units Figure 5. VOS vs. VS for 3 Representative Units 8 Figure 6. VOS vs. VS for 3 Representative Units Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 Typical Performance Characteristics (continued) Figure 7. VOS vs. VS for 3 Representative Units Figure 8. IB vs. VS Figure 9. IB vs. VS Figure 10. IS vs. VCM Figure 12. IS vs. VS Figure 11. IS vs. VCM Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 9 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com Typical Performance Characteristics (continued) 10 Figure 13. IS vs. VS Figure 14. CMRR vs. Frequency Figure 15. +PSRR vs. Frequency Figure 16. -PSRR vs. Frequency Figure 17. Open Loop Gain/Phase for Various Supplies Figure 18. Closed Loop Frequency Response for Various Gains Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 Typical Performance Characteristics (continued) Figure 19. Closed Loop Frequency Response for Various Gains Figure 20. Closed Loop Frequency Response for Various RL Figure 21. Maximum Output Swing vs. Load (1% Distortion) Figure 22. Maximum Output Swing vs. Frequency (1% Distortion) Figure 23. Closed Loop Small Signal Frequency Response for Various CL Figure 24. Overshoot vs. Cap Load Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 11 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com Typical Performance Characteristics (continued) 12 Figure 25. Settling Time (1%) & Slew Rate vs. Cap Load Figure 26. VOUT from V+ vs. ISOURCE Figure 27. VOUT from V- vs. ISINK Figure 28. Step Response for Various Amplitudes Figure 29. Step Response for Various Amplitudes Figure 30. Large Signal Step Response for Various Cap Loads Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 Typical Performance Characteristics (continued) Figure 31. THD+N vs. Input Amplitude for Various Frequency Figure 32. Input Referred Noise Density Figure 33. Closed Loop Output Impedance vs. Frequency Figure 34. Crosstalk Rejection vs. Frequency Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 13 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com 7 Application and Implementation 7.1 Block Diagram and Operational Description A) Input Stage: As seen in Figure 35, the input stage consists of two distinct differential pairs (Q1-Q2 and Q3-Q4) in order to accommodate the full Rail-to-Rail input common mode voltage range. The voltage drop across R5, R6, R7 and R8 is kept to less than 200 mV in order to allow the input to exceed the supply rails. Q13 acts as a switch to steer current away from Q3-Q4 and into Q1-Q2, as the input increases beyond 1.4 of V+. This in turn shifts the signal path from the bottom stage differential pair to the top one and causes a subsequent increase in the supply current. In transitioning from one stage to another, certain input stage parameters (VOS, Ib, IOS, en, and in) are determined based on which differential pair is "on" at the time. Input Bias current, Ib, will change in value and polarity as the input crosses the transition region. In addition, parameter such as PSRR and CMRR which involve the input offset voltage will also be effected by changes in VCM across the differential pair transition region. Figure 35. Simplified Schematic Diagram 14 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 Block Diagram and Operational Description A) Input Stage: (continued) The input stage is protected with the combination of R9-R10 and D1, D2, D3 and D4 against differential input over-voltages. This fault condition could otherwise harm the differential pairs or cause offset voltage shift in case of prolonged over voltage. As shown in Figure 36, if this voltage reaches approximately 1.4V at 25C, the diodes turn on and current flow is limited by the internal series resistors (R9 and R10). The Absolute Maximum Rating of 10V differential on VIN still needs to be observed. With temperature variation, the point were the diodes turn on will change at the rate of 5mV/C Figure 36. Input Stage Current vs. Differential Input Voltage 7.2 B) Output Stage: The output stage (see Figure 35) is comprised of complimentary NPN and PNP common-emitter stages to permit voltage swing to within a Vce(sat) of either supply rail. Q9 supplies the sourcing and Q10 supplies the sinking current load. Output current limiting is achieved by limiting the Vce of Q9 and Q10. Using this approach to current limiting alleviates the drawback to the conventional scheme which requires one Vbe reduction in output swing. The frequency compensation circuit includes Miller capacitors from collector to base of each output transistor (see Figure 35, Ccomp9 and Ccomp10). At light capacitive loads, the high frequency gain of the output transistors is high, and the Miller effect increases the effective value of the capacitors thereby stabilizing the Op Amp. Large capacitive loads greatly decrease the high frequency gain of the output transistors thus lowering the effective internal Miller capacitance - the internal pole frequency increases at the same time a low frequency pole is created at the Op Amp output due to the large load capacitor. In this fashion, the internal dominant pole compensation, which works by reducing the loop gain to less than 0dB when the phase shift around the feedback loop is more than 180, varies with the amount of capacitive load and becomes less dominant when the load capacitor has increased enough. Hence the Op Amp is very stable even at high values of load capacitance resulting in the uncharacteristic feature of stability under all capacitive loads. 7.3 C) Output Voltage Swing Close to V-: The LM8272's output stage design allows voltage swings to within millivolts of either supply rail for maximum flexibility and improved useful range. Because of this design architecture, as can be seen from Figure 35 diagram, with Output approaching either supply rail, either Q9 or Q10 Collector-Base junction reverse bias will decrease. With output less than a Vbe from either rail, the corresponding output transistor operates near saturation. In this mode of operation, the transistor will exhibit higher junction capacitance and lower ft which will reduce Phase Margin. With the Noise Gain (NG = 1 + Rf/Rg, Rf & Rg are external gain setting resistors) of 2 or higher, there is sufficient Phase Margin that this reduction (in Phase Margin) is of no consequence. However, with lower Noise Gain (<2) and with less than 150mV voltage to the supply rail, if the output loading is light, the Phase Margin reduction could result in unwanted oscillations. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 15 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com C) Output Voltage Swing Close to V-: (continued) In the case of the LM8272, due to inherent architectural specifics, the oscillation occurs only with respect to Q10 when output swings to within 150mV of V-. However, if Q10 collector current is larger than its idle value of a few microamps, the Phase Margin loss becomes insignificant. In this case, 300A is the required Q10 collector current to remedy this situation. Therefore, when all the aforementioned critical conditions are present at the same time (NG < 2, VOUT < 150mV from supply rails, & output load is light) it is possible to ensure stability by adding a load resistor to the output to provide the necessary Q10 minimum Collector Current (300A). For 12V (or 6V) operation, for example, add a 39k resistor from the output to V+ to cause 300A output sinking current and ensure stability. This is equivalent to about 15% increase in total quiescent power dissipation. 7.4 Driving Capactive Loads: The LM8272 is specifically designed to drive unlimited capacitive loads without oscillations (see Figure 25). In addition, the output current handling capability of the device allows for good slewing characteristics even with large capacitive loads (Settling Time and Slew Rate vs. Cap Load plot). The combination of these features is ideal for applications such as TFT flat panel buffers, A/D converter input amplifiers, etc. However, as in most Op Amps, addition of a series isolation resistor between the Op Amp and the capacitive load improves the settling and overshoot performance. Output current drive is an important parameter when driving capacitive loads. This parameter will determine how fast the output voltage can change. Referring to Figure 25, two distinct regions can be identified. Below about 10,000pF, the output Slew Rate is solely determined by the Op Amp's compensation capacitor value and available current into that capacitor. Beyond 10nF, the Slew Rate is determined by the Op Amp's available output current. An estimate of positive and negative slew rates for loads larger than 100nF can be made by dividing the short circuit current value by the capacitor. 7.5 Estimating the Output Voltage Swing It is important to keep in mind that the steady state output current will be less than the current available when there is an input overdrive present. For steady state conditions, Figure 37 and Figure 38 plots can be used to predict the output swing. These plots also show several load lines corresponding to loads tied between the output and ground. In each case, the intersection of the device plot at the appropriate temperature with the load line would be the typical output swing possible for that load. For example, a 600- load can accommodate an output swing to within 100mV of V- and to 250mV of V+ (VS = 5V) corresponding to a typical 9.65VPP unclipped swing. Figure 37. Steady State Output Sourcing Characteristics with Load Lines 16 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 Estimating the Output Voltage Swing (continued) Figure 38. Steady State Output Sinking Characteristics with Load Lines 7.6 Output Short Circuit Current and Dissipation Issues: The LM8272 output stage is designed for maximum output current capability. Even though momentary output shorts to ground and either supply can be tolerated at all operating voltages, longer lasting short conditions can cause the junction temperature to rise beyond the absolute maximum rating of the device, especially at higher supply voltage conditions. Below supply voltage of 6V, output short circuit condition can be tolerated indefinitely. With the Op Amp tied to a load, the device power dissipation consists of the quiescent power due to the supply current flow into the device, in addition to power dissipation due to the load current. The load portion of the power itself could include an average value (due to a DC load current) and an AC component. DC load current would flow if there is an output voltage offset, or if the output AC average current is non-zero, or if the Op Amp operates in a single supply application where the output is maintained somewhere in the range of linear operation. Therefore: Ptotal = PQ + PDC + PAC PQ = IS * VS (Op Amp Quiescent Power Dissipation) PDC = IO * (Vr - Vo) (DC Load Power) PAC = See Table 1 below (1) (2) (3) (AC Load Power) where: * IS: Supply Current * VS: Total Supply Voltage (V+ - V-) * VO: Average Output Voltage * Vr: V+ for sourcing and V- for sinking current Table 1 below shows the maximum AC component of the load power dissipated by the Op Amp for standard Sinusoidal, Triangular, and Square Waveforms: Table 1. Normalized AC Power Dissipated in the Output Stage for Standard Waveforms PAC (W./V2) SINUSOIDAL TRIANGULAR SQUARE 50.7 x 10-3 46.9 x 10-3 62.5 x 10-3 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 17 LM8272 SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 www.ti.com The table entries are normalized to VS2/RL. To figure out the AC load current component of power dissipation, simply multiply the table entry corresponding to the output waveform by the factor VS2/RL. For example, with 12V supplies, a 600 load, and triangular waveform power dissipation in the output stage is calculated as: PAC = (46.9 x 10-3) * [242/600] = 45.0mW (4) 7.7 Other Application Hints: The use of supply decoupling is mandatory in most applications. As with most relatively high speed/high output current Op Amps, best results are achieved when each supply line is decoupled with two capacitors; a small value ceramic capacitor (0.01F) placed very close to the supply lead in addition to a large value Tantalum or Aluminum (> 4.7F). The large capacitor can be shared by more than one device if necessary. The small ceramic capacitor maintains low supply impedance at high frequencies while the large capacitor will act as the charge "bucket" for fast load current spikes at the Op Amp output. The combination of these capacitors will provide supply decoupling and will help keep the Op Amp oscillation free under any load. 7.8 LM8272 Advantages: Compared to other Rail-to-Rail Input/Output devices, the LM8272 offers several advantages such as: * Improved cross over distortion * Nearly constant supply current throughout the output voltage swing range and close to either rail. * Nearly constant Unity gain frequency (fu) and Phase Margin (Phim) for all operating supplies and load conditions. * No output phase reversal under input overload condition. 18 Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 LM8272 www.ti.com SNOS515F - OCTOBER 2000 - REVISED AUGUST 2015 8 Device and Documentation Support 8.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 8.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 8.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 8.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2000-2015, Texas Instruments Incorporated Product Folder Links: LM8272 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LM8272MM NRND VSSOP DGK 8 1000 Non-RoHS & Green Call TI Call TI -40 to 85 A60 LM8272MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A60 LM8272MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A60 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM8272MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM8272MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM8272MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM8272MM VSSOP DGK 8 1000 210.0 185.0 35.0 LM8272MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM8272MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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