LTC3858
1
3858fc
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Low IQ, Dual
2-Phase Synchronous
Step-Down Controller
High Effi ciency Dual 8.5V/3.3V Step-Down Converter
n Low Operating IQ: 170μA (One Channel On)
n Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 24V
n Wide VIN Range: 4V to 38V
n RSENSE or DCR Current Sensing
n Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
n OPTI-LOOP
®
Compensation Minimizes COUT
n Phase-Lockable Frequency (75kHz-850kHz)
n Programmable Fixed Frequency (50kHz-900kHz)
n Selectable Continuous, Pulse-Skipping or
Burst Mode
®
Operation at Light Loads
n Very Low Dropout Operation: 99% Duty Cycle
n Adjustable Output Voltage Soft-Start
n Power Good Output Voltage Monitor
n Output Overvoltage Protection
n Output Latch-Off Protection During Short Circuit
n Low Shutdown IQ: 8µA
n Internal LDO Powers Gate Drive from VIN or EXTVCC
n No Current Foldback During Start-Up
n Small 5mm × 5mm QFN Package
n Automotive Systems
n Battery Operated Digital Devices
n Distributed DC Power Systems
Effi ciency and Power Loss
vs Load Current
The LTC
®
3858 is a high performance dual step-down
switching regulator controller that drives all N-channel
synchronous power MOSFET stages. A constant frequency
current mode architecture allows a phase-lockable fre-
quency of up to 850kHz. Power loss and noise due to the
input capacitor ESR are minimized by operating the two
controller outputs out of phase.
The 170A no-load quiescent current extends operating
life in battery-powered systems. OPTI-LOOP compensa-
tion allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
LTC3858 features a precision 0.8V reference and a power
good output indicator. A wide 4V to 38V input supply range
encompasses a wide range of intermediate bus voltages
and battery chemistries.
Independent soft-start pins for each controller ramp the
output voltages during start-up. The output latch-off feature
protects the circuit in short-circuit conditions.
For a leaded 28-lead SSOP package with a fi xed current
limit and one PGOOD output, without phase modulation
or a clock output, see the LTC3858-1 data sheet.
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, µModule, PolyPhase, Linear Technology and the Linear
logo are registered trademarks and No RSENSE and UltraFast are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.
0.1µF
62.5k
3.3µH
680pF
150µF
4.7µF 22µF
50V
0.007Ω
20k 15k
VOUT1
3.3V
5A
150µF
0.1µF
193k
7.2µH
680pF
0.01Ω
20k
15k
VOUT2
8.5V
3.5A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND
PGND
SENSE1+SENSE2+
SENSE1–SENSE2–
VFB1 VFB2
ITH1 ITH2
VIN INTVCC
SS1 SS2
VIN
9V TO 38V
3858 TA01
0.1µF 0.1µF
LTC3858
OUTPUT CURRENT (A)
0.0001
40
EFFICIENCY (%)
POWER LOSS (mW)
50
60
70
80
0.001 0.01 0.1 1 10
3858 TA01b
30
20
10
0
90
100
10
100
1000
1
0.1
10000
EFFICIENCY
POWER LOSS
VIN = 12V
VOUT = 3.3V
FIGURE 12 CIRCUIT
LTC3858
2
3858fc
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
(Note 1)
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1
TOP VIEW
SENSE1–
FREQ
PHASMD
CLKOUT
PLLIN/MODE
SGND
RUN1
RUN2
BOOST1
BG1
VIN
PGND
EXTVCC
INTVCC
BG2
BOOST2
SENSE1+
VFB1
ITH1
SS1
ILIM
PGOOD1
TG1
SW1
SENSE2–
SENSE2+
VFB2
ITH2
SS2
PGOOD2
TG2
SW2
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
33
SGND
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3858EUH#PBF LTC3858EUH#TRPBF 3858 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3858IUH#PBF LTC3858IUH#TRPBF 3858 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Input Supply Voltage (VIN) ......................... –0.3V to 40V
Topside Driver Voltages
BOOST1, BOOST2 ................................. –0.3V to 46V
Switch Voltage (SW1, SW2) ........................ –5V to 40V
PLLIN/MODE,(BOOST1-SW1),
(BOOST2-SW2) ........................................... –0.3V to 6V
RUN1, RUN2 ............................................... –0.3V to 8V
Maximum Current Sourced into Pin
from Source >8V...............................................100µA
SENSE1+, SENSE2+, SENSE1–
SENSE2– Voltages ...................................... –0.3V to 28V
FREQ Voltages ..................................... –0.3V to INTVCC
ILIM, PHASMD Voltages ....................... –0.3V to INTVCC
EXTVCC ...................................................... –0.3V to 14V
ITH1, ITH2,VFB1, VFB2 Voltages ...................... –0.3V to 6V
PGOOD1, PGOOD2 Voltages ....................... –0.3V to 6V
SS1, SS2, INTVCC Voltages ......................... –0.3V to 6V
Operating Junction Temperature Range
(Note 2) .................................................. –40°C to 125°C
Maximum Junction Temperature (Note 3) ............ 125°C
Storage Temperature Range ................... –65°C to 150°C
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range 4 38 V
VFB1,2 Regulated Feedback Voltage (Note 4) ITH1,2 = 1.2V
–40°C to 125°C
–40°C to 85°C
l0.788
0.792
0.800
0.800
0.812
0.808
V
V
IFB1,2 Feedback Current (Note 4) ±5 ±50 nA
VREFLNREG Reference Voltage Line Regulation (Note 4) VIN = 4.5V to 38V 0.002 0.02 %/V
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless
otherwise noted.
LTC3858
3
3858fc
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VLOADREG Output Voltage Load Regulation (Note4)
Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l0.01 0.1 %
(Note4)
Measured in Servo Loop,
∆ITH Voltage = 1.2V to 2V
l–0.01 –0.1 %
gm1,2 Transconductance Amplifi er gm(Note 4) ITH1,2 = 1.2V, Sink/Source = 5µA 2 mmho
IQInput DC Supply Current (Note 5)
Pulse Skip or Forced Continuous Mode
(One Channel On)
RUN1 = 5V and RUN2 = 0V, VFB1 = 0.83V (No Load) or
RUN1 = 0V and RUN2 = 5V, VFB2 = 0.83V (No Load)
1.3 mA
Pulse Skip or Forced Continuous Mode
(Both Channels On)
RUN1,2 = 5V, VFB1,2 = 0.83V (No Load) 2 mA
Sleep Mode (One Channel On) RUN1 = 5V and RUN2 = 0V, VFB1 = 0.83V (No Load) or
RUN1 = 0V and RUN2 = 5V, VFB2 = 0.83V (No Load)
170 250 µA
Sleep Mode (Both Channels On) RUN1,2 = 5V, VFB1,2 = 0.83V (No Load) 300 450 µA
Shutdown RUN1,2 = 0V 8 20 µA
UVLO Undervoltage Lockout INTVCC Ramping Up
INTVCC Ramping Down
l
l3.6
4.0
3.8
4.2
4
V
V
VOVL Feedback Overvoltage Protection Measured at VFB1,2, Relative to Regulated VFB1,2 71013 %
ISENSE+SENSE+ Pin Current Each Channel ±1 µA
ISENSE–SENSE– Pin Current Each Channel
VOUT1,2 < INTVCC – 0.5V
VOUT1,2 > INTVCC + 0.5V 550
±1
950
µA
µA
DFMAX Maximum Duty Factor In Dropout, FREQ = 0V 98 99.4 %
ISS1,2 Soft-Start Charge Current VSS1,2 = 0V 0.7 1.0 1.4 µA
VRUN1,2 On RUN Pin On Threshold Voltage VRUN1, VRUN2 Rising l1.23 1.28 1.33 V
VRUN1,2 Hyst RUN Pin Hysteresis Voltage 50 mV
VSS1,2 LA SS Pin Latch-Off Arming Threshold Voltage VSS1, VSS2 Rising from 1V 1.9 2 2.1 V
VSS1,2 LT SS Pin Latch-Off Threshold Voltage VSS1, VSS2 Falling from 2V 1.3 1.5 1.7 V
IDSC1,2 LT SS Discharge Current Short-Circuit Condition VFB1,2 = 0V,
VSS1,2 = 5V
71013 µA
VSENSE(MAX) Maximum Current Sense Threshold Voltage VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V, ILIM = 0
VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V, ILIM = FLOAT
VFB1,2 = 0.7V, VSENSE1–,2– = 3.3V, ILIM = INTVCC
l
l
l
22
43
64
30
50
75
36
57
86
mV
mV
mV
Gate Driver
TG1,2 Pull-Up On-Resistance
Pull-Down On-Resistance
2.5
1.5
BG1,2 Pull-Up On-Resistance
Pull-Down On-Resistance
2.4
1.1
TG1,2 tr
TG1,2 tf
TG Transistion Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
16
ns
ns
BG1,2 tr
BG1,2 tf
BG Transistion Time:
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
28
13
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver 30 ns
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless
otherwise noted.
LTC3858
4
3858fc
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 2). VIN = 12V, VRUN1,2 = 5V, EXTVCC = 0V unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
BG/TG t1D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver 30 ns
tON(MIN) Minimum On-Time (Note 7) 95 ns
INTVCC Linear Regulator
VINTVCCVIN Internal VCC Voltage 6V < VIN < 38V, VEXTVCC = 0V 4.85 5.1 5.35 V
VLDOVIN INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 0V 0.7 1.1 %
VINTVCCEXT Internal VCC Voltage 6V < VEXTVCC < 13V 4.85 5.1 5.35 V
VLDOEXT INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 8.5V 0.6 1.1 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.5 4.7 4.9 V
VLDOHYS EXTVCC Hysteresis Voltage 250 mV
Oscillator and Phase-Locked Loop
f25k Programmable Frequency RFREQ = 25k, PLLIN/MODE = DC Voltage 105 kHz
f65k Programmable Frequency RFREQ = 65k, PLLIN/MODE = DC Voltage 375 440 505 kHz
f105k Programmable Frequency RFREQ = 105k, PLLIN/MODE = DC Voltage 835 kHz
fLOW Low Fixed Frequency VFREQ = 0V, PLLIN/MODE = DC Voltage 320 350 380 kHz
fHIGH High Fixed Frequency VFREQ = INTVCC, PLLIN/MODE = DC Voltage 485 535 585 kHz
fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l75 850 kHz
PGOOD1 and PGOOD2 Outputs
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
Hysteresis
–13 –10
2.5
–7 %
%
VFB with Respect to Set Regulated Voltage
VFB Ramping Positive
Hysteresis
710
2.5
13 %
%
tPG Delay for Reporting a Fault (PGOOD Low) 25 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
Note 2: The LTC3858 is tested under pulsed conditions such that TJ ≈ TA.
The LTC3858E is guaranteed to meet performance specifi cations from
0°C to 85°C. Specifi cations over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3858I is guaranteed over the
full –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature is determined by specifi c operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
T
J = TA + (PD • 34°C/W)
Note 4: The LTC3858 is tested in a feedback loop that servos VITH1,2 to a
specifi ed voltage and measures the resultant VFB1,2. The specifi cation at
85°C is not tested in production. This specifi cation is assured by design,
characterization and correlation to production testing at 125°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 7: The minimum on-time condition is specifi ed for an inductor
peak-to-peak ripple current ≥ of 40% IMAX (See Minimum On-Time
Considerations in the Applications Information section).
LTC3858
5
3858fc
TYPICAL PERFORMANCE CHARACTERISTICS
Effi ciency and Power Loss
vs Output Current Effi ciency vs Output Current
Load Step (Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step (Pulse-Skipping Mode) Inductor Current at Light Load Soft-Start
Effi ciency vs Input Voltage
OUTPUT CURRENT (A)
0.0001
40
EFFICIENCY (%)
50
60
70
80
0.001 0.01 0.1 1 10
3858 G02
30
20
10
0
90
100
VIN = 5V
VIN = 12V
VOUT = 3.3V
FIGURE 12 CIRCUIT
INPUT VOLTAGE (V)
0
EFFICIENCY (%)
90
92
94
40
3858 G03
88
86
84
80
10 20 30
515 25 35
82
98
96
FIGURE 12 CIRCUIT
VOUT = 3.3V
IOUT = 4A
OUTPUT CURRENT (A)
0.0001
40
EFFICIENCY (%)
POWER LOSS (mW)
50
60
70
80
0.001 0.01 0.1 1 10
3858 G01
30
20
10
0
90
100
10
100
1000
1
0.1
10000
FIGURE 12 CIRCUIT
VIN = 12V
VOUT = 3.3V
Burst Mode
OPERATION
PULSE-
SKIPPING
MODE
FORCED
CONTINUOUS
MODE
VOUT
100mV/DIV
AC-
COUPLED
IL
2A/DIV
20µs/DIV 3858 G04
VOUT = 3.3V
FIGURE 12 CIRCUIT
VOUT
100mV/DIV
AC-
COUPLED
IL
2A/DIV
20µs/DIV 3858 G05
VOUT = 3.3V
FIGURE 12 CIRCUIT
VOUT
100mV/DIV
AC-
COUPLED
IL
2A/DIV
20µs/DIV 3858 G06
VOUT = 3.3V
FIGURE 12 CIRCUIT
Burst Mode
OPERATION
2A/DIV
FORCED
CONTINUOUS
MODE
PULSE-
SKIPPING
MODE
2µs/DIV 3858 G07
VOUT = 3.3V
ILOAD = 200µA
FIGURE 12 CIRCUIT
VOUT2
2V/DIV
VOUT1
2V/DIV
20ms/DIV 3858 G08
FIGURE 12 CIRCUIT
LTC3858
6
3858fc
TYPICAL PERFORMANCE CHARACTERISTICS
Total Input Supply Current
vs Input Voltage
EXTVCC Switchover and INTVCC
Voltages vs Temperature INTVCC Line Regulation
Maximum Current Sense Voltage
vs ITH Voltage SENSE– Pin Input Bias Current
Maximum Current Sense
Threshold vs Duty Cycle
Foldback Current Limit Quiescent Current vs Temperature Shutdown Current vs Temperature
INPUT VOLTAGE (V)
5
SUPPLY CURRENT (µA)
350
20
3858 G10
200
100
10 15 25
50
0
400
300
250
150
30 35 40
300µA LOAD
FIGURE 12 CIRCUIT
VOUT = 3.3V
ONE CHANNEL ON
NO LOAD
TEMPERATURE (°C)
–45
EXTVCC AND INTVCC VOLTAGE (V)
5.4
30
3858 G11
4.8
4.4
–20 5 55
4.2
4.0
5.6
5.2
5.0
4.6
80 105 130
INTVCC
EXTVCC RISING
EXTVCC FALLING
INPUT VOLTAGE (V)
0
5.0
INTVCC VOLTAGE (V)
5.1
5.1
5.2
5.2
5101520
3858 G12
25 30 35 40
VSENSE COMMON MODE VOLTAGE (V)
0
–600
SENSE– CURRENT (µA)
–500
–550
–450
–400
–300
–350
–200
–250
0
510 15 20
3858 G14
25
–50
–100
–150
FEEDBACK VOLTAGE (V)
0
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
10
30
40
50
0.6
90
3858 G16
20
0.3
0.1 0.7
0.4
0.2 0.8
0.5 0.9
60
70
80 ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
ITH PIN VOLTAGE
0
CURRENT SENSE THRESHOLD (mV)
40
60
80
0.6 1.0
3858 G13
20
0
0.2 0.4 0.8 1.2 1.4
–20
–40
PULSE SKIPPING
FORCED CONTINUOUS
Burst Mode OPERATION
(FALLING)
Burst Mode OPERATION
(RISING)
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
5% DUTY CYCLE
DUTY CYCLE (%)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
40
60
80
3858 G15
20
020 40 50 100
80
60
10 30 90
70
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
TEMPERATURE (°C)
–45
110
QUIESCENT CURRENT (µA)
190
–20 30 55 130
3858 G17
230
210
150
130
170
580 105
PLLIN/MODE = 0
VIN = 12V
VOUT = 3.3V
ONE CHANNEL ON
TEMPERATURE (°C)
–45
SHUTDOWN CURRENT (µA)
8
9
10
30 80
3858 G18
7
6
–20 5 55 105 130
5
4
LTC3858
7
3858fc
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start Pull-Up Current
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
Regulated Feedback Voltage
vs Temperature
SENSE– Pin Input Current
vs Temperature
Shutdown Input Current
vs Input Voltage
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
TEMPERATURE (°C)
–45
SS PULL-UP CURRENT (µA)
1.15
30
3858 G19
1.00
0.90
–20 5 55
0.85
0.80
1.20
1.10
1.05
0.95
80 105 130
TEMPERATURE (°C)
–45
0.90
RUN PIN VOLTAGE (V)
0.95
1.05
1.10
1.15
1.40
1.25
555 80
3858 G20
1.00
1.30
1.35
1.20
–20 30 105 130
TEMPERATURE (°C)
–45
REGULATED FEEDBACK VOLTAGE (mV)
806
30
22554 G21
800
796
–20 5 55
794
792
808
804
802
798
80 105 130
TEMPERATURE (°C)
–45
–600
SENSE– CURRENT (µA)
–550
–200
–150
50
–50
–20 30 55 130
3858 G22
0
–100
–400
–350
–500
–450
–250
–300
580 105
VOUT = 3.3V
VOUT = 28V
INPUT VOLTAGE (V)
5
8
10
14
20 30
3858 G23
6
4
10 15 25 35 40
2
0
12
INPUT CURRENT (µA)
TEMPERATURE (°C)
–45
3.4
INTVCC VOLTAGE (V)
3.5
3.7
3.8
3.9
4.4
4.1
555 80
3858 G25
3.6
4.2
4.3
4.0
–20 30 105 130
Oscillator Frequency
vs Input Voltage
INPUT VOLTAGE (V)
5
OSCILLATOR FREQUENCY (kHz)
352
354
356
20 30
3858 G28
350
348
10 15 25 35 40
346
344
FREQ = GND
TEMPERATURE (°C)
–45
FREQUENCY (kHz)
700
30
3858 G24
400
200
–20 5 55
100
0
800
600
500
300
80 105 130
FREQ = INTVCC
FREQ = GND
LTC3858
8
3858fc
PIN FUNCTIONS
SENSE1–, SENSE2– (Pin 1, Pin 9): The (–) Input to the
Differential Current Comparators. When greater than
INTVCC – 0.5V, the SENSE– pin supplies current to the
current comparator.
FREQ (Pin 2): The Frequency Control Pin for the Internal
Voltage-Controlled Oscillator (VCO). Connecting this pin
to GND forces the VCO to a fi xed low frequency of 350kHz.
Connecting this pin to INTVCC forces the VCO to a fi xed
high frequency of 535kHz. Other frequencies between
50kHz and 900kHz can be programmed using a resistor
between FREQ and GND. An internal 20µA pull-up current
develops the voltage to be used by the VCO to control the
frequency
PHASMD (Pin 3): Control input to phase selector which
determines the phase relationships between controller 1,
controller 2 and the CLKOUT signal. Pulling this pin to
ground forces TG2 and CLKOUT to be out of phase 180°
and 60° with respect to TG1. Connecting this pin to INTVCC
forces TG2 and CLKOUT to be out of phase 240° and 120°
with respect to TG1. Floating this pin forces TG2 and
CLKOUT to be out of phase 180° and 90° with respect to
TG1. Refer to the Table 1.
CLKOUT (Pin 4): Output clock signal available to daisy-
chain other controller ICs for additional MOSFET driver
stages/phases. The output levels swing from INTVCC to
ground.
PLLIN/MODE (Pin 5): External Synchronization Input to
Phase Detector and Forced Continuous Mode Input. When
an external clock is applied to this pin, the phase-locked
loop will force the rising TG1 signal to be synchronized
with the rising edge of the external clock. When not syn-
chronizing to an external clock, this input, which acts on
both controllers, determines how the LTC3858 operates at
light loads. Pulling this pin to ground selects Burst Mode
operation. An internal 100k resistor to ground also invokes
Burst Mode operation when the pin is fl oated. Tying this pin
to INTVCC forces continuous inductor current operation.
Tying this pin to a voltage greater than 1.2V and less than
INTVCC – 1.3V selects pulse-skipping operation.
SGND (Pin 6, Exposed Pad Pin 33): Small-signal ground
common to both controllers, must be routed separately
from high current grounds to the common (–) terminals
of the CIN capacitors. The exposed pad must be soldered
to the PCB for rated thermal performance.
INTVCC and EXTVCC
vs Load Current
Latch-Off Threshold Voltages
vs Temperature
LOAD CURRENT (mA)
0
INTVCC VOLTAGE (V)
5.10
5.15
5.20
160
3858 G26
5.05
5.00
4.95 20 40 60 80 100 120 140 180 200
EXTVCC = 0V
VIN = 12V
EXTVCC = 8V
TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE (°C)
–45
1.2
INTVCC VOLTAGE (V)
1.3
1.5
1.6
1.7
2.3
2.2
1.9
555 80
3858 G27
1.4
2.0
2.1
1.8
–20 30 105 130
ARMING THRESHOLD
LATCH-OFF THRESHOLD
LTC3858
9
3858fc
PIN FUNCTIONS
RUN1, RUN2 (Pin 7, Pin 8): Digital Run Control Inputs for
Each Controller. Forcing either of these pins below 1.2V
shuts down that controller. Forcing both of these pins below
0.7V shuts down the entire LTC3858, reducing quiescent
current to approximately 8µA. Do NOT fl oat these pins.
ILIM (Pin 28): Current Comparator Sense Voltage Range
Inputs. Tying this pin to SGND, FLOAT or INTVCC sets the
maximum current sense threshold to one of three different
levels for both comparators.
INTVCC (Pin 19): Output of the Internal Linear Low Dropout
Regulator. The driver and control circuits are powered
from this voltage source. Must be decoupled to power
ground with a minimum of 4.7µF ceramic or other low
ESR capacitor. Do not use the INTVCC pin for any other
purpose.
EXTVCC (Pin 20): External Power Input to an Internal LDO
Connected to INTVCC. This LDO supplies INTVCC power,
bypassing the internal LDO powered from VIN whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in
the Applications Information section. Do not exceed 14V
on this pin.
PGND (Pin 21): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs
and the (–) terminal(s) of CIN.
VIN (Pin 22): Main Input Supply Pin. A bypass capacitor
should be tied between this pin and the signal ground
pin.
BG1, BG2 (Pin 23, Pin 18): High Current Gate Drives
for Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTVCC.
BOOST1, BOOST2 (Pin 24, Pin 17): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the BOOST and SW pins and Schottky diodes are
tied between the BOOST and INTVCC pins. Voltage swing
at the BOOST pins is from INTVCC to (VIN + INTVCC).
SW1, SW2 (Pin 25, Pin 16): Switch Node Connections
to Inductors.
TG1, TG2 (Pin 26, Pin 15): High Current Gate Drives for
Top N-Channel MOSFETs. These are the outputs of fl oat-
ing drivers with a voltage swing equal to INTVCC – 0.5V
superimposed on the switch node voltage SW.
PGOOD1, PGOOD2 (Pin 27, Pin 14): Open-Drain Logic
Output. PGOOD1,2 is pulled to ground when the voltage
on the VFB1,2 pin is not within ±10% of its set point.
SS1, SS2 (Pin 29, Pin 13): External Soft-Start Input. The
LTC3858 regulates the VFB1,2 voltage to the smaller of 0.8V
or the voltage on the SS1,2 pin. An internal 1µA pull-up
current source is connected to this pin. A capacitor to
ground at this pin sets the ramp time to fi nal regulated
output voltage. This pin is also used as the short-circuit
latchoff timer.
ITH1, ITH2 (Pin 30, Pin 12): Error Amplifi er Outputs and
Switching Regulator Compensation Points. Each associ-
ated channel’s current comparator trip point increases
with this control voltage.
VFB1, VFB2 (Pin 31, Pin 11): Receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
SENSE1+, SENSE2+ (Pin 32, Pin 10): The (+) Input to
the differential current comparators that are normally
connected to inductor DCR sensing networks or current
sensing resistors. The ITH pin voltage and controlled offsets
between the SENSE– and SENSE+ pins in conjunction with
RSENSE set the current trip threshold.
LTC3858
10
3858fc
FUNCTIONAL DIAGRAM
SW
25, 16
TOP
BOOST
24, 17
TG
26, 15 CB
CIN
D
DB
CLKOUT
PGND
BOT
BG
23, 18
INTVCC
INTVCC
VIN
C
OUT
V
OUT
3858 FD
RSENSE
DROP
OUT
DET BOT
TOP ON
S
R
Q
Q
SHDN
SLEEP
0.425V
ICMP
2.7V
0.55V
IR
3mV
SLOPE COMP
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
SENSE+
32, 10
SENSE–
1, 9
PGOOD1
VFB1
0.88V
0.72V
L
27
21
+
–
+
–
+
–
+
–
PGOOD2
FREQ
VFB2
0.88V
0.72V
+
–
+
–
+
–
+
–
14
+
–
+
–
SWITCH
LOGIC
VFB
31, 11
RA
CC
RC
CC2
RB
0.80V
TRACK/SS
0.88V
0.5µA
11V
RUN
7, 8
ITH
30, 12
SS
29, 13
+
–
CSS
1µA
10µA
SHDN
CURRENT
LIMIT
FOLDBACK
SHDN
RST
2(VFB)
SHORT CKT
LATCH-OFF
4
PHASMD
3
2
PLLIN/MODE
20µA
VCO
LDO
EN
INTVCC
5.1V
SYNC
DET
100k
CLP
CLK2
CLK1
5
ILIM
28
VIN
EXTVCC
20
22
LDO
PFD
EN
4.7V
5.1V
+
–
19
SGND
6
EA
OV
LTC3858
11
3858fc
OPERATION
(Refer to the Functional Diagram)
The LTC3858 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal op-
eration, each external top MOSFET is turned on when the
clock for that channel sets the RS latch, and is turned off
when the main current comparator, ICMP, resets the RS
latch. The peak inductor current at which ICMP trips and
resets the latch is controlled by the voltage on the ITH pin,
which is the output of the error amplifi er, EA. The error
amplifi er compares the output voltage feedback signal at
the VFB pin (which is generated with an external resistor
divider connected across the output voltage, VOUT
, to
ground) to the internal 0.800V reference voltage. When the
load current increases, it causes a slight decrease in VFB
relative to the reference, which causes the EA to increase
the ITH voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin. When
the EXTVCC pin is left open or tied to a voltage less than
4.7V, the VIN LDO (low dropout linear regulator) supplies
5.1V from VIN to INTVCC. If EXTVCC is taken above 4.7V,
the VIN LDO is turned off and the EXTVCC LDO is turned on.
Once enabled, the EXTVCC LDO supplies 5.1V from EXTVCC
to INTVCC. Using the EXTVCC pin allows the INTVCC power
to be derived from a high effi ciency external source such
as one of the LTC3858 switching regulator outputs.
Each top MOSFET driver is biased from the fl oating boot-
strap capacitor, CB, which normally recharges during each
switching cycle through an external diode when the top
MOSFET turns off. If the input voltage, VIN, decreases to
a voltage close to VOUT
, the loop may enter dropout and
attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET
off for about one-twelfth of the clock period every tenth
cycle to allow CB to recharge.
Shutdown and Start-Up (RUN1, RUN2
and SS1, SS2 Pins)
The two channels of the LTC3858 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either of
these pins below 1.26V shuts down the main control loop
for that controller. Pulling both pins below 0.7V disables
both controllers and most internal circuits, including the
INTVCC LDOs. In this state, the LTC3858 draws only 8µA
of quiescent current.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to a
higher voltage (for example, VIN), so long as the maximum
current into the RUN pin does not exceed 100µA.
The start-up of each controller’s output voltage, VOUT
, is
controlled by the voltage on the SS pin for that channel.
When the voltage on the SS pin is less than the 0.8V internal
reference, the LTC3858 regulates the VFB voltage to the SS
pin voltage instead of the 0.8V reference. This allows the
SS pin to be used to program a soft-start by connecting
an external capacitor from the SS pin to SGND. An internal
1µA pull-up current charges this capacitor creating a volt-
age ramp on the SS pin. As the SS voltage rises linearly
from 0V to 0.8V (and beyond up to the absolute maximum
rating of 6V), the output voltage VOUT rises smoothly from
zero to its fi nal value.
Short-Circuit Latch-Off
After the controller has been started and been given
adequate time to ramp up the output voltage, the SS
capacitor is used in a short-circuit time-out circuit. Spe-
cifi cally, once the voltage on the SS pin rises above 2V
(the arming threshold), the short-circuit timeout circuit is
enabled (see Figure 1). If the output voltage falls below
70% of its nominal regulated voltage, the SS capacitor
begins discharging with a net 9µA pull-down current on
the assumption that the output is in an overcurrent and/or
short-circuit condition. If the condition lasts long enough
LTC3858
12
3858fc
OPERATION
(Refer to the Functional Diagram)
to allow the SS pin voltage to fall below 1.5V (the latchoff
threshold), the controller will shut down (latch off) until
the RUN pin voltage or the VIN voltage is recycled.
The delay time from when a short-circuit occurs until the
controller latches off can be calculated using the follow-
ing equation
tLATCH ≈CSS
VSS –1.5V
9µA
where VSS is the initial voltage (must be greater than 2V)
on the SS pin at the time the short-circuit occurs. Normally
the SS pin voltage will have been pulled up to the INTVCC
voltage (5.1V) by the internal 1µA pull-up current.
Note that the two controllers on the LTC3858 have separate,
independent short-circuit latchoff circuits. Latchoff can be
overridden/defeated by connecting a resistor 150k or less
from the SS pin to INTVCC. This resistor provides enough
pull-up current to overcome the 9µA pull-down current
present during a short-circuit. Note that this resistor also
shortens the soft-start period.
Foldback Current
On the other hand, when the output voltage falls to less
than 70% of its nominal level, foldback current limiting
is also activated, progressively lowering the peak current
limit in proportion to the severity of the overcurrent or
short-circuit condition. Even if a short circuit is present
and the short-circuit latch-off is not yet armed (when
SS voltage has not yet reached 2V), a safe, low output
current is provided due to internal current foldback and
actual power wasted is low due to the effi cient nature of
the current mode switching regulator. Foldback current
limiting is disabled during the soft-start interval (as long
as the VFB voltage is keeping up with the SS voltage).
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous)
(PLLIN/MODE Pin)
The LTC3858 can be enabled to enter high effi ciency
Burst Mode operation, constant frequency pulse-skip-
ping mode, or forced continuous conduction mode at
low load currents. To select Burst Mode operation, tie the
PLLIN/ MODE pin to ground. To select forced continuous
operation, tie the PLLIN/MODE pin to INTVCC. To select
pulse-skipping mode, tie the PLLIN/MODE pin to a DC
voltage greater than 1.2V and less than INTVCC – 1.3V.
When a controller is enabled for Burst Mode operation, the
minimum peak current in the inductor is set to approxi-
mately 30% of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifi er EA will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.425V, the internal
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current. If one channel is shut down
and the other channel is in sleep mode, the LTC3858 draws
only 170µA of quiescent current. If both channels are in
sleep mode, the LTC3858 draws only 300µA of quiescent
current. In sleep mode, the load current is supplied by
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
enough, the ITH pin is reconnected to the output of the
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
INTVCC
2V
0.8V 1.5V
0V
1µA
–9µA
SS VOLTAGE
LATCH-OFF
COMMAND
SS PIN
CURRENT
OUTPUT
VOLTAGE
LATCH-OFF
ENABLE
SOFT-START INTERVAL
ARMING tLATCH
3858 F01
1µA
Figure 1. Latch-Off Timing Diagram
LTC3858
13
3858fc
OPERATION
(Refer to the Functional Diagram)
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IR, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller is in discontinuous operation.
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
Frequency Selection and Phase-Locked Loop section),
the inductor current is allowed to reverse at light loads
or under large transient conditions. The peak inductor
current is determined by the voltage on the ITH pin, just
as in normal operation. In this mode, the effi ciency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry. In
forced continuous mode, the output ripple is independent
of load current.
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode, the LTC3858 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference when compared to Burst Mode
operation. It provides higher light load effi ciency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3858’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTVCC or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and SGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 9
A phase-locked loop (PLL) is available on the LTC3858
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
phase detector adjusts the voltage (through an internal
lowpass fi lter) of the VCO input to align the turn-on of
controller 1’s external top MOSFET to the rising edge of
the synchronizing signal. Thus, the turn-on of controller 2’s
external top MOSFET is 180 degrees out of phase to the
rising edge of the external clock source.
The VCO input voltage is pre-biased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
pre-bias the loop fi lter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 1MHz, with a guarantee over all
manufacturing variations to be between 75kHz and 850kHz.
In other words, the LTC3858’s PLL is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling).
PolyPhase
®
Applications (CLKOUT and PHASMD Pins)
The LTC3858 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3858 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
LTC3858
14
3858fc
OPERATION
(Refer to the Functional Diagram)
Figure 2. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Effi ciency
between the two internal controllers, as summarized in
Table 1. The phases are calculated relative to the zero
degrees phase being defi ned as the rising edge of the top
gate driver output of controller 1 (TG1).
Table 1
VPHASMD CONTROLLER 2 PHASE CLKOUT PHASE
GND 180° 60°
Floating 180° 90°
INTVCC 240° 120°
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good (PGOOD1 and PGOOD2) Pins
Each PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the corresponding VFB pin
voltage is not within ±10% of the 0.8V reference voltage.
The PGOOD pin is also pulled low when the corresponding
RUN pin is low (shut down). When the VFB pin voltage
is within the ±10% requirement, the MOSFET is turned
off and the pin is allowed to be pulled up by an external
resistor to a source no greater than 6V.
Theory and Benefi ts of 2-Phase Operation
Why the need for 2-phase operation? Up until the 2-phase
family, constant frequency dual switching regulators
operated both channels in phase (i.e., single phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current fl owing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dual
switching regulator are operated 180 degrees out of phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together. The result is a signifi cant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating effi ciency.
Figure 2 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the LTC3858
2-phase dual switching regulator. An actual measurement of
the RMS input current under these conditions shows that
2-phase operation dropped the input current from 2.53ARMS
to 1.55ARMS. While this is an impressive reduction in itself,
remember that the power losses are proportional to IRMS2,
meaning that the actual power wasted is reduced by a
IIN(MEAS) = 2.53ARMS IIN(MEAS) = 1.55ARMS
3858 F02
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
LTC3858
15
3858fc
Figure 3. RMS Input Current Comparison
factor of 2.66. The reduced input ripple voltage also means
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances
and protection circuitry. Improvements in both conducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage VIN (Duty Cycle = VOUT/VIN). Figure 3 shows how
the RMS input current varies for single phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase op-
eration are not just limited to a narrow operating range,
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
OPERATION
(Refer to the Functional Diagram)
INPUT VOLTAGE (V)
0
INPUT RMS CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
010 20 30 40
3858 F03
SINGLE PHASE
DUAL CONTROLLER
2-PHASE
DUAL CONTROLLER
VO1 = 5V/3A
VO2 = 3.3V/3A
LTC3858
16
3858fc
APPLICATIONS INFORMATION
Figure 4. Sense Lines Placement with Inductor or Sense Resistor
The Typical Application on the fi rst page is a basic LTC3858
application circuit. LTC3858 can be confi gured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design tradeoff between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power effi cient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs and Schottky diodes are selected. Finally,
input and output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maximum
current limit of the converter. When ILIM is grounded, the
maximum current limit threshold voltage of the current
comparator is programmed to be 30mV. When ILIM is
fl oated, the maximum current limit threshold is 50mV.
When ILIM is tied to INTVCC, the maximum current limit
threshold is set to 75mV.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the cur-
rent comparators. The common mode voltage range on
these pins is 0V to 28V (Abs Max), enabling the LTC3858
to regulate output voltages up to a nominal 24V (allowing
margin for tolerances and transients).
The SENSE+ pin is high impedance over the full common
mode range, drawing at most ±1µA. This high impedance
allows the current comparators to be used in inductor
DCR sensing.
The impedance of the SENSE– pin changes depending on
the common mode voltage. When SENSE– is less than
INTVCC – 0.5V, a small current of less than 1µA fl ows out
of the pin. When SENSE– is above INTVCC + 0.5V, a higher
current (~550µA) fl ows into the pin. Between INTVCC – 0.5V
and INTVCC + 0.5V, the current transitions from the smaller
current to the higher current.
Filter components mutual to the sense lines should be
placed close to the LTC3858, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 4). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If inductor DCR
sensing is used (Figure 5b), resistor R1 should be placed
close to the switching node, to prevent noise from coupling
into sensitive small-signal nodes.
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE
3858 F04
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 5a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold voltage sets the peak of the induc-
tor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
RSENSE =VSENSE(MAX)
IMAX +ΔIL
2
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided in the Typical Performance Char-
acteristics section to estimate this reduction in peak output
current depending upon the operating duty factor.
LTC3858
17
3858fc
(5a) Using a Resistor to Sense Current (5b) Using the Inductor DCR to Sense Current
Figure 5. Current Sensing Methods
APPLICATIONS INFORMATION
Inductor DCR Sensing
For applications requiring the highest possible effi ciency
at high load currents, the LTC3850 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 5b. The DCR of the inductor represents the small
amount of DC resistance of the copper wire, which can be
less than 1m for today’s low value, high current inductors.
In a high current application requiring such an inductor,
power loss through a sense resistor would cost several
points of effi ciency compared to inductor DCR sensing.
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external fi lter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value
is:
RSENSE(EQUIV) =VSENSE(MAX)
IMAX +ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Thresh-
old Voltage (VSENSE(MAX)) in the Electrical Characteristics
table (30mV, 50mV or 75mV depending on the state of
the ILIM pin).
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coeffi cient of copper, which is approximately 0.4%/°C. A
conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor (RD) value, use the divider ratio:
RD=RSENSE(EQUIV)
DCRMAX atT
L(MAX)
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
This forces R1||R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1µA current.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
R1|| R2 =L
DCR at 20°C
()
•C1
VIN VIN
INTVCC
BOOST
TG
SW
BG
PLACE CAPACITOR NEAR
SENSE PINS
SENSE+
SENSE–
SGND
LTC3858
VOUT
RSENSE
3858 F05a
VIN VIN
INTVCC
BOOST
TG
SW
BG
*PLACE C1 NEAR
SENSE PINS
INDUCTOR
DCRL
SENSE+
SENSE–
SGND
LTC3858
VOUT
3858 F05b
R1
R2C1*
(R1||R2) • C1 = L
DCR RSENSE(EQ) = DCR R2
R1 + R2
LTC3858
18
3858fc
APPLICATIONS INFORMATION
The sense resistor values are:
R1=R1|| R2
RD
; R2 =R1• RD
1–RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
P
LOSS R1=V
IN(MAX) –V
OUT
()
•V
OUT
R1
Ensure that R1 has a power rating higher than this value.
If high effi ciency is necessary at light loads, consider
this power loss when deciding whether to use inductor
DCR sensing or sense resistors. Light load power loss
can be modestly higher with a DCR network than with a
sense resistor, due to the extra switching losses incurred
through R1. However, DCR sensing eliminates a sense
resistor, reduces conduction losses and provides higher
effi ciency at heavy loads. Peak effi ciency is about the same
with either method.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is effi ciency. A higher
frequency generally results in lower effi ciency because
of MOSFET gate charge losses. In addition to this basic
tradeoff, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher induc-
tance or higher frequency and increases with higher VIN:
ΔIL=1
f
()
L
()
VOUT 1– VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
30% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fi xed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for each
controller in the LTC3858: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTVCC voltage.
This voltage is typically 5.2V during start-up (see EXTVCC
Pin Connection). Consequently, logic-level threshold
MOSFETs must be used in most applications. The only
LTC3858
19
3858fc
APPLICATIONS INFORMATION
exception is if low input voltage is expected (VIN < 4V);
then, sub-logic level threshold MOSFETs (VGS(TH) < 3V)
should be used. Pay close attention to the BVDSS speci-
fi cation for the MOSFETs as well; many of the logic-level
MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
fl at divided by the specifi ed change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specifi ed VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =VOUT
VIN
Synchronous Switch Duty Cycle =V
IN −VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN =VOUT
VIN
IMAX
()
21+δ
()
RDS(ON) +
VIN
()
2IMAX
2
⎛
⎝
⎜⎞
⎠
⎟RDR
()
CMILLER
()
•
1
VINTVCC –V
THMIN
+1
VTHMIN
⎡
⎣
⎢⎤
⎦
⎥f
()
P
SYNC =VIN –V
OUT
VIN
IMAX
()
21+δ
()
RDS(ON)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current effi ciency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes D3 and D4 shown in Figure 12
conduct during the dead-time between the conduction of
the two power MOSFETs. This prevents the body diode of
the bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
could cost as much as 3% in effi ciency at high VIN. A 1A
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition losses
due to their larger junction capacitance.
CIN and COUT Selection
The selection of CIN is simplifi ed by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (VOUT)(IOUT) product needs to be used in the
formula shown in Equation 1 to determine the maximum
RMS capacitor current requirement. Increasing the out-
put current drawn from the other controller will actually
decrease the input RMS ripple current from its maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
LTC3858
20
3858fc
APPLICATIONS INFORMATION
Figure 6. Setting Output Voltage
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈IMAX
V
IN
VOUT
()
V
IN –V
OUT
()
⎡
⎣⎤
⎦1/ 2
(1)
Equation 1 has a maximum at VIN = 2VOUT
, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even signifi cant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3858, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
The benefi t of 2-phase operation can be calculated by
using Equation 1 for the higher power controller and
then calculating the loss that would have resulted if both
controller channels switched on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefi t of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the effi ciency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common CIN (s). Separat-
ing the sources and CIN may produce undesirable voltage
and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3858, is also
suggested. A 10 resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfi ed, the capacitance is adequate for fi ltering. The
output ripple (∆VOUT) is approximated by:
ΔVOUT ≈ΔILESR +1
8•f•C
OUT
⎛
⎝
⎜⎞
⎠
⎟
where fO is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
Setting Output Voltage
The LTC3858 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 6. The regulated output voltage
is determined by:
VOUT =0.8V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
To improve the frequency response, a feedforward ca-
pacitor, CFF
, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
1/2 LTC3858
VFB
VOUT
RBCFF
RA
3858 F06
Soft-Start (SS Pins)
The start-up of each VOUT is controlled by the voltage on
the respective SS pin. When the voltage on the SS pin is
less than the internal 0.8V reference, the LTC3858 regulates
the VFB pin voltage to the voltage on the SS pin instead
of 0.8V. The SS pin can be used to program an external
soft-start function.
LTC3858
21
3858fc
APPLICATIONS INFORMATION
Figure 7. Using the TRACK/SS Pin to Program Soft-Start
Soft-start is enabled by simply connecting a capacitor from
the SS pin to ground, as shown in Figure 7. An internal 1µA
current source charges the capacitor, providing a linear
ramping voltage at the SS pin. The LTC3858 will regulate
the VFB pin (and hence VOUT) according to the voltage on
the SS pin, allowing VOUT to rise smoothly from 0V to
its fi nal regulated value. The total soft-start time will be
approximately:
tSS =CSS •0.8V
1µ A
as discussed in the Effi ciency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 3 of the Electrical Characteristics.
For example, the LTC3858 INTVCC current is limited to less
than 32mA from a 40V supply when not using the EXTVCC
supply at 70°C ambient temperature:
T
J = 70°C + (32mA)(40V)(43°C/W) = 125°C
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTVCC) at maximum VIN.
When the voltage applied to EXTVCC rises above 4.7V, the
VIN LDO is turned off and the EXTVCC LDO is enabled. The
EXTVCC LDO remains on as long as the voltage applied to
EXTVCC remains above 4.5V. The EXTVCC LDO attempts
to regulate the INTVCC voltage to 5.1V, so while EXTVCC
is less than 5.1V, the LDO is in dropout and the INTVCC
voltage is approximately equal to EXTVCC. When EXTVCC
is greater than 5.1V, up to an absolute maximum of 14V,
INTVCC is regulated to 5.1V.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from one of the switching
regulator outputs (4.7V ≤ VOUT ≤ 14V) during normal
operation and from the VIN LDO when the output is out
of regulation (e.g., start-up, short-circuit). If more current
is required through the EXTVCC LDO than is specifi ed, an
external Schottky diode can be added between the EXTVCC
and INTVCC pins. In this case, do not apply more than 6V
to the EXTVCC pin and make sure that EXTVCC ≤ VIN.
Signifi cant effi ciency and thermal gains can be realized
by powering INTVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Effi ciency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT
. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
T
J = 70°C + (32mA)(8.5V)(43°C/W) = 82°C
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive INTVCC power from
the output.
1/2 LTC3858
SS
CSS
SGND
3858 F07
INTVCC Regulators
The LTC3858 features two separate internal P-channel low
dropout linear regulators (LDO) that supply power at the
INTVCC pin from either the VIN supply pin or the EXTVCC
pin depending on the connection of the EXTVCC pin. INTVCC
powers the gate drivers and much of the internal circuitry.
The VIN LDO and the EXTVCC LDO regulate INTVCC to 5.1V.
Each of these can supply a peak current of 50mA and must
be bypassed to ground with a minimum of 4.7µF low ESR
capacitor. Regardless of what type of bulk capacitor is
used, an additional 1µF ceramic capacitor placed directly
adjacent to the INTVCC and PGND pins is highly recom-
mended. Good bypassing is needed to supply the high
transient currents required by the MOSFET gate drivers
and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs are
being driven at high frequencies may cause the maximum
junction temperature rating for the LTC3858 to be exceeded.
The INTVCC current, which is dominated by the gate charge
current, may be supplied by either the VIN LDO or the
EXTVCC LDO. When the voltage on the EXTVCC pin is less
than 4.7V, the VIN LDO is enabled. Power dissipation for the
IC in this case is highest and is equal to VIN • IINTVCC. The
gate charge current is dependent on operating frequency
LTC3858
22
3858fc
APPLICATIONS INFORMATION
Figure 8. Capacitive Charge Pump for EXTVCC
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC Left Open (or Grounded). This will cause INTVCC
to be powered from the internal 5.1V regulator result-
ing in an effi ciency penalty of up to 10% at high input
voltages.
2. EXTVCC Connected Directly to VOUT
. This is the normal
connection for a 5V to 14V regulator and provides the
highest effi ciency.
3. EXTVCC Connected to an External Supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC. Ensure that EXTVCC < VIN.
4. EXTVCC Connected to an Output-Derived Boost Network.
For 3.3V and other low voltage regulators, effi ciency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with the capacitive charge
pump shown in Figure 8. Ensure that EXTVCC < VIN.
and turns it on. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: VBOOST =
VIN + VINTVCC. The value of the boost capacitor, CB, needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the external
Schottky diode must be greater than VIN(MAX).
When adjusting the gate drive level, the fi nal arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the effi ciency has
improved. If there is no change in input current, then there
is no change in effi ciency.
Fault Conditions: Current Limit and Current Foldback
When the output current hits the current limit, the output
voltage begins to drop. If the output voltage falls below
70% of its nominal output level, then the maximum
sense voltage is progressively lowered to about half of
its maximum selected value. Under short-circuit condi-
tions with very low duty cycles, the LTC3858 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time, tON(MIN), of the LTC3858 (≈95ns), the input volt-
age and inductor value:
ΔIL(SC) =tON(MIN)
VIN
L
⎛
⎝
⎜⎞
⎠
⎟
The resulting average short-circuit current is:
ISC =50% •ILIM(MAX)
RSENSE
–1
2ΔIL(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to fl ow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the control-
ler is operating.
EXTVCC
VIN
TG1
SW
BG1
PGND
1/2 LTC3858 RSENSE
VOUT
VN2222LL
COUT
3858 F08
MBOT
MTOP
CIN
VIN
L
D
BAT85 BAT85
BAT85
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the Functional Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is turned on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the top MOSFET switch
LTC3858
23
3858fc
APPLICATIONS INFORMATION
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
for as long as the overvoltage condition persists; if VOUT
returns to a safe level, normal operation automatically
resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Phase-Locked Loop and Frequency Synchronization
The LTC3858 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass fi lter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
When not prebiased, applying an external clock will invoke
traditional PLL operation. If the external clock frequency is
greater than the internal oscillator’s frequency, fOSC, then
current is sourced continuously from the phase detector
output, pulling up the VCO input. When the external clock
frequency is less than fOSC, current is sunk continuously,
pulling down the VCO input. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time cor-
responding to the phase difference. The voltage at the
VCO input is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
impedance and the internal fi lter capacitor, CLP
, holds the
voltage at the VCO input.
Note that the LTC3858 can only be synchronized to an
external clock whose frequency is within range of the
LTC3858’s internal VCO, which is nominally 55kHz to 1MHz.
This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock
and synchronization. Although it is not required that the
free-running frequency be near external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor DC Voltage 50kHz–900kHz
Any of the Above External Clock Phase–Locked to
External Clock
Figure 9. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (k)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3858 F09
400
200
500
700
900
300
100
065 75 85 95 105 115 125
LTC3858
24
3858fc
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3858 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <VOUT
VIN f
()
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3858 is approximately
95ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 130ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a signifi cant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the effi ciency and which change would
produce the most improvement. Percent effi ciency can
be expressed as:
%Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3858 circuits: 1) IC VIN current, 2) INTVCC
regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC input supply current given
in the Electrical Characteristics table, which excludes
MOSFET driver and control currents. VIN current typi-
cally results in a small (<0.1%) loss.
2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge, dQ,
moves from INTVCC to ground. The resulting dQ/dt is
a current out of INTVCC that is typically much larger
than the control circuit current. In continuous mode,
IGATECHG = f(QT + QB), where QT and QB are the gate
charges of the topside and bottom side MOSFETs.
Supplying INTVCC from an output-derived power source
through EXTVCC will scale the VIN current required
for the driver and control circuits by a factor of (Duty
Cycle)/(Effi ciency). For example, in a 20V to 5V applica-
tion, 10mA of INTVCC current results in approximately
2.5mA of VIN current. This reduces the midcurrent loss
from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current fl ows through L and
RSENSE, but is “chopped” between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs have
approximately the same RDS(ON), then the resistance
of one MOSFET can simply be summed with the resis-
tances of L, RSENSE and ESR to obtain I2R losses. For
example, if each RDS(ON) = 30m, RL = 50m, RSENSE
= 10m and RESR = 40m (sum of both input and
output capacitance losses), then the total resistance
is 130m. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Effi ciency varies as the inverse square of VOUT for the
same external components and output power level. The
LTC3858
25
3858fc
APPLICATIONS INFORMATION
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signifi cant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) • VIN • 2 • IO(MAX) • CRSS • f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20m to 50m of ESR. The
LTC3858 2-phase architecture typically halves this input
capacitance requirement over competing solutions.
Other losses including Schottky conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT
. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC fi ltered closed-loop response test
point. The DC step, rise time and settling at this test
point truly refl ects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 12 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a resistive load and a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the fi ltered and compensated
control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
LTC3858
26
3858fc
APPLICATIONS INFORMATION
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT
, causing a rapid drop in VOUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V (max), VOUT = 3.3V, IMAX = 5A,
VSENSE(MAX) = 75mV and f = 350kHz.
The inductance value is chosen fi rst based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
ΔIL=VOUT
f
()
L
()
1– VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
A 4.7µH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =VOUT
VIN f
()
=3.3V
22V 350kHz
()
=429ns
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (64mV):
RSENSE ≤64mV
5.73A =0.011Ω
Choosing 0.5% resistors: RA = 24.9k and RB = 77.7k yields
an output voltage of 3.296V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035/0.022, CMILLER = 215pF. At
maximum input voltage with T(estimated) = 50°C:
PMAIN =3.3V
22V 5A
()
21+0.005
()
50°C–25°C
()
⎡
⎣⎤
⎦
0.035Ω
()
+22V
()
25A
22.5Ω
()
215pF
()
•
1
5V – 2.3V +1
2.3V
⎡
⎣
⎢⎤
⎦
⎥350kHz
()
=331mW
A short-circuit to ground will result in a folded back cur-
rent of:
ISC =32mV
0.015Ω–1
2
95ns 22V
()
4.7µH
⎛
⎝
⎜⎞
⎠
⎟=2.98A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
P
SYNC =2.98A
()
21.125
()
0.022Ω
()
=220mW
which is less than full-load conditions.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02 for low output ripple volt-
age. The output ripple in continuous mode will be highest
at the maximum input voltage. The output voltage ripple
due to ESR is approximately:
V
ORIPPLE = RESR (∆IL) = 0.02(1.45A) = 29mVP-P
LTC3858
27
3858fc
APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. Figure 11 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at CIN? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the CIN capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3858 VFB pins’ resistive dividers connect to
the (+) terminals of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The fi lter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the INTVCC decoupling capacitor connected close
to the IC, between the INTVCC and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the “output side” of the LTC3858 and occupy minimum
PC trace area.
7. Use a modifi ed “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the ap-
plication. The frequency of operation should be maintained
over the input voltage range down to dropout and until
the output load drops below the low current operation
threshold—typically 10% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regula-
tor bandwidth optimization is not required. Only after
each controller is checked for its individual performance
should both controllers be turned on at the same time.
A particularly diffi cult region of operation is when one
controller channel is nearing its current comparator trip
point when the other channel is turning on its top MOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
LTC3858
28
3858fc
APPLICATIONS INFORMATION
Figure 10. Recommended Printed Circuit Layout Diagram
CB2
CB1
RPU1
PGOOD1
VPULL-UP
(<6V)
CINTVCC CIN
D1
1µF
CERAMIC
M1 M2
M3 M4 D2
+
CVIN
VOUT1
VIN
RIN
L1
L2
COUT1
VOUT1
GND
VOUT2
3858 F10
+
COUT2
+
RSENSE
RSENSE
RPU2
PGOOD2
VPULL-UP
(<6V)
fIN
1µF
CERAMIC
ITH1
VFB1
SENSE1+
SENSE1–
FREQ
SENSE2–
SENSE2+
VFB2
ITH2
SS2
SS1
PGOOD2
PGOOD1
TG1
SW1
BOOST1
BG1
VIN
PGND
EXTVCC
INTVCC
BG2
BOOST2
SW2
TG2
PHASMD
CLKOUT
PLLIN/MODE
RUN1
RUN2
SGND
LTC3858
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
LTC3858
29
3858fc
APPLICATIONS INFORMATION
Figure 11. Branch Current Waveforms
RL1
D1
L1
SW1 RSENSE1 VOUT1
COUT1
VIN
CIN
RIN
RL2
D2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L2
SW2
3858 F11
RSENSE2 VOUT2
COUT2
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
LTC3858
30
3858fc
TYPICAL APPLICATIONS
Effi ciency vs Output Current Start-Up SW Node Waveforms
Figure 12. High Effi ciency Dual 8.5V/3.3V Step-Down Converter
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
RUN1
RUN2
FREQ
SS2
VFB2
SS1
ILIM
PHASMD
CLKOUT
PLLIN/MODE
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
1nF
RB1
215k
COUT1, COUT2: SANYO 10TPD150M
L1: SUMIDA CDEP105-3R2M
L2: SUMIDA CDEP105-7R2M
MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP
CF1
15pF
CITH1A 150pF
CSS1 0.1µF
CSS2 0.1µF
CITH1 820pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
9V TO 38V
D2
LTC3858
L1
3.3µH
L2
7.2µH
RSENSE1
7m
RSENSE2
10m
MBOT1
MTOP2
MTOP1
MBOT2
3858 F12
100k
100k
INTVCC
COUT1
150µF
VOUT1
3.3V
5A
VOUT2
8.5V
3A
CIN
22µF
COUT2
150µF
RA1
68.1k
RA2
44.2k
RB2
422k
CF2
39pF
RITH1 15k
C2
1nF
ITH2
CITH2 680pF
CITH2A 100pF
RITH2 27k
OUTPUT CURRENT (A)
0.00001 0.0001
40
EFFICIENCY (%)
50
60
70
80
0.001 0.01 0.1 1 10
3858 F12b
30
20
10
0
90
100
VIN = 12V
Burst Mode OPERATION
VOUT = 8.5V VOUT = 3.3V
3858 F12c
VOUT2
2V/DIV
VOUT1
2V/DIV
20ms/DIV 3858 F12d
SW1
5V/DIV
SW2
5V/DIV
1µs/DIV
LTC3858
31
3858fc
TYPICAL APPLICATIONS
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
RUN1
RUN2
FREQ
SS2
VFB2
SS1
ILIM
PHASMD
CLKOUT
PLLIN/MODE
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
1nF
RB1
143k
COUT1, COUT2: SANYO 10TPD150M
L1: SUMIDA CDEP105-2R5
L2: SUMIDA CDEP105-3R2M
MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP
CF1
22pF
CITH1A 100pF
CSS1 0.01µF
CSS2 0.01µF
CITH1 820pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
4V TO 38V
D2
LTC3858
L1
2.4µH
L2
3.2µH
RSENSE1
7m
RSENSE2
7m
MBOT1
MTOP2
MTOP1
MBOT2
3858 F13
100k
100k
INTVCC
COUT1
150µF
VOUT1
2.5V
5A
VOUT2
3.3V
5A
CIN
22µF
COUT2
150µF
RA1
68.1k
RA2
68.1k
RB2
215k
CF2
15pF
RITH1 22k
C2
1nF
ITH2
CITH2 820pF
CITH2A 150pF
RITH2 15k
High Effi ciency Dual 2.5V/3.3V Step-Down Converter
LTC3858
32
3858fc
TYPICAL APPLICATIONS
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
RUN1
RUN2
FREQ
SS2
VFB2
SS1
ILIM
PHASMD
CLKOUT
PLLIN/MODE
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
1nF
RB1
422k
COUT1: KEMET T525D476M016E035
COUT2: SANYO 10TPD150M
L1: SUMIDA CDEP105-8R8M
L2: SUMIDA CDEP105-4R3M
MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP
CF1
33pF
CITH1A 100pF
CSS1 0.01µF
CSS2 0.01µF
CITH1 680pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
12.5V TO 38V
D2
LTC3858
L1
8.8µH
L2
4.3µH
RSENSE1
10m
RSENSE2
7m
MBOT1
MTOP2
MTOP1
MBOT2
3858 TA02a
100k
100k INTVCC
COUT1
47µF
VOUT1
12V
3A
VOUT2
5V
5A
CIN
22µF
COUT2
150µF
RA1
30.1k
RA2
75k
RB2
393k
CF2
15pF
RFREQ
60k
RITH1 33k
C2
1nF
ITH2
CITH2 680pF
CITH2A 100pF
RITH2 17k
High Effi ciency Dual 12V/5V Step-Down Converter
LTC3858
33
3858fc
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
RUN1
RUN2
FREQ
SS2
VFB2
SS1
PLLIN/MODE
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
1nF
RB1
487k
COUT2: SANYO 10TPD150M
L1: SUMIDA CDRH105R-220M
L2: SUMIDA CDEP105-4R3M
MTOP1, MTOP2, MBOT1, MBOT2: VISHAY Si7848DP
CF1
18pF
CITH1A 100pF
CSS1 0.01µF
CSS2 0.01µF
CITH1 680pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
28V TO 38V
D2
LTC3858
L1
22µH
L2
4.3µH
RSENSE1
25m
RSENSE2
7m
MBOT1
MTOP2
MTOP1
MBOT2
3858 TA04
100k
100k INTVCC
COUT1
22µF
×2
CERAMIC
VOUT1
24V
1A
VOUT2
5V
5A
CIN
22µF
COUT2
150µF
RA1
16.9k
RA2
75k
RB2
392k
CF2
15pF
RFREQ
60k
RITH1 46k
C2
1nF
ITH2
CITH2 680pF
CITH2A 100pF
RITH2 17k
ILIM
PHASMD
CLKOUT
High Effi ciency Dual 24V/5V Step-Down Converter
TYPICAL APPLICATIONS
LTC3858
34
3858fc
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
RUN1
RUN2
FREQ
SS2
VFB2
SS1
ILIM
PHASMD
CLKOUT
PLLIN/MODE
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
1nF
RB1
28.7k
COUT1, COUT2: SANYO 2R5TPE220M
L1: SUMIDA CDEP105-0R4
L2: SUMIDA CDEP105-0R4
MTOP1, MTOP2: RENESAS RJK0305
MBOT1, MBOT2: RENESAS RJK0328
CF1
56pF
CITH1A 200pF
CSS1 0.01µF
CSS2 0.01µF
CITH1 1000pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
12V
D2
LTC3858
L1
0.47µH
L2
0.47µH
RSENSE1
4m
RSENSE2
4m
MBOT1
MTOP2
MTOP1
MBOT2
3858 TA03a
100k
100k INTVCC
COUT1
220µF
×2
VOUT1
1V
8A
VOUT2
1.2V
8A
CIN
22µF
COUT2
220µF
×2
RA1
115k
RA2
115k
RB2
57.6k
CF2
56pF
RFREQ
60k
RITH1 3.93k
C2
1nF
ITH2
CITH2 1000pF
CITH2A 200pF
RITH2 3.93k
High Effi ciency Dual 1V/1.2V Step-Down Converter
TYPICAL APPLICATIONS
LTC3858
35
3858fc
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
RUN1
RUN2
FREQ
SS2
VFB2
SS1
CLKOUT
PHASMD
ILIM
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
0.1µF
RB1
28.7k
COUT1, COUT2: SANYO 2R5TPE220M
L1, L2: VISHAY IHL P2525CZERR47M06
MTOP1, MTOP2: RENESAS RJK0305
MBOT1, MBOT2: RENESAS RJK0328
CF1
56pF
CITH1A 200pF
CSS1 0.01µF
CSS2 0.01µF
CITH1 1000pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
12V
D2
LTC3858
L1
0.47µH
L2
0.47µH
MBOT1
MTOP2
MTOP1
MBOT2
3858 TA05
100k
100k
RS1 1.18k
RS2 1.18k
INTVCC
COUT1
220µF
×2
VOUT1
1V
8A
VOUT2
1.2V
8A
CIN
22µF
COUT2
220µF
×2
RA1
115k
RA2
115k
RB2
57.6k
CF2
56pF
RFREQ
65k
RITH1 3.93k
C2
0.1µF
ITH2
CITH2 1000pF
CITH2A 220pF
RITH2 3.93k
High Effi ciency Dual 1V/1.2V Step-Down Converter with Inductor DCR Current Sensing
TYPICAL APPLICATIONS
LTC3858
36
3858fc
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 p 0.10
3.45 p 0.10
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 p0.05
3.50 REF
(4 SIDES)
4.10 p0.05
5.50 p0.05
0.25 p 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45o CHAMFER
R = 0.05
TYP
3.45 p 0.05
3.45 p 0.05
LTC3858
37
3858fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 12/09 Change to Absolute Maximum Ratings
Change to Electrical Characteristics
Change to Typical Performance Characteristics
Change to Pin Functions
Text Changes to Operation Section
Text Changes to Applications Information Section
Change to Table 2
Change to Figure 10
Changes to Related Parts
2
2, 3, 4
6
8, 9
11, 12, 13
21, 22, 23, 24, 26
23
28
38
B 08/10 Changes to Electrical Characteristics
Added Typical Application to Back Page and Updated Related Parts
2, 3, 4
38
C 12/10 Changes to Electrical Characteristics
Changes to Functional Diagram
Changes to Typical Applications
3
10
30 to 35, 38
LTC3858
38
3858fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
LT 1210 REV C • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
High Effi ciency 2-Phase 12V/150W Step-Down Converter
SENSE1+
SENSE1–
SENSE2–
SENSE2+
VFB1
ITH1
SGND
EXTVCC
VOUT
RUN1
RUN2
FREQ
SS2SS1
ITH1
VFB1 VFB2
SS1
ILIM
PHASMD
CLKOUT
PLLIN/MODE
PGOOD1
PGOOD2
BG1
SW1
BOOST1
TG1
VIN
INTVCC
PGND
TG2
BG2
BOOST2
SW2
C1
1nF
RB1
698k
COUT1, COUT2: SANYO 16TQC22M
L1, L2: SUMIDA CDEP106-6ROM
MTOP1, MTOP2: INFINEON BSZ097N04LS
MBOT1, MBOT2: INFINEON BSZ097N04LS
CF1
10pF
CITH1A 68pF
CSS1 0.1µF
CITH1 3300pF
CINT
4.7µF
CB1
0.47µF
CB2
0.47µF
D1
VIN
19V TO 28V
D2
LTC3858
L1
6µH
L2
6µH
RSENSE1
5m
RSENSE2
5m
MBOT1
MTOP2
MTOP1
MBOT2
3858 TA06
100k
100k
INTVCC
COUT1
22µF
16V
VOUT1
12V
12.5A
10µF
16V
CIN
10µF
50V
10µF
50V
COUT2
22µF
16V
10µF
16V
RA1
49.9k
RITH1 2.94k
C2
1nF
ITH2
PART NUMBER DESCRIPTION COMMENTS
LTC3859 Low IQ, Triple Output Buck/Buck/Boost Synchronous
DC/DC Controller
Outputs (≥5V) Remain in Regulation Through Cold Crank 2.5V ≤ VIN ≤ 38V,
VOUT(BUCKS) Up to 24V, VOUT(BOOST) Up to 60V, IQ = 55µA,
LTC3868/LTC3868-1 Low IQ, Dual Output 2-Phase Synchronous Step-
Down DC/DC Controllers with 99% Duty Cycle
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
4V ≤ VIN ≤ 24V, 0.8V ≤ VOUT ≤ 14V, IQ = 170µA
LTC3857/LTC3857-1 Low IQ, Dual Output 2-Phase Synchronous Step-
Down DC/DC Controllers with 99% Duty Cycle
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
4V≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA,
LTC3890/LTC3890-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,
4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA,
LTC3834/LTC3834-1 Low IQ, Synchronous Step-Down DC/DC Controllers Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,
4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, IQ = 30µA,
LTC3835/LTC3835-1 Low IQ, Synchronous Step-Down DC/DC Controllers Phase-Lockable Fixed Operating Frequency 140kHz to 650kHz,
4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, IQ = 80µA,
LT3845A Low IQ, High Voltage Synchronous Step-Down
DC/DC Controller
Adjustable Fixed Operating Frequency 100kHz to 500kHz, 4V ≤ VIN ≤ 60V,
1.23V ≤ VOUT ≤ 36V, IQ = 120µA, TSSOP-16
LTC3824 Low IQ, High Voltage DC/DC Controller, 100% Duty
Cycle
Selectable Fixed 200kHz to 600kHz Operating Frequency 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ VIN, IQ = 40µA, MSOP-10E
