4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet The SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C are 512K x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash(R) technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C write (Program or Erase) with a 2.7-3.6V power supply. These devices conforms to JEDEC standard pinouts for x16 memories. Features * Organized as 256K x16 * Security-ID Feature - SST: 128 bits; User: 128 words * Single Voltage Read and Write Operations * Fast Read Access Time: - 2.7-3.6V for SST39VF401C/402C - 3.0-3.6V for SST39LF401C/402C - 70 ns for SST39VF401C/402C - 55 ns for SST39LF401C/402C * Superior Reliability * Fast Erase and Word-Program: - Endurance: 100,000 Cycles (Typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 5 mA (typical) - Standby Current: 3 A (typical) - Auto Low Power Mode: 3 A (typical) * Automatic Write Timing - Internal VPP Generation * Hardware Block-Protection/WP# Input Pin * End-of-Write Detection - Top Block-Protection (top 8 KWord) - Bottom Block-Protection (bottom 8 KWord) - Toggle Bits - Data# Polling - Ready/Busy# Pin * Sector-Erase Capability - Uniform 2 KWord sectors * CMOS I/O Compatibility * Block-Erase Capability - Flexible block architecture; one 8-, two 4-, one 16-, and seven 32-KWord blocks * Chip-Erase Capability * Erase-Suspend/Erase-Resume Capabilities * Hardware Reset Pin (RST#) * Latched Address and Data (c)2011 Silicon Storage Technology, Inc. - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 40 ms (typical) - Word-Program Time: 7 s (typical) * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 48-lead TSOP (12mm x 20mm) - 48-ball TFBGA (6mm x 8mm) - 48-ball WFBGA (4mm x 6mm) * All devices are RoHS compliant www.microchip.com DS25053A 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Product Description The SST39VF401C/402C and SST39LF401C/402C devices are 512K x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF401C/402C and SST39LF401C/402C write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST39VF401C/402C and SST39LF401C/402C devices provide a typical Word-Program time of 7 sec. These devices use Toggle Bit, Data# Polling, or the RY/BY# pin to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF401C/402C and SST39LF401C/402C devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39VF401C/402C and SST39LF401C/402C are offered in 48-lead TSOP, 48-ball TFBGA, and 48-ball WFBGA packages. See Figures 2, 3, and 4 for pin assignments. (c)2011 Silicon Storage Technology, Inc. DS25053A 2 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Block Diagrams X-Decoder Memory Address SuperFlash Memory Address Buffer Latches Y-Decoder CE# OE# WE# WP# RESET# RY/BY# I/O Buffers and Data Latches Control Logic DQ15 - DQ0 25053 B1.0 Figure 1: Functional Block Diagram (c)2011 Silicon Storage Technology, Inc. DS25053A 3 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Pin Assignment A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RST# NC WP# RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Standard Pinout Top View Die Up A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1434 48-tsop EK P1.0 Figure 2: Pin Assignments for 48-Lead TSOP TOP VIEW (balls facing down) 6 5 4 3 2 1 A13 A12 A14 A15 A16 NC DQ15 VSS A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# RST# NC NC DQ5 DQ12 VDD DQ4 RY/BY# WP# NC NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F G H 25053 48-tfbga B3K P2.0 Figure 3: Pin Assignments for 48-Ball TFBGA (c)2011 Silicon Storage Technology, Inc. DS25053A 4 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet TOP VIEW (balls facing down) 6 5 4 3 2 1 A2 A4 A6 A17 A1 A3 A7 WP# A0 A5 NC NC NC WE# RST# A9 A11 RY/BY# A10 A13 A14 A8 A12 A15 CE# DQ8 DQ10 VSS OE# DQ9 DQ4 DQ11 A16 NC NC DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS A B C D E F G H J K L 25053 48-wfbga MAQ P3.0 Figure 4: Pin Assignments for 48-Ball WFBGA Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded. RST# Reset To reset and return the device to Read mode. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: 2.7-3.6V VSS Ground NC No Connection Unconnected pins. RY/BY# Ready/Busy# To output the status of a Program or Erase operation RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. T1.2 25053 1. AMS = Most significant address AMS = A17 (c)2011 Silicon Storage Technology, Inc. DS25053A 5 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Table 2: Top / Bottom Boot Block Address Bottom Boot Block Address SST39VF401C/SST39LF401C Top Boot Block Address SST39VF402C/SST39LF402C # Size (KWord) Address Range # Size (KWord) Address Range 18 8 3E000H-3FFFFH 10 32 38000H-3FFFFH 17 4 3D000H-3DFFFH 9 32 30000H-37FFFH 16 4 3C000H-3CFFFH 8 32 28000H-2FFFFH 15 16 38000H-3BFFFH 7 32 20000H-27FFFH 14 32 30000H-37FFFH 6 32 18000H-1FFFFH 13 32 28000H-2FFFFH 5 32 10000H-17FFFH 12 32 20000H-27FFFH 4 32 08000H-0FFFFH 11 32 18000H-1FFFFH 3 16 04000H-07FFFH 10 32 10000H-17FFFH 2 4 03000H-03FFFH 9 32 08000H-0FFFFH 1 4 02000H-02FFFH 8 32 00000H-07FFFH 0 8 00000H-01FFFH T2.25053 (c)2011 Silicon Storage Technology, Inc. DS25053A 6 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF401C/402C and SST39LF401C/402C also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 5 mA to typically 3 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39VF401C/402C and SST39LF401C/402C is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). Word-Program Operation The SST39VF401C/402C and SST39LF401C/402C are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 s. See Figures 7 and 8 for WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST39VF401C/402C and SST39LF401C/402C offer both Sector-Erase and Block-Erase mode. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on non-uniform block sizes--seven 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks. See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the (c)2011 Silicon Storage Technology, Inc. DS25053A 7 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 12 and 13 for timing waveforms and Figure 26 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with EraseSuspend command (B0H). The device automatically enters read mode typically within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/ blocks will output DQ2 toggling and DQ6 at `1'. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Chip-Erase Operation The SST39VF401C/402C and SST39LF401C/402C provide a Chip-Erase operation, which allows the user to erase the entire memory array to the `1' state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 7 for the command sequence, Figure 11 for timing diagram, and Figure 26 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. Write Operation Status Detection The SST39VF401C/402C and SST39LF401C/402C provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. (c)2011 Silicon Storage Technology, Inc. DS25053A 8 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Ready/Busy# (RY/BY#) The devices include a Ready/Busy# (RY/BY#) output signal. RY/BY# is an open drain output pin that indicates whether an Erase or Program operation is in progress. Since RY/BY# is an open drain output, it allows several devices to be tied in parallel to VDD via an external pull-up resistor. After the rising edge of the final WE# pulse in the command sequence, the RY/BY# status is valid. When RY/BY# is actively pulled low, it indicates that an Erase or Program operation is in progress. When RY/BY# is high (Ready), the devices may be read or left in standby mode. Data# Polling (DQ7) When the SST39VF401C/402C and SST39LF401C/402C are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 23 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `1's and `0's, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to `1' if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 23 for a flowchart. Table 3: Write Operation Status Status Normal Operation Erase-Suspend Mode DQ7 DQ6 DQ2 RY/BY# DQ7# Toggle No Toggle 0 Standard Erase 0 Toggle Toggle 0 Read from Erase-Suspended Sector/Block 1 1 Toggle 1 Read from Non-EraseSuspended Sector/Block Data Data Data 1 Program DQ7# Toggle N/A 0 Standard Program T3.0 25053 Note: DQ7 and DQ2 require a valid address when reading status information. (c)2011 Silicon Storage Technology, Inc. DS25053A 9 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Data Protection The SST39VF401C/402C and SST39LF401C/402C provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The SST39VF402C/SST39LF402C support top hardware block protection, which protects the top 8 KWord block of the device. The SST39VF401C/SST39LF401C support bottom hardware block protection, which protects the bottom 8KWord block of the device. The Boot Block address ranges are described in Table 4. Program and Erase operations are prevented on the 8 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Table 4: Boot Block Address Ranges Product Address Range Bottom Boot Block SST39VF401C/SST39LF401C 00000H - 01FFFH Top Boot Block SST39VF402C/SST39LF402C 3E000H - 3FFFFH T4.0 25053 Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 18). The Erase or Program operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. Software Data Protection (SDP) The SST39VF401C/402C and SST39LF401C/402C provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 7 for (c)2011 Silicon Storage Technology, Inc. DS25053A 10 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Common Flash Memory Interface (CFI) The SST39VF401C/402C and SST39LF401C/402C also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Product Identification The Product Identification mode identifies the devices as the SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C, and manufacturer as SST. This mode may be accessed software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the Software ID Entry command sequence flowchart. Table 5: Product Identification Address Data 0000H BFH SST39VF401C/SST39LF401C 0001H 2321H SST39VF402C/SST39LF402C 0001H 2322H Manufacturer's ID Device ID T5.2 25053 Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Figure 25 for flowcharts. (c)2011 Silicon Storage Technology, Inc. DS25053A 11 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Security ID The SST39VF401C/402C and SST39LF401C/402C devices offer a 136 Word Security ID space. The Secure ID space is divided into two segments--one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The user segment, with a 128 word space, is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a three-byte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 7 for more details. (c)2011 Silicon Storage Technology, Inc. DS25053A 12 10/11 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C A Microchip Technology Company Data Sheet Operations Table 6: Operation Modes Selection Mode CE# OE# WE# Read Program VIL VIL VIL VIH Address VIH DOUT AIN VIL DIN AIN VIL X1 Sector or block address, XXH for ChipErase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit VIH DQ Product Identification Software Mode See Table 7 T6.0 25053 1. X can be VIL or VIH, but no other value. Table 7: Software Command Sequence Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle Addr1 Addr1 Data2 Addr1 Data2 Addr1 Data2 Data AAH Data2 3rd Bus Write Cycle 4th Bus Write Cycle Word-Program 555H AAH 2AAH 55H 555H A0H WA3 Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAH 55H SAX4 50H 4 Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX 30H Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Erase-Suspend XXXH B0H Erase-Resume XXXH 30H ID5 555H AAH 2AAH 55H 555H 88H User Security ID Word-Program 555H AAH 2AAH 55H 555H A5H WA6 Data User Security ID Program LockOut 555H AAH 2AAH 55H 555H 85H XXH6 0000 H Software ID Entry7,8 555H AAH 2AAH 55H 555H 90H CFI Query Entry 555H AAH 2AAH 55H 555H 98H 2AAH 55H 555H F0H Query Sec 55H 98H Software ID Exit9,10 /CFI Exit/Sec ID Exit 555H AAH Software ID Exit9,10 /CFI Exit/Sec ID Exit XXH F0H CFI Query Entry T7.6 25053 1. 2. 3. 4. Address format A10-A0 (Hex). Addresses A11-A17 can be VIL or VIH, but no other value, for Command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence WA = Program Word address SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address; AMS = A17 (c)2011 Silicon Storage Technology, Inc. DS25053A 13 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000008H to 000087H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39VF401C/SST39LF401C Device ID = 233BH, is read with A0 = 1, SST39VF402C/SST39LF402C Device ID = 233AH, is read with A0 = 1, AMS = Most significant address; AMS = A17 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed `0' bits cannot be reversed to `1'). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H-000087H. Table 8: CFI Query Identification String1 Address Data 10H 0051H 11H 0052H 12H 0059H 13H 0002H 14H 0000H 15H 0000H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T8.1 25053 1. Refer to CFI publication 100 for more details. Table 9: System Interface Information Address Data 1BH 0027H Data 1CH 0036H VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min. (00H = no VPP pin) VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1EH 0000H VPP max. (00H = no VPP pin) 1FH 0003H Typical time out for Word-Program 2N s (23 = 8 s) 20H 0000H Typical time out for min. size buffer program 2N s (00H = not supported) 21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 0005H Typical time out for Chip-Erase 2N ms (25 = 32 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 23 = 16 s) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) T9.3 25053 (c)2011 Silicon Storage Technology, Inc. DS25053A 14 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Table 10:Device Geometry Information Address Data 27H 0013H Device size = 2N Bytes 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H 2BH 0000H 2CH 0005H Number of Erase Sector/Block sizes supported by device 2DH 0000H Erase Block Region 1 Information (Refer to the CFI specification or CFI publication 100) 2EH 0000H 2FH 0040H 30H 0000H 31H 0001H 32H 0000H 33H 0020H 34H 0000H 35H 0000H 36H 0000H 37H 0080H 38H 0000H 39H 0007H 3AH 0000H 3BH 0000H 3CH 0001H Data Maximum number of byte in multi-byte write = 2N (00H = not supported) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information T10.0 25053 (c)2011 Silicon Storage Technology, Inc. DS25053A 15 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Electrical Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. Table 11:Operating Range Range Ambient Temp Commercial Industrial VDD 0C to +70C 2.7-3.6V -40C to +85C 2.7-3.6V T11.0 25053 Table 12:AC Conditions of Test1 Input Rise/Fall Time Output Load 5ns CL = 30 pF T12.1 25053 1. See Figures 20 and 21 (c)2011 Silicon Storage Technology, Inc. DS25053A 16 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Power Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 s to ensure a proper reset. TPU-READ 1 00 s VDD min VDD 0V VIH RESET# TRHR 5 0ns CE# 25053 F24.0 Figure 5: Power-Up Diagram Table 13:DC Operating Characteristics VDD = 2.7-3.6V1 Limits Symbol IDD Parameter Power Supply Current Min Max Units ISB Read3 Program and Erase Standby VDD Current 18 30 20 mA mA A IALP Auto Low Power 20 A ILI ILIW Input Leakage Current Input Leakage Current on WP# pin and RST# 1 10 A A Test Conditions Address input=VILT/VIHT2, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max RST#=VDD0.3, WP#=VDD0.3, WE#=VDD0.3 CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC VIN=GND to VDD, VDD=VDD Max WP#=GND to VDD or RST#=GND to VDD ILO VIL VILC VIH VIHC VOL VOH Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage 10 0.8 0.3 VDD+0.3 VDD+0.3 0.2 A V V V V V V VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min 0.7VDD VDD-0.3 VDD-0.2 T13.8 25053 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 3V. Not 100% tested. 2. See Figure 20 3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. (c)2011 Silicon Storage Technology, Inc. DS25053A 17 10/11 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C A Microchip Technology Company Data Sheet Table 14:Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 s Power-up to Program/Erase Operation 100 s TPU-WRITE 1 T14.0 25053 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 15:Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter CI/O Description 1 CIN1 Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T15.0 25053 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 16:Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T16.2 25053 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. (c)2011 Silicon Storage Technology, Inc. DS25053A 18 10/11 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C A Microchip Technology Company Data Sheet AC Characteristics Table 17:Read Cycle Timing Parameters VDD = 2.7-3.6V SST39VF401C/402C Min SST39LF401C/402C Symbol Parameter TRC Read Cycle Time TCE Chip Enable Access Time 70 55 ns TAA Address Access Time 70 55 ns TOE Output Enable Access Time TCLZ1 CE# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 CE# High to High-Z Output 1 OE# High to High-Z Output TOHZ Max 55 30 0 TRHR1 ns ns 0 ns 15 20 TRP1 Units ns 20 Output Hold from Address Change TRY Min 35 TOH1 1,2 Max 70 15 ns ns 0 0 ns RST# Pulse Width 500 500 ns RST# High before Read 50 50 ns RST# Pin Low to Read Mode 20 20 s T17.3 25053 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase operations. Table 18:Program/Erase Cycle Timing Parameters Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 TCPH1 TDS TDH1 TIDA1 TSE TBE TSCE TBY1,2 TBR1 Parameter Word-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase RY/BY# Delay Time Bus Recovery Time Min Max 10 0 30 0 0 0 10 40 40 30 30 30 0 150 25 25 50 90 0 Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns s T18.1 25053 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. (c)2011 Silicon Storage Technology, Inc. DS25053A 19 10/11 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C A Microchip Technology Company Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCHZ TOH TCLZ HIGH-Z HIGH-Z DQ15-0 DATA VALID DATA VALID 25053 F03.0 Note: AMS = Most significant address AMS = A17 Figure 6: Read Cycle Timing Diagram TBP ADDRESSES 555 2AA 555 ADDR TAH TWP WE# TWPH TAS OE# TCH CE# TCS TBY TBR RY/BY# TDS DQ15-0 XXAA XX55 XXA0 TDH DATA VALID WORD (ADDR/DATA) 25053 F25.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 7: WE# Controlled Program Cycle Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25053A 20 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet TBP 555 ADDRESSES 2AA 555 ADDR TAH TCP CE# TAS TCPH OE# TCH WE# TCS TBY TBR RY/BY# TDS DQ15-0 XXAA XX55 XXA0 TDH DATA VALID WORD (ADDR/DATA) 25053 F26.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 8: CE# Controlled Program Cycle Timing Diagram ADDRESS A17-0 TCE CE# TOEH TOES OE# TOE WE# TBY RY/BY# DQ7 DATA DATA# DATA# DATA 25053 F27.0 Figure 9: Data# Polling Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25053A 21 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 25053 F07.0 Note: AMS = Most significant address AMS = A17 Figure 10:Toggle Bits Timing Diagram TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESSES 555 2AA 555 555 2AA 555 CE# OE# TOEH WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 25053 F31.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 18). WP# must be held in proper logic state (VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 11:WE# Controlled Chip-Erase Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25053A 22 10/11 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C A Microchip Technology Company Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESSES 555 2AA 555 555 2AA BAX CE# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XXAA XX80 XX55 XX30 VALID 25053 F32.0 Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 18). BAX = Block Address WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 12:WE# Controlled Block-Erase Timing Diagram TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESSES 555 2AA 555 555 2AA SAX CE# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XXAA XX80 XX55 XX50 VALID 25053 F28.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 18). SAX = Block Address WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 13:WE# Controlled Sector-Erase Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25053A 23 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Three-Byte Sequence for Software ID Entry ADDRESS 555 2AA 555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 SW0 SW1 SW2 00BF Device ID Note: Device ID = 233BH for SST39VF401C/SST39LF401C and 233AH for SST39VF401C/SST39LF401C WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. 25053 F11.0 Figure 14:Software ID Entry and Read Three-Byte Sequence for CFI Query Entry ADDRESS 555 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX98 SW0 SW1 SW2 25053 F12.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 15:CFI Query Entry and Read (c)2011 Silicon Storage Technology, Inc. DS25053A 24 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS DQ15-0 555 2AA XXAA 555 XX55 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 25053 F13.0 Note: WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 16:Software ID Exit/CFI Exit THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS AMS-0 555 2AA 555 CE# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 25053 F20.0 Note: AMS = Most significant address AMS = A17 WP# must be held in proper logic state (VIL or VIH) 1s prior to and 1s after the command sequence. X can be VIL or VIH, but no other value. Figure 17:Sec ID Entry (c)2011 Silicon Storage Technology, Inc. DS25053A 25 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet RY/BY# 0V TRP RST# TRHR CE#/OE# 25053 F29.0 Figure 18:RST# Timing Diagram (When no internal operation is in progress) TRY RY/BY# TRP RST# CE# TBR OE# 25053 F30.0 Figure 19:RST# Timing Diagram (During Program or Erase operation) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 25053 F14.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic `1' and VILT (0.1 VDD) for a logic `0'. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test Figure 20:AC Input/Output Reference Waveforms (c)2011 Silicon Storage Technology, Inc. DS25053A 26 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet TO TESTER TO DUT CL 25053 F15.0 Figure 21:A Test Load Example (c)2011 Silicon Storage Technology, Inc. DS25053A 27 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 25053 F16.0 Note: X can VIL or VIH, but no other value. Figure 22:Word-Program Algorithm (c)2011 Silicon Storage Technology, Inc. DS25053A 28 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Internal Timer Toggle Bit Data# Polling RY/BY# Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read RY/BY# Read same word Program/Erase Completed No Is DQ7 = true data No Is RY/BY# = 1 Yes Yes No Does DQ6 match Program/Erase Completed Program/Erase Completed Yes Program/Erase Completed 25053 F17.0 Figure 23:Wait Options (c)2011 Silicon Storage Technology, Inc. DS25053A 29 10/11 4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C A Microchip Technology Company Data Sheet CFI Query Entry Command Sequence Sec ID Query Entry Command Sequence Software Product ID Entry Command Sequence Load data: XXAAH Address: 555H Load data: XX98H Address: 55H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Wait TIDA Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX98H Address: 55H Read CFI data Load data: XX88H Address: 555H Load data: XX90H Address: 555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Sec ID Read Software ID 25053 F21.0 Note: X can VIL or VIH, but no other value. Figure 24:Software ID/CFI Entry Command Flowcharts (c)2011 Silicon Storage Technology, Inc. DS25053A 30 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAH Wait TIDA Load data: XXF0H Address: 555H Return to normal operation Wait TIDA Return to normal operation 25053 F18.0 Note: X can be VIL or VIH, but no other value. Figure 25:Software ID/CFI Exit Command Flowcharts (c)2011 Silicon Storage Technology, Inc. DS25053A 31 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX50H Address: SAX Load data: XX30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 25053 F19.0 Note: X can be VIL or VIH, but no other value. Figure 26:Erase Command Sequence (c)2011 Silicon Storage Technology, Inc. DS25053A 32 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Product Ordering Information SST 39 VF XX XX 401C XXXX - 70 XX - 4C XX - EKE XXX Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Q = 48 balls (66 possible positions) Package Type E = TSOP (type1, die up, 12mm x 20mm) B3 = TFBGA (6mm x 8mm, 0.8mm pitch) MA = WFBGA (4mm x 6mm, 0.5mm pitch) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 55 = 55 ns Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block Device Density 40 = 4 Mbit Voltage V = 2.7-3.6V L = 3.0-3.6V Product Series 39 = Multi-Purpose Flash 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". (c)2011 Silicon Storage Technology, Inc. DS25053A 33 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Valid Combinations for SST39VF401C SST39VF401C-70-4C-EKE SST39VF401C-70-4I-EKE SST39VF401C-70-4C-B3KE SST39VF401C-70-4I-B3KE SST39VF401C-70-4C-MAQE SST39VF401C-70-4I-MAQE Valid Combinations for SST39VF402C SST39VF402C-70-4C-EKE SST39VF402C-70-4I-EKE SST39VF402C-70-4C-B3KE SST39VF402C-70-4I-B3KE SST39VF402C-70-4C-MAQE SST39VF402C-70-4I-MAQE Valid Combinations for SST39LF401C SST39LF401C-55-4C-EKE SST39LF401C-55-4C-B3KE SST39LF401C-55-4C-MAQE Valid Combinations for SST39LF402C SST39LF402C-55-4C-EKE SST39LF402C-55-4C-B3KE SST39LF402C-55-4C-MAQE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2011 Silicon Storage Technology, Inc. DS25053A 34 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Packaging Diagrams 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 12.20 11.80 0.15 0.05 18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 1mm 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50 48-tsop-EK-8 Figure 27:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm SST Package Code: EK (c)2011 Silicon Storage Technology, Inc. DS25053A 35 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet TOP VIEW BOTTOM VIEW 8.00 0.10 5.60 0.45 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 0.10 3 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A 1.10 0.10 A1 CORNER 0.12 SEATING PLANE 1mm 0.35 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-5 Figure 28:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K (c)2011 Silicon Storage Technology, Inc. DS25053A 36 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet TOP VIEW BOTTOM VIEW 5.00 6.00 0.08 6 5 4 3 2 1 0.50 4.00 0.08 0.50 A1 CORNER DETAIL 6 5 4 3 2 1 2.50 A B C D E F G H J K L 0.32 0.05 (48X) L K J H G F E D C B A A1 INDICATOR 0.73 max. 0.636 nom. SIDE VIEW 0.08 SEATING PLANE 0.20 0.06 Note: 1mm 1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger and bottom side A1 indicator is triangle at corner. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm 4. Ball opening size is 0.29 mm ( 0.05 mm) 48-wfbga-MAQ-4x6-32mic-2.0 Figure 29:48-ball Very, Very Thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm SST Package Code: MAQ (c)2011 Silicon Storage Technology, Inc. DS25053A 37 10/11 4 Mbit (x16) Multi-Purpose Flash Plus A Microchip Technology Company SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C Data Sheet Table 19:Revision History Number A Description * Initial release Date Oct 2011 ISBN:978-1-61341-676-1 (c) 2011 Silicon Storage Technology, Inc-a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see www.microchip.com. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com (c)2011 Silicon Storage Technology, Inc. DS25053A 38 10/11 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: SST39VF1601C-70-4I-B3KE-MCF-T SST39VF1601C-70-4I-MAQE SST39VF1602C-70-4C-MAQE SST39VF1602C70-4I-MAQE SST39VF1601C-70-4C-MAQE SST39LF402C-55-4C-EKE SST39VF401C-70-4C-EKE SST39VF401C70-4I-EKE SST39LF401C-55-4C-EKE SST39VF402C-70-4C-EKE SST39VF402C-70-4I-EKE SST39VF401C-70-4IB3KE SST39VF402C-70-4I-B3KE SST39VF401C-70-4I-EKE-T SST39VF401C-70-4C-MAQE SST39LF402C-55-4CMAQE SST39VF401C-70-4C-B3KE SST39VF402C-70-4I-MAQE-T SST39LF401C-55-4C-MAQE-T