SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Bidirectional Transceivers
D
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.11 and X.27
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
3-State Driver and Receiver Outputs
D
Individual Driver and Receiver Enables
D
Wide Positive and Negative Input/Output
Bus Voltage Ranges
D
Driver Output Capability . . . ±60 mA Max
D
Thermal Shutdown Protection
D
Driver Positive and Negative Current
Limiting
D
Receiver Input Impedance . . . 12 kΩ Min
D
Receiver Input Sensitivity . . . ±200 mV
D
Receiver Input Hysteresis . . . 50 mV Typ
D
Operate From Single 5-V Supply
description/ordering information
The SN65176B and SN75176B differential bus transceivers are integrated circuits designed for bidirectional
data communication on multipoint bus transmission lines. They are designed for balanced transmission lines
and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low
enables, respectively, that can be connected together externally to function as a direction control. The driver
differential outputs and the receiver dif ferential inputs are connected internally to form dif ferential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0.
These ports feature wide positive and negative common-mode voltage ranges, making the device suitable for
party-line applications.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP (P) T ube of 50 SN75176BP SN75176BP
0
°
Cto70
°
C
SOIC (D)
T ube of 75 SN75176BD
75176B
0°C
to
70°C
SOIC
(D)
Reel of 2500 SN75176BDR
75176B
SOP (PS) Reel of 2000 SN75176BPSR A176B
PDIP (P) T ube of 50 SN65176BP SN65176BP
–40°C to 105°C
SOIC (D)
T ube of 75 SN65176BD
65176B
SOIC
(D)
Reel of 2500 SN65176BDR
65176B
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
R
RE
DE
D
VCC
B
A
GND
SN65176B ...D OR P PACKAGE
SN75176B . . . D, P, OR PS PACKAGE
(TOP VIEW)
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The driver is designed for up to 60 mA of sink or source current. The driver features positive and negative current
limiting and thermal shutdown for protection from line-fault conditions. Thermal shutdown is designed to occur
at a junction temperature of approximately 150°C. The receiver features a minimum input impedance of 12 kΩ,
an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mV.
The SN65176B and SN75176B can be used in transmission-line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
Function Tables
DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z
RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
A–B RE R
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ –0.2 V L L
X H Z
Open L ?
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
logic diagram (positive logic)
DE
RE
R
6
7
3
1
2
B
ABus
D4
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
Output
85 Ω
NOM
TYPICAL OF RECEIVER OUTPUT
Input/Output
Port
960 Ω
NOM
16.8 kΩ
NOM
TYPICAL OF A AND B I/O PORTS
Driver input: R(eq) = 3 kΩ NOM
Enable inputs: R(eq )= 8 kΩ NOM
R(eq) = Equivalent Resistor
R(eq)
VCC
EQUIVALENT OF EACH INPUT
VCC
Input
960 Ω
NOM
VCC
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus terminal –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 2 and 3): D package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS package 95°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN TYP MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIor VIC
Voltage at any bus terminal (se
p
arately or common mode)
12
V
V
I
or
V
IC
Voltage
at
any
bus
terminal
(separately
or
common
mode)
–7
V
VIH High-level input voltage D, DE, and RE 2 V
VIL Low-level input voltage D, DE, and RE 0.8 V
VID Differential input voltage (see Note 4) ±12 V
IOH
High level out
p
ut current
Driver –60 mA
I
OH
High
-
level
output
current
Receiver –400 µA
IOL
Low level out
p
ut current
Driver 60
mA
I
OL
Low
-
level
output
current
Receiver 8
mA
TA
O
p
erating free air tem
p
erature
SN65176B –40 105
°C
T
A
Operating
free
-
air
temperature
SN75176B 0 70
°C
NOTE 4: Differential input/output bus voltage is measured at the noninverting terminal A, with respect to the inverting terminal B.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VOOutput voltage IO = 0 0 6 V
|VOD1|Differential output voltage IO = 0 1.5 3.6 6 V
|VOD2|Differential output voltage RL = 100 Ω, See Figure 1 1/2 VOD1
or 2¶V
OD2
g
RL = 54 Ω, See Figure 1 1.5 2.5 5
VOD3 Differential output voltage See Note 5 1.5 5 V
∆|VOD|
Chan
g
e in ma
g
nitude
RL=54Ωor 100 Ω
See Figure 1
±02
V
∆|V
OD
|
gg
of differential output voltage§
R
L =
54
Ω
or
100
Ω
,
See
Figure
1
±0
.
2
V
VOC
Common mode out
p
ut voltage
RL=54Ωor 100 Ω
See Figure 1
+3
V
V
OC
Common
-
mode
output
voltage
R
L =
54
Ω
or
100
Ω
,
See
Figure
1
–1
V
∆|VOC|
Chan
g
e in ma
g
nitude
RL=54Ωor 100 Ω
See Figure 1
±02
V
∆|V
OC
|
gg
of common-modeoutput voltage§
R
L =
54
Ω
or
100
Ω
,
See
Figure
1
±0
.
2
V
IO
Out
p
ut current
Output disabled, VO = 12 V 1
mA
I
O
Output
current
,
See Note 6 VO = –7 V –0.8
mA
IIH High-level input current VI = 2.4 V 20 µA
IIL Low-level input current VI = 0.4 V –400 µA
VO = –7V –250
IOS
Short circuit out
p
ut current
VO = 0 –150
mA
I
OS
Short
-
circuit
output
current
VO = VCC 250
mA
VO = 12 V 250
ICC
Su
pp
ly current (total
p
ackage)
No load
Outputs enabled 42 70
mA
I
CC
Supply
current
(total
package)
No
load
Outputs disabled 26 35
mA
†The power-off measurement in ANSI Standard TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡All typical values are at VCC = 5 V and TA = 25°C.
§∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively , that occur when the input is changed from a high level to a low
level.
¶The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTES: 5. See ANSI Standard TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.
6. This applies for both power on and off; refer to ANSI Standard TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does
not apply for a combined driver and receiver terminal.
switching characteristics, VCC = 5 V, RL = 110 Ω, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential-output delay time RL = 54 Ω,See Figure 3 15 22 ns
tt(OD) Differential-output transition time RL = 54 Ω,See Figure 3 20 30 ns
tPZH Output enable time to high level See Figure 4 85 120 ns
tPZL Output enable time to low level See Figure 5 40 60 ns
tPHZ Output disable time from high level See Figure 4 150 250 ns
tPLZ Output disable time from low level See Figure 5 20 30 ns
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A
VOVoa, Vob Voa, Vob
|VOD1| VoVo
|VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
|VOD3|
V
t
(test termination
|V
OD3
|
t(
measurement 2)
∆|VOD|| |Vt| – |Vt| | | |Vt – |Vt| |
VOC |Vos| |Vos|
∆|VOC| |Vos – V os||Vos – Vos|
IOS |Isa|, |Isb|
IO|Ixa|, |Ixb| Iia, Iib
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
VIT–Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.2‡V
Vhys Input hysteresis voltage (VIT+ – VIT–) 50 mV
VIK Enable Input clamp voltage II = –18 mA –1.5 V
VOH
High level out
p
ut voltage
V
ID
= 200 mV, I
OH
= –400
µ
A,
27
V
V
OH
High
-
level
output
voltage
ID ,
See Figure 2
OH µ,
2
.
7
V
VOL
Low level out
p
ut voltage
V
ID
= –200 mV, I
OL
= 8 mA,
045
V
V
OL
Low
-
level
output
voltage
ID ,
See Figure 2
OL ,
0
.
45
V
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
II
Line in
p
ut current
Other input = 0 V, VI = 12 V 1
mA
I
I
Line
input
current
,
See Note 7 VI = –7 V –0.8
mA
IIH High-level enable input current VIH = 2.7 V 20 µA
IIL Low-level enable input current VIL = 0.4 V –100 µA
rIInput resistance VI = 12 V 12 kΩ
IOS Short-circuit output current –15 –85 mA
ICC
Su
pp
ly current (total
p
ackage)
No load
Outputs enabled 42 55
mA
I
CC
Supply
current
(total
package)
No
load
Outputs disabled 26 35
mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 7: This applies for both power on and power off. Refer to EIA Standard TIA/EIA-485-A for exact conditions.
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output
VID = 0 to 3 V See Figure 6
21 35
ns
tPHL Propagation delay time, high- to low-level output
V
ID =
0
to
3
V
,
See
Figure
6
23 35
ns
tPZH Output enable time to high level
See Figure 7
10 20
ns
tPZL Output enable time to low level
See
Figure
7
12 20
ns
tPHZ Output disable time from high level
See Figure 7
20 35
ns
tPLZ Output disable time from low level
See
Figure
7
17 25
ns
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD and VOC
2
RL
VOD2
VOC
2
RL
Figure 2. Receiver VOH and VOL
VID
VOL
VOH
–IOH
+IOL
3 V
VOLTAGE WAVEFORMS
tt(OD)
td(OD)
1.5 V
10%
tt(OD)
≈2.5 V
≈–2.5 V
90%
50%
Output
td(OD)
0 V
3 V
1.5 V
Input
TEST CIRCUIT
Output
CL = 50 pF
(see Note A)
50 ΩRL = 54 Ω
Generator
(see Note B) 50%
10%
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 3. Driver Test Circuit and Voltage Waveforms
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
tPHZ
1.5 V
2.3 V
0.5 V0 V
3 V
tPZH
Output
Input 1.5 V
S1
0 V or 3 V
Output
CL = 50 pF
(see Note A)
TEST CIRCUIT
50 Ω
VOH
Voff ≈0 V
RL = 110 Ω
Generator
(see Note B)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 4. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
5 V
VOL
0.5 V
tPZL
3 V
0 V
tPLZ
2.3 V
1.5 V
Output
Input
TEST CIRCUIT
Output
RL = 110 Ω
5 V
S1
CL = 50 pF
(see Note A)
50 Ω
3 V or 0 V
Generator
(see Note B)
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 5. Driver Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
1.3 V
0 V
3 V
VOL
VOH
tPHL
tPLH
1.5 V
Output
Input
TEST CIRCUIT
CL = 15 pF
(see Note A)
Output
0 V
1.5 V
51 Ω
Generator
(see Note B)
1.5 V
1.3 V
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 6. Receiver Test Circuit and Voltage Waveforms
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
0.5 V
≈1.3 V
tPHZ
Output
Input 1.5 V
0 V
3 V S1 to 1.5 V
S2 Closed
S3 Closed
tPLZ
≈1.3 V
VOL
0.5 V
Output
Input 1.5 V
0 V
3 V
≈4.5 V
VOL
1.5 V
S3 Open
S2 Closed
S1 to –1.5 V
0 V
1.5 V
3 V
tPZL
Output
Input
0 V
1.5 V
VOH
0 V
Output
Input
tPZH S3 Closed
S2 Open
S1 to 1.5 V
1.5 V
3 V
TEST CIRCUIT
50 Ω
1N916 or Equivalent
S3
5 V
S2
2 kΩ
5 kΩ
S1
–1.5 V
1.5 V
VOLTAGE WAVEFORMS
S1 to –1.5 V
S2 Closed
S3 Closed
Generator
(see Note B)
CL = 15 pF
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 7. Receiver Test Circuit and Voltage Waveforms
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
VOH – High-Level Output Voltage – V
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 5 V
4.5
4
3.5
3
2.5
2
1.5
1
0.5
–100–80–60–40–20
0–120
5
IOH – High-Level Output Current – mA
0
VOH
TA = 25°C
Figure 9
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VCC = 5 V
TA = 25°C
IOL – Low-Level Output Current – mA
0 12020 40 60 80 100
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
– Low-Level Output Voltage – V
VOL
VOD – Differential Output Voltage – V
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.5
3
2.5
2
1.5
1
0.5
908070605040302010
0100
4
IO – Output Current – mA
0
VOD
VCC = 5 V
TA = 25°C
Figure 10
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
–25
Figure 11
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
0–10 –20 –30 –40 –50
5
0
1
2
3
4
IOH – High-Level Output Current – mA
VOH – High-Level Output Voltage – V
VOH
4.5
3.5
2.5
1.5
0.5
–5–15 –35 –45
VID = 0.2 V
TA = 25°C
Figure 12
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE †
4
3
2
1
100806040200–20
0120
5
TA – Free-Air Temperature – °C
–40
VCC = 5 V
VID = 200 mV
IOH = –440 µA
VOH – High-Level Output Voltage – V
VOH
4.5
3.5
2.5
1.5
0.5
†Only the 0°C to 70°C portion of the curve applies to the
SN75176B.
Figure 13
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA = 25°C
VCC = 5 V
0.5
0.4
0.3
0.2
0.1
252015105
030
0.6
IOL – Low-Level Output Current – mA
0
VOL – Low-Level Output Voltage – V
VOL
Figure 14
VOL – Low-Level Output Voltage – V
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VID = –200 mV
VCC = 5 V
TA – Free-Air Temperature – °C
0.6
0
0.1
0.2
0.3
0.4
0.5
100806040200–20 120–40
VOL
IOL = 8 mA
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101D – JULY 1985 – REVISED APRIL 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
VO – Output Voltage – V
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
VCC = 5 V
VCC = 5.25 V
TA = 25°C
VID = 0.2 V
0VI – Enable Voltage – V 30.5 1 1.5 2 2.5
4
3
2
1
0
5
VO
Load = 8 kΩ to GND
VCC = 4.75 V
Figure 16
VO – Output Voltage – V
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
4
3
2
1
2.521.510.5
03
6
VI – Enable Voltage – V
0
VO
Load = 1 kΩ to VCC
VCC = 5 V
VCC = 5.25 V
TA = 25°C
VID = –0.2 V
VCC = 4.75 V
APPLICATION INFORMATION
Up to 32
Transceivers
SN65176B
SN75176B
SN65176B
SN75176B
RT
RT
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths of f the main line should be kept
as short as possible.
Figure 17. Typical Application Circuit
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65176BD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65176BDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65176BDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65176BDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65176BP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN65176BPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75176BD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BDE4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BDRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75176BPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN75176BPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75176BPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75176BPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65176BDR SOIC D 8 2500 340.5 338.1 20.6
SN75176BDR SOIC D 8 2500 340.5 338.1 20.6
SN75176BPSR SO PS 8 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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