HI-546, HI-547, HI-548, HI-549 S E M I C O N D U C T O R Single 16 and 8, Differential 8-Channel and 4-Channel CMOS Analog MUXs with Active Overvoltage Protection August 1997 Features Description * Analog Overvoltage Protection . . . . . 70VP-P The HI-546, HI-547, HI-548 and HI-549 are analog multiplexers with active overvoltage protection and guaranteed rON matching. Analog input * No Channel Interaction During Overvoltage levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection * Guaranteed rON Matching circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. * 44V Maximum Power Supply Analog inputs can withstand constant 70VP-P levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either * Analog Signal Range . . . . . . . . . . . . . . 15V supply. In addition, signal sources are protected from short circuiting should * Access Time (Typical) . . . . . . . . . . . . 500ns multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-546, HI-547, HI-548 and HI-549 * Standby Power (Typical) . . . . . . . . . .7.5mW ideal for use in systems where the analog inputs originate from external equipment or separately powered circuitry. All devices are fabricated with 44V Dielectrically Isolated CMOS technology. The HI-546 is a single 16-Channel, Applications the HI-547 is an 8-Channel differential, the HI-548 is a single 8-Channel and the HI-549 is a 4-Channel differential device. If input overvoltage protection is * Data Acquisition not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521. The HI-546 and * Industrial Controls HI-547 devices are available in a 28 lead Plastic or Ceramic DIP and a 28 pad * Telemetry Ceramic LCC package. The HI-548/549 devices are available in a 16 lead Plastic or Ceramic DIP and a 20 pad Ceramic LCC package. * Break-Before-Make Switching The HI-546, HI-547, HI-548 and HI-549 are offered in industrial/commercial and military grades. Additional Hi-Rel screening including 160 hour Burn-In is specified by the "-8" suffix. For MIL-STD-883 compliant parts, request the HI-546/883, HI-547/883, HI-548/883 and HI-549/883 datasheets. Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE HI1-0546-4 -25 to 85 28 Ld CERDIP F28.6 HI1-0548-2 -55 to 125 16 Ld CERDIP F16.3 HI1-0546-5 0 to 75 28 Ld CERDIP F28.6 HI1-0548-4 -25 to 85 16 Ld CERDIP F16.3 HI1-0546-2 -55 to 125 28 Ld CERDIP F28.6 HI1-0548-5 0 to 75 16 Ld CERDIP F16.3 HI1-0546/883 -55 to 125 28 Ld CERDIP F28.6 HI1-0548/883 -55 to 125 16 Ld CERDIP F16.3 HI3-0546-5 0 to 75 28 Ld PDIP E28.6 HI3-0548-5 HI3-0546-9 -40 to 85 28 Ld PDIP E28.6 HI4-0548/883 HI4-0546/883 -55 to 125 28 Ld CLCC J28.A 0 to 75 28 Ld PLCC N28.45 HI9P0546-5 0 to 75 28 Ld SOIC M28.3 HI9P0548-9 -40 to 85 16 Ld SOIC M16.15 HI9P0546-9 -40 to 85 28 Ld SOIC M28.3 HI1-0549-2 -55 to 125 16 Ld CERDIP F16.3 HI1-0547-2 -55 to 125 28 Ld CERDIP F28.6 HI1-0549-4 -25 to 85 16 Ld CERDIP F16.3 HI1-0547-4 -25 to 85 28 Ld CERDIP F28.6 HI1-0549-5 0 to 75 16 Ld CERDIP F16.3 0 to 75 28 Ld CERDIP F28.6 HI1-0549/883 -55 to 125 16 Ld CERDIP F16.3 -55 to 125 28 Ld CERDIP F28.6 HI3-0549-5 0 to 75 16 Ld PDIP E16.3 0 to 75 28 Ld PDIP E28.6 HI3-0549-9 -40 to 85 16 Ld PDIP E16.3 -55 to 125 28 Ld CLCC J28.A HI4-0549/883 -55 to 125 20 Ld CLCC J20.A HI4P0547-5 0 to 75 28 Ld PLCC N28.45 HI4P0549-5 0 to 75 20 Ld PLCC N20.35 HI9P0547-5 0to 75 28 Ld SOIC M28.3 HI9P0549-5 0 to 75 16 Ld SOIC M16.15 HI9P0547-9 -40 to 85 28 Ld SOIC M28.3 HI9P0549-9 -40 to 85 16 Ld SOIC M16.15 HI4P0546-5 HI1-0547-5 HI1-0547/883 HI3-0547-5 HI4-0547/883 0 to 75 16 Ld PDIP E16.3 -55 to 125 20 Ld CLCC J20.A HI4P0548-5 0 to 75 20 Ld PLCC N20.35 HI9P0548-5 0 to 75 16 Ld SOIC M16.15 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 11-114 File Number 3150.1 HI-546, HI-547, HI-548, HI-549 Pinouts HI1-0546 (CERDIP), HI3-0546 (PDIP), HI9P0546 (SOIC) TOP VIEW HI1-0547 (CERDIP), HI3-0547 (PDIP), HI9P0547 (SOIC) TOP VIEW 28 OUT A +VSUPPLY 1 28 OUT +VSUPPLY 1 NC 2 27 -VSUPPLY 27 -VSUPPLY OUT B 2 NC 3 26 IN 8 NC 3 26 IN 8A IN 16 4 25 IN 7 IN 8B 4 25 IN 7A IN 15 5 24 IN 6 IN 7B 5 24 IN 6A IN 14 6 23 IN 5 IN 6B 6 23 IN 5A IN 13 7 22 IN 4 IN 5B 7 22 IN 4A IN 12 8 21 IN 3 IN 4B 8 21 IN 3A IN 11 9 20 IN 2 IN 3B 9 20 IN 2A IN 10 10 19 IN 1 IN 2B 10 19 IN 1A 18 ENABLE IN 1B 11 18 ENABLE IN 9 11 GND 12 17 ADDRESS A0 GND 12 17 ADDRESS A0 VREF 13 16 ADDRESS A1 VREF 13 16 ADDRESS A1 ADDRESS A3 14 15 ADDRESS A2 NC 14 15 ADDRESS A2 NC NC +VSUPPLY OUT -VSUPPLY IN 8 IN 8B NC OUT B +VSUPPLY OUT A -VSUPPLY IN 8A H14-0547 (CLCC HI4P0547 (PLCC) TOP VIEW IN 16 H14-0546 (CLCC HI4P0546 (PLCC) TOP VIEW 4 3 2 1 28 27 26 4 3 2 1 28 27 26 22 IN 4A IN 11 9 21 IN 3 IN 3B 9 21 IN 3A IN 10 10 20 IN 2 IN 2B 10 20 IN 2A IN 9 11 19 IN 1 IN 1B 11 19 IN 1A 12 13 14 15 16 17 18 HI1-0548 (CERDIP), HI3-0548 (PDIP), HI9P0548 (SOIC) TOP VIEW 12 13 14 15 16 17 18 ENABLE IN 4B 8 A0 22 IN 4 A1 IN 12 8 A2 23 IN 5A NC 23 IN 5 VREF IN 13 7 GND 24 IN 6A IN 5B 7 ENABLE IN 6B 6 A0 24 IN 6 A1 IN 14 6 A2 25 IN 7A A3 IN 7B 5 GND 25 IN 7 VREF IN 15 5 HI1-0549 (CERDIP), HI3-0549 (PDIP), HI9P0549 (SOIC) TOP VIEW A0 1 16 A1 ENABLE 2 15 A2 ENABLE 2 15 GND -VSUPPLY 3 14 GND -VSUPPLY 3 14 +VSUPPLY A0 1 16 A1 IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B OUT 8 9 IN 8 OUT A 8 11-115 9 OUT B HI-546, HI-547, HI-548, HI-549 Pinouts (Continued) 10 11 12 13 IN 8 IN 7 A1 GND 19 18 +VSUPPLY 17 IN 1B 16 NC IN 2A 7 15 IN 2B IN 3A 8 14 IN 3B 9 10 11 12 13 IN 4B 9 NC 14 IN 6 OUT IN 3 8 IN 4 15 IN 5 20 NC 6 16 NC IN 2 7 1 IN 1A 5 17 +V SUPPLY NC 6 2 -VSUPPLY 4 18 GND IN 1 5 3 OUT B -VSUPPLY 4 NC 19 NC 20 A0 A2 1 OUT A A1 2 ENABLE NC 3 IN 4A A0 HI4-0549 (CLCC) HI4P0549 (PLCC) TOP VIEW ENABLE HI14-0548 (CLCC) HI4P0548 (PLCC) TOP VIEW Functional Diagrams HI-546 HI-547 OUT 1K IN 1 OUT A 1K IN 1A 1K 1K IN 2 OUT B IN 8A 1K DECODER/ DRIVER IN 1B 1K 1K DECODER/ DRIVER IN 8B IN 16 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION LEVEL SHIFT DIGITAL INPUT 5V REF LEVEL SHIFT DIGITAL INPUT VREF A0 A1 A2 EN PROTECTION PROTECTION VREF A0 A1 A2 A3 EN HI-548 HI-549 OUT 1K OUT A 1K IN 1A IN 1 1K 1K OUT B IN 4A IN 2 1K DECODER/ DRIVER IN 1B 1K 1K DECODER/ DRIVER IN 4B IN 8 OVERVOLTAGE CLAMP AND SIGNAL ISOLATION DIGITAL INPUT 5V REF OVERVOLTAGE CLAMP AND SIGNAL ISOLATION LEVEL SHIFT DIGITAL INPUT 5V REF LEVEL SHIFT A0 A1 EN PROTECTION PROTECTION A0 A1 A2 EN 11-116 HI-546, HI-547, HI-548, HI-549 Schematic Diagrams ADDRESS DECODER +V P P P P A0 OR A0 A1 OR A1 P P P N N N N N A2 OR A2 TO P-CHANNEL DEVICE OF THE SWITCH TO N-CHANNEL DEVICE OF THE SWITCH N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-549 DELETE A2 OR A2 INPUT FOR HI-549 V- MULTIPLEX SWITCH FROM DECODE OVERVOLTAGE PROTECTION N V+ P R11 1K D6 Q5 D7 D4 D5 N IN N Q6 V- P FROM DECODE 11-117 OUT HI-546, HI-547, HI-548, HI-549 Schematic Diagrams (Continued) ADDRESS INPUT BUFFER AND LEVEL SHIFTER TTL REFERENCE CIRCUIT V+ R10 R9 Q1 VREF Q4 D3 GND LEVEL SHIFTER V+ OVERVOLTAGE PROTECTION P P P N R2 P P P P R5 V+ R3 D1 V- P LEVEL SHIFTED ADDRESS TO DECODE R7 R6 N P R4 D2 R1 200 P N N N N R8 N N N V- GND ADD IN 11-118 N HI-546, HI-547, HI-548, HI-549 Absolute Maximum Ratings Thermal Information VSUPPLY(+) to VSUPPLY(-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V VSUPPLY(+) to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +22V VSUPPLY(-) to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25V Digital Input Overvoltage +VEN , +VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V -VEN , -VA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -4V or 20mA, Whichever Occurs First Analog Signal Overvoltage (Note 6) +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +20V -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY -20V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA (Pulsed at 1ms, 10% Duty Cycle Max) Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 16 Ld CERDIP Package . . . . . . . . . . . . 85 32 28 Ld CERDIP Package . . . . . . . . . . . . 55 18 20 Ld CLCC Package . . . . . . . . . . . . . . 80 28 28 Ld CLCC Package . . . . . . . . . . . . . . 70 20 28 Ld PDIP Package . . . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . . 100 N/A 28 Ld PLCC Package . . . . . . . . . . . . . . 70 N/A 20 Ld PLCC Package . . . . . . . . . . . . . . 80 N/A 28 Ld SOIC Package . . . . . . . . . . . . . . . 70 N/A 16 Ld SOIC Package . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (PLCC, SOIC - Lead Tips Only) Operating Conditions Operating Temperature Ranges HI-546/547/548/549-2 . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-546/547/548/549-4 . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = +4V; VAL (Logic Level Low) = +0.8V; Unless Otherwise Specified. For Test Conditions, Consult Performance Curves HI-54X-2 HI-54X-4, -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS 25 - 0.5 - - 0.5 - s Full - - 1.0 - - 1.0 s Break-Before Make Delay, tOPEN 25 25 80 - 25 80 - ns Enable Delay (ON), tON(EN) 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns 25 - 300 500 - 300 - ns Full - - 1000 - - 1000 ns 25 - 1.2 - - 1.2 - s 25 - 3.5 - - 3.5 - s 25 50 68 - 50 68 - dB 25 - 5 - - 5 - pF HI-546 25 - 52 - - 52 - pF HI-547 25 - 30 - - 30 - pF HI-548 25 - 25 - - 25 - pF HI-549 25 - 12 - - 12 - pF 25 - 0.1 - - 0.1 - pF Full - - 0.8 - - 0.8 V PARAMETER TEST CONDITIONS SWITCHING CHARACTERISTICS Access Time, tA Enable Delay (OFF), tOFF(EN) Settling Time (0.1%) (0.01%) "Off Isolation" Channel Input Capacitance, CS(OFF) Note 5 Channel Output Capacitance CD(OFF) Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, TTL Drive, VAL 11-119 HI-546, HI-547, HI-548, HI-549 Electrical Specifications Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = +4V; VAL (Logic Level Low) = +0.8V; Unless Otherwise Specified. For Test Conditions, Consult Performance Curves (Continued) PARAMETER TEST CONDITIONS HI-54X-2 HI-54X-4, -5, -9 TEMP (oC) MIN TYP MAX MIN TYP MAX UNITS Input High Threshold, VAH Note 7 Full 4.0 - - 4.0 - - V MOS Drive (HI-546/547 Only), VAL Note 8 25 - - 0.8 - - 0.8 V MOS Drive (HI-546/547 Only), VAH Note 8 25 6.0 - - 6.0 - - V Input Leakage Current (High or Low), IA Note 4 Full - - 1.0 - - 1.0 A Full -15 - +15 -15 - +15 V 25 - 1.2 1.5 - 1.5 1.8 k Full - 1.5 1.8 - 1.8 2.0 k 25 - - 7.0 - - 7.0 % 25 - 0.03 - - 0.03 - nA Full - - 50 - - 50 nA 25 - 0.1 - - 0.1 - nA HI-546 Full - - 300 - - 300 nA HI-547 Full - - 200 - - 200 nA HI-548 Full - - 200 - - 200 nA HI-549 Full - - 100 - - 100 nA 25 - 4.0 - - 4.0 - nA Full - - 2.0 - - - A 25 - 0.1 - - 0.1 - nA HI-546 Full - - 300 - - 300 nA HI-547 Full - - 200 - - 200 nA HI-548 Full - - 200 - - 200 nA HI-549 Full - - 100 - - 100 nA Full - - 50 - - 50 nA Full - 7.5 - - 7.5 - mW ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VS Note 1 On Resistance, rON rON , (Any Two Channels) Off Input Leakage Current, IS(OFF) Off Output Leakage Current, ID(OFF) With Input Overvoltage Applied, ID(OFF) On Channel Leakage Current, ID(ON) Note 2 Note 2 Note 3 Note 2 Differential Off Output Leakage Current (HI-547, HI-549 Only), IDIFF POWER REQUIREMENTS Power Dissipation, PD Current, I+ Note 6 Full - 0.5 2.0 - 0.5 2.0 mA Current, I- Note 6 Full - 0.02 1.0 - 0.02 1.0 mA NOTES: 1. VOUT = 10V, IOUT = 100A. 2. 10nA is the practical lower limit for high speed measurement in the production test environments. 3. Analog Overvoltage = 33V. 4. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 5. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 6. VEN , VA = 0V or 4V. 7. To drive from DTL/TTLCircuits, 1k pull-up resistors to +5VSUPPLY are recommended. 8. VREF = +10V. 11-120 HI-546, HI-547, HI-548, HI-549 Typical Performance Curves TA = 25oC, VSUPPLY = 15V, VAH = +4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified -100A V2 IN OUT VIN rON = V2 100A FIGURE 1A. ON RESISTANCE TEST CIRCUIT 1.4 1.2 1.1 TA = 25oC 1.0 TA = 55oC 0.9 0.8 0.7 0.6 -10 -8 -6 -4 -2 0 +2 +4 +6 +8 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 5 +10 ANALOG INPUT (V) 6 7 8 9 10 11 12 13 14 SUPPLY VOLTAGE (V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 100nA LEAKAGE CURRENT 10nA ON LEAKAGE CURRENT ID(ON) OFF OUTPUT CURRENT ID(OFF) +0.8V EN OUT 1nA A 10V OFF INPUT LEAKAGE CURRENT IS(OFF) 100pA 10pA 25 50 75 100 TEMPERATURE (oC) 125 FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT 11-121 ID(OFF) ON RESISTANCE (k) NORMALIZED ON RESISTANCE (REFERRED TO VALUE AT 15V) TA = 125oC 1.3 10V 15 HI-546, HI-547, HI-548, HI-549 Typical Performance Curves TA = 25oC, VSUPPLY = 15V, VAH = +4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) OUT OUT IS(OFF) A +0.8V A EN 10V ID(ON) EN 10V 10V 10V +2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT FIGURE 2D. ID(ON) TEST CIRCUIT NOTE: 1. Two measurements per channel: +10V/-10V and -10V/+10V. (Two measurements per device for ID(OFF): +10V/-10V and -10V/+10V.) FIGURE 2. LEAKAGE CURRENT ANALOG INPUT CURRENT (IIN) 15 5 12 4 9 3 6 2 OUTPUT OFF LEAKAGE CURRENT ID(OFF) 3 1 0 0 15 18 21 24 27 30 33 ANALOG INPUT OVERVOLTAGE (V) OUTPUT OFF LEAKAGE CURRENT (nA) ANALOG INPUT CURRENT (mA) 18 A IIN A ID(OFF) VIN 36 FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF LEAKAGE CURRENT vs ANALOG INPUT OVER-VOLTAGE FIGURE 3B. ANALOG INPUT OVERVOLTAGE TEST CIRCUIT FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARACTERISTICS 14 -55oC SWITCH CURRENT (mA) 12 10 25oC 125oC 8 6 VIN 4 A 2 0 0 2 4 6 8 10 12 VOLTAGE ACROSS SWITCH (V) 14 FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. ON CHANNEL CURRENT TEST CIRCUIT FIGURE 4. ON CHANNEL CURRENT 11-122 HI-546, HI-547, HI-548, HI-549 Typical Performance Curves TA = 25oC, VSUPPLY = 15V, VAH = +4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued) 8 6 +V IN 1 A3 50 VSUPPLY = 10V 2 +4V A1 IN 2 THRU IN 15 A0 IN 16 EN GND VA 10V/5V HI-546 A2 VSUPPLY = 15V 4 +15V/+10V +ISUPPLY SUPPLY CURRENT (mA) A 10V/ 5V OUT -V 10k A 0 1K 10K 100K 1M 10M 50pF -ISUPPLY -15V/-10V TOGGLE FREQUENCY (Hz) Similar connection for HI-547/HI-548/HI-549. FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5. SUPPLY CURRENT +15V 900 ACCESS TIME (ns) VREF A3 700 VA 50 10V IN 2 THRU IN 15 A2 600 +V IN 1 A1 HI-546 A0 IN 16 VREF = OPEN FOR LOGIC HIGH LEVEL < 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V 800 10V PROBE 500 +4V EN GND OUT -V 400 10k 300 3 4 5 6 8 7 9 10 11 LOGIC LEVEL (HIGH) (V) 12 13 14 -15V 15 Similar connection for HI-547/HI-548/HI-549. FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 6B. ACCESS TIME TEST CIRCUIT FIGURE 6. ACCESS TIME Switching Waveforms VAH = 4.0V 1/2 VAH ADDRESS DRIVE (VA) VA INPUT 2V/DIV. 50% 0V +10V OUTPUT 90% OUTPUT A 5V/DIV. -10V tA 200ns/DIV. FIGURE 7A. ACCESS TIME MEASUREMENT FIGURE 7B. ACCESS TIME WAVEFORMS FIGURE 7. ACCESS TIME (Refer to Figure 6B for Test Circuit) 11-123 50pF HI-546, HI-547, HI-548, HI-549 Switching Waveforms A3 (Continued) HI-546 A2 A3 +5V IN 1 HI-546 A2 IN 1 A1 IN 2 THRU IN16 +10V IN 2 THRU VA 50 +4V A1 IN 15 A0 IN 16 A0 VOUT OUT EN OUT EN GND -VA 50pF 1k GND 50 50pF 1k Similar connection for HI-547/HI-548/HI-549 Similar connection for HI-547/HI-548/HI-549 FIGURE 8A. BREAK-BEFORE-MAKE DELAY TEST CIRCUIT FIGURE 9A. ENABLE DELAY TEST CIRCUIT VAH = 4V VAH = 4V 50% 50% ADDRESS DRIVE (VA) 0V 0V OUTPUT 90% OUTPUT 90% 50% 50% t ON(EN) t OFF(EN) tOPEN FIGURE 8B. BREAK-BEFORE-MAKE DELAY MEASUREMENT FIGURE 9B. ENABLE DELAY MEASUREMENTS VA INPUT 2V/DIV. 1A ON 8A ON 1A ON OUTPUT A 0.5V/DIV. IN 1 THRU IN 8 OFF OUTPUT A 2V/DIV. 100ns/DIV. 100ns/DIV. FIGURE 8C. BREAK-BEFORE-MAKE DELAY WAVEFORMS FIGURE 9C. ENABLE DELAY WAVEFORMS FIGURE 8. BREAK-BEFORE-MAKE DELAY (t OPEN) FIGURE 9. ENABLE DELAY (t ON(EN) , t OFF(EN)) 11-124 HI-546, HI-547, HI-548, HI-549 Truth Tables HI-546 HI-548 A3 A2 A1 A0 EN "ON" CHANNEL A2 A1 A0 EN "ON" CHANNEL X X X X L None X X X L None L L L L H 1 L L L H 1 L L L H H 2 L L H H 2 L L H L H 3 L H L H 3 L L H H H 4 L H H H 4 L H L L H 5 H L L H 5 L H L H H 6 H L H H 6 L H H L H 7 H H L H 7 L H H H H 8 H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 HI-549 HI-547 A2 A1 A0 EN "ON" CHANNEL PAIR X X X L None L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 11-125 A1 A0 EN "ON" CHANNEL PAIR X X L None L L H 1 L H H 2 H L H 3 H H H 4 HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 83.9 mils x 159 mils x 19 mils METALLIZATION: TRANSISTOR COUNT: Type: CuAl Thickness: 16kA 2kA HI-546: 485 HI-547: 485 PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-546 EN (18) A0 (17) A1 A2 (16) (15) HI-547 A3 VREF (14) (13) EN (18) GND (12) A0 (17) A1 A2 (16) (15) NC VREF (14) (13) GND (12) IN 1B (11) IN 2B (10) IN 1 (19) IN 9 (11) IN 1A (19) IN 2 (20) IN 10 (10) IN 2A (20) IN 3 (21) IN 11 (9) IN 3A (21) IN 3B (9) IN 4 (22) IN 12 (8) IN 4A (22) IN 4B (8) IN 5 (23) IN 6 (24) IN 13 (7) IN 14 (6) IN 5A (23) IN 6A (24) IN 5B (7) IN 6B (6) IN 7 (25) IN 15 (5) IN 7A (25) IN 7B (5) IN 8 (26) IN 16 (4) IN 8A (26) IN 8B (4) V- (27) OUT (28) +V (1) V- (27) NC (2) 11-126 OUT A (28) +V (1) OUT B(2) HI-546, HI-547, HI-548, HI-549 Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm 83 mils x 108 mils x 19 mils TRANSISTOR COUNT: METALLIZATION: HI-548: 253 HI-549: 253 Type: CuAl Thickness: 16kA 2kA PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Type: Nitride Over Silox Nitride Thickness: 3.5kA 1kA Silox Thickness: 12kA 2kA NOTE: The substrate appears resistive to the -VSUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -VSUPPLY potential. Metallization Mask Layouts HI-548 IN 6 (11) IN 7 IN 8 (10) (9) HI-549 OUT (8) IN 4 IN 3 (7) (6) IN 3B IN 4B OUT B (11) (10) (9) OUT A (8) IN 4A IN 3A (7) (6) IN 5 (12) IN 2 (5) IN 2B (12) IN 2A (5) +V (13) GND (14) IN 1 (4) -V (3) IN 1B (13) +V (14) IN 1A (4) -V (3) A2 (15) A1 (16) A0 (1) GND (15) EN (2) 11-127 A1 (16) A0 (1) EN (2)