ANALOG DEVICES LCM0S 10-Bit Sampling A/D Converters AD7579/AD7580 FEATURES 20s Conversion Time On-Chip Sample-Hold 50kHz Sampling Rate 25kHz Full-Power Input Bandwidth Choice of Data Formats Single +5V Supply Low Power (50mW) Skinny 24-Pin DIP and 28-Terminal Surface Mount Packages GENERAL DESCRIPTION The AD7579 and AD7580 are 10-bit, successive approximation ADCs, They have differential analog inputs that will accept unipolar or bipolar input signals while operating from only a single +5V supply. Input ranges of 0 to +2.5V, 0 to +5V and +2.5V are possible with no external signal conditioning. Only an external 2.5V reference and clock and control signals are required to make them operate. With conversion time of less than 20s and an on-chip sample-hold amplifier, the devices are ideally suited for digitizing ac signals. The maximum sampling rate is 50kHz, giving an input bandwidth of 25kHz. The parts are specified not only with traditional static specifications such as linearity and offset but also with dynamic specifications (SNR, Harmonic Distortion, IMD). The AD7579 and AD7580 are microprocessor-compatible with standard microprocessor control inputs (CS, RD, WR, RDY, INT) and data outputs capable of interfacing to high-speed data buses. There is a choice of data formats, with the AD7579 offering an (8 +2) read and the AD7580 offering a 10-bit parallel word. Space saving and low power are also features of these devices. They dissipate less than S0mW from a single + SV supply and are offered in a 0.3, 24-pin package and in plastic/ceramic chip carrier for surface mounting. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assurned by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result fram its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAMS Voo R al Vin tA (4 R SAMPLING Vint +1B (2 n + OMPARATOR Vint 1A G Nw - AD7579 Vint 18 (4 _ Vaer (5 | 10-BIT DAC ts (7 wr (8 0 CN ad IN THREE 22) 0B7 1 DATA DATA STATE 0 8 aD (s 1 ratTcH SELECTOAT 8 | aGereRS __ CONTROL Ty mv is) DBO int (0 LoGic cik G1 SAR le HEEN (13 ] > es 4 AGND DGND re. Von a R SF ValtiaA R SAMPLING AD7580 Vint +18 (2 +\_ COMPARATOR R Vii -14 G - R Vint 1B (4 - Vaer (5 10-BIT DAC ws of PN THREE hom 10 | DATA) aot state | 10! wa (3 LATCH) ray] BUFFERS py bBo RD (8)-*) contro - mG Loic sar CLK (11 r] oS Rov (3, AGND DGNO PRODUCT HIGHLIGHTS 1. 20us conversion time with on-chip sample-hold makes the AD7579 and AD7580 ideal for audio and higher bandwidth signals, e.g., modem applications. 2. Differential analog inputs can accept unipolar or bipolar input signals, but only a single, +5V power supply is needed. 3. Versatile and easy-to-use digital interface has fast bus access/ relinquish times, allowing connection to most popular micro- processors. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 Telex: 924491 Cable: ANALOG NORWOODMASS a)AD7579/AD7580SPECIF (Voo = +5V + 5%, Veer = +2.5V, AGND = DGND = OV; fer, = 2.5MHz; All specifications Tyiy to Tyax unless otherwise noted. Test conditions as in Figure 12 unless otherwise stated). ICATIONS JA K, Parameter Versions Versions S Version Units Conditions/Comments STATIC CHARACTERISTICS These specifications apply for the Resolution 10 10 10 Bits three Analog Input Ranges. See Differential Applications. Integral Nonlinearity 1 +2 +1 LSB max No missing codes guaranteed over the Differential Linearity Error 09 +0.9 +0.9 LSB max full temperature range. Full-Scale Error +5 +5 +5 LSB max Zero Code Error? +2 +1 +2 LSB max Connected as in Figure 12. +3 +2 +3 LSB max Connected as in Figure 14or 15S. Power Supply Rejection +0.5 +0.5 +0.5 LSB max 4.75V<Vpp<5.25V DYNAMIC CHARACTERISTICS** Conversion Time 16.9 16.9 16.9 ps min fork = 2.5MHZz, twr = 100ns. 18.5 18.5 18.5 ys max See Functional Description. Sampling Rate 50 50 50 kHz max Clock Range 250/2.5 250/2.5 250/2.5 kHz min/MHz max Signal-to-Noise Ratio 55 55 55 dB min See Terminology. Ta = 25C. 58 60 58 dB typ Total Harmonic Distortion 58 58 58 dB max Ta=25C. - 64 -68 64 dBtyp Intermodulation Distortion -67 -67 -67 dBtyp This is characterized to both SMPTE and CCITT standards. T, = 25C. Slew Rate 160 160 160 mV/s max See Terminology ANALOG INPUT RANGES Figure 12 AD7579/AD7580 connected as in Figure 12 Span Veer VREF VreF Vmax Common-Mode Range Oto Vpp Oto Vpp Oto Vpn V max CMRR 0.5 0.5 0.5 LSB/V typ Figure 14 AD7579/AD7580 connected as in Figure 14 Span 2VREF 2VREF 2VREF V max Common-Mode Range Oto 2Vpp 0to2Vpp O0to2Vpp V max CMRR 0.5 0.5 0.5 LSBV/V typ Figure 15 AD7579/AD7580 connected as in Figure 15 Span 2VREF 2VREF 2VREF V max Common-Mode Range Vrerrto Veer to Vrer to V max (2Vpp VrrF) | (2Vpp- Vrer) | @Vpp Vrer) CMRR 0.5 0.5 0.5 LSB/V typ ATTENUATOR INPUT RESISTANCE 5/15 5/15 S/S kO min/kQ max 10k typical. Resistance measured between. Vin( +A, Vin( +B or Ving A, Vin( )B COMPARATOR INPUT RESISTANCE 10 10 10 MQ) min AD7579/AD7580 connected as in Figure 12 REFERENCE INPUT . Veer (For Specified Performance) +2.5 +2.5 +2,5 Vv +5% Iner 1.5 15 15 mA max LOGIC INPUTS CS, RD, WR, HBEN, CLK Vin; Input Low Voltage 0.8 0.8 0.8 V max Vin Input High Voltage 2.4 2.4 2.4 Vmin Ip, Input Current 25C | +1 +1 pA max Vi~=0o0r Vpp Tmin tO Tinax +10 +10 +10 pA max Vin = 0or Vpp Cin; Input Capacitance* 10 10 10 pF max LOGIC OUTPUTS DBO to DB7 (DB9) VoL; Output Low Voltage 0.4 0.4 0.4 V max Isinx = 1.6mA Vou, Output High Voltage 4.0 4.0 4.0 Vmin Tsource = 400pA Floating State Leakage Current +1 +1 +10 pA max Vour=0to Vpn Floating State Output 10 10 10 pF max Capacitance* RDY, INT Vox, Output Low Voltage 0.4 0.4 0.4 V max Isinx = 1.6mA POWER REQUIREMENT Vpp +5 +5 +5 Vv + 5% for Specified Performance Ipp 10 10 10 mA max Typically 5mA with Vpp= + 5V Power Dissipation 50 50 50 mW max NOTES "Temperature Ranges as follows: J, K Versions; 0 to + 70C A,B Versions; 25C to + 85C S Version; 55C to + 125C ?Zero code error and gain error adjusted to zero. 3Zero code error is measured with respect to an ideal first code transition which occurs at 1/2LSB. Sample tested at 25C to ensure compliance. ese specifications apply for full-scale input signals up to 20kHz. SAccuracy may degrade at conversion times other than those specified. 7Vin( + ) must always be equal to or more positive than Vjjq( ), in Figures 12, 14, 15. Specifications subject to change without notice. 2- REV. AAD7579/AD7580 TIMING SPECIFICATIONS Limit at Limit at Limit at 25C Tins T max Trnin> T max Parameter**** | (All Grades) | (J, KK, A,BGrades)| (S Grade) Units | Test Conditions/Comments ty 0 0 0 nsmin | CSto WR Setup Time tz 40 50 50 nsmin | WR Pulse Width t3 0 0 0 nsmin | CSto WR Hold Time & 100 100 120 nsmax | WRtoINT Propagation Delay ts 0 0 0 nsmin | CSto RD Setup Time te ti ti ti2 ns min RD Pulse Width ty 0 0 0 nsmin | CS toRD Hold Time tg 20 20 30 nsmin | HBENtoRD Setup Time ty 10 10 10 nsmin | HBEN toRD Hold Time tio 110 135 150 nsmin | RDY Access Time ty 100 100 120 osmax | RD to INT Propagation Delay ti 110 135 150 ns max | Data Access Time After RD tp 10 10 10 nsmin | Data Hold Time, RDY Hold Time 65 80 90 ns max NOTES 1. Timing specifications are sample tested at + 25C to ensure compliance. All input control signals are specified with tr=tr=20ns (10% to 90% of +5V) and timed from a voltage level of + 1.6V. 2. tg, thos th, and t)2 are measured with the load circuits of Figures 3 and 5 and defined as the time required for an output to cross 0.8V or 2.4V. 3. tyg is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 4. 4. INT and RDY are open-drain outputs and need 3k external pull-up resistors for operation. Specifications subject to change without notice. +5V 3k. 4k ef DBN DBN 3k 100pF 100pF we SO ib b DGND = r a. High-Z to Vow b. High-Z to Vor *]NT HAS A 3k EXTERNAL PULL-UP RESISTOR Figure 3. Load Circuits for Access Time Tests (t;2) +5V Figure 1. AD7579/AD7580 Start Cycle Timing 3ko DBN DBN l 1 3k 10pF 10pF a se L JL DGND DGND rr - if a. Vow to High-Z b. Vor to High-Z | ae he's Figure 4. Load Circuits for Output Float Delay {t;3) ' { forts) I ! \ | ae i [ ! 3kQ int+ ; \ RDY* ao tet \ RDY VALID I a t" 1 be-tiz-o4 \ | HIGH IMPEDANCE DATA HIGH IMPEDANCE _ _ <x DATA VALID | SE Goon b *INT AND RDY HAVE 3k{2 EXTERNAL PULL-UP RESISTORS a. High-Z to Vor b. Vo, to High-Z Figure 5. Load Circuit for INT Propagation Delays Figure 2, AD7579/AD7580 Read Cycle Timing REV. A -3-AD7579/AD7580 ABSOLUTE MAXIMUM RATINGS* VpptoAGND ..............-- 0.3V to +7V Vpp toDGND .......... 0000 +0.3V to +7V AGND toDGND ................ -0.3V, Vpp Digital Input Voltage to DGND Digital Output Voltage to DGND CLK Input Voltage to DGND -0.3V, Vpp +0.3V 0.3V, Vpp +0.3V -0.3V, Vpp +0.3V Vrer toAGND ... 2... . 2.02.2 000.% 0.3V, Vop Vin(+ A, Vin(+)B to AGND (Figure 12) ............-.. 0.3V, Vpp +0.3V Vin( A, Vin()B to AGND (Figure 12) 2... .......0.05- 0.3V, Vpp +0.3V Vin(+)A to AGND (Figure 14)... . . 0.6V, 2Vpp +0.6V Vin()A to AGND (Figure 14)... . . 0.6V, 2Vpp +0.6V Vin(+)A to AGND (Figure 15) rs _ VREF _ 0.6V, 2Vpp _ VREF +0.6V Vin()A to AGND (Figure 15) Vrer 0.6V, 2Vpp Vrer +0.6V Operating Temperature Range Commercial (J, K Versions) Industrial (A, B Versions) ee ee 0 to +70C 25C to + 85C Extended (S Version) ............ 55C to +125C Storage Temperature Range. ........ 65C to + 150C Lead Temperature (soldering, 10sec) ......... + 300C Power Dissipation (Any Package) to +75C ..... 450mW Derates Above + 75C by . 2... 2... ee ee ee 6mW/C *Suress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protect- ed; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. Ur a a ESD SENSITIVE DEVICE TERMINOLOGY LEAST SIGNIFICANT BIT (LSB) An ADC with 10-bit resolution can resolve one part in 2) (1/1024 of full scale). For the AD7579/AD7580 operating in the unipolar range with 2.5V span, one LSB is 2.44mV. ZERO CODE ERROR This is a measure of the difference between the ideal (0.5LSB) and the actual differential analog input level required to produce the first positive LSB code transition (00... 00 to 00... O1). FULL-SCALE ERROR The ideal difference between the first transition voltage and last transition voltage for an ADC is (F.S. 2LSB). AD7579/AD7580 Full-Scale Error is defined as the deviation between this ideal difference and the measured difference. COMMON-MODE RANGE The voltage at both inputs to the AD7579/AD7580 can be raised above or lowered below analog ground potential, providing Vin( +) is equal to or more positive than Vpy(). Figures 12, 14, and 15 show circuits for various Analog Input Ranges. The Common-Mode Range represents the voltage extremes which can be applied to the circuits of Figure 12, 14 or 15. For example, when the AD7579/AD7580 is connected as in Figure 15, the Common-Mode Range is 2.5V to +7.5V. SLEW RATE : Slew Rate is the maximum allowable rate of change of input signal such that the digital sample values are not in error. The Slew Rate performance of AD7579/AD7580 allows sampling of an input full-scale (2.5V pk-pk) sine wave up to 20kHz. SIGNAL-TO-NOISE RATIO Signal-to-Noise Ratio (SNR) is measured signal to noise at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency. SNR is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quaritization noise. The theoretical SNR for a sine-wave input is given by: SNR =(6.02N + 1.76) dB, where N is the number of bits in the ADC. Thus for an ideal 10-bit ADC, SNR = 62dB. INTERMODULATION DISTORTION With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequencies of mfa+nfb, where m,n = 0,1,2,3,----. Intermodulation terms are those for which m or n is not equal to zero. HARMONIC DISTORTION Harmonic distortion is the ratio of the square root of the sum-of- the-squares of the rms values of the harmonics to the rms value of the fundamental. For the AD7579/AD7580, Harmonic Dis- tortion is: 20 log \/(V27 + V3? + Va? + Vs? +V6*) dB, Vy where V, is the rms amplitude of the fundamental and V>, V3, V4, Vs, Vo are the rms amplitudes of the individual harmonics. REV. AAD7579/AD7580 ORDERING GUIDE Temperature Package Temperature Package Model!>? Range INL Option? Model?? Range INL Option AD7579IN 0C to + 70C +1LSB_ | N-24 AD7580JN 0C to + 70C +I1LSB_ | N-24 AD7579KN 0C to + 70C + 1/2LSB | N-24 AD7580KN 0C to + 70C + 1/2LSB | N-24 AD7579JP 0C to + 70C +1LSB_ | P-28A AD7580JP 0C to + 70C +1LSB_ | P-28A AD7579KP 0C to + 70C + 1/2LSB | P-28A AD7580KP 0C to + 70C +1/2LSB | P-28A AD7579AQ 25Cto +85C | +I1LSB_ | Q-24 AD7580AQ 25Cto + 85C | +1LSB_ | Q-24 AD7579BQ 25Cto +85C: | + 1/2LSB | Q-24 AD7580BQ 25Cto +85C | + 1/2LSB | Q-24 AD7579SQ 55Cto +125C |+1LSB_ | Q-24 AD7580SQ 55Cto + 125C | +1LSB_ | Q-24 AD7579SE 55Cto +125C | +1LSB_ | E-28A AD7580SE 55Cto +125C | +1LSB_ | E-28A NOTES NOTES Analog Devices reserves the right to ship ceramic (D-24A) in lieu of cerdip (Q-24) hermetic packages. 2To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheet. 312 = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip. For outline information see Package Information section. DIP VY vat 14 [7 | e 241 Voo Vint +18 [2 | 23] LC. vias [22] 87 oe 21| OBE Vaer [5 | 20 | DB5 ano [6 | AD7579 19 | DBs TOP VIEW cs |7 (Not to Scale) [48 | pB3 WR | 8 17 | DB2 RD| 3 16|DB1 INT | 10 15 | DBO (LSB) cuk [11 [14] Roy DGND] 12 13 | HBEN TTS valtiala | 24] Voo Vint +18 [2 | 23 |DBS (MSB) Vel-)AL 3 | 22 | pps Vid -1B [a | 21) 87 Veer [5 | 20 | DB6 acno [6 | AD7580 19 |DB5 TOP VIEW cs CE] (Not to Scale) 16 | DB4 wr fe] 17 | DB3 7 [3 | 16 | DB2 INT | 10 15|DB1 cuk {11 14 | DBO (LSB) DGND | 12 13 |RDY REV. A Analog Devices reserves the right to ship ceramic (D-24A) in lieu of cerdip (Q-24) hermetic packages. 2To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheet. 31D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip. For outline information see Package Information section. PIN CONFIGURATIONS LCcc = Vinl-JA Vini +) S Vinita 28 27 26 Vin(1B Vner AGND AD7579 TOP VIEW (Not to Scale) 12 13 14 15 16 17 18 EveOQovueu2z> ge 2 o 3 < a e 4 a NC=NO CONNECT a a dae 2 tot + ~ @ERo 8BaA >>> 27> 408 4 3 2 1 28 27 26 A Viai-IB 5 Vier 6 AGND 7 AD7580 Nc 8 TOP VIEW w9 {Not to Scale) WR 10 RD 11 12 13 14 zw 2 a NC =NO CONNECT DGNI NC in RDY & DBI & DBO (LSB) S DB6 DBS DB4 NC DB3 DB2 DBI DB? DB6 DB5 NC DB4 DB3 DB2 Vinl -14 |e | Vint +)B - <= NC = NOCONNECT 8 Vint 1A NC=NO CONNECT PLCC [=| Nc 13] Yoo is] ic = + 2 > [2] AD7579 TOP VIEW (Not to Scale) ha} bs] [26] [17] 9283 g 25 5 + = 2g 338 Blalcle AD7580 TOP VIEW (Not to Scale} |S] DB7 DBO (LSB) [5 | [| psaAD7579/AD7580 PIN FUNCTION DESCRIPTION (DIP PACKAGE) Mnemonic Pin Number Description Mnemonic Pin Number Description AD7579 AD7580 AD7579 AD7580 Vin(+)A 1 1 Analog Input Pin. DGND 12 12 Digital Ground. Vin(+)B 2 2 Analog Input Pin. HBEN 13 - High Byte Enable Input. Used Vin(-)A 3 3 Analog Input Pin. in AD7579 for 2 Byte Reading. Vin()B 4 4 Analog Input Pin. The four See Tables II, IV. Either the analog input pins connect to High Byte or the Low Byte the on-chip input attenuator may be read first. (see Figure 6) and may be RDY 14 13 Open Drain Output. This is configured as in Table I for accessed during Read Cycle. various input ranges. When accessed, it is low during VrReF 5 5 Veer Input. This is nominally conversion and high impedance +2.5V. when conversion is complete. AGND 6 6 Analog Ground DBO-DB7 15-22) - Three-State Data Outputs on cs 7 7 Chip Select Input. AD7579, The data format is WR 8 8 Write Input. Used with CS to right justified. start conversion. See Tables DBO-DB9_ - 14-23 Three-State Data Outputs on II, Il. __ AD7580. RD 9 9 Read Input. Used with CS to I.C. 23 = Internal connection. This pin read data. See Tables II, IIT. is connected internally on the INT 10 10 Open Drain Output. High AD7579. It should be left impedance during conversion. open and not used as a feed- Goes low when conversion is through pin in double-sided complete. printed circuit boards. CLK 11 11 Clock Input. Vpp 24 24 Positive Power Supply. This is +5V nominal. Analog Input Connections Analog Input | Common-Mode cS | WR| RD | HBEN| Function Range Vint +)A | Vint +)B | Vint =A | Viw()B | Span Range 1 Ix [x [x Not Selected Figure 12 Vind+) | Vint+) | Vin(-) | Vint-) | 2.5V OVto +5V o f1 Ji |x Selected, WAIT for WR, RD Figure 14 Vitt) | AGND | Vin(-) | AGND | 5V 0Vto + 10V o ju ji |x Start Conversion on {_ of WR . , o |1 |o Jo Enable ADC Data (8 LSBs)* Figure 15 Vint+) | Vrer Vint-) | Veer 5V 2,5Vt0 +7.5V o 11 |o |1 | Enable ADC Data(2 MSBs)* *Data is Right Justified. Table |. Analog Input Ranges Table Il. AD7579 Truth Table CS | WR | RD | Function HBEN | DB7_|DB6 | DBS | DB4 | DB3 | DB2 | DBI | DBO 1 x x Not Selected _ Td 0 1 1 Selected, WAIT for. WR, RD LOW | DB7 | DB6 | DBS | DB4 | DB3 | DB2 | DB! | DBO o |u fl Start Conversion on Y_ of WR HIGH | EOC*}0 0 0 0 0 DB9 | DBS 0 [1 |0 | Enable ADC data(10 Bits) _ *EOC is an internal End of Conversion flag. Table Ill. AD7580 Truth Table Table IV. AD7579 Output Data Format CIRCUIT INFORMATION ANALOG INPUT CIRCUITRY . The AD7579 is a 10-bit ADC with an (8+ 2) output bus structure greater than or equal to AGND and that V + is less than or designed for 8-bit microprocessor systems. The AD7580 is a 10- equal to Vpp. These conditions must be satisfied when using bit ADC with a 10-bit parallel output bus structure. The ADC the ADC in any of the voltage ranges. circuitry is identical in both parts. Block diagrams are shown on the first page of this data sheet. Vint +38 noe R v+ Figure 6 shows the input circuitry to the ADC comparator. Vin( +18 v v_ This comparator has differential inputs which are accessed through Vind VA nT _ the attenuator networks made up of resistors R. The attenuators Vint 18 rl Vo=AHV+ ~V~) ~Voncl can be used to scale and offset analog input voltages, and this is done in Figures 14 and 15 to alter the basic ADC input range. The analog inputs to the comparator are differential with the provisos that V+ is always greater than or equal to V, V is Voac Figure 6. AD7579/AD7580 Input Circuit -6- REV. AAD7579/AD7580 Figure 7 shows an ac equivalent input circuit for the AD7579/ AD7580 when used in the 2.5V Unipolar Mode of Figure 12. The ADC comparator is a sampled data comparator and the input circuitry for this is represented by Sa, Req and Ca. Req is a combination of the switch-on resistance and the input impedance of the comparator. When conversion starts, Vin( +) is sampled for at least (2tcr~. + twr + 200ns) before the comparator goes into the hold mode. This means that the analog input has a minimum of 1.1ps (fepK = 2.5MHz, twr = 100ns) to settle before the comparator makes a decision. By using the typical values in Figure 7 for R, Req and Ca, the input time constant is 50ns. Settling to + 1/4LSB in a 10-bit system takes 8.3 time constants or 415ns in this case. This means that Vjy( +) has plenty of time to settle before the ADC comparison cycle begins. It is important to remember that any source resistance or source capacitance appearing at the input will also increase the settling time and this should be kept to a minimum in all cases. R SkQO Vil +38, w7F SAMPLING SWITCH, Vel +18 Cs CLOSED = REO v O.5pF Sa 25k AGND , R Cy 5kQ. 10pF Vinl -1A, Tr wT GL Vl 1B c AGND 0.5pF Gaon Figure 7. AD7579/AD7580 Equivalent Input Circuit During Sampling With a 2.5MHz clock, the AD7579/AD7580 has a maximum conversion time of 18.5ys. If lus is allowed for reading the data outputs, the maximum sampling rate for the device is 50kHz. This means that the maximum analog input frequency is 25kHz according to the Nyquist theory. The ADC input impedance in the Unipolar Configuration of Figure 12 is 1OMQ. A medium bandwidth op amp will drive this at 25kHz. When the input attenuators are used for signal conditioning, the input impedance is 10kQ. The drive requirements on the amplifier will now be greater but any errors resulting will be gain errors only. Suitable op amps for driving the AD7579/AD7580 in any of the input configurations are the AD711, AD OP-27, AD544. These will deliver specified device performance over the input bandwidth. REFERENCE INPUT The AD7579/AD7580 Vrer input is connected to the on-chip DAC. The input impedance of this is code dependent and the greatest variation occurs when the DAC resistors are at their lower limit.-In this case, the impedance changes from 1.75k0 to 5.25kQ, as the DAC is switched. To ensure that the error during conversion is less than 1/2LSB, the Reference output impedance should be less than 1. References which satisfy this are the AD580 (shown in Figure 8) and the AD 1403 from Analog Devices. If a trimmable reference such as the AD584 is used, it is possible to trim out the ADC full-scale error by adjusting the reference output. REV. A -7- INTERNAL SAMPLE-AND-HOLD When an ADC without sample-and-hold is used to digitize ac signals, the analog input must not change by more than 1/2LSB during the conversion. This puts severe limitations on the allowable input signal bandwidth to such devices. A sample-and-hold amplifier must be used in front of the ADC if increased bandwidth is required. The charge balanced comparator used in the AD7579/ AD7580 for the A/D conversion provides the user with an inherent sample-and-hold function. The ADC is specified to work with sampling rates up to 50kHz. This rate allows time todoa conversion and read the result into memory. Since at least two samples are needed to define an input sine wave according to the Nyquist theory, the analog input signal bandwidth for the AD7579/AD7580 is 25kHz. Figures 20, 21 and 22 show the performance of the ADC when digitizing ac signals. Vpp = +5V ADS580 | +E AD7579/80 Figure 8. Using the AD580 as the Reference for the AD7579/AD7580 While the AD7579/AD7580 is converting, V+ (see Figure 6) is held and V is being tracked. This limits the rate of change, 4/dt, on Vin(). For example, if the Common-Mode frequency is 60Hz, then the allowable amplitude of this to introduce no more than 1/2LSB linearity error is 160mV pk-pk. As the Common- Mode frequency increases, this allowable amplitude decreases. Figure 9 shows how a 100mV pk-pk Common-Mode signal affects linearity error as its frequency is increased up to 1kHz. INTEGRAL LINEARITY ERROR (LSBs) COMMON-MODE AMPLITUDE = 100mV pk-pk COMMON-MODE FREQUENCY (Hz) L L L i 250 500 750 1k Figure 9. AD7579/AD7580 Error vs. Common-Mode FrequencyAD7579/AD7580 CLOCK INPUT The AD7579/AD7580 is specified to operate with a 2.5MHz clock on the CLK input pin. This pin may be driven directly by CMOS or TTL buffers. The mark/space ratio on the clock can vary from 40/60 to 60/40. As the clock frequency is slowed down, it can result in slightly degraded accuracy performance. This is due to leakage effects on the hold capacitor in the internal sample-and-hold. Figure 10 is a typical plot of accuracy versus clock frequency for the ADC. NORMALIZED LINEARITY ERROR Nv 20k 50k = 100k 1M 2M 2.5M_ feun (Hz) Figure 10. Normalized Linearity Error vs. Clock Frequency FUNCTIONAL DESCRIPTION Figure 11 shows the events sequence when the AD7579/AD7580 is converting. The device is selected when CS goes low and the first phase of conversion begins when WR goes low. This is an initializaton phase and causes the internal DAC to be set to full scale, comparators set to auto-zero and V+ (see Figure 6) to be sampled. The second phase begins some time after WR goes back high. This time can vary between 0 and 4 clock periods and depends on the state of an on-chip divide-by-4 counter which is used for internal synchronization. This is the start of the successive approximation procedure. V+ is held after 2-1/2 clock periods have elapsed. V is sampled and the DAC output is switched into the comparator. There is (1-1/2 x tc_x) left for comparison and then the MSB result is latched. The MSB test takes 4 clock cycles as do each of the succeeding bit tests. Thus, the successive approximation always takes 40 clock cycles. When all the bits have been tested, the SAR holds a 10-bit word representing the input signal. After a further 2 clock cycles this is transferred to a three state output latch, and three internal START SUCCESSIVE APPROXIMATION -SB DECISION MSB DECISION END OF CONVERSION CLK i START CONVERSION } Figure 11. AD7579/AD7580 Conversion Sequence flag bits (RDY, INT, EOC) are set. The user can access the data outputs by bringing RD and CS low. RDY and INT are both open drain outputs with RDY accessed by RD and INT being permanently available. When INT is loaded with the circuit of Figure 5(a), it typically takes 60ns to reach Vor. EOC is only available on the AD7579 (see Table V). It appears on DB7, when reading the high Byte. When the ADC is finished the conversion, the conditions of V+, V- and the comparators are maintained and the ADC is now ready to start a new conversion. If WR and CLK are asyn- chronous, the total time from start to end of conversion is variable. Minimum conversion time is (twr +42 tc_K), and maximum conversion time is (twr +46 tcLK)- APPLYING THE AD7579/AD7580 The AD7579/AD7580 has a flexible input stage consisting of two input attenuators. It is possible to realize various analog input ranges by reconfiguring these attenuators. The follow- ing diagrams show the ADC connected in the most popular configurations. DIFFERENTIAL APPLICATIONS Figure 12 shows the AD7579/AD7580 connected in the standard unipolar mode. Figure 13 and Table V show the ideal input/output +5V +2.5V & + + I 47k L 0.1pF I 47 uF 1 0.1pF ; Veer Vpp Vin( +14 NAA ROY F | conTROL int QUTPUTS Vinl+) O4 po Vt Vial +8 AAA CLK Fe for x = 2.5MHz AD7579 Ge ke Vin 1A oe AD7580 Vv RD F* | contro. Vm) Lye wa INPUTS Vint - 1B - We HBEN* [- , DBO - DB9 (DB7) AGND DATA OUT DGND *AD7579 ONLY Figure 12. Unipolar 2.5V Operational Diagram OUTPUT CODE FULL-SCALE TRANSITION WA 11...110 11...101 - ' I 7 t t 7 ! e ese2sv v a. FS | | 7 USB = F504 I wf 7 ' 1 7 1 y 00...011 00...010 00...001 00...0009 Sahin ee hl 1 2 3 $ Fs LSB LSBs LSBs FS_ 188 Figure 13. Ideal Input/Output Transfer Characteristic REV. AAD7579/AD7580 Differential Analog Digital Output Input, Volts DB9 DBO +0.000 00 0000 0000 |. +0.00244 } 00 0000 0001 | a x x Y +1.24756 rook at in) +1.25 10 0000 0000 | + 1.25244 100000 0001 | r +2.49512 Moi iio 7 + 2.49756 Wow wn Table V. Input/Output Code Table for Figure 12 transfer characteristic and the input/output code table respectively. Code transitions occur between successive integer LSB values (i.e., 1/2LSB, 3/2LSBs, etc.). The output code is straight binary with ILSB = FS/1024 = 2.5/1024V = 2.4mV. The input voltage span is 2.5V and the common-mode range is OV to +5V, when Vpp = 5V. This means that the lowest voltage which can be tolerated at any of the analog inputs is OV, and the highest voltage which can be tolerated is + 5V. Figures 14 and 15 show the input attenuators on the AD7579/ AD7580 configured to change the basic range of the device. A 5V range can be configured by grounding one end of each at- tenuator and applying the differential input to the other ends. This is shown in Figure 14. The span is 5V and the common-mode range is 0 to + 10V. In Figure 15, one end of each attenuator is tied to Vrer (2.5V), and this allows each of the other legs to go to 2.5V without causing the comparator input to go negative. Assuming Ver is 2.5V, the span of this circuit is SV and the common-mode range is ~2.5V to +7.5V. Note that reducing Vpp below 5 volts causes a corresponding reduction in CMR. See Specifications page for full details. Vpo = +5V AD7579* AD7580 Vil +) Vint+) Vini-) OUTPUT CODE ov 00 o00 occa 0.00488V 00 0000 0001 2.500V 10 0000 0000 4.99612V 44:12111111 Vint -} *DECOUPLING CIRCUITRY AND CONTROL CIRCUITRY AS IN FIGURE 12 Figure 14. 5V Span with 0 to 10V CMR Vpp= +5V AD7579* Vaee (2.5) AD7580 Vinl +) Vinl +) Vint) OUTPUT CODE ov 00 c000 0000 0.00488V 00 9000 0001 2.500V 10 0000 0000 4.99512V 110199191911 Vinl-} OJ *DECOUPLING CIRCUITRY AND CONTROL CIRCUITRY ASIN FIGURE 12 Figure 15. 5V Span with 2.5V to +7.5V CMR REV. A AD7579* AD7580 Veer (2.5V} Vint +) OUTPUT CODE 2.500V 00 9000 0000 Vini +) O4 2.49512V 00 0000 0001 0.00V 10 0000 0000 +2.49592V 0 11:1111 1111 *DECOUPLING CIRCUITRY AND CONTROL CIRCUITRY AS IN FIGURE 12 Figure 16. Single-Ended Bipolar Operation, 2.5V to +2.5V SINGLE-ENDED APPLICATIONS In many cases, users of the AD7579/AD7580 will want to measure single-ended input voltages (i.e., ground referred signals). The circuits of Figures 12, 14 and 15 can be easily adapted to accept such signals. If Vixy() in Figure 12 is tied to AGND, then the analog input range is OV to +2.5V. By connecting Vin() of Figure 14 to AGND, the analog input range becomes OV to +5V. Figure 15 can be modified as in Figure 16 to accept input voltages in the range 2.5V to +2.5V. Each of these circuits are special cases of the Differential Input circuits and are achieved by making the negative input to the internal comparator equal to AGND. OFFSET AND FULL-SCALE ADJUSTMENT Figure 17 shows the AD7579/AD7580 connected in the single- ended Unipolar 2.5V range with offset and full-scale calibration circuitry. The zero error of the ADC is the deviation of the actual LSB transition from the ideal LSB transition. In many cases, the zero of the ADC will not need adjustment. When it does, R1 in Figure 17 provides 25mV of adjustment which is sufficient to null out both the op amp and ADC offset error. Resistors R3 and R4 bias Vyy() to approximately 8mV and ensure that the offset error is never positive. This allows the error to be nulled in the single supply system of Figure 17. Apply +0.5LSB to Vpy and adjust R1 until the ADC output code flickers between 00 000 and 00 001. For full-scale calibration, apply a voltage of (2.5V 1.5LSB) to Vin. Then adjust R2 until the output code flickers between 11 sees 110 and 11 111. When the full-scale calibration is complete, return to the offset adjustment procedure and check that further adjustment is not necessary. *DECOUPLING CIRCUITRY OMITTED FOR CLARITY Figure 17. Offset and Full-Scale Calibration for Single- Ended CircuitAD7579/AD7580 Veer =2.5V Vaer=2.5V Vp =5V LOAD CELL AD7579/AD7580 Vv NOTES 1, Re =19.6k9?, Rg = 1.21ki2. 2. SEE AD625 DATA SHEET FOR RECOMMENDED INPUT PROTECTION CIRCUITRY. 3. POWER SUPPLY AND REFERENCE DECOUPLING OMITTED FOR CLARITY. Vv Figure 18a. AD7579/AD7580 and AD625 in a Data Acquisition System AD7579/AD7580 IN DATA ACQUISITION SYSTEMS The AD7579/AD7580 is suitable for many data acquisition circuits. Figure 18a shows one such circuit in which a load cell is used to produce a signal in response to an applied force. Typically these transducers produce 30mV full scale per volt of excitation. Since the excitation in this case is 2.5V, the output from the load cell is +75mV when the maximum specified force is applied. The AD625 Instrumentation Amplifier is set for a gain of 33.33 which means that the input signal to the ADC is +2.5V. Thus, the AD7579/AD7580 is configured in the single- ended, +2.5V range of Figure 16. When no force is applied to the load cell, the ADC output will sit at mid-scale. With maximum negative force applied the ADC output will be all zeros; whereas, with maximum positive force the output will be all 1s. Offset and gain calibration of this system can be accomplished by trimming the offsets and gain of the instrumentation amplifier. Figure 18b shows a differential transducer unbalanced by ~100. supplying a 0 to 20mV maximum signal. The resistors are chosen for a gain of 125, and the ADC is configured to accept 0 to 2.5V differential signal. This is a lower-cost alternative to using an instrumentation amplifier. Note that in the circuits of Figure 18, Veer for the ADC and the excitation voltage for the load cell are both +2.5V. If the same reference drives both these points, then the ADC operation is ratiometric which eliminates system errors due to reference drift. The main reason why the same reference would not be used to drive both load cell and ADC is physical location. When the load cell is remote from the ADC circuitry, it might not be practical to have the same drive for both circuits. Veer = 2.5V 5 Veer = 2.5V 3500) 35022 121k 4 75k 3502: Figure 18b. AD7579/AD7580 and AD648 in a Data Acquisition System APPLICATIONS HINTS Layout: To obtain the best performance from the AD7579/AD7580, lay it out on a printed circuit board. Digital and analog lines on the board should be separated as much as possible. In particular, take care not to run any digital track adjacent to an analog signal track or underneath the AD7579/AD7580. The analog inputs should be screened by AGND. Grounding: Establish a single-point analog ground (STAR ground) at Pin 6 (AGND) or as close as possible to the AD7579/AD7580. This is shown in Figure 19. Pin 12 (AD7579/AD7580 DGND) and all other analog grounds should be connected to this single analog ground point. However, do not connect any other digital grounds to this analog ground point. Low impedance analog and digital power supply returns are essential to low noise operation of the ADC and these tracks should be kept as wide as possible. Noise: Input signal leads to Vin(+)A, Vin(+)B, Vin()A, Vin( )B and signal return leads from AGND (Pin 6) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible a shielded cable between source and ADC is recommended. ANALOG DIGITAL SUPPLY SUPPLY +15V GND -15V +5V c Set BEE e41HHk aHeH 4 ANALOG AGND Vppo DGND DIGITAL CIRCUITRY AD Teno CIRCUITRY Figure 19. Power Supply Grounding Practice -10- REV.AAD7579/AD7580 DIGITAL SIGNAL PROCESSING APPLICATIONS In Digital Signal Processing (DSP) application areas like voice recognition, echo cancellation and adaptive filtering, the dynamic characteristics (SNR, Harmonic Distortion, Intermodulation Distortion) of ADCs are critical. For this reason, the AD7579/ AD7580 is specified dynamically as well as with standard D.C. specifications (linearity error, offset error, etc.). Figure 20 shows a 2048 point FFT plot of an AD7579/AD7580 with an input signal of 3.58kHz. The SNR is 60.1dBs. The largest harmonic appears at 2fo (7.16kHz) and is 70dB down from the fundamental. Harmonics above 3fp are in the noise floor. Note that when SNR is calculated, it includes harmonics. OdB 20dB INPUT FREQUENCY: 3.58kHz SAMPLING RATE: 51.2kHz SNR: 60.11dB 40dB SIGNAL AMPLITUDE 1 : 100dB 120dB + OHz 25.5kHz FREQUENCY Figure 20. AD7579/AD7580 Spectral Response If these were excluded the SNR figure would be closer to the ideal of 62dB for a 10-bit ADC. The relationship between Signal- to-Noise Ratio (SNR) and ADC resolution is expressed in the following equation: SNR = (6.02N + 1.76)dB This is for an ideal ADC with no differential or integral linearity errors. These errors will cause a degradation in SNR. By working backwards in the above equation it is possible to get a measure of ADC performance expressed in effective number of bits. This is shown over frequency in Figure 21 for the AD7579/AD7580. The effective number of bits typically falls between 9.7 and 9.8 corresponding to SNRs of 60.0 and 60.6dBs. 0 fF a SAMPLING RATE: 51.2kHz 85 EFFECTIVE NUMBER OF BITS ry o 5 10 15 20 a INPUT FREQUENCY - kHz Figure 21. AD7579/AD7580 Effective Number of Bits REV. A -i1- When a sine wave of specified frequency is applied to the AD7579/ AD7580 and several thousand samples are taken, it is possible to plot a histogram showing the frequency of occurrence of each of 1024 ADC codes. A perfect ADC would produce a cusp probability density function described by the equation 1 mY) = a V5 A is the peak amplitude of the sine wave and p(V) the probability of occurrence at the voltage V. If a particular step is wider than the ideal width, then the code associated with that step will accumulate more counts than the code for an ideal step. Likewise, a step narrower than ideal width will have fewer counts. Missing codes are easily seen because a missing code means zero counts for a particular code. The absence of large spikes in the histogram indicates small differential nonlinearity. The actual histogram obtained is shown in Figure 22 and corresponds very well with the ideal cusp shape. It shows that the AD7579/AD7580 has very small differential nonlinearity and no missing codes with an input frequency of 25kHz. 1200 INPUT FREQUENCY: 25kHz SAMPLE FREQUENCY: 51.2kHz NUMBER OF SAMPLES: 200,000 w 8 ou > 2 600 wi 2 9 Ww 256 12 768 1023 CODE Figure 22. Histogram Plot for AD7579/AD7580 Whenever the AD7579/AD7580 is used to sample ac signals, it is essential that the signal sampling occurs at exactly equal intervals. This minimizes errors due to sampling uncertainty or jitter. The WR command for the AD7579/AD7580 needs to be synchronized with the CLK input to ensure equal interval sampling. Two conditions must be satisfied to ensure proper synchronization: 1) The time interval between successive WR signals needs to be long enough to allow a conversion to finish and the data to be read into memory. 2) Because of the internal operation of the ADC, the number of clock pulses between successive write signals must be a multiple of four. The conversion time for the AD7579/AD7580 has a maximum value of (twr + 46 tor). If 4 teLx is allowed for reading the data outputs into a buffer then the interval between successive WR signals must be at least 50 tcLx. The easiest way to satisfy both this requirement and number 2 above is to divide fox by 64 to produce the WR signal. Alternatively, if a programmable timer/counter on a processor board is available, then it will be possible to easily divide fo_x by 52.AD7579/AD7580 MICROPROCESSOR INTERFACING Reading Data Conversion is started in the AD7579/AD7580 by bringing WR low. It is recommended that the user wait until conversion is complete before reading data. This can be achieved in any of the following ways: 1. Insert a software delay greater than the ADC conversion time between the conversion start instruction and the data read instructions. 2. Use the externally available INT signal to interrupt the microprocessor. This is an open drain output which goes low at the end of conversion. 3. On the AD7579, it is possible to interrogate the EOC status flag (See Table IV) to determine when conversion is complete. Reading may then proceed. MC68000 Interface Figure 23 shows an interface diagram for the AD7580 and the MC68000. The address decoding means that the AD7580 is a memory mapped device. For example, if the AD7580 is memory mapped as address COOOH, then a write instruction to this address will start a conversion, i.e., MOVE.W DO COOO starts a conversion. When the conversion is complete, the MC68000 acquires the result by reading from COOOH, i.-c., MOVE.W COOO, DO. A1-A23 ADDRESS BUS ( ADDRESS = AS DECODE cs . Sl RW ; MC68000 | ry RD BTACK AD7580* NY Do-D15 DATA BUS DBo-DBS LJ v' *LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 23. MC68000 to AD7580 Interface 8088 Interface The AD7579, with its (8+ 2) data format, is ideal for use with the 8088 microprocessor. Figure 24 is the interface diagram. Again, a write instruction is required to start a conversion and a read at the end of conversion reads data into the processor. For the 8088 the appropriate instructions are: MOV COOO, AX Start aconversion MOV AX,COOI Read 2 MSBs of data MOV AX,COOO Read 8 LSBs of data MNIMX - Voc AS-AIS ADDRESS BUS Ao ( 8088 Z L ; ADDRESS ae BEN (o/M -o DECODE cs RD RD WR WR AD7579* ALE F-*)STB 8282 1 n DATA BUS LJ v *LINEAR CIRCUITRY OMITTED FOR CLARITY. ADO-AD7 DBO-DB7 Figure 24. 8088 to AD7579 Interface TMS32020 Interface Figure 25 shows the AD7580 to TMS32020 interface. OUTA,PA starts a conversion and INA,PA reads data from the ADC when conversion is complete. PA is the Port Address. A0-A15 ADDRESS BUS ( ADDRESS zs os DECODE cs S32020 L b>) > a ; AD7580* DO-D15 DATA BUS DBO-DB9 Se *LINEAR CIRCUITRY OMITTED FOR CLARITY. Figure 25. TMS32020 to AD7580 Interface -12- REV. AAD7579/AD7580 PRINTED CIRCUIT BOARD LAYOUT Figure 26 is a circuit diagram showing the AD7579 or AD7580 being used to digitize an analog signal. The circuit board contains the ADC, reference, and a grid where the user can add additional circuitry. If the AD7580 is used, then links L6 and L8 should be inserted; and if AD7579 is used, L7 should be inserted with L6 and L8 omitted. Note that Pins 13 to 23 are not labelled. Depending on which ADC is used the function of these pins changes. See the Pin Function Description section for full details. Links L1 to LS at the analog input allow the user to choose various analog input ranges. With L1, L2 and L3 in place and the others omitted, the input range is OV to +2.5V. Omitting L3 allows the user to measure input voltages which have a common- mode signal. The 0V to +5V range is achieved by inserting L2, L3 and L4 and omitting L1 and LS. With L2, L3 and LS in place and L1, L4 omitted, the Analog input range is 2.5V to +2.5V. IC2 (AD580) provides the +2.5V reference for the ADC. All the input and output control signals enter and leave the board through J1, which can be a Eurocard connector or a standard edge connector. Resistors R1 and R2 are the pull-ups required for the RDY and INT open-drain outputs. Note that the complete circuit operates from a +5V power supply. The printed circuit board layout is shown in Figures 27 and 28. Figure 27 is the component side layout and Figure 28 is the solder side layout. The component overlay is shown in Figure 29. In the layout, the AD580 is kept as close to the AD7579/AD7580 as possible. The STAR ground point is located at Pin 6 (AGND) of the ADC, Pin 12 (DGND), reference ground and the analog ground plane are connected to this point. To ensure optimum performance, the AD7579/AD7580 power supply is decoupled with C1 and C2. The Vrgr input to the ADC is decoupled with C3 and C4. Note how all the decoupling capacitors are placed as close as possible to the ADC. J1 Ci/A1 Vin(+) Vin(-) O +5V Toe Ic2 AD580 | Eour 1c1 AGND AD7580/AD7579 C2/A2 } R2 4 g C17/A17 C19/A19 C7/A7 C8/A8 C9/AS C10/A10 C1IV/A11 C12/A12 C13/A13 C14/A14 C15/A15 C16/A16 C18/A18 C20/A20 C21/A21 C22/A22 C32/A32 Figure 26. Schematic for AD7579/AD7580 Board REV. AAD7979/AD7580 Tt Te, e 000060080 8 Oo seococeecoeoesooooooeoeoo 3.94 Ge eoncccsccoosocoossocooosS (100mm) 000000000000000000000000000 0000000006000000000000000000 000000000000000000000000000 000000006000000000000000000 000 000006000000000000000600 000000000600 0000000000000000 000000000000000000000000000 0000000000000000000000000008 ooV5eo eo 000000000000000000000080000 eo5ece eo 0900000000000 0000000CC0CCCO eooee e 0060000000600 00000000C000000 eocee eo 00000000000000600680000800000 ecoee eo 0000000000000 86060C00C8CCOO ecoee ee SCOCHHHHOHOHEOOOHSOHOEOOEESOOHOOOCEOCOCEOOO eceeeeeoeee oC SCOCHHCHOHOHEHHOOSSOEHHHOOHSEOOOOCOOCECECOOE ecoecoecoocoee e e vy L- Figure 27. PCB Component Side Layout for Figure 26 o | -J Figure 28. PC8 Solder Side Layout for Figure 26 -14- REV. AAD7579/AD 7580 REV. A r AD7579/AD7580 BOARD VIN(+)A VINGHB VIN{)A VIN(-)B oO a u L2 tay? Is 113 ca ca 5 Le) CO bie R1 R2 Figure 29. Component Overlay for Circuit of Figure 26 -15- 6 | te LYAD7579/AD7580 MECHANICAL INFORMATION OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-PIN PLASTIC (SUFFIX N) AAAAAARAAAAALA Z 0.260 + 0.001 (6.61 + 0.03) VUVVVVVVVVV 1.228 (31.19) 1,226 (31.14) [ _\ 0.13013.30) 0.128 (3.25) bob 0.32 (8.128) f 0.30 (7.62) * 0.011 (0.28) 0.009 (.23) ale ie 4 0.02 [0.5} 0.11 (2.79) 9.07 (1.78) 15 9.016 (0.41) 0.09 (2.28) 0.06 {1.27} tT NOTES 7. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN LEAD PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 24-PIN CERAMIC (SUFFIX Q) 0.295 + 0.01 D {7.49 + 0.26) oo eee ort L 1.200 + 0.012 | lug 0.300 + 0.010 | U (30.48 +0.31) | i (7.62 + 0.25} SEATING __ 0.085 = 0.009 PLANE "9 475 (16 =O i445) Y alle -afke 0.018 +0.002 0,100 = 0.005 0.05 (1.27) oro #002 (4e=005) (2.54 = 0.13) TyP 0.019 _ 9 001 Te $0.05 1.100 + 0,005 (a.28 003 (27.94 = 0.13) TOLNON ACCUM NOTES 1. LEAO NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. CERAMIC DIP LEADS WILL BE EITHEA GOLD OR TIN PLATED IN AGCORDANCE WITH MIL-M-385 TO REQUIREMENTS. 3. METAL LID IS CONNECTED TO DGND. 24-PIN CERDIP (SUFFIX Q) om mo a a 24 WToooorUoUoOoO oOo ae |____ 1.290 {32.77} MAX __, t 13 0.295 (7.493) MAX zw) 0.320 (8.128) 0.290 (7 = obs | __} 0.180 15.715) (4.572) PLANE oe, He t 0.042 (0.305) 9.175 0.070/1.778 . : MIN o ; i 0.020 (0.508) 9.008 (0.203) 9.921(0.533) 0.110 {2.794 0.065 (1.651) 0.015 (0.381) 0.090 {2.286) 0.055 (1.397} = TvP TvP 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH. 2. CERDIP LEAOS WILL BE EfTHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS. 28-TERMINAL LEADLESS CERAMIC CHIP CARRIER (SUFFIX E) 0.045 (1.14) 0.055 (1.40) 9.75 191 | fr REF i. 4a 022 (0.56) Fe 028 (0.71) 0.064 (1.63)" 0108 1254 7 = 9.050 = 0.005 ~ (1.27 =0.13) NO. 1 PIN INDEX BOTTOM VIEW ooo xass eo (1.02 x45") | 0.020 x 45 REF 3 PLCS cm (057 x45" REF 0.442 (11.23)? NOTES 1. THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS. 2. APPLIES TO ALL FOUR SIDES. 3. ALL TERMINALS ARE GOLD PLATED 28-TERMINAL PLASTIC LEADED CHIP CARRIER (SUFFIX P) / o NG.1PIN 0.050 + 0.005 c IDENTIFIER 5 Cra) cea} q a 0,430 (10.5) qd 0.390(8.9) TOP Nn 4+ q VIEW 0.021 (0.533) D TF 0.013 10.331) c A someas . ; oDoUooUU * 0.456 (11.582) im pose tees) ; : . 0.090 {2.29) .600,11.4a0) S- 0.18014.51) 0.498(12.57) co 0.965 (4.20) 0.485 (12.32) PO REV. A C1072-9-7/87 PRINTED IN U.S.A.