Silicon SPDT Switch, Nonreflective, 100 MHz to 44 GHz ADRF5026-EP Enhanced Product GND GND RF2 GND GND 19 18 17 16 20 GND FUNCTIONAL BLOCK DIAGRAM 1 15 VSS EN 50 2 14 RFC 3 DRIVER 13 GND 4 GND 5 9 GND GND 10 8 RF1 7 GND 50 GND 12 CTRL 11 VDD 23688-001 GND 6 Ultrawideband frequency range: 100 MHz to 44 GHz Nonreflective design Low insertion loss: 1.2 dB to 18 GHz, 1.7 dB to 26 GHz, 2.4 dB to 40 GHz, 3.8 dB to 44 GHz High isolation: 55 dB to 18 GHz, 53 dB to 26 GHz, 50 dB to 40 GHz, 45 dB to 44 GHz High input linearity: 27 dBm typical P1dB, 53 dBm typical IP3 High power handling: 24 dBm insertion loss path, 24 dBm isolation path All off state control No low frequency spurious signals 0.1 dB RF settling time: 40 ns typical 20-terminal, 3 mm x 3 mm LGA package Pin compatible with ADRF5027, low frequency cutoff version GND FEATURES Figure 1. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range (-55C to +105C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5026-EP operates from 100 MHz to 44 GHz with better than 3.8 dB of insertion loss and 45 dB of isolation. The ADRF5026-EP features an all off control, where both RF ports are in an isolation state. The ADRF5026-EP has a nonreflective design and both of the RF ports are internally terminated to 50 . The ADRF5026-EP RF ports are designed to match a characteristic impedance of 50 . For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the ADRF5026 data sheet for an example of a matched circuit that achieves a flat insertion loss response of 2.4 dB from 28 GHz to 43 GHz. The ADRF5026-EP requires a dual-supply voltage of +3.3 V and -3.3 V. The device employs CMOS and low voltage transistor transistor logic (LVTTL)-compatible controls. The ADRF5026-EP comes in a 20-terminal, 3 mm x 3 mm, RoHS compliant, land grid array (LGA) package and can operate from -55C to +105C. The ADRF5026-EP is a nonreflective, single-pole, double-throw (SPDT) RF switch manufactured in a silicon process. The ADRF5026-EP is pin compatible with the ADRF5027 low frequency cutoff version, which operates from 9 kHz to 44 GHz. Rev. 0 Additional application and technical information can be found in the ADRF5026 data sheet. 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Technical Support www.analog.com ADRF5026-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Resistance .......................................................................5 Enhanced Product Features ............................................................ 1 Power Derating Curves ................................................................5 Applications ...................................................................................... 1 ESD Caution ..................................................................................5 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions .............................6 General Description ......................................................................... 1 Interface Schematics .....................................................................6 Revision History ............................................................................... 2 Typical Performance Characteristics .............................................7 Specifications .................................................................................... 3 Outline Dimensions ..........................................................................8 Electrical Specifications ............................................................... 3 Ordering Guide .............................................................................8 Absolute Maximum Ratings ........................................................... 5 REVISION HISTORY 10/2020--Revision 0: Initial Version Rev. 0 | Page 2 of 8 Enhanced Product ADRF5026-EP SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V, VSS = -3.3 V, CTRL pin voltage (VCTRL) = EN pin voltage (VEN) = 0 V or VDD, and TCASE = 25C in a 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Between RFC and RF1/RF2 Symbol RETURN LOSS RFC and RF1/RF2 (On) RL Min 100 Typ Max 44,000 Unit MHz IL RF1/RF2 (Off) ISOLATION Between RFC and RF1/RF2 Between RF1 and RF2 SWITCHING CHARACTERISTICS Rise and Fall Time On and Off Time RF Settling Time 0.1 dB 0.05 dB INPUT LINEARITY 1 dB Compression Third-Order Intercept SUPPLY CURRENT Positive Negative Test Conditions/Comments tRISE, tFALL tON, tOFF P1dB IP3 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz1 1.2 1.7 2.2 2.4 3.8 dB dB dB dB dB 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz1 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz1 22 12 9 10 7 23 23 21 13 12 dB dB dB dB dB dB dB dB dB dB 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 100 MHz to 18 GHz 18 GHz to 26 GHz 26 GHz to 35 GHz 35 GHz to 40 GHz 40 GHz to 44 GHz 55 53 53 50 45 63 60 60 63 55 dB dB dB dB dB dB dB dB dB dB 10% to 90% of RF output 50% of triggered VCTRL to 90% of RF output 3 14 ns ns 50% of triggered VCTRL to 0.1 dB of final RF output 50% of triggered VCTRL to 0.05 dB of final RF output 100 MHz to 40 GHz 40 45 ns ns 27 53 dBm dBm 2 100 A A Two-tone input power = 12 dBm each tone, f = 1 MHz VDD and VSS pins IDD ISS Rev. 0 | Page 3 of 8 ADRF5026-EP Parameter DIGITAL CONTROL INPUTS Voltage Low High Current Low and High Current RECOMMENDED OPERATING CONDITONS Supply Voltage Positive Negative Digital Control Voltage RF Input Power2 Insertion Loss Path Enhanced Product Symbol VINL VINH Min VDD VSS VCTRL, VEN PIN Typ 0 1.2 IINL, IINH Isolation Path Hot Switching Case Temperature Test Conditions/Comments CTRL and EN pins Max Unit 0.8 3.3 V V <1 3.15 -3.45 0 f = 100 MHz to 40 GHz, TCASE = 85C3 RF signal is applied to RFC or through connected RF1/RF2 RF signal is applied to terminated RF1/RF2 RF signal is present at RFC while switching between RF1 and RF2 TCASE -55 A 3.45 -3.15 VDD V V V 24 dBm 24 24 dBm dBm +105 C Impedance matching on RF transmission lines improves high frequency performance. Refer to the ADRF5026 data sheet for more information. For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path, isolation path, and hot switching power specifications. 3 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. 1 2 Rev. 0 | Page 4 of 8 Enhanced Product ADRF5026-EP ABSOLUTE MAXIMUM RATINGS POWER DERATING CURVES For recommended operating conditions, see Table 1. 2 Table 2. 0 Rating -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD + 0.3 V 3 mA POWER DERATING (dB) 26 dBm 25 dBm 25 dBm -2 -4 -6 -8 -10 -12 -14 10k 100k 10M 100M 1G 10G 100G FREQUENCY (Hz) 135C -65C to +150C 260C Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85C 2 POWER DERATING (dB) 0 500 V 2000 V 1250 V For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path, isolation path, and hot switching power specifications. 2 For 105C operation, the power handling degrades from the TCASE = 85C specification by 3 dB. 1 -2 -4 -6 -8 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JC is the junction to case bottom (channel to package bottom) thermal resistance. 34 36 38 40 42 44 46 48 50 Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85C 0.500 0.450 0.400 0.350 0.300 0.250 0.200 0.150 0.100 0.050 0 -55 -45 -35 -25 -15 -5 Table 3. Thermal Resistance 5 15 35 35 45 55 65 75 85 95 105 CASE TEMPERATURE (C) JC Unit 423 241 C/W C/W Figure 4. Maximum Power Dissipation vs. Case Temperature ESD CAUTION Rev. 0 | Page 5 of 8 23688-008 THERMAL RESISTANCE 32 FREQUENCY (GHz) MAXIMUM POWER DISSIPATION (Watts) Only one absolute maximum rating can be applied at any one time. -12 30 23688-003 -10 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Package Type CC-20-4 Through Path Terminated Path 1M 23688-002 Parameter Positive Supply Voltage Negative Supply Voltage Digital Control Inputs Voltage Current RF Input Power1 (100 MHz to 40 GHz at TCASE = 85C2) Insertion Loss Path Isolation Path Hot Switching Temperature Junction, TJ Storage Range Reflow Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) RFC, RF1, RF2 Pins Digital Pins Charged Device Model (CDM) ADRF5026-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 20 19 1 GND 2 RFC 3 GND RF2 18 17 16 15 VSS TOP VIEW (Not to Scale) 14 EN 13 GND 6 7 8 9 10 GND GND 11 VDD RF1 12 CTRL 5 GND 4 GND GND GND NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO THE RF AND DC GROUND OF THE PCB. 23688-004 GND GND GND GND ADRF5026-EP Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 2, 4, 5, 6, 7, 9, 10, 13, 16, 17, 19, 20 3 Mnemonic GND Description Ground. These pins must be connected to the RF and dc ground of the PCB. RFC 8 RF1 11 12 14 15 18 VDD CTRL EN VSS RF2 RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic. RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic. Positive Supply Voltage. Control Input Voltage. See Figure 7 for the interface schematic. Enable Input Voltage. See Figure 7 for the interface schematic. Negative Supply Voltage. RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 . No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic. Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB. EPAD INTERFACE SCHEMATICS VDD VDD 23688-005 23688-006 CTRL, EN RFC, RF1, RF2 Figure 7. CTRL, EN Interface Schematic Figure 6. RFC, RF1, RF2 Interface Schematic Rev. 0 | Page 6 of 8 Enhanced Product ADRF5026-EP TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3.3 V, VSS = -3.3 V, VCTRL/VEN = 0 V or VDD, and TCASE = 25C in a 50 system, unless otherwise noted. Insertion loss is measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. Signal coupling between the probes limits the isolation performance of the ADRF5026-EP. Isolation is measured on the ADRF5026-EVALZ evaluation board. See the ADRF5026 data sheet for details on the ADRF5026-EVALZ evaluation board and probe matrix board. See the ADRF5026 data sheet for a full set of Typical Performance Characteristics plots. 0 -2 -3 -4 -5 TCASE TCASE TCASE TCASE TCASE -6 -7 -8 0 5 10 = +105C = +85C = +25C = -55C = -40C 15 20 25 30 35 40 45 FREQUENCY (GHz) 50 23688-007 INSERTION LOSS (dB) -1 Figure 8. Insertion Loss vs. Frequency over Temperature Rev. 0 | Page 7 of 8 ADRF5026-EP Enhanced Product OUTLINE DIMENSIONS 3.10 3.00 2.90 16 CHAMFERED PIN 1 (0.3 x 45) 20 1 15 1.60 REF SQ 0.40 BSC TOP VIEW 0.776 0.726 0.676 SIDE VIEW 1.60 1.50 SQ 1.40 EXPOSED PAD 11 5 10 6 BOTTOM VIEW 0.13 REF 0.530 REF 0.236 0.196 0.156 PKG-005264 0.75 REF FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 06-21-2018-D PIN 1 CORNER AREA 0.25 0.20 0.15 0.30 0.25 0.20 Figure 9. 20-Terminal Land Grid Array [LGA] 3 mm x 3 mm Body and 0.726 mm Package Height (CC-20-4) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRF5026SCCZ-EP ADRF5026SCCZ-EPR7 1 Temperature Range -55C to +105C -55C to +105C Package Description 20-Terminal Land Grid Array [LGA] 20-Terminal Land Grid Array [LGA] Z = RoHS Compliant Part. (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D23688-10/20(0) Rev. 0 | Page 8 of 8 Package Option CC-20-4 CC-20-4 Marking Code 6EP 6EP